1 /* $NetBSD: cpc700.c,v 1.7 2003/11/07 17:06:42 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The IBM CPC700 is a bridge chip for the PowerPC. It contains 41 * - CPU interface 42 * - DRAM controller 43 * - PCI bus master & slave controller 44 * - interrupt controller 45 * - timer 46 * - two UARTs 47 * - two IIC ports 48 * 49 * This driver handles the overall device and enumeration of the 50 * supported subdevices. NetBSD knows how to handle: 51 * - PCI master 52 * - interrupt controller 53 * - UARTs 54 * Skeleton drivers are provided for the timer and IIC. 55 * 56 * XXX This driver assumes that there is only one instance of it. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.7 2003/11/07 17:06:42 augustss Exp $"); 61 62 #include "pci.h" 63 #include "opt_pci.h" 64 65 #include <sys/param.h> 66 #include <sys/extent.h> 67 #include <sys/device.h> 68 #include <sys/malloc.h> 69 #include <sys/systm.h> 70 71 #include <machine/bus.h> 72 #include "locators.h" 73 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pciconf.h> 77 78 #include <dev/ic/cpc700reg.h> 79 #include <dev/ic/cpc700var.h> 80 #include <dev/ic/cpc700uic.h> 81 82 union attach_args { 83 const char *busname; /* first elem of all */ 84 struct pcibus_attach_args pba; 85 struct cpcbus_attach_args cba; 86 }; 87 88 89 void 90 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 91 bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci, 92 uint freq); 93 94 static bus_space_tag_t the_cpc_tag; 95 static bus_space_handle_t the_cpc_handle; 96 #define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a)) 97 #define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d) 98 99 static int 100 cpc_print(void *aux, const char *pnp) 101 { 102 struct cpcbus_attach_args *caa = aux; 103 104 if (pnp) 105 aprint_normal("%s at %s", caa->cpca_name, pnp); 106 107 aprint_normal(" addr 0x%08x", caa->cpca_addr); 108 if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT) 109 aprint_normal(" irq %d", caa->cpca_irq); 110 111 return (UNCONF); 112 } 113 114 static int 115 cpcpci_print(void *aux, const char *pnp) 116 { 117 union attach_args *aa = aux; 118 119 if (pnp) 120 aprint_normal("%s at %s", aa->busname, pnp); 121 122 return (UNCONF); 123 } 124 125 static int 126 cpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 127 { 128 struct cpcbus_attach_args *caa = aux; 129 130 if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr) 131 return (0); 132 133 return (config_match(parent, cf, aux)); 134 } 135 136 /* 137 * Attach the cpc. 138 */ 139 void 140 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 141 bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci, 142 uint freq) 143 { 144 union attach_args aa; 145 int i; 146 pcitag_t tag; 147 pcireg_t erren; 148 pcireg_t v; 149 static struct { 150 const char *name; 151 bus_addr_t addr; 152 int irq; 153 } devs[] = { 154 { "com", CPC_COM0, CPC_IB_UART_0 }, 155 { "com", CPC_COM1, CPC_IB_UART_1 }, 156 { "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT }, 157 { "cpciic", CPC_IIC0, CPC_IB_IIC_0 }, 158 { "cpciic", CPC_IIC1, CPC_IB_IIC_1 }, 159 { NULL, 0 } 160 }; 161 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 162 struct extent *ioext, *memext; 163 #ifdef PCI_CONFIGURE_VERBOSE 164 extern int pci_conf_debug; 165 166 pci_conf_debug = 1; 167 #endif 168 #endif 169 170 printf(": IBM CPC700\n"); 171 172 the_cpc_tag = mem; 173 if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0, 174 &the_cpc_handle)) { 175 printf("%s: can't map i/o space\n", self->dv_xname); 176 return; 177 } 178 179 aa.cba.cpca_tag = mem; 180 aa.cba.cpca_freq = freq; 181 for (i = 0; devs[i].name; i++) { 182 aa.cba.cpca_name = devs[i].name; 183 aa.cba.cpca_addr = devs[i].addr; 184 aa.cba.cpca_irq = devs[i].irq; 185 config_found_sm(self, &aa.cba, cpc_print, cpc_submatch); 186 } 187 188 tag = pci_make_tag(pc, 0, 0, 0); 189 190 aa.pba.pba_busname = "pci"; 191 aa.pba.pba_iot = pciio; 192 aa.pba.pba_memt = mem; 193 aa.pba.pba_dmat = dma; 194 aa.pba.pba_pc = 0; 195 aa.pba.pba_flags = PCI_FLAGS_MEM_ENABLED | PCI_FLAGS_IO_ENABLED; 196 aa.pba.pba_bus = 0; 197 198 /* Save PCI error condition reg. */ 199 erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR); 200 /* Don't generate errors during probe. */ 201 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0); 202 203 /* Program MITL */ 204 v = pci_conf_read(pc, tag, CPC_BRIDGE_OPTIONS2); 205 v &= ~(CPC_BRIDGE_O2_ILAT_MASK | CPC_BRIDGE_O2_SLAT_MASK); 206 v |= (CPC_BRIDGE_O2_ILAT_PRIM_ASYNC << CPC_BRIDGE_O2_ILAT_SHIFT) | 207 (CPC_BRIDGE_O2_2LAT_PRIM_ASYNC << CPC_BRIDGE_O2_SLAT_SHIFT); 208 pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v); 209 210 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 211 ioext = extent_create("pciio", CPC_PCI_IO_START, CPC_PCI_IO_END, 212 M_DEVBUF, NULL, 0, EX_NOWAIT); 213 memext = extent_create("pcimem", CPC_PCI_MEM_BASE, CPC_PCI_MEM_END, 214 M_DEVBUF, NULL, 0, EX_NOWAIT); 215 216 pci_configure_bus(0, ioext, memext, NULL, 0, 32); 217 218 extent_destroy(ioext); 219 extent_destroy(memext); 220 #endif 221 222 config_found(self, &aa.pba, cpcpci_print); 223 224 /* Restore error triggers, and clear errors */ 225 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR); 226 } 227 228 /***************************************************************************/ 229 230 /* 231 * Interrupt controller. 232 */ 233 234 void 235 cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh, 236 u_int32_t active, u_int32_t level) 237 { 238 /* XXX */ 239 the_cpc_tag = bt; 240 the_cpc_handle = bh; 241 /* 242 * See CPC700 manual for information about what 243 * interrupts have which properties. 244 */ 245 OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */ 246 OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */ 247 OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */ 248 OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */ 249 OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */ 250 OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */ 251 } 252 253 int 254 cpc700_read_irq(void) 255 { 256 int irq; 257 u_int32_t irqs; 258 259 irqs = INL(CPC_UIC_MSR); 260 for (irq = 0; irq < ICU_LEN; irq++) { 261 if (irqs & CPC_INTR_MASK(irq)) 262 return (irq); 263 } 264 return (-1); 265 } 266 267 void 268 cpc700_eoi(int irq) 269 { 270 OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq)); 271 } 272 273 void 274 cpc700_disable_irq(int irq) 275 { 276 u_int32_t reg; 277 278 reg = INL(CPC_UIC_ER); 279 reg &= ~CPC_INTR_MASK(irq); 280 OUTL(CPC_UIC_ER, reg); 281 } 282 283 void 284 cpc700_enable_irq(int irq) 285 { 286 u_int32_t reg; 287 288 reg = INL(CPC_UIC_ER); 289 reg |= CPC_INTR_MASK(irq); 290 OUTL(CPC_UIC_ER, reg); 291 } 292