1 /* $NetBSD: cpc700.c,v 1.8 2004/08/30 15:05:19 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The IBM CPC700 is a bridge chip for the PowerPC. It contains 41 * - CPU interface 42 * - DRAM controller 43 * - PCI bus master & slave controller 44 * - interrupt controller 45 * - timer 46 * - two UARTs 47 * - two IIC ports 48 * 49 * This driver handles the overall device and enumeration of the 50 * supported subdevices. NetBSD knows how to handle: 51 * - PCI master 52 * - interrupt controller 53 * - UARTs 54 * Skeleton drivers are provided for the timer and IIC. 55 * 56 * XXX This driver assumes that there is only one instance of it. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.8 2004/08/30 15:05:19 drochner Exp $"); 61 62 #include "pci.h" 63 #include "opt_pci.h" 64 65 #include <sys/param.h> 66 #include <sys/extent.h> 67 #include <sys/device.h> 68 #include <sys/malloc.h> 69 #include <sys/systm.h> 70 71 #include <machine/bus.h> 72 #include "locators.h" 73 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pciconf.h> 77 78 #include <dev/ic/cpc700reg.h> 79 #include <dev/ic/cpc700var.h> 80 #include <dev/ic/cpc700uic.h> 81 82 union attach_args { 83 struct pcibus_attach_args pba; 84 struct cpcbus_attach_args cba; 85 }; 86 87 88 void 89 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 90 bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci, 91 uint freq); 92 93 static bus_space_tag_t the_cpc_tag; 94 static bus_space_handle_t the_cpc_handle; 95 #define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a)) 96 #define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d) 97 98 static int 99 cpc_print(void *aux, const char *pnp) 100 { 101 struct cpcbus_attach_args *caa = aux; 102 103 if (pnp) 104 aprint_normal("%s at %s", caa->cpca_name, pnp); 105 106 aprint_normal(" addr 0x%08x", caa->cpca_addr); 107 if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT) 108 aprint_normal(" irq %d", caa->cpca_irq); 109 110 return (UNCONF); 111 } 112 113 static int 114 cpc_submatch(struct device *parent, struct cfdata *cf, 115 const locdesc_t *ldesc, void *aux) 116 { 117 struct cpcbus_attach_args *caa = aux; 118 119 if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr) 120 return (0); 121 122 return (config_match(parent, cf, aux)); 123 } 124 125 /* 126 * Attach the cpc. 127 */ 128 void 129 cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem, 130 bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci, 131 uint freq) 132 { 133 union attach_args aa; 134 int i; 135 pcitag_t tag; 136 pcireg_t erren; 137 pcireg_t v; 138 static struct { 139 const char *name; 140 bus_addr_t addr; 141 int irq; 142 } devs[] = { 143 { "com", CPC_COM0, CPC_IB_UART_0 }, 144 { "com", CPC_COM1, CPC_IB_UART_1 }, 145 { "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT }, 146 { "cpciic", CPC_IIC0, CPC_IB_IIC_0 }, 147 { "cpciic", CPC_IIC1, CPC_IB_IIC_1 }, 148 { NULL, 0 } 149 }; 150 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 151 struct extent *ioext, *memext; 152 #ifdef PCI_CONFIGURE_VERBOSE 153 extern int pci_conf_debug; 154 155 pci_conf_debug = 1; 156 #endif 157 #endif 158 159 printf(": IBM CPC700\n"); 160 161 the_cpc_tag = mem; 162 if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0, 163 &the_cpc_handle)) { 164 printf("%s: can't map i/o space\n", self->dv_xname); 165 return; 166 } 167 168 aa.cba.cpca_tag = mem; 169 aa.cba.cpca_freq = freq; 170 for (i = 0; devs[i].name; i++) { 171 aa.cba.cpca_name = devs[i].name; 172 aa.cba.cpca_addr = devs[i].addr; 173 aa.cba.cpca_irq = devs[i].irq; 174 config_found_sm_loc(self, "cpcbus", NULL, &aa.cba, 175 cpc_print, cpc_submatch); 176 } 177 178 tag = pci_make_tag(pc, 0, 0, 0); 179 180 aa.pba.pba_iot = pciio; 181 aa.pba.pba_memt = mem; 182 aa.pba.pba_dmat = dma; 183 aa.pba.pba_pc = 0; 184 aa.pba.pba_flags = PCI_FLAGS_MEM_ENABLED | PCI_FLAGS_IO_ENABLED; 185 aa.pba.pba_bus = 0; 186 187 /* Save PCI error condition reg. */ 188 erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR); 189 /* Don't generate errors during probe. */ 190 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0); 191 192 /* Program MITL */ 193 v = pci_conf_read(pc, tag, CPC_BRIDGE_OPTIONS2); 194 v &= ~(CPC_BRIDGE_O2_ILAT_MASK | CPC_BRIDGE_O2_SLAT_MASK); 195 v |= (CPC_BRIDGE_O2_ILAT_PRIM_ASYNC << CPC_BRIDGE_O2_ILAT_SHIFT) | 196 (CPC_BRIDGE_O2_2LAT_PRIM_ASYNC << CPC_BRIDGE_O2_SLAT_SHIFT); 197 pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v); 198 199 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 200 ioext = extent_create("pciio", CPC_PCI_IO_START, CPC_PCI_IO_END, 201 M_DEVBUF, NULL, 0, EX_NOWAIT); 202 memext = extent_create("pcimem", CPC_PCI_MEM_BASE, CPC_PCI_MEM_END, 203 M_DEVBUF, NULL, 0, EX_NOWAIT); 204 205 pci_configure_bus(0, ioext, memext, NULL, 0, 32); 206 207 extent_destroy(ioext); 208 extent_destroy(memext); 209 #endif 210 211 config_found_ia(self, "pcibus", &aa.pba, pcibusprint); 212 213 /* Restore error triggers, and clear errors */ 214 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR); 215 } 216 217 /***************************************************************************/ 218 219 /* 220 * Interrupt controller. 221 */ 222 223 void 224 cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh, 225 u_int32_t active, u_int32_t level) 226 { 227 /* XXX */ 228 the_cpc_tag = bt; 229 the_cpc_handle = bh; 230 /* 231 * See CPC700 manual for information about what 232 * interrupts have which properties. 233 */ 234 OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */ 235 OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */ 236 OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */ 237 OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */ 238 OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */ 239 OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */ 240 } 241 242 int 243 cpc700_read_irq(void) 244 { 245 int irq; 246 u_int32_t irqs; 247 248 irqs = INL(CPC_UIC_MSR); 249 for (irq = 0; irq < ICU_LEN; irq++) { 250 if (irqs & CPC_INTR_MASK(irq)) 251 return (irq); 252 } 253 return (-1); 254 } 255 256 void 257 cpc700_eoi(int irq) 258 { 259 OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq)); 260 } 261 262 void 263 cpc700_disable_irq(int irq) 264 { 265 u_int32_t reg; 266 267 reg = INL(CPC_UIC_ER); 268 reg &= ~CPC_INTR_MASK(irq); 269 OUTL(CPC_UIC_ER, reg); 270 } 271 272 void 273 cpc700_enable_irq(int irq) 274 { 275 u_int32_t reg; 276 277 reg = INL(CPC_UIC_ER); 278 reg |= CPC_INTR_MASK(irq); 279 OUTL(CPC_UIC_ER, reg); 280 } 281