1 /* $NetBSD: com.c,v 1.333 2015/04/13 16:33:24 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.333 2015/04/13 16:33:24 riastradh Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #ifdef COM_HAYESP 126 #include <dev/ic/hayespreg.h> 127 #endif 128 #define com_lcr com_cfcr 129 #include <dev/cons.h> 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 extern struct cfdriver com_cd; 194 195 dev_type_open(comopen); 196 dev_type_close(comclose); 197 dev_type_read(comread); 198 dev_type_write(comwrite); 199 dev_type_ioctl(comioctl); 200 dev_type_stop(comstop); 201 dev_type_tty(comtty); 202 dev_type_poll(compoll); 203 204 static struct comcons_info comcons_info; 205 206 /* 207 * Following are all routines needed for COM to act as console 208 */ 209 static struct consdev comcons = { 210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 211 NODEV, CN_NORMAL 212 }; 213 214 215 const struct cdevsw com_cdevsw = { 216 .d_open = comopen, 217 .d_close = comclose, 218 .d_read = comread, 219 .d_write = comwrite, 220 .d_ioctl = comioctl, 221 .d_stop = comstop, 222 .d_tty = comtty, 223 .d_poll = compoll, 224 .d_mmap = nommap, 225 .d_kqfilter = ttykqfilter, 226 .d_discard = nodiscard, 227 .d_flag = D_TTY 228 }; 229 230 /* 231 * Make this an option variable one can patch. 232 * But be warned: this must be a power of 2! 233 */ 234 u_int com_rbuf_size = COM_RING_SIZE; 235 236 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 237 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 238 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 239 240 static int comconsattached; 241 static struct cnm_state com_cnm_state; 242 243 #ifdef KGDB 244 #include <sys/kgdb.h> 245 246 static struct com_regs comkgdbregs; 247 static int com_kgdb_attached; 248 249 int com_kgdb_getc(void *); 250 void com_kgdb_putc(void *, int); 251 #endif /* KGDB */ 252 253 #ifdef COM_REGMAP 254 /* initializer for typical 16550-ish hardware */ 255 #define COM_REG_16550 { \ 256 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 257 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 258 /* 16750-specific register set, additional UART status register */ 259 #define COM_REG_16750 { \ 260 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 261 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 263 264 #ifdef COM_16750 265 const bus_size_t com_std_map[32] = COM_REG_16750; 266 #else 267 const bus_size_t com_std_map[16] = COM_REG_16550; 268 #endif /* COM_16750 */ 269 #endif /* COM_REGMAP */ 270 271 #define COMDIALOUT_MASK TTDIALOUT_MASK 272 273 #define COMUNIT(x) TTUNIT(x) 274 #define COMDIALOUT(x) TTDIALOUT(x) 275 276 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 277 device_is_active((sc)->sc_dev)) 278 279 #define BR BUS_SPACE_BARRIER_READ 280 #define BW BUS_SPACE_BARRIER_WRITE 281 #define COM_BARRIER(r, f) \ 282 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 283 284 /*ARGSUSED*/ 285 int 286 comspeed(long speed, long frequency, int type) 287 { 288 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 289 290 int x, err; 291 int divisor = 16; 292 293 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 294 divisor = 13; 295 } 296 297 if (speed == 0) 298 return (0); 299 if (speed < 0) 300 return (-1); 301 x = divrnd(frequency / divisor, speed); 302 if (x <= 0) 303 return (-1); 304 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 305 if (err < 0) 306 err = -err; 307 if (err > COM_TOLERANCE) 308 return (-1); 309 return (x); 310 311 #undef divrnd 312 } 313 314 #ifdef COM_DEBUG 315 int com_debug = 0; 316 317 void comstatus(struct com_softc *, const char *); 318 void 319 comstatus(struct com_softc *sc, const char *str) 320 { 321 struct tty *tp = sc->sc_tty; 322 323 aprint_normal_dev(sc->sc_dev, 324 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 325 str, 326 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 327 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 328 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 329 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 330 sc->sc_tx_stopped ? '+' : '-'); 331 332 aprint_normal_dev(sc->sc_dev, 333 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 334 str, 335 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 336 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 337 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 338 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 339 sc->sc_rx_flags); 340 } 341 #endif 342 343 int 344 com_probe_subr(struct com_regs *regs) 345 { 346 347 /* force access to id reg */ 348 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 349 CSR_WRITE_1(regs, COM_REG_IIR, 0); 350 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 351 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 352 return (0); 353 354 return (1); 355 } 356 357 int 358 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 359 { 360 struct com_regs regs; 361 362 regs.cr_iot = iot; 363 regs.cr_ioh = ioh; 364 #ifdef COM_REGMAP 365 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 366 #endif 367 368 return com_probe_subr(®s); 369 } 370 371 /* 372 * No locking in this routine; it is only called during attach, 373 * or with the port already locked. 374 */ 375 static void 376 com_enable_debugport(struct com_softc *sc) 377 { 378 379 /* Turn on line break interrupt, set carrier. */ 380 sc->sc_ier = IER_ERXRDY; 381 if (sc->sc_type == COM_TYPE_PXA2x0) 382 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 383 if (sc->sc_type == COM_TYPE_INGENIC) 384 sc->sc_ier |= IER_ERXTOUT; 385 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 386 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 387 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 388 } 389 390 void 391 com_attach_subr(struct com_softc *sc) 392 { 393 struct com_regs *regsp = &sc->sc_regs; 394 struct tty *tp; 395 #if defined(COM_16650) || defined(COM_16750) 396 u_int8_t lcr; 397 #endif 398 const char *fifo_msg = NULL; 399 prop_dictionary_t dict; 400 bool is_console = true; 401 402 aprint_naive("\n"); 403 404 dict = device_properties(sc->sc_dev); 405 prop_dictionary_get_bool(dict, "is_console", &is_console); 406 callout_init(&sc->sc_diag_callout, 0); 407 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 408 409 /* Disable interrupts before configuring the device. */ 410 if (sc->sc_type == COM_TYPE_PXA2x0) 411 sc->sc_ier = IER_EUART; 412 else 413 sc->sc_ier = 0; 414 415 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 416 417 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 418 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 419 comconsattached = 1; 420 421 if (cn_tab == NULL && comcnreattach() != 0) { 422 printf("can't re-init serial console @%lx\n", 423 (u_long)comcons_info.regs.cr_iobase); 424 } 425 426 #ifdef COM_16750 427 /* Use in comintr(). */ 428 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 429 #endif 430 431 /* Make sure the console is always "hardwired". */ 432 delay(10000); /* wait for output to finish */ 433 if (is_console) { 434 SET(sc->sc_hwflags, COM_HW_CONSOLE); 435 } 436 437 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 438 } 439 440 /* Probe for FIFO */ 441 switch (sc->sc_type) { 442 case COM_TYPE_HAYESP: 443 goto fifodone; 444 445 case COM_TYPE_AU1x00: 446 sc->sc_fifolen = 16; 447 fifo_msg = "Au1X00 UART, working fifo"; 448 SET(sc->sc_hwflags, COM_HW_FIFO); 449 goto fifodelay; 450 451 case COM_TYPE_16550_NOERS: 452 sc->sc_fifolen = 16; 453 fifo_msg = "ns16650, no ERS, working fifo"; 454 SET(sc->sc_hwflags, COM_HW_FIFO); 455 goto fifodelay; 456 457 case COM_TYPE_OMAP: 458 sc->sc_fifolen = 64; 459 fifo_msg = "OMAP UART, working fifo"; 460 SET(sc->sc_hwflags, COM_HW_FIFO); 461 goto fifodelay; 462 463 case COM_TYPE_INGENIC: 464 sc->sc_fifolen = 16; 465 fifo_msg = "Ingenic UART, working fifo"; 466 SET(sc->sc_hwflags, COM_HW_FIFO); 467 SET(sc->sc_hwflags, COM_HW_NOIEN); 468 goto fifodelay; 469 } 470 471 sc->sc_fifolen = 1; 472 /* look for a NS 16550AF UART with FIFOs */ 473 if (sc->sc_type == COM_TYPE_INGENIC) { 474 CSR_WRITE_1(regsp, COM_REG_FIFO, 475 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 476 FIFO_TRIGGER_14 | FIFO_UART_ON); 477 } else 478 CSR_WRITE_1(regsp, COM_REG_FIFO, 479 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 480 delay(100); 481 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 482 == IIR_FIFO_MASK) 483 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 484 == FIFO_TRIGGER_14) { 485 SET(sc->sc_hwflags, COM_HW_FIFO); 486 487 #ifdef COM_16650 488 /* 489 * IIR changes into the EFR if LCR is set to LCR_EERS 490 * on 16650s. We also know IIR != 0 at this point. 491 * Write 0 into the EFR, and read it. If the result 492 * is 0, we have a 16650. 493 * 494 * Older 16650s were broken; the test to detect them 495 * is taken from the Linux driver. Apparently 496 * setting DLAB enable gives access to the EFR on 497 * these chips. 498 */ 499 lcr = CSR_READ_1(regsp, COM_REG_LCR); 500 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 501 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 502 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 503 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 504 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 505 CLR(sc->sc_hwflags, COM_HW_FIFO); 506 sc->sc_fifolen = 0; 507 } else { 508 SET(sc->sc_hwflags, COM_HW_FLOW); 509 sc->sc_fifolen = 32; 510 } 511 } else 512 #endif 513 sc->sc_fifolen = 16; 514 515 #ifdef COM_16750 516 /* 517 * TL16C750 can enable 64byte FIFO, only when DLAB 518 * is 1. However, some 16750 may always enable. For 519 * example, restrictions according to DLAB in a data 520 * sheet for SC16C750 were not described. 521 * Please enable 'options COM_16650', supposing you 522 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 523 * should become effective. 524 */ 525 uint8_t iir1, iir2; 526 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 527 528 if (sc->sc_type == COM_TYPE_INGENIC) 529 fcr |= FIFO_UART_ON; 530 531 lcr = CSR_READ_1(regsp, COM_REG_LCR); 532 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 533 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 534 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 535 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 536 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 538 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 539 540 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 541 542 if (!ISSET(iir1, IIR_64B_FIFO) && 543 ISSET(iir2, IIR_64B_FIFO)) { 544 /* It is TL16C750. */ 545 sc->sc_fifolen = 64; 546 SET(sc->sc_hwflags, COM_HW_AFE); 547 } else 548 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 549 #endif 550 551 #ifdef COM_16650 552 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 553 if (sc->sc_fifolen == 0) 554 fifo_msg = "st16650, broken fifo"; 555 else if (sc->sc_fifolen == 32) 556 fifo_msg = "st16650a, working fifo"; 557 else 558 #endif 559 #ifdef COM_16750 560 if (sc->sc_fifolen == 64) 561 fifo_msg = "tl16c750, working fifo"; 562 else 563 #endif 564 fifo_msg = "ns16550a, working fifo"; 565 } else 566 fifo_msg = "ns16550, broken fifo"; 567 else 568 fifo_msg = "ns8250 or ns16450, no fifo"; 569 if (sc->sc_type == COM_TYPE_INGENIC) { 570 CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON); 571 } else 572 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 573 fifodelay: 574 /* 575 * Some chips will clear down both Tx and Rx FIFOs when zero is 576 * written to com_fifo. If this chip is the console, writing zero 577 * results in some of the chip/FIFO description being lost, so delay 578 * printing it until now. 579 */ 580 delay(10); 581 aprint_normal(": %s\n", fifo_msg); 582 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 583 sc->sc_fifolen = 1; 584 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 585 } 586 587 fifodone: 588 589 tp = tty_alloc(); 590 tp->t_oproc = comstart; 591 tp->t_param = comparam; 592 tp->t_hwiflow = comhwiflow; 593 tp->t_softc = sc; 594 595 sc->sc_tty = tp; 596 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 597 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 598 sc->sc_rbavail = com_rbuf_size; 599 if (sc->sc_rbuf == NULL) { 600 aprint_error_dev(sc->sc_dev, 601 "unable to allocate ring buffer\n"); 602 return; 603 } 604 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 605 606 tty_attach(tp); 607 608 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 609 SET(sc->sc_mcr, MCR_IENABLE); 610 611 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 612 int maj; 613 614 /* locate the major number */ 615 maj = cdevsw_lookup_major(&com_cdevsw); 616 617 tp->t_dev = cn_tab->cn_dev = makedev(maj, 618 device_unit(sc->sc_dev)); 619 620 aprint_normal_dev(sc->sc_dev, "console\n"); 621 } 622 623 #ifdef KGDB 624 /* 625 * Allow kgdb to "take over" this port. If this is 626 * not the console and is the kgdb device, it has 627 * exclusive use. If it's the console _and_ the 628 * kgdb device, it doesn't. 629 */ 630 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 631 regsp->cr_iobase == comkgdbregs.cr_iobase) { 632 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 633 com_kgdb_attached = 1; 634 635 SET(sc->sc_hwflags, COM_HW_KGDB); 636 } 637 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 638 } 639 #endif 640 641 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 642 643 #ifdef RND_COM 644 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 645 RND_TYPE_TTY, RND_FLAG_DEFAULT); 646 #endif 647 648 /* if there are no enable/disable functions, assume the device 649 is always enabled */ 650 if (!sc->enable) 651 sc->enabled = 1; 652 653 com_config(sc); 654 655 SET(sc->sc_hwflags, COM_HW_DEV_OK); 656 } 657 658 void 659 com_config(struct com_softc *sc) 660 { 661 struct com_regs *regsp = &sc->sc_regs; 662 663 /* Disable interrupts before configuring the device. */ 664 if (sc->sc_type == COM_TYPE_PXA2x0) 665 sc->sc_ier = IER_EUART; 666 else 667 sc->sc_ier = 0; 668 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 669 (void) CSR_READ_1(regsp, COM_REG_IIR); 670 671 #ifdef COM_HAYESP 672 /* Look for a Hayes ESP board. */ 673 if (sc->sc_type == COM_TYPE_HAYESP) { 674 675 /* Set 16550 compatibility mode */ 676 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 677 HAYESP_SETMODE); 678 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 679 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 680 HAYESP_MODE_SCALE); 681 682 /* Set RTS/CTS flow control */ 683 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 684 HAYESP_SETFLOWTYPE); 685 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 686 HAYESP_FLOW_RTS); 687 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 688 HAYESP_FLOW_CTS); 689 690 /* Set flow control levels */ 691 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 692 HAYESP_SETRXFLOW); 693 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 694 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 695 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 696 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 697 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 698 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 699 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 700 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 701 } 702 #endif 703 704 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 705 com_enable_debugport(sc); 706 } 707 708 #if 0 709 static int 710 comcngetc_detached(dev_t dev) 711 { 712 return 0; 713 } 714 715 static void 716 comcnputc_detached(dev_t dev, int c) 717 { 718 } 719 #endif 720 721 int 722 com_detach(device_t self, int flags) 723 { 724 struct com_softc *sc = device_private(self); 725 int maj, mn; 726 727 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 728 return EBUSY; 729 730 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 731 (flags & DETACH_SHUTDOWN) != 0) 732 return EBUSY; 733 734 if (sc->disable != NULL && sc->enabled != 0) { 735 (*sc->disable)(sc); 736 sc->enabled = 0; 737 } 738 739 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 740 comconsattached = 0; 741 cn_tab = NULL; 742 } 743 744 /* locate the major number */ 745 maj = cdevsw_lookup_major(&com_cdevsw); 746 747 /* Nuke the vnodes for any open instances. */ 748 mn = device_unit(self); 749 vdevgone(maj, mn, mn, VCHR); 750 751 mn |= COMDIALOUT_MASK; 752 vdevgone(maj, mn, mn, VCHR); 753 754 if (sc->sc_rbuf == NULL) { 755 /* 756 * Ring buffer allocation failed in the com_attach_subr, 757 * only the tty is allocated, and nothing else. 758 */ 759 tty_free(sc->sc_tty); 760 return 0; 761 } 762 763 /* Free the receive buffer. */ 764 free(sc->sc_rbuf, M_DEVBUF); 765 766 /* Detach and free the tty. */ 767 tty_detach(sc->sc_tty); 768 tty_free(sc->sc_tty); 769 770 /* Unhook the soft interrupt handler. */ 771 softint_disestablish(sc->sc_si); 772 773 #ifdef RND_COM 774 /* Unhook the entropy source. */ 775 rnd_detach_source(&sc->rnd_source); 776 #endif 777 callout_destroy(&sc->sc_diag_callout); 778 779 /* Destroy the lock. */ 780 mutex_destroy(&sc->sc_lock); 781 782 return (0); 783 } 784 785 void 786 com_shutdown(struct com_softc *sc) 787 { 788 struct tty *tp = sc->sc_tty; 789 790 mutex_spin_enter(&sc->sc_lock); 791 792 /* If we were asserting flow control, then deassert it. */ 793 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 794 com_hwiflow(sc); 795 796 /* Clear any break condition set with TIOCSBRK. */ 797 com_break(sc, 0); 798 799 /* 800 * Hang up if necessary. Wait a bit, so the other side has time to 801 * notice even if we immediately open the port again. 802 * Avoid tsleeping above splhigh(). 803 */ 804 if (ISSET(tp->t_cflag, HUPCL)) { 805 com_modem(sc, 0); 806 mutex_spin_exit(&sc->sc_lock); 807 /* XXX will only timeout */ 808 (void) kpause(ttclos, false, hz, NULL); 809 mutex_spin_enter(&sc->sc_lock); 810 } 811 812 /* Turn off interrupts. */ 813 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 814 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 815 if ((sc->sc_type == COM_TYPE_PXA2x0) || 816 (sc->sc_type == COM_TYPE_INGENIC)) 817 sc->sc_ier |= IER_ERXTOUT; 818 } else 819 sc->sc_ier = 0; 820 821 if (sc->sc_type == COM_TYPE_PXA2x0) 822 sc->sc_ier |= IER_EUART; 823 824 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 825 826 mutex_spin_exit(&sc->sc_lock); 827 828 if (sc->disable) { 829 #ifdef DIAGNOSTIC 830 if (!sc->enabled) 831 panic("com_shutdown: not enabled?"); 832 #endif 833 (*sc->disable)(sc); 834 sc->enabled = 0; 835 } 836 } 837 838 int 839 comopen(dev_t dev, int flag, int mode, struct lwp *l) 840 { 841 struct com_softc *sc; 842 struct tty *tp; 843 int s; 844 int error; 845 846 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 847 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 848 sc->sc_rbuf == NULL) 849 return (ENXIO); 850 851 if (!device_is_active(sc->sc_dev)) 852 return (ENXIO); 853 854 #ifdef KGDB 855 /* 856 * If this is the kgdb port, no other use is permitted. 857 */ 858 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 859 return (EBUSY); 860 #endif 861 862 tp = sc->sc_tty; 863 864 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 865 return (EBUSY); 866 867 s = spltty(); 868 869 /* 870 * Do the following iff this is a first open. 871 */ 872 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 873 struct termios t; 874 875 tp->t_dev = dev; 876 877 if (sc->enable) { 878 if ((*sc->enable)(sc)) { 879 splx(s); 880 aprint_error_dev(sc->sc_dev, 881 "device enable failed\n"); 882 return (EIO); 883 } 884 mutex_spin_enter(&sc->sc_lock); 885 sc->enabled = 1; 886 com_config(sc); 887 } else { 888 mutex_spin_enter(&sc->sc_lock); 889 } 890 891 /* Turn on interrupts. */ 892 sc->sc_ier = IER_ERXRDY | IER_ERLS; 893 if (!ISSET(tp->t_cflag, CLOCAL)) 894 sc->sc_ier |= IER_EMSC; 895 896 if (sc->sc_type == COM_TYPE_PXA2x0) 897 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 898 else if (sc->sc_type == COM_TYPE_INGENIC) 899 sc->sc_ier |= IER_ERXTOUT; 900 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 901 902 /* Fetch the current modem control status, needed later. */ 903 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 904 905 /* Clear PPS capture state on first open. */ 906 mutex_spin_enter(&timecounter_lock); 907 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 908 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 909 pps_init(&sc->sc_pps_state); 910 mutex_spin_exit(&timecounter_lock); 911 912 mutex_spin_exit(&sc->sc_lock); 913 914 /* 915 * Initialize the termios status to the defaults. Add in the 916 * sticky bits from TIOCSFLAGS. 917 */ 918 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 919 t.c_ospeed = comcons_info.rate; 920 t.c_cflag = comcons_info.cflag; 921 } else { 922 t.c_ospeed = TTYDEF_SPEED; 923 t.c_cflag = TTYDEF_CFLAG; 924 } 925 t.c_ispeed = t.c_ospeed; 926 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 927 SET(t.c_cflag, CLOCAL); 928 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 929 SET(t.c_cflag, CRTSCTS); 930 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 931 SET(t.c_cflag, MDMBUF); 932 /* Make sure comparam() will do something. */ 933 tp->t_ospeed = 0; 934 (void) comparam(tp, &t); 935 tp->t_iflag = TTYDEF_IFLAG; 936 tp->t_oflag = TTYDEF_OFLAG; 937 tp->t_lflag = TTYDEF_LFLAG; 938 ttychars(tp); 939 ttsetwater(tp); 940 941 mutex_spin_enter(&sc->sc_lock); 942 943 /* 944 * Turn on DTR. We must always do this, even if carrier is not 945 * present, because otherwise we'd have to use TIOCSDTR 946 * immediately after setting CLOCAL, which applications do not 947 * expect. We always assert DTR while the device is open 948 * unless explicitly requested to deassert it. 949 */ 950 com_modem(sc, 1); 951 952 /* Clear the input ring, and unblock. */ 953 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 954 sc->sc_rbavail = com_rbuf_size; 955 com_iflush(sc); 956 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 957 com_hwiflow(sc); 958 959 #ifdef COM_DEBUG 960 if (com_debug) 961 comstatus(sc, "comopen "); 962 #endif 963 964 mutex_spin_exit(&sc->sc_lock); 965 } 966 967 splx(s); 968 969 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 970 if (error) 971 goto bad; 972 973 error = (*tp->t_linesw->l_open)(dev, tp); 974 if (error) 975 goto bad; 976 977 return (0); 978 979 bad: 980 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 981 /* 982 * We failed to open the device, and nobody else had it opened. 983 * Clean up the state as appropriate. 984 */ 985 com_shutdown(sc); 986 } 987 988 return (error); 989 } 990 991 int 992 comclose(dev_t dev, int flag, int mode, struct lwp *l) 993 { 994 struct com_softc *sc = 995 device_lookup_private(&com_cd, COMUNIT(dev)); 996 struct tty *tp = sc->sc_tty; 997 998 /* XXX This is for cons.c. */ 999 if (!ISSET(tp->t_state, TS_ISOPEN)) 1000 return (0); 1001 1002 (*tp->t_linesw->l_close)(tp, flag); 1003 ttyclose(tp); 1004 1005 if (COM_ISALIVE(sc) == 0) 1006 return (0); 1007 1008 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1009 /* 1010 * Although we got a last close, the device may still be in 1011 * use; e.g. if this was the dialout node, and there are still 1012 * processes waiting for carrier on the non-dialout node. 1013 */ 1014 com_shutdown(sc); 1015 } 1016 1017 return (0); 1018 } 1019 1020 int 1021 comread(dev_t dev, struct uio *uio, int flag) 1022 { 1023 struct com_softc *sc = 1024 device_lookup_private(&com_cd, COMUNIT(dev)); 1025 struct tty *tp = sc->sc_tty; 1026 1027 if (COM_ISALIVE(sc) == 0) 1028 return (EIO); 1029 1030 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1031 } 1032 1033 int 1034 comwrite(dev_t dev, struct uio *uio, int flag) 1035 { 1036 struct com_softc *sc = 1037 device_lookup_private(&com_cd, COMUNIT(dev)); 1038 struct tty *tp = sc->sc_tty; 1039 1040 if (COM_ISALIVE(sc) == 0) 1041 return (EIO); 1042 1043 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1044 } 1045 1046 int 1047 compoll(dev_t dev, int events, struct lwp *l) 1048 { 1049 struct com_softc *sc = 1050 device_lookup_private(&com_cd, COMUNIT(dev)); 1051 struct tty *tp = sc->sc_tty; 1052 1053 if (COM_ISALIVE(sc) == 0) 1054 return (POLLHUP); 1055 1056 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1057 } 1058 1059 struct tty * 1060 comtty(dev_t dev) 1061 { 1062 struct com_softc *sc = 1063 device_lookup_private(&com_cd, COMUNIT(dev)); 1064 struct tty *tp = sc->sc_tty; 1065 1066 return (tp); 1067 } 1068 1069 int 1070 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1071 { 1072 struct com_softc *sc; 1073 struct tty *tp; 1074 int error; 1075 1076 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1077 if (sc == NULL) 1078 return ENXIO; 1079 if (COM_ISALIVE(sc) == 0) 1080 return (EIO); 1081 1082 tp = sc->sc_tty; 1083 1084 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1085 if (error != EPASSTHROUGH) 1086 return (error); 1087 1088 error = ttioctl(tp, cmd, data, flag, l); 1089 if (error != EPASSTHROUGH) 1090 return (error); 1091 1092 error = 0; 1093 switch (cmd) { 1094 case TIOCSFLAGS: 1095 error = kauth_authorize_device_tty(l->l_cred, 1096 KAUTH_DEVICE_TTY_PRIVSET, tp); 1097 break; 1098 default: 1099 /* nothing */ 1100 break; 1101 } 1102 if (error) { 1103 return error; 1104 } 1105 1106 mutex_spin_enter(&sc->sc_lock); 1107 1108 switch (cmd) { 1109 case TIOCSBRK: 1110 com_break(sc, 1); 1111 break; 1112 1113 case TIOCCBRK: 1114 com_break(sc, 0); 1115 break; 1116 1117 case TIOCSDTR: 1118 com_modem(sc, 1); 1119 break; 1120 1121 case TIOCCDTR: 1122 com_modem(sc, 0); 1123 break; 1124 1125 case TIOCGFLAGS: 1126 *(int *)data = sc->sc_swflags; 1127 break; 1128 1129 case TIOCSFLAGS: 1130 sc->sc_swflags = *(int *)data; 1131 break; 1132 1133 case TIOCMSET: 1134 case TIOCMBIS: 1135 case TIOCMBIC: 1136 tiocm_to_com(sc, cmd, *(int *)data); 1137 break; 1138 1139 case TIOCMGET: 1140 *(int *)data = com_to_tiocm(sc); 1141 break; 1142 1143 case PPS_IOC_CREATE: 1144 case PPS_IOC_DESTROY: 1145 case PPS_IOC_GETPARAMS: 1146 case PPS_IOC_SETPARAMS: 1147 case PPS_IOC_GETCAP: 1148 case PPS_IOC_FETCH: 1149 #ifdef PPS_SYNC 1150 case PPS_IOC_KCBIND: 1151 #endif 1152 mutex_spin_enter(&timecounter_lock); 1153 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1154 mutex_spin_exit(&timecounter_lock); 1155 break; 1156 1157 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1158 mutex_spin_enter(&timecounter_lock); 1159 #ifndef PPS_TRAILING_EDGE 1160 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1161 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1162 #else 1163 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1164 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1165 #endif 1166 mutex_spin_exit(&timecounter_lock); 1167 break; 1168 1169 default: 1170 error = EPASSTHROUGH; 1171 break; 1172 } 1173 1174 mutex_spin_exit(&sc->sc_lock); 1175 1176 #ifdef COM_DEBUG 1177 if (com_debug) 1178 comstatus(sc, "comioctl "); 1179 #endif 1180 1181 return (error); 1182 } 1183 1184 integrate void 1185 com_schedrx(struct com_softc *sc) 1186 { 1187 1188 sc->sc_rx_ready = 1; 1189 1190 /* Wake up the poller. */ 1191 softint_schedule(sc->sc_si); 1192 } 1193 1194 void 1195 com_break(struct com_softc *sc, int onoff) 1196 { 1197 1198 if (onoff) 1199 SET(sc->sc_lcr, LCR_SBREAK); 1200 else 1201 CLR(sc->sc_lcr, LCR_SBREAK); 1202 1203 if (!sc->sc_heldchange) { 1204 if (sc->sc_tx_busy) { 1205 sc->sc_heldtbc = sc->sc_tbc; 1206 sc->sc_tbc = 0; 1207 sc->sc_heldchange = 1; 1208 } else 1209 com_loadchannelregs(sc); 1210 } 1211 } 1212 1213 void 1214 com_modem(struct com_softc *sc, int onoff) 1215 { 1216 1217 if (sc->sc_mcr_dtr == 0) 1218 return; 1219 1220 if (onoff) 1221 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1222 else 1223 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1224 1225 if (!sc->sc_heldchange) { 1226 if (sc->sc_tx_busy) { 1227 sc->sc_heldtbc = sc->sc_tbc; 1228 sc->sc_tbc = 0; 1229 sc->sc_heldchange = 1; 1230 } else 1231 com_loadchannelregs(sc); 1232 } 1233 } 1234 1235 void 1236 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1237 { 1238 u_char combits; 1239 1240 combits = 0; 1241 if (ISSET(ttybits, TIOCM_DTR)) 1242 SET(combits, MCR_DTR); 1243 if (ISSET(ttybits, TIOCM_RTS)) 1244 SET(combits, MCR_RTS); 1245 1246 switch (how) { 1247 case TIOCMBIC: 1248 CLR(sc->sc_mcr, combits); 1249 break; 1250 1251 case TIOCMBIS: 1252 SET(sc->sc_mcr, combits); 1253 break; 1254 1255 case TIOCMSET: 1256 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1257 SET(sc->sc_mcr, combits); 1258 break; 1259 } 1260 1261 if (!sc->sc_heldchange) { 1262 if (sc->sc_tx_busy) { 1263 sc->sc_heldtbc = sc->sc_tbc; 1264 sc->sc_tbc = 0; 1265 sc->sc_heldchange = 1; 1266 } else 1267 com_loadchannelregs(sc); 1268 } 1269 } 1270 1271 int 1272 com_to_tiocm(struct com_softc *sc) 1273 { 1274 u_char combits; 1275 int ttybits = 0; 1276 1277 combits = sc->sc_mcr; 1278 if (ISSET(combits, MCR_DTR)) 1279 SET(ttybits, TIOCM_DTR); 1280 if (ISSET(combits, MCR_RTS)) 1281 SET(ttybits, TIOCM_RTS); 1282 1283 combits = sc->sc_msr; 1284 if (sc->sc_type == COM_TYPE_INGENIC) { 1285 SET(ttybits, TIOCM_CD); 1286 } else { 1287 if (ISSET(combits, MSR_DCD)) 1288 SET(ttybits, TIOCM_CD); 1289 } 1290 if (ISSET(combits, MSR_CTS)) 1291 SET(ttybits, TIOCM_CTS); 1292 if (ISSET(combits, MSR_DSR)) 1293 SET(ttybits, TIOCM_DSR); 1294 if (ISSET(combits, MSR_RI | MSR_TERI)) 1295 SET(ttybits, TIOCM_RI); 1296 1297 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1298 SET(ttybits, TIOCM_LE); 1299 1300 return (ttybits); 1301 } 1302 1303 static u_char 1304 cflag2lcr(tcflag_t cflag) 1305 { 1306 u_char lcr = 0; 1307 1308 switch (ISSET(cflag, CSIZE)) { 1309 case CS5: 1310 SET(lcr, LCR_5BITS); 1311 break; 1312 case CS6: 1313 SET(lcr, LCR_6BITS); 1314 break; 1315 case CS7: 1316 SET(lcr, LCR_7BITS); 1317 break; 1318 case CS8: 1319 SET(lcr, LCR_8BITS); 1320 break; 1321 } 1322 if (ISSET(cflag, PARENB)) { 1323 SET(lcr, LCR_PENAB); 1324 if (!ISSET(cflag, PARODD)) 1325 SET(lcr, LCR_PEVEN); 1326 } 1327 if (ISSET(cflag, CSTOPB)) 1328 SET(lcr, LCR_STOPB); 1329 1330 return (lcr); 1331 } 1332 1333 int 1334 comparam(struct tty *tp, struct termios *t) 1335 { 1336 struct com_softc *sc = 1337 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1338 int ospeed; 1339 u_char lcr; 1340 1341 if (COM_ISALIVE(sc) == 0) 1342 return (EIO); 1343 1344 #ifdef COM_HAYESP 1345 if (sc->sc_type == COM_TYPE_HAYESP) { 1346 int prescaler, speed; 1347 1348 /* 1349 * Calculate UART clock prescaler. It should be in 1350 * range of 0 .. 3. 1351 */ 1352 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1353 prescaler++, speed /= 2) 1354 if ((ospeed = comspeed(speed, sc->sc_frequency, 1355 sc->sc_type)) > 0) 1356 break; 1357 1358 if (prescaler == 4) 1359 return (EINVAL); 1360 sc->sc_prescaler = prescaler; 1361 } else 1362 #endif 1363 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1364 1365 /* Check requested parameters. */ 1366 if (ospeed < 0) 1367 return (EINVAL); 1368 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1369 return (EINVAL); 1370 1371 /* 1372 * For the console, always force CLOCAL and !HUPCL, so that the port 1373 * is always active. 1374 */ 1375 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1376 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1377 SET(t->c_cflag, CLOCAL); 1378 CLR(t->c_cflag, HUPCL); 1379 } 1380 1381 /* 1382 * If there were no changes, don't do anything. This avoids dropping 1383 * input and improves performance when all we did was frob things like 1384 * VMIN and VTIME. 1385 */ 1386 if (tp->t_ospeed == t->c_ospeed && 1387 tp->t_cflag == t->c_cflag) 1388 return (0); 1389 1390 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1391 1392 mutex_spin_enter(&sc->sc_lock); 1393 1394 sc->sc_lcr = lcr; 1395 1396 /* 1397 * If we're not in a mode that assumes a connection is present, then 1398 * ignore carrier changes. 1399 */ 1400 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1401 sc->sc_msr_dcd = 0; 1402 else 1403 sc->sc_msr_dcd = MSR_DCD; 1404 /* 1405 * Set the flow control pins depending on the current flow control 1406 * mode. 1407 */ 1408 if (ISSET(t->c_cflag, CRTSCTS)) { 1409 sc->sc_mcr_dtr = MCR_DTR; 1410 sc->sc_mcr_rts = MCR_RTS; 1411 sc->sc_msr_cts = MSR_CTS; 1412 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1413 SET(sc->sc_mcr, MCR_AFE); 1414 } else { 1415 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1416 } 1417 } else if (ISSET(t->c_cflag, MDMBUF)) { 1418 /* 1419 * For DTR/DCD flow control, make sure we don't toggle DTR for 1420 * carrier detection. 1421 */ 1422 sc->sc_mcr_dtr = 0; 1423 sc->sc_mcr_rts = MCR_DTR; 1424 sc->sc_msr_cts = MSR_DCD; 1425 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1426 CLR(sc->sc_mcr, MCR_AFE); 1427 } else { 1428 sc->sc_efr = 0; 1429 } 1430 } else { 1431 /* 1432 * If no flow control, then always set RTS. This will make 1433 * the other side happy if it mistakenly thinks we're doing 1434 * RTS/CTS flow control. 1435 */ 1436 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1437 sc->sc_mcr_rts = 0; 1438 sc->sc_msr_cts = 0; 1439 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1440 CLR(sc->sc_mcr, MCR_AFE); 1441 } else { 1442 sc->sc_efr = 0; 1443 } 1444 if (ISSET(sc->sc_mcr, MCR_DTR)) 1445 SET(sc->sc_mcr, MCR_RTS); 1446 else 1447 CLR(sc->sc_mcr, MCR_RTS); 1448 } 1449 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1450 1451 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1452 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1453 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1454 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1455 1456 sc->sc_dlbl = ospeed; 1457 sc->sc_dlbh = ospeed >> 8; 1458 1459 /* 1460 * Set the FIFO threshold based on the receive speed. 1461 * 1462 * * If it's a low speed, it's probably a mouse or some other 1463 * interactive device, so set the threshold low. 1464 * * If it's a high speed, trim the trigger level down to prevent 1465 * overflows. 1466 * * Otherwise set it a bit higher. 1467 */ 1468 if (sc->sc_type == COM_TYPE_HAYESP) 1469 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1470 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1471 if (t->c_ospeed <= 1200) 1472 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1473 else if (t->c_ospeed <= 38400) 1474 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1475 else 1476 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1477 } else 1478 sc->sc_fifo = 0; 1479 1480 if (sc->sc_type == COM_TYPE_INGENIC) 1481 sc->sc_fifo |= FIFO_UART_ON; 1482 1483 /* And copy to tty. */ 1484 tp->t_ispeed = t->c_ospeed; 1485 tp->t_ospeed = t->c_ospeed; 1486 tp->t_cflag = t->c_cflag; 1487 1488 if (!sc->sc_heldchange) { 1489 if (sc->sc_tx_busy) { 1490 sc->sc_heldtbc = sc->sc_tbc; 1491 sc->sc_tbc = 0; 1492 sc->sc_heldchange = 1; 1493 } else 1494 com_loadchannelregs(sc); 1495 } 1496 1497 if (!ISSET(t->c_cflag, CHWFLOW)) { 1498 /* Disable the high water mark. */ 1499 sc->sc_r_hiwat = 0; 1500 sc->sc_r_lowat = 0; 1501 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1502 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1503 com_schedrx(sc); 1504 } 1505 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1506 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1507 com_hwiflow(sc); 1508 } 1509 } else { 1510 sc->sc_r_hiwat = com_rbuf_hiwat; 1511 sc->sc_r_lowat = com_rbuf_lowat; 1512 } 1513 1514 mutex_spin_exit(&sc->sc_lock); 1515 1516 /* 1517 * Update the tty layer's idea of the carrier bit, in case we changed 1518 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1519 * explicit request. 1520 */ 1521 if (sc->sc_type == COM_TYPE_INGENIC) { 1522 /* no DCD here */ 1523 (void) (*tp->t_linesw->l_modem)(tp, 1); 1524 } else 1525 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1526 1527 #ifdef COM_DEBUG 1528 if (com_debug) 1529 comstatus(sc, "comparam "); 1530 #endif 1531 1532 if (!ISSET(t->c_cflag, CHWFLOW)) { 1533 if (sc->sc_tx_stopped) { 1534 sc->sc_tx_stopped = 0; 1535 comstart(tp); 1536 } 1537 } 1538 1539 return (0); 1540 } 1541 1542 void 1543 com_iflush(struct com_softc *sc) 1544 { 1545 struct com_regs *regsp = &sc->sc_regs; 1546 #ifdef DIAGNOSTIC 1547 int reg; 1548 #endif 1549 int timo; 1550 1551 #ifdef DIAGNOSTIC 1552 reg = 0xffff; 1553 #endif 1554 timo = 50000; 1555 /* flush any pending I/O */ 1556 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1557 && --timo) 1558 #ifdef DIAGNOSTIC 1559 reg = 1560 #else 1561 (void) 1562 #endif 1563 CSR_READ_1(regsp, COM_REG_RXDATA); 1564 #ifdef DIAGNOSTIC 1565 if (!timo) 1566 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1567 #endif 1568 1569 #ifdef COM_16750 1570 uint8_t fifo; 1571 /* 1572 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1573 * This should prevent triggering busy interrupt while 1574 * manipulating divisors. 1575 */ 1576 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1577 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1578 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1579 FIFO_XMT_RST); 1580 delay(100); 1581 #endif 1582 } 1583 1584 void 1585 com_loadchannelregs(struct com_softc *sc) 1586 { 1587 struct com_regs *regsp = &sc->sc_regs; 1588 1589 /* XXXXX necessary? */ 1590 com_iflush(sc); 1591 1592 if (sc->sc_type == COM_TYPE_PXA2x0) 1593 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1594 else 1595 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1596 1597 if (sc->sc_type == COM_TYPE_OMAP) { 1598 /* disable before changing settings */ 1599 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1600 } 1601 1602 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1603 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1604 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1605 /* no EFR on alchemy */ 1606 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1607 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1608 } 1609 if (sc->sc_type == COM_TYPE_AU1x00) { 1610 /* alchemy has single separate 16-bit clock divisor register */ 1611 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1612 (sc->sc_dlbh << 8)); 1613 } else { 1614 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1615 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1616 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1617 } 1618 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1619 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1620 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1621 #ifdef COM_HAYESP 1622 if (sc->sc_type == COM_TYPE_HAYESP) { 1623 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1624 HAYESP_SETPRESCALER); 1625 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1626 sc->sc_prescaler); 1627 } 1628 #endif 1629 if (sc->sc_type == COM_TYPE_OMAP) { 1630 /* setup the fifos. the FCR value is not used as long 1631 as SCR[6] and SCR[7] are 0, which they are at reset 1632 and we never touch the SCR register */ 1633 uint8_t rx_fifo_trig = 40; 1634 uint8_t tx_fifo_trig = 60; 1635 uint8_t rx_start = 8; 1636 uint8_t rx_halt = 60; 1637 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1638 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1639 1640 /* enable access to TCR & TLR */ 1641 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1642 1643 /* write tcr and tlr values */ 1644 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1645 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1646 1647 /* disable access to TCR & TLR */ 1648 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1649 1650 /* enable again, but mode is based on speed */ 1651 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1652 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1653 } else { 1654 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1655 } 1656 } 1657 1658 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1659 } 1660 1661 int 1662 comhwiflow(struct tty *tp, int block) 1663 { 1664 struct com_softc *sc = 1665 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1666 1667 if (COM_ISALIVE(sc) == 0) 1668 return (0); 1669 1670 if (sc->sc_mcr_rts == 0) 1671 return (0); 1672 1673 mutex_spin_enter(&sc->sc_lock); 1674 1675 if (block) { 1676 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1677 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1678 com_hwiflow(sc); 1679 } 1680 } else { 1681 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1682 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1683 com_schedrx(sc); 1684 } 1685 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1686 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1687 com_hwiflow(sc); 1688 } 1689 } 1690 1691 mutex_spin_exit(&sc->sc_lock); 1692 return (1); 1693 } 1694 1695 /* 1696 * (un)block input via hw flowcontrol 1697 */ 1698 void 1699 com_hwiflow(struct com_softc *sc) 1700 { 1701 struct com_regs *regsp= &sc->sc_regs; 1702 1703 if (sc->sc_mcr_rts == 0) 1704 return; 1705 1706 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1707 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1708 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1709 } else { 1710 SET(sc->sc_mcr, sc->sc_mcr_rts); 1711 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1712 } 1713 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1714 } 1715 1716 1717 void 1718 comstart(struct tty *tp) 1719 { 1720 struct com_softc *sc = 1721 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1722 struct com_regs *regsp = &sc->sc_regs; 1723 int s; 1724 1725 if (COM_ISALIVE(sc) == 0) 1726 return; 1727 1728 s = spltty(); 1729 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1730 goto out; 1731 if (sc->sc_tx_stopped) 1732 goto out; 1733 if (!ttypull(tp)) 1734 goto out; 1735 1736 /* Grab the first contiguous region of buffer space. */ 1737 { 1738 u_char *tba; 1739 int tbc; 1740 1741 tba = tp->t_outq.c_cf; 1742 tbc = ndqb(&tp->t_outq, 0); 1743 1744 mutex_spin_enter(&sc->sc_lock); 1745 1746 sc->sc_tba = tba; 1747 sc->sc_tbc = tbc; 1748 } 1749 1750 SET(tp->t_state, TS_BUSY); 1751 sc->sc_tx_busy = 1; 1752 1753 /* Enable transmit completion interrupts if necessary. */ 1754 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1755 SET(sc->sc_ier, IER_ETXRDY); 1756 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1757 } 1758 1759 /* Output the first chunk of the contiguous buffer. */ 1760 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1761 u_int n; 1762 1763 n = sc->sc_tbc; 1764 if (n > sc->sc_fifolen) 1765 n = sc->sc_fifolen; 1766 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1767 sc->sc_tbc -= n; 1768 sc->sc_tba += n; 1769 } 1770 1771 mutex_spin_exit(&sc->sc_lock); 1772 out: 1773 splx(s); 1774 return; 1775 } 1776 1777 /* 1778 * Stop output on a line. 1779 */ 1780 void 1781 comstop(struct tty *tp, int flag) 1782 { 1783 struct com_softc *sc = 1784 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1785 1786 mutex_spin_enter(&sc->sc_lock); 1787 if (ISSET(tp->t_state, TS_BUSY)) { 1788 /* Stop transmitting at the next chunk. */ 1789 sc->sc_tbc = 0; 1790 sc->sc_heldtbc = 0; 1791 if (!ISSET(tp->t_state, TS_TTSTOP)) 1792 SET(tp->t_state, TS_FLUSH); 1793 } 1794 mutex_spin_exit(&sc->sc_lock); 1795 } 1796 1797 void 1798 comdiag(void *arg) 1799 { 1800 struct com_softc *sc = arg; 1801 int overflows, floods; 1802 1803 mutex_spin_enter(&sc->sc_lock); 1804 overflows = sc->sc_overflows; 1805 sc->sc_overflows = 0; 1806 floods = sc->sc_floods; 1807 sc->sc_floods = 0; 1808 sc->sc_errors = 0; 1809 mutex_spin_exit(&sc->sc_lock); 1810 1811 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1812 device_xname(sc->sc_dev), 1813 overflows, overflows == 1 ? "" : "s", 1814 floods, floods == 1 ? "" : "s"); 1815 } 1816 1817 integrate void 1818 com_rxsoft(struct com_softc *sc, struct tty *tp) 1819 { 1820 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1821 u_char *get, *end; 1822 u_int cc, scc; 1823 u_char lsr; 1824 int code; 1825 1826 end = sc->sc_ebuf; 1827 get = sc->sc_rbget; 1828 scc = cc = com_rbuf_size - sc->sc_rbavail; 1829 1830 if (cc == com_rbuf_size) { 1831 sc->sc_floods++; 1832 if (sc->sc_errors++ == 0) 1833 callout_reset(&sc->sc_diag_callout, 60 * hz, 1834 comdiag, sc); 1835 } 1836 1837 /* If not yet open, drop the entire buffer content here */ 1838 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1839 get += cc << 1; 1840 if (get >= end) 1841 get -= com_rbuf_size << 1; 1842 cc = 0; 1843 } 1844 while (cc) { 1845 code = get[0]; 1846 lsr = get[1]; 1847 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1848 if (ISSET(lsr, LSR_OE)) { 1849 sc->sc_overflows++; 1850 if (sc->sc_errors++ == 0) 1851 callout_reset(&sc->sc_diag_callout, 1852 60 * hz, comdiag, sc); 1853 } 1854 if (ISSET(lsr, LSR_BI | LSR_FE)) 1855 SET(code, TTY_FE); 1856 if (ISSET(lsr, LSR_PE)) 1857 SET(code, TTY_PE); 1858 } 1859 if ((*rint)(code, tp) == -1) { 1860 /* 1861 * The line discipline's buffer is out of space. 1862 */ 1863 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1864 /* 1865 * We're either not using flow control, or the 1866 * line discipline didn't tell us to block for 1867 * some reason. Either way, we have no way to 1868 * know when there's more space available, so 1869 * just drop the rest of the data. 1870 */ 1871 get += cc << 1; 1872 if (get >= end) 1873 get -= com_rbuf_size << 1; 1874 cc = 0; 1875 } else { 1876 /* 1877 * Don't schedule any more receive processing 1878 * until the line discipline tells us there's 1879 * space available (through comhwiflow()). 1880 * Leave the rest of the data in the input 1881 * buffer. 1882 */ 1883 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1884 } 1885 break; 1886 } 1887 get += 2; 1888 if (get >= end) 1889 get = sc->sc_rbuf; 1890 cc--; 1891 } 1892 1893 if (cc != scc) { 1894 sc->sc_rbget = get; 1895 mutex_spin_enter(&sc->sc_lock); 1896 1897 cc = sc->sc_rbavail += scc - cc; 1898 /* Buffers should be ok again, release possible block. */ 1899 if (cc >= sc->sc_r_lowat) { 1900 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1901 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1902 SET(sc->sc_ier, IER_ERXRDY); 1903 #ifdef COM_PXA2X0 1904 if (sc->sc_type == COM_TYPE_PXA2x0) 1905 SET(sc->sc_ier, IER_ERXTOUT); 1906 #endif 1907 if (sc->sc_type == COM_TYPE_INGENIC) 1908 sc->sc_ier |= IER_ERXTOUT; 1909 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1910 sc->sc_ier); 1911 } 1912 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1913 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1914 com_hwiflow(sc); 1915 } 1916 } 1917 mutex_spin_exit(&sc->sc_lock); 1918 } 1919 } 1920 1921 integrate void 1922 com_txsoft(struct com_softc *sc, struct tty *tp) 1923 { 1924 1925 CLR(tp->t_state, TS_BUSY); 1926 if (ISSET(tp->t_state, TS_FLUSH)) 1927 CLR(tp->t_state, TS_FLUSH); 1928 else 1929 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1930 (*tp->t_linesw->l_start)(tp); 1931 } 1932 1933 integrate void 1934 com_stsoft(struct com_softc *sc, struct tty *tp) 1935 { 1936 u_char msr, delta; 1937 1938 mutex_spin_enter(&sc->sc_lock); 1939 msr = sc->sc_msr; 1940 delta = sc->sc_msr_delta; 1941 sc->sc_msr_delta = 0; 1942 mutex_spin_exit(&sc->sc_lock); 1943 1944 if (ISSET(delta, sc->sc_msr_dcd)) { 1945 /* 1946 * Inform the tty layer that carrier detect changed. 1947 */ 1948 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1949 } 1950 1951 if (ISSET(delta, sc->sc_msr_cts)) { 1952 /* Block or unblock output according to flow control. */ 1953 if (ISSET(msr, sc->sc_msr_cts)) { 1954 sc->sc_tx_stopped = 0; 1955 (*tp->t_linesw->l_start)(tp); 1956 } else { 1957 sc->sc_tx_stopped = 1; 1958 } 1959 } 1960 1961 #ifdef COM_DEBUG 1962 if (com_debug) 1963 comstatus(sc, "com_stsoft"); 1964 #endif 1965 } 1966 1967 void 1968 comsoft(void *arg) 1969 { 1970 struct com_softc *sc = arg; 1971 struct tty *tp; 1972 1973 if (COM_ISALIVE(sc) == 0) 1974 return; 1975 1976 tp = sc->sc_tty; 1977 1978 if (sc->sc_rx_ready) { 1979 sc->sc_rx_ready = 0; 1980 com_rxsoft(sc, tp); 1981 } 1982 1983 if (sc->sc_st_check) { 1984 sc->sc_st_check = 0; 1985 com_stsoft(sc, tp); 1986 } 1987 1988 if (sc->sc_tx_done) { 1989 sc->sc_tx_done = 0; 1990 com_txsoft(sc, tp); 1991 } 1992 } 1993 1994 int 1995 comintr(void *arg) 1996 { 1997 struct com_softc *sc = arg; 1998 struct com_regs *regsp = &sc->sc_regs; 1999 2000 u_char *put, *end; 2001 u_int cc; 2002 u_char lsr, iir; 2003 2004 if (COM_ISALIVE(sc) == 0) 2005 return (0); 2006 2007 KASSERT(regsp != NULL); 2008 2009 mutex_spin_enter(&sc->sc_lock); 2010 iir = CSR_READ_1(regsp, COM_REG_IIR); 2011 2012 /* Handle ns16750-specific busy interrupt. */ 2013 #ifdef COM_16750 2014 int timeout; 2015 if ((iir & IIR_BUSY) == IIR_BUSY) { 2016 for (timeout = 10000; 2017 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2018 if (timeout <= 0) { 2019 aprint_error_dev(sc->sc_dev, 2020 "timeout while waiting for BUSY interrupt " 2021 "acknowledge\n"); 2022 mutex_spin_exit(&sc->sc_lock); 2023 return (0); 2024 } 2025 2026 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2027 iir = CSR_READ_1(regsp, COM_REG_IIR); 2028 } 2029 #endif /* COM_16750 */ 2030 2031 2032 if (ISSET(iir, IIR_NOPEND)) { 2033 mutex_spin_exit(&sc->sc_lock); 2034 return (0); 2035 } 2036 2037 end = sc->sc_ebuf; 2038 put = sc->sc_rbput; 2039 cc = sc->sc_rbavail; 2040 2041 again: do { 2042 u_char msr, delta; 2043 2044 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2045 if (ISSET(lsr, LSR_BI)) { 2046 int cn_trapped = 0; /* see above: cn_trap() */ 2047 2048 cn_check_magic(sc->sc_tty->t_dev, 2049 CNC_BREAK, com_cnm_state); 2050 if (cn_trapped) 2051 continue; 2052 #if defined(KGDB) && !defined(DDB) 2053 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2054 kgdb_connect(1); 2055 continue; 2056 } 2057 #endif 2058 } 2059 2060 if (ISSET(lsr, LSR_RCV_MASK) && 2061 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2062 while (cc > 0) { 2063 int cn_trapped = 0; 2064 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2065 put[1] = lsr; 2066 cn_check_magic(sc->sc_tty->t_dev, 2067 put[0], com_cnm_state); 2068 if (cn_trapped) 2069 goto next; 2070 put += 2; 2071 if (put >= end) 2072 put = sc->sc_rbuf; 2073 cc--; 2074 next: 2075 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2076 if (!ISSET(lsr, LSR_RCV_MASK)) 2077 break; 2078 } 2079 2080 /* 2081 * Current string of incoming characters ended because 2082 * no more data was available or we ran out of space. 2083 * Schedule a receive event if any data was received. 2084 * If we're out of space, turn off receive interrupts. 2085 */ 2086 sc->sc_rbput = put; 2087 sc->sc_rbavail = cc; 2088 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2089 sc->sc_rx_ready = 1; 2090 2091 /* 2092 * See if we are in danger of overflowing a buffer. If 2093 * so, use hardware flow control to ease the pressure. 2094 */ 2095 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2096 cc < sc->sc_r_hiwat) { 2097 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2098 com_hwiflow(sc); 2099 } 2100 2101 /* 2102 * If we're out of space, disable receive interrupts 2103 * until the queue has drained a bit. 2104 */ 2105 if (!cc) { 2106 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2107 #ifdef COM_PXA2X0 2108 if (sc->sc_type == COM_TYPE_PXA2x0) 2109 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2110 else 2111 #endif 2112 if (sc->sc_type == COM_TYPE_INGENIC) 2113 sc->sc_ier |= IER_ERXRDY|IER_ERXTOUT; 2114 else 2115 CLR(sc->sc_ier, IER_ERXRDY); 2116 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2117 } 2118 } else { 2119 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2120 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2121 continue; 2122 } 2123 } 2124 2125 msr = CSR_READ_1(regsp, COM_REG_MSR); 2126 delta = msr ^ sc->sc_msr; 2127 sc->sc_msr = msr; 2128 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2129 (delta & MSR_DCD)) { 2130 mutex_spin_enter(&timecounter_lock); 2131 pps_capture(&sc->sc_pps_state); 2132 pps_event(&sc->sc_pps_state, 2133 (msr & MSR_DCD) ? 2134 PPS_CAPTUREASSERT : 2135 PPS_CAPTURECLEAR); 2136 mutex_spin_exit(&timecounter_lock); 2137 } 2138 2139 /* 2140 * Process normal status changes 2141 */ 2142 if (ISSET(delta, sc->sc_msr_mask)) { 2143 SET(sc->sc_msr_delta, delta); 2144 2145 /* 2146 * Stop output immediately if we lose the output 2147 * flow control signal or carrier detect. 2148 */ 2149 if (ISSET(~msr, sc->sc_msr_mask)) { 2150 sc->sc_tbc = 0; 2151 sc->sc_heldtbc = 0; 2152 #ifdef COM_DEBUG 2153 if (com_debug) 2154 comstatus(sc, "comintr "); 2155 #endif 2156 } 2157 2158 sc->sc_st_check = 1; 2159 } 2160 } while (!ISSET((iir = 2161 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2162 /* 2163 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2164 * by IIR read, so we can't do this way: `process all interrupts, 2165 * then do TX if possible'. 2166 */ 2167 (iir & IIR_IMASK) != IIR_TXRDY); 2168 2169 /* 2170 * Read LSR again, since there may be an interrupt between 2171 * the last LSR read and IIR read above. 2172 */ 2173 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2174 2175 /* 2176 * See if data can be transmitted as well. 2177 * Schedule tx done event if no data left 2178 * and tty was marked busy. 2179 */ 2180 if (ISSET(lsr, LSR_TXRDY)) { 2181 /* 2182 * If we've delayed a parameter change, do it now, and restart 2183 * output. 2184 */ 2185 if (sc->sc_heldchange) { 2186 com_loadchannelregs(sc); 2187 sc->sc_heldchange = 0; 2188 sc->sc_tbc = sc->sc_heldtbc; 2189 sc->sc_heldtbc = 0; 2190 } 2191 2192 /* Output the next chunk of the contiguous buffer, if any. */ 2193 if (sc->sc_tbc > 0) { 2194 u_int n; 2195 2196 n = sc->sc_tbc; 2197 if (n > sc->sc_fifolen) 2198 n = sc->sc_fifolen; 2199 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2200 sc->sc_tbc -= n; 2201 sc->sc_tba += n; 2202 } else { 2203 /* Disable transmit completion interrupts if necessary. */ 2204 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2205 CLR(sc->sc_ier, IER_ETXRDY); 2206 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2207 } 2208 if (sc->sc_tx_busy) { 2209 sc->sc_tx_busy = 0; 2210 sc->sc_tx_done = 1; 2211 } 2212 } 2213 } 2214 2215 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2216 goto again; 2217 2218 mutex_spin_exit(&sc->sc_lock); 2219 2220 /* Wake up the poller. */ 2221 softint_schedule(sc->sc_si); 2222 2223 #ifdef RND_COM 2224 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2225 #endif 2226 2227 return (1); 2228 } 2229 2230 /* 2231 * The following functions are polled getc and putc routines, shared 2232 * by the console and kgdb glue. 2233 * 2234 * The read-ahead code is so that you can detect pending in-band 2235 * cn_magic in polled mode while doing output rather than having to 2236 * wait until the kernel decides it needs input. 2237 */ 2238 2239 #define MAX_READAHEAD 20 2240 static int com_readahead[MAX_READAHEAD]; 2241 static int com_readaheadcount = 0; 2242 2243 int 2244 com_common_getc(dev_t dev, struct com_regs *regsp) 2245 { 2246 int s = splserial(); 2247 u_char stat, c; 2248 2249 /* got a character from reading things earlier */ 2250 if (com_readaheadcount > 0) { 2251 int i; 2252 2253 c = com_readahead[0]; 2254 for (i = 1; i < com_readaheadcount; i++) { 2255 com_readahead[i-1] = com_readahead[i]; 2256 } 2257 com_readaheadcount--; 2258 splx(s); 2259 return (c); 2260 } 2261 2262 /* don't block until a character becomes available */ 2263 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2264 splx(s); 2265 return -1; 2266 } 2267 2268 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2269 stat = CSR_READ_1(regsp, COM_REG_IIR); 2270 { 2271 int cn_trapped = 0; /* required by cn_trap, see above */ 2272 #ifdef DDB 2273 extern int db_active; 2274 if (!db_active) 2275 #endif 2276 cn_check_magic(dev, c, com_cnm_state); 2277 } 2278 splx(s); 2279 return (c); 2280 } 2281 2282 static void 2283 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2284 { 2285 int s = splserial(); 2286 int cin, stat, timo; 2287 2288 if (com_readaheadcount < MAX_READAHEAD 2289 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2290 int cn_trapped = 0; 2291 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2292 stat = CSR_READ_1(regsp, COM_REG_IIR); 2293 cn_check_magic(dev, cin, com_cnm_state); 2294 com_readahead[com_readaheadcount++] = cin; 2295 } 2296 2297 /* wait for any pending transmission to finish */ 2298 timo = 150000; 2299 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2300 continue; 2301 2302 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2303 COM_BARRIER(regsp, BR | BW); 2304 2305 splx(s); 2306 } 2307 2308 /* 2309 * Initialize UART for use as console or KGDB line. 2310 */ 2311 int 2312 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2313 tcflag_t cflag) 2314 { 2315 2316 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2317 ®sp->cr_ioh)) 2318 return (ENOMEM); /* ??? */ 2319 2320 if (type == COM_TYPE_OMAP) { 2321 /* disable before changing settings */ 2322 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2323 } 2324 2325 rate = comspeed(rate, frequency, type); 2326 if (__predict_true(rate != -1)) { 2327 if (type == COM_TYPE_AU1x00) { 2328 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2329 } else { 2330 /* no EFR on alchemy */ 2331 if ((type != COM_TYPE_16550_NOERS) && 2332 (type != COM_TYPE_INGENIC)) { 2333 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2334 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2335 } 2336 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2337 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2338 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2339 } 2340 } 2341 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2342 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2343 2344 if (type == COM_TYPE_INGENIC) { 2345 CSR_WRITE_1(regsp, COM_REG_FIFO, 2346 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2347 FIFO_TRIGGER_1 | FIFO_UART_ON); 2348 } else { 2349 CSR_WRITE_1(regsp, COM_REG_FIFO, 2350 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2351 FIFO_TRIGGER_1); 2352 } 2353 2354 if (type == COM_TYPE_OMAP) { 2355 /* setup the fifos. the FCR value is not used as long 2356 as SCR[6] and SCR[7] are 0, which they are at reset 2357 and we never touch the SCR register */ 2358 uint8_t rx_fifo_trig = 40; 2359 uint8_t tx_fifo_trig = 60; 2360 uint8_t rx_start = 8; 2361 uint8_t rx_halt = 60; 2362 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2363 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2364 2365 /* enable access to TCR & TLR */ 2366 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2367 2368 /* write tcr and tlr values */ 2369 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2370 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2371 2372 /* disable access to TCR & TLR */ 2373 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2374 2375 /* enable again, but mode is based on speed */ 2376 if (rate > 230400) { 2377 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2378 } else { 2379 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2380 } 2381 } 2382 2383 #ifdef COM_PXA2X0 2384 if (type == COM_TYPE_PXA2x0) 2385 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2386 else 2387 #endif 2388 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2389 2390 return (0); 2391 } 2392 2393 int 2394 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2395 tcflag_t cflag) 2396 { 2397 int res; 2398 2399 comcons_info.regs = *regsp; 2400 2401 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2402 if (res) 2403 return (res); 2404 2405 cn_tab = &comcons; 2406 cn_init_magic(&com_cnm_state); 2407 cn_set_magic("\047\001"); /* default magic is BREAK */ 2408 2409 comcons_info.frequency = frequency; 2410 comcons_info.type = type; 2411 comcons_info.rate = rate; 2412 comcons_info.cflag = cflag; 2413 2414 return (0); 2415 } 2416 2417 int 2418 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2419 int type, tcflag_t cflag) 2420 { 2421 struct com_regs regs; 2422 2423 memset(®s, 0, sizeof regs); 2424 regs.cr_iot = iot; 2425 regs.cr_iobase = iobase; 2426 regs.cr_nports = COM_NPORTS; 2427 #ifdef COM_REGMAP 2428 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2429 #endif 2430 2431 return comcnattach1(®s, rate, frequency, type, cflag); 2432 } 2433 2434 static int 2435 comcnreattach(void) 2436 { 2437 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2438 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2439 } 2440 2441 int 2442 comcngetc(dev_t dev) 2443 { 2444 2445 return (com_common_getc(dev, &comcons_info.regs)); 2446 } 2447 2448 /* 2449 * Console kernel output character routine. 2450 */ 2451 void 2452 comcnputc(dev_t dev, int c) 2453 { 2454 2455 com_common_putc(dev, &comcons_info.regs, c); 2456 } 2457 2458 void 2459 comcnpollc(dev_t dev, int on) 2460 { 2461 2462 com_readaheadcount = 0; 2463 } 2464 2465 #ifdef KGDB 2466 int 2467 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2468 tcflag_t cflag) 2469 { 2470 int res; 2471 2472 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2473 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2474 #if !defined(DDB) 2475 return (EBUSY); /* cannot share with console */ 2476 #else 2477 comkgdbregs = *regsp; 2478 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2479 #endif 2480 } else { 2481 comkgdbregs = *regsp; 2482 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2483 if (res) 2484 return (res); 2485 2486 /* 2487 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2488 * expects this to be initialized 2489 */ 2490 cn_init_magic(&com_cnm_state); 2491 cn_set_magic("\047\001"); 2492 } 2493 2494 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2495 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2496 2497 return (0); 2498 } 2499 2500 int 2501 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2502 int frequency, int type, tcflag_t cflag) 2503 { 2504 struct com_regs regs; 2505 2506 regs.cr_iot = iot; 2507 regs.cr_nports = COM_NPORTS; 2508 regs.cr_iobase = iobase; 2509 #ifdef COM_REGMAP 2510 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2511 #endif 2512 2513 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2514 } 2515 2516 /* ARGSUSED */ 2517 int 2518 com_kgdb_getc(void *arg) 2519 { 2520 2521 return (com_common_getc(NODEV, &comkgdbregs)); 2522 } 2523 2524 /* ARGSUSED */ 2525 void 2526 com_kgdb_putc(void *arg, int c) 2527 { 2528 2529 com_common_putc(NODEV, &comkgdbregs, c); 2530 } 2531 #endif /* KGDB */ 2532 2533 /* helper function to identify the com ports used by 2534 console or KGDB (and not yet autoconf attached) */ 2535 int 2536 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2537 { 2538 bus_space_handle_t help; 2539 2540 if (!comconsattached && 2541 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2542 iobase == comcons_info.regs.cr_iobase) 2543 help = comcons_info.regs.cr_ioh; 2544 #ifdef KGDB 2545 else if (!com_kgdb_attached && 2546 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2547 iobase == comkgdbregs.cr_iobase) 2548 help = comkgdbregs.cr_ioh; 2549 #endif 2550 else 2551 return (0); 2552 2553 if (ioh) 2554 *ioh = help; 2555 return (1); 2556 } 2557 2558 /* 2559 * this routine exists to serve as a shutdown hook for systems that 2560 * have firmware which doesn't interact properly with a com device in 2561 * FIFO mode. 2562 */ 2563 bool 2564 com_cleanup(device_t self, int how) 2565 { 2566 struct com_softc *sc = device_private(self); 2567 2568 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2569 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2570 2571 return true; 2572 } 2573 2574 bool 2575 com_suspend(device_t self, const pmf_qual_t *qual) 2576 { 2577 struct com_softc *sc = device_private(self); 2578 2579 #if 0 2580 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2581 cn_tab = &comcons_suspend; 2582 #endif 2583 2584 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2585 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2586 2587 return true; 2588 } 2589 2590 bool 2591 com_resume(device_t self, const pmf_qual_t *qual) 2592 { 2593 struct com_softc *sc = device_private(self); 2594 2595 mutex_spin_enter(&sc->sc_lock); 2596 com_loadchannelregs(sc); 2597 mutex_spin_exit(&sc->sc_lock); 2598 2599 return true; 2600 } 2601