1 /* $NetBSD: com.c,v 1.296 2010/03/22 23:00:08 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.296 2010/03/22 23:00:08 dyoung Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/conf.h> 108 #include <sys/file.h> 109 #include <sys/uio.h> 110 #include <sys/kernel.h> 111 #include <sys/syslog.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/timepps.h> 115 #include <sys/vnode.h> 116 #include <sys/kauth.h> 117 #include <sys/intr.h> 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #ifdef COM_HAYESP 126 #include <dev/ic/hayespreg.h> 127 #endif 128 #define com_lcr com_cfcr 129 #include <dev/cons.h> 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 extern struct cfdriver com_cd; 194 195 dev_type_open(comopen); 196 dev_type_close(comclose); 197 dev_type_read(comread); 198 dev_type_write(comwrite); 199 dev_type_ioctl(comioctl); 200 dev_type_stop(comstop); 201 dev_type_tty(comtty); 202 dev_type_poll(compoll); 203 204 static struct comcons_info comcons_info; 205 206 /* 207 * Following are all routines needed for COM to act as console 208 */ 209 static struct consdev comcons = { 210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 211 NODEV, CN_NORMAL 212 }; 213 214 215 const struct cdevsw com_cdevsw = { 216 comopen, comclose, comread, comwrite, comioctl, 217 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 218 }; 219 220 /* 221 * Make this an option variable one can patch. 222 * But be warned: this must be a power of 2! 223 */ 224 u_int com_rbuf_size = COM_RING_SIZE; 225 226 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 227 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 228 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 229 230 static int comconsattached; 231 static struct cnm_state com_cnm_state; 232 233 #ifdef KGDB 234 #include <sys/kgdb.h> 235 236 static struct com_regs comkgdbregs; 237 static int com_kgdb_attached; 238 239 int com_kgdb_getc(void *); 240 void com_kgdb_putc(void *, int); 241 #endif /* KGDB */ 242 243 #ifdef COM_REGMAP 244 /* initializer for typical 16550-ish hardware */ 245 #define COM_REG_16550 { \ 246 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 247 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 248 249 const bus_size_t com_std_map[16] = COM_REG_16550; 250 #endif /* COM_REGMAP */ 251 252 #define COMUNIT_MASK 0x7ffff 253 #define COMDIALOUT_MASK 0x80000 254 255 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 256 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 257 258 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 259 device_is_active((sc)->sc_dev)) 260 261 #define BR BUS_SPACE_BARRIER_READ 262 #define BW BUS_SPACE_BARRIER_WRITE 263 #define COM_BARRIER(r, f) \ 264 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 265 266 /* XXX Comparing bus_space_tag_t's is not allowed! */ 267 static bool 268 tags_are_equal(const bus_space_tag_t lt, const bus_space_tag_t rt) 269 { 270 return true; 271 } 272 273 /*ARGSUSED*/ 274 int 275 comspeed(long speed, long frequency, int type) 276 { 277 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 278 279 int x, err; 280 int divisor = 16; 281 282 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 283 divisor = 13; 284 } 285 286 #if 0 287 if (speed == 0) 288 return (0); 289 #endif 290 if (speed <= 0) 291 return (-1); 292 x = divrnd(frequency / divisor, speed); 293 if (x <= 0) 294 return (-1); 295 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 296 if (err < 0) 297 err = -err; 298 if (err > COM_TOLERANCE) 299 return (-1); 300 return (x); 301 302 #undef divrnd 303 } 304 305 #ifdef COM_DEBUG 306 int com_debug = 0; 307 308 void comstatus(struct com_softc *, const char *); 309 void 310 comstatus(struct com_softc *sc, const char *str) 311 { 312 struct tty *tp = sc->sc_tty; 313 314 aprint_normal_dev(sc->sc_dev, 315 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 316 str, 317 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 318 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 319 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 320 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 321 sc->sc_tx_stopped ? '+' : '-'); 322 323 aprint_normal_dev(sc->sc_dev, 324 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 325 str, 326 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 327 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 328 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 329 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 330 sc->sc_rx_flags); 331 } 332 #endif 333 334 int 335 com_probe_subr(struct com_regs *regs) 336 { 337 338 /* force access to id reg */ 339 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 340 CSR_WRITE_1(regs, COM_REG_IIR, 0); 341 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 342 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 343 return (0); 344 345 return (1); 346 } 347 348 int 349 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 350 { 351 struct com_regs regs; 352 353 regs.cr_iot = iot; 354 regs.cr_ioh = ioh; 355 #ifdef COM_REGMAP 356 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 357 #endif 358 359 return com_probe_subr(®s); 360 } 361 362 /* 363 * No locking in this routine; it is only called during attach, 364 * or with the port already locked. 365 */ 366 static void 367 com_enable_debugport(struct com_softc *sc) 368 { 369 370 /* Turn on line break interrupt, set carrier. */ 371 sc->sc_ier = IER_ERXRDY; 372 if (sc->sc_type == COM_TYPE_PXA2x0) 373 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 374 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 375 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 376 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 377 } 378 379 void 380 com_attach_subr(struct com_softc *sc) 381 { 382 struct com_regs *regsp = &sc->sc_regs; 383 struct tty *tp; 384 #ifdef COM_16650 385 u_int8_t lcr; 386 #endif 387 const char *fifo_msg = NULL; 388 389 aprint_naive("\n"); 390 391 callout_init(&sc->sc_diag_callout, 0); 392 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 393 394 /* Disable interrupts before configuring the device. */ 395 if (sc->sc_type == COM_TYPE_PXA2x0) 396 sc->sc_ier = IER_EUART; 397 else 398 sc->sc_ier = 0; 399 400 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 401 402 if (tags_are_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 403 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 404 comconsattached = 1; 405 406 if (cn_tab == NULL && comcnreattach() != 0) { 407 printf("can't re-init serial console @%lx\n", 408 (u_long)comcons_info.regs.cr_iobase); 409 } 410 411 /* Make sure the console is always "hardwired". */ 412 delay(10000); /* wait for output to finish */ 413 SET(sc->sc_hwflags, COM_HW_CONSOLE); 414 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 415 } 416 417 /* Probe for FIFO */ 418 switch (sc->sc_type) { 419 case COM_TYPE_HAYESP: 420 goto fifodone; 421 422 case COM_TYPE_AU1x00: 423 sc->sc_fifolen = 16; 424 fifo_msg = "Au1X00 UART, working fifo"; 425 SET(sc->sc_hwflags, COM_HW_FIFO); 426 goto fifodelay; 427 428 case COM_TYPE_16550_NOERS: 429 sc->sc_fifolen = 16; 430 fifo_msg = "ns16650, no ERS, working fifo"; 431 SET(sc->sc_hwflags, COM_HW_FIFO); 432 goto fifodelay; 433 434 case COM_TYPE_OMAP: 435 sc->sc_fifolen = 64; 436 fifo_msg = "OMAP UART, working fifo"; 437 SET(sc->sc_hwflags, COM_HW_FIFO); 438 goto fifodelay; 439 } 440 441 sc->sc_fifolen = 1; 442 /* look for a NS 16550AF UART with FIFOs */ 443 CSR_WRITE_1(regsp, COM_REG_FIFO, 444 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 445 delay(100); 446 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 447 == IIR_FIFO_MASK) 448 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 449 == FIFO_TRIGGER_14) { 450 SET(sc->sc_hwflags, COM_HW_FIFO); 451 452 #ifdef COM_16650 453 /* 454 * IIR changes into the EFR if LCR is set to LCR_EERS 455 * on 16650s. We also know IIR != 0 at this point. 456 * Write 0 into the EFR, and read it. If the result 457 * is 0, we have a 16650. 458 * 459 * Older 16650s were broken; the test to detect them 460 * is taken from the Linux driver. Apparently 461 * setting DLAB enable gives access to the EFR on 462 * these chips. 463 */ 464 lcr = CSR_READ_1(regsp, COM_REG_LCR); 465 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 466 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 467 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 468 CSR_WRITE_1(regsp, COM_REG_LCR, 469 lcr | LCR_DLAB); 470 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 471 CLR(sc->sc_hwflags, COM_HW_FIFO); 472 sc->sc_fifolen = 0; 473 } else { 474 SET(sc->sc_hwflags, COM_HW_FLOW); 475 sc->sc_fifolen = 32; 476 } 477 } else 478 #endif 479 sc->sc_fifolen = 16; 480 481 #ifdef COM_16650 482 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 483 if (sc->sc_fifolen == 0) 484 fifo_msg = "st16650, broken fifo"; 485 else if (sc->sc_fifolen == 32) 486 fifo_msg = "st16650a, working fifo"; 487 else 488 #endif 489 fifo_msg = "ns16550a, working fifo"; 490 } else 491 fifo_msg = "ns16550, broken fifo"; 492 else 493 fifo_msg = "ns8250 or ns16450, no fifo"; 494 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 495 fifodelay: 496 /* 497 * Some chips will clear down both Tx and Rx FIFOs when zero is 498 * written to com_fifo. If this chip is the console, writing zero 499 * results in some of the chip/FIFO description being lost, so delay 500 * printing it until now. 501 */ 502 delay(10); 503 aprint_normal(": %s\n", fifo_msg); 504 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 505 sc->sc_fifolen = 1; 506 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 507 } 508 509 fifodone: 510 511 tp = ttymalloc(); 512 tp->t_oproc = comstart; 513 tp->t_param = comparam; 514 tp->t_hwiflow = comhwiflow; 515 516 sc->sc_tty = tp; 517 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 518 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 519 sc->sc_rbavail = com_rbuf_size; 520 if (sc->sc_rbuf == NULL) { 521 aprint_error_dev(sc->sc_dev, 522 "unable to allocate ring buffer\n"); 523 return; 524 } 525 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 526 527 tty_attach(tp); 528 529 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 530 SET(sc->sc_mcr, MCR_IENABLE); 531 532 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 533 int maj; 534 535 /* locate the major number */ 536 maj = cdevsw_lookup_major(&com_cdevsw); 537 538 tp->t_dev = cn_tab->cn_dev = makedev(maj, 539 device_unit(sc->sc_dev)); 540 541 aprint_normal_dev(sc->sc_dev, "console\n"); 542 } 543 544 #ifdef KGDB 545 /* 546 * Allow kgdb to "take over" this port. If this is 547 * not the console and is the kgdb device, it has 548 * exclusive use. If it's the console _and_ the 549 * kgdb device, it doesn't. 550 */ 551 if (tags_are_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 552 regsp->cr_iobase == comkgdbregs.cr_iobase) { 553 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 554 com_kgdb_attached = 1; 555 556 SET(sc->sc_hwflags, COM_HW_KGDB); 557 } 558 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 559 } 560 #endif 561 562 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 563 564 #if NRND > 0 && defined(RND_COM) 565 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 566 RND_TYPE_TTY, 0); 567 #endif 568 569 /* if there are no enable/disable functions, assume the device 570 is always enabled */ 571 if (!sc->enable) 572 sc->enabled = 1; 573 574 com_config(sc); 575 576 SET(sc->sc_hwflags, COM_HW_DEV_OK); 577 } 578 579 void 580 com_config(struct com_softc *sc) 581 { 582 struct com_regs *regsp = &sc->sc_regs; 583 584 /* Disable interrupts before configuring the device. */ 585 if (sc->sc_type == COM_TYPE_PXA2x0) 586 sc->sc_ier = IER_EUART; 587 else 588 sc->sc_ier = 0; 589 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 590 (void) CSR_READ_1(regsp, COM_REG_IIR); 591 592 #ifdef COM_HAYESP 593 /* Look for a Hayes ESP board. */ 594 if (sc->sc_type == COM_TYPE_HAYESP) { 595 596 /* Set 16550 compatibility mode */ 597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 598 HAYESP_SETMODE); 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 600 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 601 HAYESP_MODE_SCALE); 602 603 /* Set RTS/CTS flow control */ 604 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 605 HAYESP_SETFLOWTYPE); 606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 607 HAYESP_FLOW_RTS); 608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 609 HAYESP_FLOW_CTS); 610 611 /* Set flow control levels */ 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 613 HAYESP_SETRXFLOW); 614 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 615 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 616 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 617 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 618 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 619 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 620 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 621 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 622 } 623 #endif 624 625 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 626 com_enable_debugport(sc); 627 } 628 629 #if 0 630 static int 631 comcngetc_detached(dev_t dev) 632 { 633 return 0; 634 } 635 636 static void 637 comcnputc_detached(dev_t dev, int c) 638 { 639 } 640 #endif 641 642 int 643 com_detach(device_t self, int flags) 644 { 645 struct com_softc *sc = device_private(self); 646 int maj, mn; 647 648 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 649 return EBUSY; 650 651 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 652 (flags & DETACH_SHUTDOWN) != 0) 653 return EBUSY; 654 655 if (sc->disable != NULL && sc->enabled != 0) { 656 (*sc->disable)(sc); 657 sc->enabled = 0; 658 } 659 660 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 661 comconsattached = 0; 662 cn_tab = NULL; 663 } 664 665 /* locate the major number */ 666 maj = cdevsw_lookup_major(&com_cdevsw); 667 668 /* Nuke the vnodes for any open instances. */ 669 mn = device_unit(self); 670 vdevgone(maj, mn, mn, VCHR); 671 672 mn |= COMDIALOUT_MASK; 673 vdevgone(maj, mn, mn, VCHR); 674 675 if (sc->sc_rbuf == NULL) { 676 /* 677 * Ring buffer allocation failed in the com_attach_subr, 678 * only the tty is allocated, and nothing else. 679 */ 680 ttyfree(sc->sc_tty); 681 return 0; 682 } 683 684 /* Free the receive buffer. */ 685 free(sc->sc_rbuf, M_DEVBUF); 686 687 /* Detach and free the tty. */ 688 tty_detach(sc->sc_tty); 689 ttyfree(sc->sc_tty); 690 691 /* Unhook the soft interrupt handler. */ 692 softint_disestablish(sc->sc_si); 693 694 #if NRND > 0 && defined(RND_COM) 695 /* Unhook the entropy source. */ 696 rnd_detach_source(&sc->rnd_source); 697 #endif 698 callout_destroy(&sc->sc_diag_callout); 699 700 /* Destroy the lock. */ 701 mutex_destroy(&sc->sc_lock); 702 703 return (0); 704 } 705 706 void 707 com_shutdown(struct com_softc *sc) 708 { 709 struct tty *tp = sc->sc_tty; 710 711 mutex_spin_enter(&sc->sc_lock); 712 713 /* If we were asserting flow control, then deassert it. */ 714 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 715 com_hwiflow(sc); 716 717 /* Clear any break condition set with TIOCSBRK. */ 718 com_break(sc, 0); 719 720 /* 721 * Hang up if necessary. Wait a bit, so the other side has time to 722 * notice even if we immediately open the port again. 723 * Avoid tsleeping above splhigh(). 724 */ 725 if (ISSET(tp->t_cflag, HUPCL)) { 726 com_modem(sc, 0); 727 mutex_spin_exit(&sc->sc_lock); 728 /* XXX will only timeout */ 729 (void) kpause(ttclos, false, hz, NULL); 730 mutex_spin_enter(&sc->sc_lock); 731 } 732 733 /* Turn off interrupts. */ 734 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 735 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 736 if (sc->sc_type == COM_TYPE_PXA2x0) 737 sc->sc_ier |= IER_ERXTOUT; 738 } else 739 sc->sc_ier = 0; 740 741 if (sc->sc_type == COM_TYPE_PXA2x0) 742 sc->sc_ier |= IER_EUART; 743 744 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 745 746 mutex_spin_exit(&sc->sc_lock); 747 748 if (sc->disable) { 749 #ifdef DIAGNOSTIC 750 if (!sc->enabled) 751 panic("com_shutdown: not enabled?"); 752 #endif 753 (*sc->disable)(sc); 754 sc->enabled = 0; 755 } 756 } 757 758 int 759 comopen(dev_t dev, int flag, int mode, struct lwp *l) 760 { 761 struct com_softc *sc; 762 struct tty *tp; 763 int s; 764 int error; 765 766 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 767 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 768 sc->sc_rbuf == NULL) 769 return (ENXIO); 770 771 if (!device_is_active(sc->sc_dev)) 772 return (ENXIO); 773 774 #ifdef KGDB 775 /* 776 * If this is the kgdb port, no other use is permitted. 777 */ 778 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 779 return (EBUSY); 780 #endif 781 782 tp = sc->sc_tty; 783 784 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 785 return (EBUSY); 786 787 s = spltty(); 788 789 /* 790 * Do the following iff this is a first open. 791 */ 792 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 793 struct termios t; 794 795 tp->t_dev = dev; 796 797 798 if (sc->enable) { 799 if ((*sc->enable)(sc)) { 800 splx(s); 801 aprint_error_dev(sc->sc_dev, 802 "device enable failed\n"); 803 return (EIO); 804 } 805 mutex_spin_enter(&sc->sc_lock); 806 sc->enabled = 1; 807 com_config(sc); 808 } else { 809 mutex_spin_enter(&sc->sc_lock); 810 } 811 812 /* Turn on interrupts. */ 813 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 814 if (sc->sc_type == COM_TYPE_PXA2x0) 815 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 816 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 817 818 /* Fetch the current modem control status, needed later. */ 819 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 820 821 /* Clear PPS capture state on first open. */ 822 mutex_spin_enter(&timecounter_lock); 823 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 824 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 825 pps_init(&sc->sc_pps_state); 826 mutex_spin_exit(&timecounter_lock); 827 828 mutex_spin_exit(&sc->sc_lock); 829 830 /* 831 * Initialize the termios status to the defaults. Add in the 832 * sticky bits from TIOCSFLAGS. 833 */ 834 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 835 t.c_ospeed = comcons_info.rate; 836 t.c_cflag = comcons_info.cflag; 837 } else { 838 t.c_ospeed = TTYDEF_SPEED; 839 t.c_cflag = TTYDEF_CFLAG; 840 } 841 t.c_ispeed = t.c_ospeed; 842 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 843 SET(t.c_cflag, CLOCAL); 844 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 845 SET(t.c_cflag, CRTSCTS); 846 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 847 SET(t.c_cflag, MDMBUF); 848 /* Make sure comparam() will do something. */ 849 tp->t_ospeed = 0; 850 (void) comparam(tp, &t); 851 tp->t_iflag = TTYDEF_IFLAG; 852 tp->t_oflag = TTYDEF_OFLAG; 853 tp->t_lflag = TTYDEF_LFLAG; 854 ttychars(tp); 855 ttsetwater(tp); 856 857 mutex_spin_enter(&sc->sc_lock); 858 859 /* 860 * Turn on DTR. We must always do this, even if carrier is not 861 * present, because otherwise we'd have to use TIOCSDTR 862 * immediately after setting CLOCAL, which applications do not 863 * expect. We always assert DTR while the device is open 864 * unless explicitly requested to deassert it. 865 */ 866 com_modem(sc, 1); 867 868 /* Clear the input ring, and unblock. */ 869 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 870 sc->sc_rbavail = com_rbuf_size; 871 com_iflush(sc); 872 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 873 com_hwiflow(sc); 874 875 #ifdef COM_DEBUG 876 if (com_debug) 877 comstatus(sc, "comopen "); 878 #endif 879 880 mutex_spin_exit(&sc->sc_lock); 881 } 882 883 splx(s); 884 885 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 886 if (error) 887 goto bad; 888 889 error = (*tp->t_linesw->l_open)(dev, tp); 890 if (error) 891 goto bad; 892 893 return (0); 894 895 bad: 896 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 897 /* 898 * We failed to open the device, and nobody else had it opened. 899 * Clean up the state as appropriate. 900 */ 901 com_shutdown(sc); 902 } 903 904 return (error); 905 } 906 907 int 908 comclose(dev_t dev, int flag, int mode, struct lwp *l) 909 { 910 struct com_softc *sc = 911 device_lookup_private(&com_cd, COMUNIT(dev)); 912 struct tty *tp = sc->sc_tty; 913 914 /* XXX This is for cons.c. */ 915 if (!ISSET(tp->t_state, TS_ISOPEN)) 916 return (0); 917 918 (*tp->t_linesw->l_close)(tp, flag); 919 ttyclose(tp); 920 921 if (COM_ISALIVE(sc) == 0) 922 return (0); 923 924 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 925 /* 926 * Although we got a last close, the device may still be in 927 * use; e.g. if this was the dialout node, and there are still 928 * processes waiting for carrier on the non-dialout node. 929 */ 930 com_shutdown(sc); 931 } 932 933 return (0); 934 } 935 936 int 937 comread(dev_t dev, struct uio *uio, int flag) 938 { 939 struct com_softc *sc = 940 device_lookup_private(&com_cd, COMUNIT(dev)); 941 struct tty *tp = sc->sc_tty; 942 943 if (COM_ISALIVE(sc) == 0) 944 return (EIO); 945 946 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 947 } 948 949 int 950 comwrite(dev_t dev, struct uio *uio, int flag) 951 { 952 struct com_softc *sc = 953 device_lookup_private(&com_cd, COMUNIT(dev)); 954 struct tty *tp = sc->sc_tty; 955 956 if (COM_ISALIVE(sc) == 0) 957 return (EIO); 958 959 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 960 } 961 962 int 963 compoll(dev_t dev, int events, struct lwp *l) 964 { 965 struct com_softc *sc = 966 device_lookup_private(&com_cd, COMUNIT(dev)); 967 struct tty *tp = sc->sc_tty; 968 969 if (COM_ISALIVE(sc) == 0) 970 return (POLLHUP); 971 972 return ((*tp->t_linesw->l_poll)(tp, events, l)); 973 } 974 975 struct tty * 976 comtty(dev_t dev) 977 { 978 struct com_softc *sc = 979 device_lookup_private(&com_cd, COMUNIT(dev)); 980 struct tty *tp = sc->sc_tty; 981 982 return (tp); 983 } 984 985 int 986 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 987 { 988 struct com_softc *sc; 989 struct tty *tp; 990 int error; 991 992 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 993 if (sc == NULL) 994 return ENXIO; 995 if (COM_ISALIVE(sc) == 0) 996 return (EIO); 997 998 tp = sc->sc_tty; 999 1000 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1001 if (error != EPASSTHROUGH) 1002 return (error); 1003 1004 error = ttioctl(tp, cmd, data, flag, l); 1005 if (error != EPASSTHROUGH) 1006 return (error); 1007 1008 error = 0; 1009 switch (cmd) { 1010 case TIOCSFLAGS: 1011 error = kauth_authorize_device_tty(l->l_cred, 1012 KAUTH_DEVICE_TTY_PRIVSET, tp); 1013 break; 1014 default: 1015 /* nothing */ 1016 break; 1017 } 1018 if (error) { 1019 return error; 1020 } 1021 1022 mutex_spin_enter(&sc->sc_lock); 1023 1024 switch (cmd) { 1025 case TIOCSBRK: 1026 com_break(sc, 1); 1027 break; 1028 1029 case TIOCCBRK: 1030 com_break(sc, 0); 1031 break; 1032 1033 case TIOCSDTR: 1034 com_modem(sc, 1); 1035 break; 1036 1037 case TIOCCDTR: 1038 com_modem(sc, 0); 1039 break; 1040 1041 case TIOCGFLAGS: 1042 *(int *)data = sc->sc_swflags; 1043 break; 1044 1045 case TIOCSFLAGS: 1046 sc->sc_swflags = *(int *)data; 1047 break; 1048 1049 case TIOCMSET: 1050 case TIOCMBIS: 1051 case TIOCMBIC: 1052 tiocm_to_com(sc, cmd, *(int *)data); 1053 break; 1054 1055 case TIOCMGET: 1056 *(int *)data = com_to_tiocm(sc); 1057 break; 1058 1059 case PPS_IOC_CREATE: 1060 case PPS_IOC_DESTROY: 1061 case PPS_IOC_GETPARAMS: 1062 case PPS_IOC_SETPARAMS: 1063 case PPS_IOC_GETCAP: 1064 case PPS_IOC_FETCH: 1065 #ifdef PPS_SYNC 1066 case PPS_IOC_KCBIND: 1067 #endif 1068 mutex_spin_enter(&timecounter_lock); 1069 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1070 mutex_spin_exit(&timecounter_lock); 1071 break; 1072 1073 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1074 mutex_spin_enter(&timecounter_lock); 1075 #ifndef PPS_TRAILING_EDGE 1076 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1077 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1078 #else 1079 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1080 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1081 #endif 1082 mutex_spin_exit(&timecounter_lock); 1083 break; 1084 1085 default: 1086 error = EPASSTHROUGH; 1087 break; 1088 } 1089 1090 mutex_spin_exit(&sc->sc_lock); 1091 1092 #ifdef COM_DEBUG 1093 if (com_debug) 1094 comstatus(sc, "comioctl "); 1095 #endif 1096 1097 return (error); 1098 } 1099 1100 integrate void 1101 com_schedrx(struct com_softc *sc) 1102 { 1103 1104 sc->sc_rx_ready = 1; 1105 1106 /* Wake up the poller. */ 1107 softint_schedule(sc->sc_si); 1108 } 1109 1110 void 1111 com_break(struct com_softc *sc, int onoff) 1112 { 1113 1114 if (onoff) 1115 SET(sc->sc_lcr, LCR_SBREAK); 1116 else 1117 CLR(sc->sc_lcr, LCR_SBREAK); 1118 1119 if (!sc->sc_heldchange) { 1120 if (sc->sc_tx_busy) { 1121 sc->sc_heldtbc = sc->sc_tbc; 1122 sc->sc_tbc = 0; 1123 sc->sc_heldchange = 1; 1124 } else 1125 com_loadchannelregs(sc); 1126 } 1127 } 1128 1129 void 1130 com_modem(struct com_softc *sc, int onoff) 1131 { 1132 1133 if (sc->sc_mcr_dtr == 0) 1134 return; 1135 1136 if (onoff) 1137 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1138 else 1139 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1140 1141 if (!sc->sc_heldchange) { 1142 if (sc->sc_tx_busy) { 1143 sc->sc_heldtbc = sc->sc_tbc; 1144 sc->sc_tbc = 0; 1145 sc->sc_heldchange = 1; 1146 } else 1147 com_loadchannelregs(sc); 1148 } 1149 } 1150 1151 void 1152 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1153 { 1154 u_char combits; 1155 1156 combits = 0; 1157 if (ISSET(ttybits, TIOCM_DTR)) 1158 SET(combits, MCR_DTR); 1159 if (ISSET(ttybits, TIOCM_RTS)) 1160 SET(combits, MCR_RTS); 1161 1162 switch (how) { 1163 case TIOCMBIC: 1164 CLR(sc->sc_mcr, combits); 1165 break; 1166 1167 case TIOCMBIS: 1168 SET(sc->sc_mcr, combits); 1169 break; 1170 1171 case TIOCMSET: 1172 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1173 SET(sc->sc_mcr, combits); 1174 break; 1175 } 1176 1177 if (!sc->sc_heldchange) { 1178 if (sc->sc_tx_busy) { 1179 sc->sc_heldtbc = sc->sc_tbc; 1180 sc->sc_tbc = 0; 1181 sc->sc_heldchange = 1; 1182 } else 1183 com_loadchannelregs(sc); 1184 } 1185 } 1186 1187 int 1188 com_to_tiocm(struct com_softc *sc) 1189 { 1190 u_char combits; 1191 int ttybits = 0; 1192 1193 combits = sc->sc_mcr; 1194 if (ISSET(combits, MCR_DTR)) 1195 SET(ttybits, TIOCM_DTR); 1196 if (ISSET(combits, MCR_RTS)) 1197 SET(ttybits, TIOCM_RTS); 1198 1199 combits = sc->sc_msr; 1200 if (ISSET(combits, MSR_DCD)) 1201 SET(ttybits, TIOCM_CD); 1202 if (ISSET(combits, MSR_CTS)) 1203 SET(ttybits, TIOCM_CTS); 1204 if (ISSET(combits, MSR_DSR)) 1205 SET(ttybits, TIOCM_DSR); 1206 if (ISSET(combits, MSR_RI | MSR_TERI)) 1207 SET(ttybits, TIOCM_RI); 1208 1209 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1210 SET(ttybits, TIOCM_LE); 1211 1212 return (ttybits); 1213 } 1214 1215 static u_char 1216 cflag2lcr(tcflag_t cflag) 1217 { 1218 u_char lcr = 0; 1219 1220 switch (ISSET(cflag, CSIZE)) { 1221 case CS5: 1222 SET(lcr, LCR_5BITS); 1223 break; 1224 case CS6: 1225 SET(lcr, LCR_6BITS); 1226 break; 1227 case CS7: 1228 SET(lcr, LCR_7BITS); 1229 break; 1230 case CS8: 1231 SET(lcr, LCR_8BITS); 1232 break; 1233 } 1234 if (ISSET(cflag, PARENB)) { 1235 SET(lcr, LCR_PENAB); 1236 if (!ISSET(cflag, PARODD)) 1237 SET(lcr, LCR_PEVEN); 1238 } 1239 if (ISSET(cflag, CSTOPB)) 1240 SET(lcr, LCR_STOPB); 1241 1242 return (lcr); 1243 } 1244 1245 int 1246 comparam(struct tty *tp, struct termios *t) 1247 { 1248 struct com_softc *sc = 1249 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1250 int ospeed; 1251 u_char lcr; 1252 1253 if (COM_ISALIVE(sc) == 0) 1254 return (EIO); 1255 1256 #ifdef COM_HAYESP 1257 if (sc->sc_type == COM_TYPE_HAYESP) { 1258 int prescaler, speed; 1259 1260 /* 1261 * Calculate UART clock prescaler. It should be in 1262 * range of 0 .. 3. 1263 */ 1264 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1265 prescaler++, speed /= 2) 1266 if ((ospeed = comspeed(speed, sc->sc_frequency, 1267 sc->sc_type)) > 0) 1268 break; 1269 1270 if (prescaler == 4) 1271 return (EINVAL); 1272 sc->sc_prescaler = prescaler; 1273 } else 1274 #endif 1275 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1276 1277 /* Check requested parameters. */ 1278 if (ospeed < 0) 1279 return (EINVAL); 1280 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1281 return (EINVAL); 1282 1283 /* 1284 * For the console, always force CLOCAL and !HUPCL, so that the port 1285 * is always active. 1286 */ 1287 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1288 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1289 SET(t->c_cflag, CLOCAL); 1290 CLR(t->c_cflag, HUPCL); 1291 } 1292 1293 /* 1294 * If there were no changes, don't do anything. This avoids dropping 1295 * input and improves performance when all we did was frob things like 1296 * VMIN and VTIME. 1297 */ 1298 if (tp->t_ospeed == t->c_ospeed && 1299 tp->t_cflag == t->c_cflag) 1300 return (0); 1301 1302 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1303 1304 mutex_spin_enter(&sc->sc_lock); 1305 1306 sc->sc_lcr = lcr; 1307 1308 /* 1309 * If we're not in a mode that assumes a connection is present, then 1310 * ignore carrier changes. 1311 */ 1312 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1313 sc->sc_msr_dcd = 0; 1314 else 1315 sc->sc_msr_dcd = MSR_DCD; 1316 /* 1317 * Set the flow control pins depending on the current flow control 1318 * mode. 1319 */ 1320 if (ISSET(t->c_cflag, CRTSCTS)) { 1321 sc->sc_mcr_dtr = MCR_DTR; 1322 sc->sc_mcr_rts = MCR_RTS; 1323 sc->sc_msr_cts = MSR_CTS; 1324 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1325 } else if (ISSET(t->c_cflag, MDMBUF)) { 1326 /* 1327 * For DTR/DCD flow control, make sure we don't toggle DTR for 1328 * carrier detection. 1329 */ 1330 sc->sc_mcr_dtr = 0; 1331 sc->sc_mcr_rts = MCR_DTR; 1332 sc->sc_msr_cts = MSR_DCD; 1333 sc->sc_efr = 0; 1334 } else { 1335 /* 1336 * If no flow control, then always set RTS. This will make 1337 * the other side happy if it mistakenly thinks we're doing 1338 * RTS/CTS flow control. 1339 */ 1340 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1341 sc->sc_mcr_rts = 0; 1342 sc->sc_msr_cts = 0; 1343 sc->sc_efr = 0; 1344 if (ISSET(sc->sc_mcr, MCR_DTR)) 1345 SET(sc->sc_mcr, MCR_RTS); 1346 else 1347 CLR(sc->sc_mcr, MCR_RTS); 1348 } 1349 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1350 1351 #if 0 1352 if (ospeed == 0) 1353 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1354 else 1355 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1356 #endif 1357 1358 sc->sc_dlbl = ospeed; 1359 sc->sc_dlbh = ospeed >> 8; 1360 1361 /* 1362 * Set the FIFO threshold based on the receive speed. 1363 * 1364 * * If it's a low speed, it's probably a mouse or some other 1365 * interactive device, so set the threshold low. 1366 * * If it's a high speed, trim the trigger level down to prevent 1367 * overflows. 1368 * * Otherwise set it a bit higher. 1369 */ 1370 if (sc->sc_type == COM_TYPE_HAYESP) 1371 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1372 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1373 if (t->c_ospeed <= 1200) 1374 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1375 else if (t->c_ospeed <= 38400) 1376 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1377 else 1378 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1379 } else 1380 sc->sc_fifo = 0; 1381 1382 /* And copy to tty. */ 1383 tp->t_ispeed = t->c_ospeed; 1384 tp->t_ospeed = t->c_ospeed; 1385 tp->t_cflag = t->c_cflag; 1386 1387 if (!sc->sc_heldchange) { 1388 if (sc->sc_tx_busy) { 1389 sc->sc_heldtbc = sc->sc_tbc; 1390 sc->sc_tbc = 0; 1391 sc->sc_heldchange = 1; 1392 } else 1393 com_loadchannelregs(sc); 1394 } 1395 1396 if (!ISSET(t->c_cflag, CHWFLOW)) { 1397 /* Disable the high water mark. */ 1398 sc->sc_r_hiwat = 0; 1399 sc->sc_r_lowat = 0; 1400 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1401 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1402 com_schedrx(sc); 1403 } 1404 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1405 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1406 com_hwiflow(sc); 1407 } 1408 } else { 1409 sc->sc_r_hiwat = com_rbuf_hiwat; 1410 sc->sc_r_lowat = com_rbuf_lowat; 1411 } 1412 1413 mutex_spin_exit(&sc->sc_lock); 1414 1415 /* 1416 * Update the tty layer's idea of the carrier bit, in case we changed 1417 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1418 * explicit request. 1419 */ 1420 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1421 1422 #ifdef COM_DEBUG 1423 if (com_debug) 1424 comstatus(sc, "comparam "); 1425 #endif 1426 1427 if (!ISSET(t->c_cflag, CHWFLOW)) { 1428 if (sc->sc_tx_stopped) { 1429 sc->sc_tx_stopped = 0; 1430 comstart(tp); 1431 } 1432 } 1433 1434 return (0); 1435 } 1436 1437 void 1438 com_iflush(struct com_softc *sc) 1439 { 1440 struct com_regs *regsp = &sc->sc_regs; 1441 #ifdef DIAGNOSTIC 1442 int reg; 1443 #endif 1444 int timo; 1445 1446 #ifdef DIAGNOSTIC 1447 reg = 0xffff; 1448 #endif 1449 timo = 50000; 1450 /* flush any pending I/O */ 1451 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1452 && --timo) 1453 #ifdef DIAGNOSTIC 1454 reg = 1455 #else 1456 (void) 1457 #endif 1458 CSR_READ_1(regsp, COM_REG_RXDATA); 1459 #ifdef DIAGNOSTIC 1460 if (!timo) 1461 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1462 #endif 1463 } 1464 1465 void 1466 com_loadchannelregs(struct com_softc *sc) 1467 { 1468 struct com_regs *regsp = &sc->sc_regs; 1469 1470 /* XXXXX necessary? */ 1471 com_iflush(sc); 1472 1473 if (sc->sc_type == COM_TYPE_PXA2x0) 1474 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1475 else 1476 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1477 1478 if (sc->sc_type == COM_TYPE_OMAP) { 1479 /* disable before changing settings */ 1480 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1481 } 1482 1483 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1484 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1485 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1486 /* no EFR on alchemy */ 1487 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1488 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1489 } 1490 if (sc->sc_type == COM_TYPE_AU1x00) { 1491 /* alchemy has single separate 16-bit clock divisor register */ 1492 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1493 (sc->sc_dlbh << 8)); 1494 } else { 1495 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1496 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1497 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1498 } 1499 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1500 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1501 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1502 #ifdef COM_HAYESP 1503 if (sc->sc_type == COM_TYPE_HAYESP) { 1504 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1505 HAYESP_SETPRESCALER); 1506 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1507 sc->sc_prescaler); 1508 } 1509 #endif 1510 if (sc->sc_type == COM_TYPE_OMAP) { 1511 /* setup the fifos. the FCR value is not used as long 1512 as SCR[6] and SCR[7] are 0, which they are at reset 1513 and we never touch the SCR register */ 1514 uint8_t rx_fifo_trig = 40; 1515 uint8_t tx_fifo_trig = 60; 1516 uint8_t rx_start = 8; 1517 uint8_t rx_halt = 60; 1518 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1519 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1520 1521 /* enable access to TCR & TLR */ 1522 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1523 1524 /* write tcr and tlr values */ 1525 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1526 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1527 1528 /* disable access to TCR & TLR */ 1529 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1530 1531 /* enable again, but mode is based on speed */ 1532 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1533 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1534 } else { 1535 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1536 } 1537 } 1538 1539 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1540 } 1541 1542 int 1543 comhwiflow(struct tty *tp, int block) 1544 { 1545 struct com_softc *sc = 1546 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1547 1548 if (COM_ISALIVE(sc) == 0) 1549 return (0); 1550 1551 if (sc->sc_mcr_rts == 0) 1552 return (0); 1553 1554 mutex_spin_enter(&sc->sc_lock); 1555 1556 if (block) { 1557 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1558 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1559 com_hwiflow(sc); 1560 } 1561 } else { 1562 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1563 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1564 com_schedrx(sc); 1565 } 1566 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1567 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1568 com_hwiflow(sc); 1569 } 1570 } 1571 1572 mutex_spin_exit(&sc->sc_lock); 1573 return (1); 1574 } 1575 1576 /* 1577 * (un)block input via hw flowcontrol 1578 */ 1579 void 1580 com_hwiflow(struct com_softc *sc) 1581 { 1582 struct com_regs *regsp= &sc->sc_regs; 1583 1584 if (sc->sc_mcr_rts == 0) 1585 return; 1586 1587 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1588 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1589 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1590 } else { 1591 SET(sc->sc_mcr, sc->sc_mcr_rts); 1592 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1593 } 1594 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1595 } 1596 1597 1598 void 1599 comstart(struct tty *tp) 1600 { 1601 struct com_softc *sc = 1602 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1603 struct com_regs *regsp = &sc->sc_regs; 1604 int s; 1605 1606 if (COM_ISALIVE(sc) == 0) 1607 return; 1608 1609 s = spltty(); 1610 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1611 goto out; 1612 if (sc->sc_tx_stopped) 1613 goto out; 1614 if (!ttypull(tp)) 1615 goto out; 1616 1617 /* Grab the first contiguous region of buffer space. */ 1618 { 1619 u_char *tba; 1620 int tbc; 1621 1622 tba = tp->t_outq.c_cf; 1623 tbc = ndqb(&tp->t_outq, 0); 1624 1625 mutex_spin_enter(&sc->sc_lock); 1626 1627 sc->sc_tba = tba; 1628 sc->sc_tbc = tbc; 1629 } 1630 1631 SET(tp->t_state, TS_BUSY); 1632 sc->sc_tx_busy = 1; 1633 1634 /* Enable transmit completion interrupts if necessary. */ 1635 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1636 SET(sc->sc_ier, IER_ETXRDY); 1637 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1638 } 1639 1640 /* Output the first chunk of the contiguous buffer. */ 1641 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1642 u_int n; 1643 1644 n = sc->sc_tbc; 1645 if (n > sc->sc_fifolen) 1646 n = sc->sc_fifolen; 1647 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1648 sc->sc_tbc -= n; 1649 sc->sc_tba += n; 1650 } 1651 1652 mutex_spin_exit(&sc->sc_lock); 1653 out: 1654 splx(s); 1655 return; 1656 } 1657 1658 /* 1659 * Stop output on a line. 1660 */ 1661 void 1662 comstop(struct tty *tp, int flag) 1663 { 1664 struct com_softc *sc = 1665 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1666 1667 mutex_spin_enter(&sc->sc_lock); 1668 if (ISSET(tp->t_state, TS_BUSY)) { 1669 /* Stop transmitting at the next chunk. */ 1670 sc->sc_tbc = 0; 1671 sc->sc_heldtbc = 0; 1672 if (!ISSET(tp->t_state, TS_TTSTOP)) 1673 SET(tp->t_state, TS_FLUSH); 1674 } 1675 mutex_spin_exit(&sc->sc_lock); 1676 } 1677 1678 void 1679 comdiag(void *arg) 1680 { 1681 struct com_softc *sc = arg; 1682 int overflows, floods; 1683 1684 mutex_spin_enter(&sc->sc_lock); 1685 overflows = sc->sc_overflows; 1686 sc->sc_overflows = 0; 1687 floods = sc->sc_floods; 1688 sc->sc_floods = 0; 1689 sc->sc_errors = 0; 1690 mutex_spin_exit(&sc->sc_lock); 1691 1692 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1693 device_xname(sc->sc_dev), 1694 overflows, overflows == 1 ? "" : "s", 1695 floods, floods == 1 ? "" : "s"); 1696 } 1697 1698 integrate void 1699 com_rxsoft(struct com_softc *sc, struct tty *tp) 1700 { 1701 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1702 u_char *get, *end; 1703 u_int cc, scc; 1704 u_char lsr; 1705 int code; 1706 1707 end = sc->sc_ebuf; 1708 get = sc->sc_rbget; 1709 scc = cc = com_rbuf_size - sc->sc_rbavail; 1710 1711 if (cc == com_rbuf_size) { 1712 sc->sc_floods++; 1713 if (sc->sc_errors++ == 0) 1714 callout_reset(&sc->sc_diag_callout, 60 * hz, 1715 comdiag, sc); 1716 } 1717 1718 /* If not yet open, drop the entire buffer content here */ 1719 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1720 get += cc << 1; 1721 if (get >= end) 1722 get -= com_rbuf_size << 1; 1723 cc = 0; 1724 } 1725 while (cc) { 1726 code = get[0]; 1727 lsr = get[1]; 1728 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1729 if (ISSET(lsr, LSR_OE)) { 1730 sc->sc_overflows++; 1731 if (sc->sc_errors++ == 0) 1732 callout_reset(&sc->sc_diag_callout, 1733 60 * hz, comdiag, sc); 1734 } 1735 if (ISSET(lsr, LSR_BI | LSR_FE)) 1736 SET(code, TTY_FE); 1737 if (ISSET(lsr, LSR_PE)) 1738 SET(code, TTY_PE); 1739 } 1740 if ((*rint)(code, tp) == -1) { 1741 /* 1742 * The line discipline's buffer is out of space. 1743 */ 1744 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1745 /* 1746 * We're either not using flow control, or the 1747 * line discipline didn't tell us to block for 1748 * some reason. Either way, we have no way to 1749 * know when there's more space available, so 1750 * just drop the rest of the data. 1751 */ 1752 get += cc << 1; 1753 if (get >= end) 1754 get -= com_rbuf_size << 1; 1755 cc = 0; 1756 } else { 1757 /* 1758 * Don't schedule any more receive processing 1759 * until the line discipline tells us there's 1760 * space available (through comhwiflow()). 1761 * Leave the rest of the data in the input 1762 * buffer. 1763 */ 1764 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1765 } 1766 break; 1767 } 1768 get += 2; 1769 if (get >= end) 1770 get = sc->sc_rbuf; 1771 cc--; 1772 } 1773 1774 if (cc != scc) { 1775 sc->sc_rbget = get; 1776 mutex_spin_enter(&sc->sc_lock); 1777 1778 cc = sc->sc_rbavail += scc - cc; 1779 /* Buffers should be ok again, release possible block. */ 1780 if (cc >= sc->sc_r_lowat) { 1781 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1782 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1783 SET(sc->sc_ier, IER_ERXRDY); 1784 #ifdef COM_PXA2X0 1785 if (sc->sc_type == COM_TYPE_PXA2x0) 1786 SET(sc->sc_ier, IER_ERXTOUT); 1787 #endif 1788 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1789 } 1790 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1791 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1792 com_hwiflow(sc); 1793 } 1794 } 1795 mutex_spin_exit(&sc->sc_lock); 1796 } 1797 } 1798 1799 integrate void 1800 com_txsoft(struct com_softc *sc, struct tty *tp) 1801 { 1802 1803 CLR(tp->t_state, TS_BUSY); 1804 if (ISSET(tp->t_state, TS_FLUSH)) 1805 CLR(tp->t_state, TS_FLUSH); 1806 else 1807 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1808 (*tp->t_linesw->l_start)(tp); 1809 } 1810 1811 integrate void 1812 com_stsoft(struct com_softc *sc, struct tty *tp) 1813 { 1814 u_char msr, delta; 1815 1816 mutex_spin_enter(&sc->sc_lock); 1817 msr = sc->sc_msr; 1818 delta = sc->sc_msr_delta; 1819 sc->sc_msr_delta = 0; 1820 mutex_spin_exit(&sc->sc_lock); 1821 1822 if (ISSET(delta, sc->sc_msr_dcd)) { 1823 /* 1824 * Inform the tty layer that carrier detect changed. 1825 */ 1826 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1827 } 1828 1829 if (ISSET(delta, sc->sc_msr_cts)) { 1830 /* Block or unblock output according to flow control. */ 1831 if (ISSET(msr, sc->sc_msr_cts)) { 1832 sc->sc_tx_stopped = 0; 1833 (*tp->t_linesw->l_start)(tp); 1834 } else { 1835 sc->sc_tx_stopped = 1; 1836 } 1837 } 1838 1839 #ifdef COM_DEBUG 1840 if (com_debug) 1841 comstatus(sc, "com_stsoft"); 1842 #endif 1843 } 1844 1845 void 1846 comsoft(void *arg) 1847 { 1848 struct com_softc *sc = arg; 1849 struct tty *tp; 1850 1851 if (COM_ISALIVE(sc) == 0) 1852 return; 1853 1854 tp = sc->sc_tty; 1855 1856 if (sc->sc_rx_ready) { 1857 sc->sc_rx_ready = 0; 1858 com_rxsoft(sc, tp); 1859 } 1860 1861 if (sc->sc_st_check) { 1862 sc->sc_st_check = 0; 1863 com_stsoft(sc, tp); 1864 } 1865 1866 if (sc->sc_tx_done) { 1867 sc->sc_tx_done = 0; 1868 com_txsoft(sc, tp); 1869 } 1870 } 1871 1872 int 1873 comintr(void *arg) 1874 { 1875 struct com_softc *sc = arg; 1876 struct com_regs *regsp = &sc->sc_regs; 1877 1878 u_char *put, *end; 1879 u_int cc; 1880 u_char lsr, iir; 1881 1882 if (COM_ISALIVE(sc) == 0) 1883 return (0); 1884 1885 KASSERT(regsp != NULL); 1886 1887 mutex_spin_enter(&sc->sc_lock); 1888 iir = CSR_READ_1(regsp, COM_REG_IIR); 1889 if (ISSET(iir, IIR_NOPEND)) { 1890 mutex_spin_exit(&sc->sc_lock); 1891 return (0); 1892 } 1893 1894 end = sc->sc_ebuf; 1895 put = sc->sc_rbput; 1896 cc = sc->sc_rbavail; 1897 1898 again: do { 1899 u_char msr, delta; 1900 1901 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1902 if (ISSET(lsr, LSR_BI)) { 1903 int cn_trapped = 0; 1904 1905 cn_check_magic(sc->sc_tty->t_dev, 1906 CNC_BREAK, com_cnm_state); 1907 if (cn_trapped) 1908 continue; 1909 #if defined(KGDB) && !defined(DDB) 1910 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1911 kgdb_connect(1); 1912 continue; 1913 } 1914 #endif 1915 } 1916 1917 if (ISSET(lsr, LSR_RCV_MASK) && 1918 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1919 while (cc > 0) { 1920 int cn_trapped = 0; 1921 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1922 put[1] = lsr; 1923 cn_check_magic(sc->sc_tty->t_dev, 1924 put[0], com_cnm_state); 1925 if (cn_trapped) 1926 goto next; 1927 put += 2; 1928 if (put >= end) 1929 put = sc->sc_rbuf; 1930 cc--; 1931 next: 1932 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1933 if (!ISSET(lsr, LSR_RCV_MASK)) 1934 break; 1935 } 1936 1937 /* 1938 * Current string of incoming characters ended because 1939 * no more data was available or we ran out of space. 1940 * Schedule a receive event if any data was received. 1941 * If we're out of space, turn off receive interrupts. 1942 */ 1943 sc->sc_rbput = put; 1944 sc->sc_rbavail = cc; 1945 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1946 sc->sc_rx_ready = 1; 1947 1948 /* 1949 * See if we are in danger of overflowing a buffer. If 1950 * so, use hardware flow control to ease the pressure. 1951 */ 1952 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1953 cc < sc->sc_r_hiwat) { 1954 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1955 com_hwiflow(sc); 1956 } 1957 1958 /* 1959 * If we're out of space, disable receive interrupts 1960 * until the queue has drained a bit. 1961 */ 1962 if (!cc) { 1963 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1964 #ifdef COM_PXA2X0 1965 if (sc->sc_type == COM_TYPE_PXA2x0) 1966 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1967 else 1968 #endif 1969 CLR(sc->sc_ier, IER_ERXRDY); 1970 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1971 } 1972 } else { 1973 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1974 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1975 continue; 1976 } 1977 } 1978 1979 msr = CSR_READ_1(regsp, COM_REG_MSR); 1980 delta = msr ^ sc->sc_msr; 1981 sc->sc_msr = msr; 1982 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1983 (delta & MSR_DCD)) { 1984 mutex_spin_enter(&timecounter_lock); 1985 pps_capture(&sc->sc_pps_state); 1986 pps_event(&sc->sc_pps_state, 1987 (msr & MSR_DCD) ? 1988 PPS_CAPTUREASSERT : 1989 PPS_CAPTURECLEAR); 1990 mutex_spin_exit(&timecounter_lock); 1991 } 1992 1993 /* 1994 * Process normal status changes 1995 */ 1996 if (ISSET(delta, sc->sc_msr_mask)) { 1997 SET(sc->sc_msr_delta, delta); 1998 1999 /* 2000 * Stop output immediately if we lose the output 2001 * flow control signal or carrier detect. 2002 */ 2003 if (ISSET(~msr, sc->sc_msr_mask)) { 2004 sc->sc_tbc = 0; 2005 sc->sc_heldtbc = 0; 2006 #ifdef COM_DEBUG 2007 if (com_debug) 2008 comstatus(sc, "comintr "); 2009 #endif 2010 } 2011 2012 sc->sc_st_check = 1; 2013 } 2014 } while (!ISSET((iir = 2015 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2016 /* 2017 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2018 * by IIR read, so we can't do this way: `process all interrupts, 2019 * then do TX if possble'. 2020 */ 2021 (iir & IIR_IMASK) != IIR_TXRDY); 2022 2023 /* 2024 * Read LSR again, since there may be an interrupt between 2025 * the last LSR read and IIR read above. 2026 */ 2027 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2028 2029 /* 2030 * See if data can be transmitted as well. 2031 * Schedule tx done event if no data left 2032 * and tty was marked busy. 2033 */ 2034 if (ISSET(lsr, LSR_TXRDY)) { 2035 /* 2036 * If we've delayed a parameter change, do it now, and restart 2037 * output. 2038 */ 2039 if (sc->sc_heldchange) { 2040 com_loadchannelregs(sc); 2041 sc->sc_heldchange = 0; 2042 sc->sc_tbc = sc->sc_heldtbc; 2043 sc->sc_heldtbc = 0; 2044 } 2045 2046 /* Output the next chunk of the contiguous buffer, if any. */ 2047 if (sc->sc_tbc > 0) { 2048 u_int n; 2049 2050 n = sc->sc_tbc; 2051 if (n > sc->sc_fifolen) 2052 n = sc->sc_fifolen; 2053 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2054 sc->sc_tbc -= n; 2055 sc->sc_tba += n; 2056 } else { 2057 /* Disable transmit completion interrupts if necessary. */ 2058 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2059 CLR(sc->sc_ier, IER_ETXRDY); 2060 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2061 } 2062 if (sc->sc_tx_busy) { 2063 sc->sc_tx_busy = 0; 2064 sc->sc_tx_done = 1; 2065 } 2066 } 2067 } 2068 2069 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2070 goto again; 2071 2072 mutex_spin_exit(&sc->sc_lock); 2073 2074 /* Wake up the poller. */ 2075 softint_schedule(sc->sc_si); 2076 2077 #if NRND > 0 && defined(RND_COM) 2078 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2079 #endif 2080 2081 return (1); 2082 } 2083 2084 /* 2085 * The following functions are polled getc and putc routines, shared 2086 * by the console and kgdb glue. 2087 * 2088 * The read-ahead code is so that you can detect pending in-band 2089 * cn_magic in polled mode while doing output rather than having to 2090 * wait until the kernel decides it needs input. 2091 */ 2092 2093 #define MAX_READAHEAD 20 2094 static int com_readahead[MAX_READAHEAD]; 2095 static int com_readaheadcount = 0; 2096 2097 int 2098 com_common_getc(dev_t dev, struct com_regs *regsp) 2099 { 2100 int s = splserial(); 2101 u_char stat, c; 2102 2103 /* got a character from reading things earlier */ 2104 if (com_readaheadcount > 0) { 2105 int i; 2106 2107 c = com_readahead[0]; 2108 for (i = 1; i < com_readaheadcount; i++) { 2109 com_readahead[i-1] = com_readahead[i]; 2110 } 2111 com_readaheadcount--; 2112 splx(s); 2113 return (c); 2114 } 2115 2116 /* block until a character becomes available */ 2117 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2118 ; 2119 2120 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2121 stat = CSR_READ_1(regsp, COM_REG_IIR); 2122 { 2123 int cn_trapped = 0; /* unused */ 2124 #ifdef DDB 2125 extern int db_active; 2126 if (!db_active) 2127 #endif 2128 cn_check_magic(dev, c, com_cnm_state); 2129 } 2130 splx(s); 2131 return (c); 2132 } 2133 2134 static void 2135 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2136 { 2137 int s = splserial(); 2138 int cin, stat, timo; 2139 2140 if (com_readaheadcount < MAX_READAHEAD 2141 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2142 int cn_trapped = 0; 2143 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2144 stat = CSR_READ_1(regsp, COM_REG_IIR); 2145 cn_check_magic(dev, cin, com_cnm_state); 2146 com_readahead[com_readaheadcount++] = cin; 2147 } 2148 2149 /* wait for any pending transmission to finish */ 2150 timo = 150000; 2151 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2152 continue; 2153 2154 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2155 COM_BARRIER(regsp, BR | BW); 2156 2157 splx(s); 2158 } 2159 2160 /* 2161 * Initialize UART for use as console or KGDB line. 2162 */ 2163 int 2164 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2165 tcflag_t cflag) 2166 { 2167 2168 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2169 ®sp->cr_ioh)) 2170 return (ENOMEM); /* ??? */ 2171 2172 if (type == COM_TYPE_OMAP) { 2173 /* disable before changing settings */ 2174 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2175 } 2176 2177 rate = comspeed(rate, frequency, type); 2178 if (type != COM_TYPE_AU1x00) { 2179 /* no EFR on alchemy */ 2180 if (type != COM_TYPE_16550_NOERS) { 2181 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2182 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2183 } 2184 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2185 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2186 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2187 } else { 2188 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2189 } 2190 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2191 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2192 CSR_WRITE_1(regsp, COM_REG_FIFO, 2193 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2194 2195 if (type == COM_TYPE_OMAP) { 2196 /* setup the fifos. the FCR value is not used as long 2197 as SCR[6] and SCR[7] are 0, which they are at reset 2198 and we never touch the SCR register */ 2199 uint8_t rx_fifo_trig = 40; 2200 uint8_t tx_fifo_trig = 60; 2201 uint8_t rx_start = 8; 2202 uint8_t rx_halt = 60; 2203 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2204 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2205 2206 /* enable access to TCR & TLR */ 2207 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2208 2209 /* write tcr and tlr values */ 2210 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2211 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2212 2213 /* disable access to TCR & TLR */ 2214 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2215 2216 /* enable again, but mode is based on speed */ 2217 if (rate > 230400) { 2218 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2219 } else { 2220 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2221 } 2222 } 2223 2224 #ifdef COM_PXA2X0 2225 if (type == COM_TYPE_PXA2x0) 2226 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2227 else 2228 #endif 2229 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2230 2231 return (0); 2232 } 2233 2234 int 2235 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2236 tcflag_t cflag) 2237 { 2238 int res; 2239 2240 comcons_info.regs = *regsp; 2241 2242 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2243 if (res) 2244 return (res); 2245 2246 cn_tab = &comcons; 2247 cn_init_magic(&com_cnm_state); 2248 cn_set_magic("\047\001"); /* default magic is BREAK */ 2249 2250 comcons_info.frequency = frequency; 2251 comcons_info.type = type; 2252 comcons_info.rate = rate; 2253 comcons_info.cflag = cflag; 2254 2255 return (0); 2256 } 2257 2258 int 2259 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2260 int type, tcflag_t cflag) 2261 { 2262 struct com_regs regs; 2263 2264 memset(®s, 0, sizeof regs); 2265 regs.cr_iot = iot; 2266 regs.cr_iobase = iobase; 2267 regs.cr_nports = COM_NPORTS; 2268 #ifdef COM_REGMAP 2269 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2270 #endif 2271 2272 return comcnattach1(®s, rate, frequency, type, cflag); 2273 } 2274 2275 static int 2276 comcnreattach(void) 2277 { 2278 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2279 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2280 } 2281 2282 int 2283 comcngetc(dev_t dev) 2284 { 2285 2286 return (com_common_getc(dev, &comcons_info.regs)); 2287 } 2288 2289 /* 2290 * Console kernel output character routine. 2291 */ 2292 void 2293 comcnputc(dev_t dev, int c) 2294 { 2295 2296 com_common_putc(dev, &comcons_info.regs, c); 2297 } 2298 2299 void 2300 comcnpollc(dev_t dev, int on) 2301 { 2302 2303 } 2304 2305 #ifdef KGDB 2306 int 2307 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2308 tcflag_t cflag) 2309 { 2310 int res; 2311 2312 if (tags_are_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2313 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2314 #if !defined(DDB) 2315 return (EBUSY); /* cannot share with console */ 2316 #else 2317 comkgdbregs = *regsp; 2318 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2319 #endif 2320 } else { 2321 comkgdbregs = *regsp; 2322 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2323 if (res) 2324 return (res); 2325 2326 /* 2327 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2328 * expects this to be initialized 2329 */ 2330 cn_init_magic(&com_cnm_state); 2331 cn_set_magic("\047\001"); 2332 } 2333 2334 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2335 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2336 2337 return (0); 2338 } 2339 2340 int 2341 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2342 int frequency, int type, tcflag_t cflag) 2343 { 2344 struct com_regs regs; 2345 2346 regs.cr_iot = iot; 2347 regs.cr_nports = COM_NPORTS; 2348 regs.cr_iobase = iobase; 2349 #ifdef COM_REGMAP 2350 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2351 #endif 2352 2353 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2354 } 2355 2356 /* ARGSUSED */ 2357 int 2358 com_kgdb_getc(void *arg) 2359 { 2360 2361 return (com_common_getc(NODEV, &comkgdbregs)); 2362 } 2363 2364 /* ARGSUSED */ 2365 void 2366 com_kgdb_putc(void *arg, int c) 2367 { 2368 2369 com_common_putc(NODEV, &comkgdbregs, c); 2370 } 2371 #endif /* KGDB */ 2372 2373 /* helper function to identify the com ports used by 2374 console or KGDB (and not yet autoconf attached) */ 2375 int 2376 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2377 { 2378 bus_space_handle_t help; 2379 2380 if (!comconsattached && 2381 tags_are_equal(iot, comcons_info.regs.cr_iot) && 2382 iobase == comcons_info.regs.cr_iobase) 2383 help = comcons_info.regs.cr_ioh; 2384 #ifdef KGDB 2385 else if (!com_kgdb_attached && 2386 tags_are_equal(iot, comkgdbregs.cr_iot) && iobase == comkgdbregs.cr_iobase) 2387 help = comkgdbregs.cr_ioh; 2388 #endif 2389 else 2390 return (0); 2391 2392 if (ioh) 2393 *ioh = help; 2394 return (1); 2395 } 2396 2397 /* 2398 * this routine exists to serve as a shutdown hook for systems that 2399 * have firmware which doesn't interact properly with a com device in 2400 * FIFO mode. 2401 */ 2402 bool 2403 com_cleanup(device_t self, int how) 2404 { 2405 struct com_softc *sc = device_private(self); 2406 2407 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2408 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2409 2410 return true; 2411 } 2412 2413 bool 2414 com_suspend(device_t self, const pmf_qual_t *qual) 2415 { 2416 struct com_softc *sc = device_private(self); 2417 2418 #if 0 2419 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2420 cn_tab = &comcons_suspend; 2421 #endif 2422 2423 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2424 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2425 2426 return true; 2427 } 2428 2429 bool 2430 com_resume(device_t self, const pmf_qual_t *qual) 2431 { 2432 struct com_softc *sc = device_private(self); 2433 2434 mutex_spin_enter(&sc->sc_lock); 2435 com_loadchannelregs(sc); 2436 mutex_spin_exit(&sc->sc_lock); 2437 2438 return true; 2439 } 2440