1 /* $NetBSD: com.c,v 1.327 2014/08/10 16:44:35 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.327 2014/08/10 16:44:35 tls Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 .d_open = comopen, 219 .d_close = comclose, 220 .d_read = comread, 221 .d_write = comwrite, 222 .d_ioctl = comioctl, 223 .d_stop = comstop, 224 .d_tty = comtty, 225 .d_poll = compoll, 226 .d_mmap = nommap, 227 .d_kqfilter = ttykqfilter, 228 .d_discard = nodiscard, 229 .d_flag = D_TTY 230 }; 231 232 /* 233 * Make this an option variable one can patch. 234 * But be warned: this must be a power of 2! 235 */ 236 u_int com_rbuf_size = COM_RING_SIZE; 237 238 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 239 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 240 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 241 242 static int comconsattached; 243 static struct cnm_state com_cnm_state; 244 245 #ifdef KGDB 246 #include <sys/kgdb.h> 247 248 static struct com_regs comkgdbregs; 249 static int com_kgdb_attached; 250 251 int com_kgdb_getc(void *); 252 void com_kgdb_putc(void *, int); 253 #endif /* KGDB */ 254 255 #ifdef COM_REGMAP 256 /* initializer for typical 16550-ish hardware */ 257 #define COM_REG_16550 { \ 258 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 259 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 260 /* 16750-specific register set, additional UART status register */ 261 #define COM_REG_16750 { \ 262 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 263 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 265 266 #ifdef COM_16750 267 const bus_size_t com_std_map[32] = COM_REG_16750; 268 #else 269 const bus_size_t com_std_map[16] = COM_REG_16550; 270 #endif /* COM_16750 */ 271 #endif /* COM_REGMAP */ 272 273 #define COMUNIT_MASK 0x7ffff 274 #define COMDIALOUT_MASK 0x80000 275 276 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 277 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 278 279 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 280 device_is_active((sc)->sc_dev)) 281 282 #define BR BUS_SPACE_BARRIER_READ 283 #define BW BUS_SPACE_BARRIER_WRITE 284 #define COM_BARRIER(r, f) \ 285 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 286 287 /*ARGSUSED*/ 288 int 289 comspeed(long speed, long frequency, int type) 290 { 291 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 292 293 int x, err; 294 int divisor = 16; 295 296 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 297 divisor = 13; 298 } 299 300 if (speed == 0) 301 return (0); 302 if (speed < 0) 303 return (-1); 304 x = divrnd(frequency / divisor, speed); 305 if (x <= 0) 306 return (-1); 307 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 308 if (err < 0) 309 err = -err; 310 if (err > COM_TOLERANCE) 311 return (-1); 312 return (x); 313 314 #undef divrnd 315 } 316 317 #ifdef COM_DEBUG 318 int com_debug = 0; 319 320 void comstatus(struct com_softc *, const char *); 321 void 322 comstatus(struct com_softc *sc, const char *str) 323 { 324 struct tty *tp = sc->sc_tty; 325 326 aprint_normal_dev(sc->sc_dev, 327 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 328 str, 329 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 331 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 333 sc->sc_tx_stopped ? '+' : '-'); 334 335 aprint_normal_dev(sc->sc_dev, 336 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 337 str, 338 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 339 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 340 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 341 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 342 sc->sc_rx_flags); 343 } 344 #endif 345 346 int 347 com_probe_subr(struct com_regs *regs) 348 { 349 350 /* force access to id reg */ 351 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 352 CSR_WRITE_1(regs, COM_REG_IIR, 0); 353 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 354 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 355 return (0); 356 357 return (1); 358 } 359 360 int 361 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 362 { 363 struct com_regs regs; 364 365 regs.cr_iot = iot; 366 regs.cr_ioh = ioh; 367 #ifdef COM_REGMAP 368 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 369 #endif 370 371 return com_probe_subr(®s); 372 } 373 374 /* 375 * No locking in this routine; it is only called during attach, 376 * or with the port already locked. 377 */ 378 static void 379 com_enable_debugport(struct com_softc *sc) 380 { 381 382 /* Turn on line break interrupt, set carrier. */ 383 sc->sc_ier = IER_ERXRDY; 384 if (sc->sc_type == COM_TYPE_PXA2x0) 385 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 386 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 387 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 388 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 389 } 390 391 void 392 com_attach_subr(struct com_softc *sc) 393 { 394 struct com_regs *regsp = &sc->sc_regs; 395 struct tty *tp; 396 #if defined(COM_16650) || defined(COM_16750) 397 u_int8_t lcr; 398 #endif 399 const char *fifo_msg = NULL; 400 prop_dictionary_t dict; 401 bool is_console = true; 402 403 aprint_naive("\n"); 404 405 dict = device_properties(sc->sc_dev); 406 prop_dictionary_get_bool(dict, "is_console", &is_console); 407 408 callout_init(&sc->sc_diag_callout, 0); 409 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 410 411 /* Disable interrupts before configuring the device. */ 412 if (sc->sc_type == COM_TYPE_PXA2x0) 413 sc->sc_ier = IER_EUART; 414 else 415 sc->sc_ier = 0; 416 417 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 418 419 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 420 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 421 comconsattached = 1; 422 423 if (cn_tab == NULL && comcnreattach() != 0) { 424 printf("can't re-init serial console @%lx\n", 425 (u_long)comcons_info.regs.cr_iobase); 426 } 427 428 #ifdef COM_16750 429 /* Use in comintr(). */ 430 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 431 #endif 432 433 /* Make sure the console is always "hardwired". */ 434 delay(10000); /* wait for output to finish */ 435 if (is_console) { 436 SET(sc->sc_hwflags, COM_HW_CONSOLE); 437 } 438 439 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 440 } 441 442 /* Probe for FIFO */ 443 switch (sc->sc_type) { 444 case COM_TYPE_HAYESP: 445 goto fifodone; 446 447 case COM_TYPE_AU1x00: 448 sc->sc_fifolen = 16; 449 fifo_msg = "Au1X00 UART, working fifo"; 450 SET(sc->sc_hwflags, COM_HW_FIFO); 451 goto fifodelay; 452 453 case COM_TYPE_16550_NOERS: 454 sc->sc_fifolen = 16; 455 fifo_msg = "ns16650, no ERS, working fifo"; 456 SET(sc->sc_hwflags, COM_HW_FIFO); 457 goto fifodelay; 458 459 case COM_TYPE_OMAP: 460 sc->sc_fifolen = 64; 461 fifo_msg = "OMAP UART, working fifo"; 462 SET(sc->sc_hwflags, COM_HW_FIFO); 463 goto fifodelay; 464 } 465 466 sc->sc_fifolen = 1; 467 /* look for a NS 16550AF UART with FIFOs */ 468 CSR_WRITE_1(regsp, COM_REG_FIFO, 469 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 470 delay(100); 471 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 472 == IIR_FIFO_MASK) 473 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 474 == FIFO_TRIGGER_14) { 475 SET(sc->sc_hwflags, COM_HW_FIFO); 476 477 #ifdef COM_16650 478 /* 479 * IIR changes into the EFR if LCR is set to LCR_EERS 480 * on 16650s. We also know IIR != 0 at this point. 481 * Write 0 into the EFR, and read it. If the result 482 * is 0, we have a 16650. 483 * 484 * Older 16650s were broken; the test to detect them 485 * is taken from the Linux driver. Apparently 486 * setting DLAB enable gives access to the EFR on 487 * these chips. 488 */ 489 lcr = CSR_READ_1(regsp, COM_REG_LCR); 490 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 491 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 492 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 493 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 494 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 495 CLR(sc->sc_hwflags, COM_HW_FIFO); 496 sc->sc_fifolen = 0; 497 } else { 498 SET(sc->sc_hwflags, COM_HW_FLOW); 499 sc->sc_fifolen = 32; 500 } 501 } else 502 #endif 503 sc->sc_fifolen = 16; 504 505 #ifdef COM_16750 506 /* 507 * TL16C750 can enable 64byte FIFO, only when DLAB 508 * is 1. However, some 16750 may always enable. For 509 * example, restrictions according to DLAB in a data 510 * sheet for SC16C750 were not described. 511 * Please enable 'options COM_16650', supposing you 512 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 513 * should become effective. 514 */ 515 uint8_t iir1, iir2; 516 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 517 518 lcr = CSR_READ_1(regsp, COM_REG_LCR); 519 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 520 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 521 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 522 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 523 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 524 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 525 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 526 527 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 528 529 if (!ISSET(iir1, IIR_64B_FIFO) && 530 ISSET(iir2, IIR_64B_FIFO)) { 531 /* It is TL16C750. */ 532 sc->sc_fifolen = 64; 533 SET(sc->sc_hwflags, COM_HW_AFE); 534 } else 535 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 536 #endif 537 538 #ifdef COM_16650 539 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 540 if (sc->sc_fifolen == 0) 541 fifo_msg = "st16650, broken fifo"; 542 else if (sc->sc_fifolen == 32) 543 fifo_msg = "st16650a, working fifo"; 544 else 545 #endif 546 #ifdef COM_16750 547 if (sc->sc_fifolen == 64) 548 fifo_msg = "tl16c750, working fifo"; 549 else 550 #endif 551 fifo_msg = "ns16550a, working fifo"; 552 } else 553 fifo_msg = "ns16550, broken fifo"; 554 else 555 fifo_msg = "ns8250 or ns16450, no fifo"; 556 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 557 fifodelay: 558 /* 559 * Some chips will clear down both Tx and Rx FIFOs when zero is 560 * written to com_fifo. If this chip is the console, writing zero 561 * results in some of the chip/FIFO description being lost, so delay 562 * printing it until now. 563 */ 564 delay(10); 565 aprint_normal(": %s\n", fifo_msg); 566 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 567 sc->sc_fifolen = 1; 568 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 569 } 570 571 fifodone: 572 573 tp = tty_alloc(); 574 tp->t_oproc = comstart; 575 tp->t_param = comparam; 576 tp->t_hwiflow = comhwiflow; 577 tp->t_softc = sc; 578 579 sc->sc_tty = tp; 580 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 581 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 582 sc->sc_rbavail = com_rbuf_size; 583 if (sc->sc_rbuf == NULL) { 584 aprint_error_dev(sc->sc_dev, 585 "unable to allocate ring buffer\n"); 586 return; 587 } 588 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 589 590 tty_attach(tp); 591 592 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 593 SET(sc->sc_mcr, MCR_IENABLE); 594 595 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 596 int maj; 597 598 /* locate the major number */ 599 maj = cdevsw_lookup_major(&com_cdevsw); 600 601 tp->t_dev = cn_tab->cn_dev = makedev(maj, 602 device_unit(sc->sc_dev)); 603 604 aprint_normal_dev(sc->sc_dev, "console\n"); 605 } 606 607 #ifdef KGDB 608 /* 609 * Allow kgdb to "take over" this port. If this is 610 * not the console and is the kgdb device, it has 611 * exclusive use. If it's the console _and_ the 612 * kgdb device, it doesn't. 613 */ 614 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 615 regsp->cr_iobase == comkgdbregs.cr_iobase) { 616 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 617 com_kgdb_attached = 1; 618 619 SET(sc->sc_hwflags, COM_HW_KGDB); 620 } 621 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 622 } 623 #endif 624 625 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 626 627 #ifdef RND_COM 628 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 629 RND_TYPE_TTY, RND_FLAG_DEFAULT); 630 #endif 631 632 /* if there are no enable/disable functions, assume the device 633 is always enabled */ 634 if (!sc->enable) 635 sc->enabled = 1; 636 637 com_config(sc); 638 639 SET(sc->sc_hwflags, COM_HW_DEV_OK); 640 } 641 642 void 643 com_config(struct com_softc *sc) 644 { 645 struct com_regs *regsp = &sc->sc_regs; 646 647 /* Disable interrupts before configuring the device. */ 648 if (sc->sc_type == COM_TYPE_PXA2x0) 649 sc->sc_ier = IER_EUART; 650 else 651 sc->sc_ier = 0; 652 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 653 (void) CSR_READ_1(regsp, COM_REG_IIR); 654 655 #ifdef COM_HAYESP 656 /* Look for a Hayes ESP board. */ 657 if (sc->sc_type == COM_TYPE_HAYESP) { 658 659 /* Set 16550 compatibility mode */ 660 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 661 HAYESP_SETMODE); 662 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 663 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 664 HAYESP_MODE_SCALE); 665 666 /* Set RTS/CTS flow control */ 667 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 668 HAYESP_SETFLOWTYPE); 669 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 670 HAYESP_FLOW_RTS); 671 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 672 HAYESP_FLOW_CTS); 673 674 /* Set flow control levels */ 675 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 676 HAYESP_SETRXFLOW); 677 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 678 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 679 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 680 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 681 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 682 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 683 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 684 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 685 } 686 #endif 687 688 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 689 com_enable_debugport(sc); 690 } 691 692 #if 0 693 static int 694 comcngetc_detached(dev_t dev) 695 { 696 return 0; 697 } 698 699 static void 700 comcnputc_detached(dev_t dev, int c) 701 { 702 } 703 #endif 704 705 int 706 com_detach(device_t self, int flags) 707 { 708 struct com_softc *sc = device_private(self); 709 int maj, mn; 710 711 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 712 return EBUSY; 713 714 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 715 (flags & DETACH_SHUTDOWN) != 0) 716 return EBUSY; 717 718 if (sc->disable != NULL && sc->enabled != 0) { 719 (*sc->disable)(sc); 720 sc->enabled = 0; 721 } 722 723 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 724 comconsattached = 0; 725 cn_tab = NULL; 726 } 727 728 /* locate the major number */ 729 maj = cdevsw_lookup_major(&com_cdevsw); 730 731 /* Nuke the vnodes for any open instances. */ 732 mn = device_unit(self); 733 vdevgone(maj, mn, mn, VCHR); 734 735 mn |= COMDIALOUT_MASK; 736 vdevgone(maj, mn, mn, VCHR); 737 738 if (sc->sc_rbuf == NULL) { 739 /* 740 * Ring buffer allocation failed in the com_attach_subr, 741 * only the tty is allocated, and nothing else. 742 */ 743 tty_free(sc->sc_tty); 744 return 0; 745 } 746 747 /* Free the receive buffer. */ 748 free(sc->sc_rbuf, M_DEVBUF); 749 750 /* Detach and free the tty. */ 751 tty_detach(sc->sc_tty); 752 tty_free(sc->sc_tty); 753 754 /* Unhook the soft interrupt handler. */ 755 softint_disestablish(sc->sc_si); 756 757 #ifdef RND_COM 758 /* Unhook the entropy source. */ 759 rnd_detach_source(&sc->rnd_source); 760 #endif 761 callout_destroy(&sc->sc_diag_callout); 762 763 /* Destroy the lock. */ 764 mutex_destroy(&sc->sc_lock); 765 766 return (0); 767 } 768 769 void 770 com_shutdown(struct com_softc *sc) 771 { 772 struct tty *tp = sc->sc_tty; 773 774 mutex_spin_enter(&sc->sc_lock); 775 776 /* If we were asserting flow control, then deassert it. */ 777 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 778 com_hwiflow(sc); 779 780 /* Clear any break condition set with TIOCSBRK. */ 781 com_break(sc, 0); 782 783 /* 784 * Hang up if necessary. Wait a bit, so the other side has time to 785 * notice even if we immediately open the port again. 786 * Avoid tsleeping above splhigh(). 787 */ 788 if (ISSET(tp->t_cflag, HUPCL)) { 789 com_modem(sc, 0); 790 mutex_spin_exit(&sc->sc_lock); 791 /* XXX will only timeout */ 792 (void) kpause(ttclos, false, hz, NULL); 793 mutex_spin_enter(&sc->sc_lock); 794 } 795 796 /* Turn off interrupts. */ 797 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 798 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 799 if (sc->sc_type == COM_TYPE_PXA2x0) 800 sc->sc_ier |= IER_ERXTOUT; 801 } else 802 sc->sc_ier = 0; 803 804 if (sc->sc_type == COM_TYPE_PXA2x0) 805 sc->sc_ier |= IER_EUART; 806 807 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 808 809 mutex_spin_exit(&sc->sc_lock); 810 811 if (sc->disable) { 812 #ifdef DIAGNOSTIC 813 if (!sc->enabled) 814 panic("com_shutdown: not enabled?"); 815 #endif 816 (*sc->disable)(sc); 817 sc->enabled = 0; 818 } 819 } 820 821 int 822 comopen(dev_t dev, int flag, int mode, struct lwp *l) 823 { 824 struct com_softc *sc; 825 struct tty *tp; 826 int s; 827 int error; 828 829 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 830 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 831 sc->sc_rbuf == NULL) 832 return (ENXIO); 833 834 if (!device_is_active(sc->sc_dev)) 835 return (ENXIO); 836 837 #ifdef KGDB 838 /* 839 * If this is the kgdb port, no other use is permitted. 840 */ 841 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 842 return (EBUSY); 843 #endif 844 845 tp = sc->sc_tty; 846 847 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 848 return (EBUSY); 849 850 s = spltty(); 851 852 /* 853 * Do the following iff this is a first open. 854 */ 855 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 856 struct termios t; 857 858 tp->t_dev = dev; 859 860 if (sc->enable) { 861 if ((*sc->enable)(sc)) { 862 splx(s); 863 aprint_error_dev(sc->sc_dev, 864 "device enable failed\n"); 865 return (EIO); 866 } 867 mutex_spin_enter(&sc->sc_lock); 868 sc->enabled = 1; 869 com_config(sc); 870 } else { 871 mutex_spin_enter(&sc->sc_lock); 872 } 873 874 /* Turn on interrupts. */ 875 sc->sc_ier = IER_ERXRDY | IER_ERLS; 876 if (!ISSET(tp->t_cflag, CLOCAL)) 877 sc->sc_ier |= IER_EMSC; 878 879 if (sc->sc_type == COM_TYPE_PXA2x0) 880 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 881 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 882 883 /* Fetch the current modem control status, needed later. */ 884 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 885 886 /* Clear PPS capture state on first open. */ 887 mutex_spin_enter(&timecounter_lock); 888 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 889 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 890 pps_init(&sc->sc_pps_state); 891 mutex_spin_exit(&timecounter_lock); 892 893 mutex_spin_exit(&sc->sc_lock); 894 895 /* 896 * Initialize the termios status to the defaults. Add in the 897 * sticky bits from TIOCSFLAGS. 898 */ 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 900 t.c_ospeed = comcons_info.rate; 901 t.c_cflag = comcons_info.cflag; 902 } else { 903 t.c_ospeed = TTYDEF_SPEED; 904 t.c_cflag = TTYDEF_CFLAG; 905 } 906 t.c_ispeed = t.c_ospeed; 907 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 908 SET(t.c_cflag, CLOCAL); 909 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 910 SET(t.c_cflag, CRTSCTS); 911 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 912 SET(t.c_cflag, MDMBUF); 913 /* Make sure comparam() will do something. */ 914 tp->t_ospeed = 0; 915 (void) comparam(tp, &t); 916 tp->t_iflag = TTYDEF_IFLAG; 917 tp->t_oflag = TTYDEF_OFLAG; 918 tp->t_lflag = TTYDEF_LFLAG; 919 ttychars(tp); 920 ttsetwater(tp); 921 922 mutex_spin_enter(&sc->sc_lock); 923 924 /* 925 * Turn on DTR. We must always do this, even if carrier is not 926 * present, because otherwise we'd have to use TIOCSDTR 927 * immediately after setting CLOCAL, which applications do not 928 * expect. We always assert DTR while the device is open 929 * unless explicitly requested to deassert it. 930 */ 931 com_modem(sc, 1); 932 933 /* Clear the input ring, and unblock. */ 934 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 935 sc->sc_rbavail = com_rbuf_size; 936 com_iflush(sc); 937 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 938 com_hwiflow(sc); 939 940 #ifdef COM_DEBUG 941 if (com_debug) 942 comstatus(sc, "comopen "); 943 #endif 944 945 mutex_spin_exit(&sc->sc_lock); 946 } 947 948 splx(s); 949 950 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 951 if (error) 952 goto bad; 953 954 error = (*tp->t_linesw->l_open)(dev, tp); 955 if (error) 956 goto bad; 957 958 return (0); 959 960 bad: 961 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 962 /* 963 * We failed to open the device, and nobody else had it opened. 964 * Clean up the state as appropriate. 965 */ 966 com_shutdown(sc); 967 } 968 969 return (error); 970 } 971 972 int 973 comclose(dev_t dev, int flag, int mode, struct lwp *l) 974 { 975 struct com_softc *sc = 976 device_lookup_private(&com_cd, COMUNIT(dev)); 977 struct tty *tp = sc->sc_tty; 978 979 /* XXX This is for cons.c. */ 980 if (!ISSET(tp->t_state, TS_ISOPEN)) 981 return (0); 982 983 (*tp->t_linesw->l_close)(tp, flag); 984 ttyclose(tp); 985 986 if (COM_ISALIVE(sc) == 0) 987 return (0); 988 989 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 990 /* 991 * Although we got a last close, the device may still be in 992 * use; e.g. if this was the dialout node, and there are still 993 * processes waiting for carrier on the non-dialout node. 994 */ 995 com_shutdown(sc); 996 } 997 998 return (0); 999 } 1000 1001 int 1002 comread(dev_t dev, struct uio *uio, int flag) 1003 { 1004 struct com_softc *sc = 1005 device_lookup_private(&com_cd, COMUNIT(dev)); 1006 struct tty *tp = sc->sc_tty; 1007 1008 if (COM_ISALIVE(sc) == 0) 1009 return (EIO); 1010 1011 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1012 } 1013 1014 int 1015 comwrite(dev_t dev, struct uio *uio, int flag) 1016 { 1017 struct com_softc *sc = 1018 device_lookup_private(&com_cd, COMUNIT(dev)); 1019 struct tty *tp = sc->sc_tty; 1020 1021 if (COM_ISALIVE(sc) == 0) 1022 return (EIO); 1023 1024 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1025 } 1026 1027 int 1028 compoll(dev_t dev, int events, struct lwp *l) 1029 { 1030 struct com_softc *sc = 1031 device_lookup_private(&com_cd, COMUNIT(dev)); 1032 struct tty *tp = sc->sc_tty; 1033 1034 if (COM_ISALIVE(sc) == 0) 1035 return (POLLHUP); 1036 1037 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1038 } 1039 1040 struct tty * 1041 comtty(dev_t dev) 1042 { 1043 struct com_softc *sc = 1044 device_lookup_private(&com_cd, COMUNIT(dev)); 1045 struct tty *tp = sc->sc_tty; 1046 1047 return (tp); 1048 } 1049 1050 int 1051 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1052 { 1053 struct com_softc *sc; 1054 struct tty *tp; 1055 int error; 1056 1057 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1058 if (sc == NULL) 1059 return ENXIO; 1060 if (COM_ISALIVE(sc) == 0) 1061 return (EIO); 1062 1063 tp = sc->sc_tty; 1064 1065 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1066 if (error != EPASSTHROUGH) 1067 return (error); 1068 1069 error = ttioctl(tp, cmd, data, flag, l); 1070 if (error != EPASSTHROUGH) 1071 return (error); 1072 1073 error = 0; 1074 switch (cmd) { 1075 case TIOCSFLAGS: 1076 error = kauth_authorize_device_tty(l->l_cred, 1077 KAUTH_DEVICE_TTY_PRIVSET, tp); 1078 break; 1079 default: 1080 /* nothing */ 1081 break; 1082 } 1083 if (error) { 1084 return error; 1085 } 1086 1087 mutex_spin_enter(&sc->sc_lock); 1088 1089 switch (cmd) { 1090 case TIOCSBRK: 1091 com_break(sc, 1); 1092 break; 1093 1094 case TIOCCBRK: 1095 com_break(sc, 0); 1096 break; 1097 1098 case TIOCSDTR: 1099 com_modem(sc, 1); 1100 break; 1101 1102 case TIOCCDTR: 1103 com_modem(sc, 0); 1104 break; 1105 1106 case TIOCGFLAGS: 1107 *(int *)data = sc->sc_swflags; 1108 break; 1109 1110 case TIOCSFLAGS: 1111 sc->sc_swflags = *(int *)data; 1112 break; 1113 1114 case TIOCMSET: 1115 case TIOCMBIS: 1116 case TIOCMBIC: 1117 tiocm_to_com(sc, cmd, *(int *)data); 1118 break; 1119 1120 case TIOCMGET: 1121 *(int *)data = com_to_tiocm(sc); 1122 break; 1123 1124 case PPS_IOC_CREATE: 1125 case PPS_IOC_DESTROY: 1126 case PPS_IOC_GETPARAMS: 1127 case PPS_IOC_SETPARAMS: 1128 case PPS_IOC_GETCAP: 1129 case PPS_IOC_FETCH: 1130 #ifdef PPS_SYNC 1131 case PPS_IOC_KCBIND: 1132 #endif 1133 mutex_spin_enter(&timecounter_lock); 1134 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1135 mutex_spin_exit(&timecounter_lock); 1136 break; 1137 1138 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1139 mutex_spin_enter(&timecounter_lock); 1140 #ifndef PPS_TRAILING_EDGE 1141 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1142 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1143 #else 1144 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1145 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1146 #endif 1147 mutex_spin_exit(&timecounter_lock); 1148 break; 1149 1150 default: 1151 error = EPASSTHROUGH; 1152 break; 1153 } 1154 1155 mutex_spin_exit(&sc->sc_lock); 1156 1157 #ifdef COM_DEBUG 1158 if (com_debug) 1159 comstatus(sc, "comioctl "); 1160 #endif 1161 1162 return (error); 1163 } 1164 1165 integrate void 1166 com_schedrx(struct com_softc *sc) 1167 { 1168 1169 sc->sc_rx_ready = 1; 1170 1171 /* Wake up the poller. */ 1172 softint_schedule(sc->sc_si); 1173 } 1174 1175 void 1176 com_break(struct com_softc *sc, int onoff) 1177 { 1178 1179 if (onoff) 1180 SET(sc->sc_lcr, LCR_SBREAK); 1181 else 1182 CLR(sc->sc_lcr, LCR_SBREAK); 1183 1184 if (!sc->sc_heldchange) { 1185 if (sc->sc_tx_busy) { 1186 sc->sc_heldtbc = sc->sc_tbc; 1187 sc->sc_tbc = 0; 1188 sc->sc_heldchange = 1; 1189 } else 1190 com_loadchannelregs(sc); 1191 } 1192 } 1193 1194 void 1195 com_modem(struct com_softc *sc, int onoff) 1196 { 1197 1198 if (sc->sc_mcr_dtr == 0) 1199 return; 1200 1201 if (onoff) 1202 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1203 else 1204 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1205 1206 if (!sc->sc_heldchange) { 1207 if (sc->sc_tx_busy) { 1208 sc->sc_heldtbc = sc->sc_tbc; 1209 sc->sc_tbc = 0; 1210 sc->sc_heldchange = 1; 1211 } else 1212 com_loadchannelregs(sc); 1213 } 1214 } 1215 1216 void 1217 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1218 { 1219 u_char combits; 1220 1221 combits = 0; 1222 if (ISSET(ttybits, TIOCM_DTR)) 1223 SET(combits, MCR_DTR); 1224 if (ISSET(ttybits, TIOCM_RTS)) 1225 SET(combits, MCR_RTS); 1226 1227 switch (how) { 1228 case TIOCMBIC: 1229 CLR(sc->sc_mcr, combits); 1230 break; 1231 1232 case TIOCMBIS: 1233 SET(sc->sc_mcr, combits); 1234 break; 1235 1236 case TIOCMSET: 1237 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1238 SET(sc->sc_mcr, combits); 1239 break; 1240 } 1241 1242 if (!sc->sc_heldchange) { 1243 if (sc->sc_tx_busy) { 1244 sc->sc_heldtbc = sc->sc_tbc; 1245 sc->sc_tbc = 0; 1246 sc->sc_heldchange = 1; 1247 } else 1248 com_loadchannelregs(sc); 1249 } 1250 } 1251 1252 int 1253 com_to_tiocm(struct com_softc *sc) 1254 { 1255 u_char combits; 1256 int ttybits = 0; 1257 1258 combits = sc->sc_mcr; 1259 if (ISSET(combits, MCR_DTR)) 1260 SET(ttybits, TIOCM_DTR); 1261 if (ISSET(combits, MCR_RTS)) 1262 SET(ttybits, TIOCM_RTS); 1263 1264 combits = sc->sc_msr; 1265 if (ISSET(combits, MSR_DCD)) 1266 SET(ttybits, TIOCM_CD); 1267 if (ISSET(combits, MSR_CTS)) 1268 SET(ttybits, TIOCM_CTS); 1269 if (ISSET(combits, MSR_DSR)) 1270 SET(ttybits, TIOCM_DSR); 1271 if (ISSET(combits, MSR_RI | MSR_TERI)) 1272 SET(ttybits, TIOCM_RI); 1273 1274 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1275 SET(ttybits, TIOCM_LE); 1276 1277 return (ttybits); 1278 } 1279 1280 static u_char 1281 cflag2lcr(tcflag_t cflag) 1282 { 1283 u_char lcr = 0; 1284 1285 switch (ISSET(cflag, CSIZE)) { 1286 case CS5: 1287 SET(lcr, LCR_5BITS); 1288 break; 1289 case CS6: 1290 SET(lcr, LCR_6BITS); 1291 break; 1292 case CS7: 1293 SET(lcr, LCR_7BITS); 1294 break; 1295 case CS8: 1296 SET(lcr, LCR_8BITS); 1297 break; 1298 } 1299 if (ISSET(cflag, PARENB)) { 1300 SET(lcr, LCR_PENAB); 1301 if (!ISSET(cflag, PARODD)) 1302 SET(lcr, LCR_PEVEN); 1303 } 1304 if (ISSET(cflag, CSTOPB)) 1305 SET(lcr, LCR_STOPB); 1306 1307 return (lcr); 1308 } 1309 1310 int 1311 comparam(struct tty *tp, struct termios *t) 1312 { 1313 struct com_softc *sc = 1314 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1315 int ospeed; 1316 u_char lcr; 1317 1318 if (COM_ISALIVE(sc) == 0) 1319 return (EIO); 1320 1321 #ifdef COM_HAYESP 1322 if (sc->sc_type == COM_TYPE_HAYESP) { 1323 int prescaler, speed; 1324 1325 /* 1326 * Calculate UART clock prescaler. It should be in 1327 * range of 0 .. 3. 1328 */ 1329 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1330 prescaler++, speed /= 2) 1331 if ((ospeed = comspeed(speed, sc->sc_frequency, 1332 sc->sc_type)) > 0) 1333 break; 1334 1335 if (prescaler == 4) 1336 return (EINVAL); 1337 sc->sc_prescaler = prescaler; 1338 } else 1339 #endif 1340 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1341 1342 /* Check requested parameters. */ 1343 if (ospeed < 0) 1344 return (EINVAL); 1345 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1346 return (EINVAL); 1347 1348 /* 1349 * For the console, always force CLOCAL and !HUPCL, so that the port 1350 * is always active. 1351 */ 1352 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1353 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1354 SET(t->c_cflag, CLOCAL); 1355 CLR(t->c_cflag, HUPCL); 1356 } 1357 1358 /* 1359 * If there were no changes, don't do anything. This avoids dropping 1360 * input and improves performance when all we did was frob things like 1361 * VMIN and VTIME. 1362 */ 1363 if (tp->t_ospeed == t->c_ospeed && 1364 tp->t_cflag == t->c_cflag) 1365 return (0); 1366 1367 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1368 1369 mutex_spin_enter(&sc->sc_lock); 1370 1371 sc->sc_lcr = lcr; 1372 1373 /* 1374 * If we're not in a mode that assumes a connection is present, then 1375 * ignore carrier changes. 1376 */ 1377 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1378 sc->sc_msr_dcd = 0; 1379 else 1380 sc->sc_msr_dcd = MSR_DCD; 1381 /* 1382 * Set the flow control pins depending on the current flow control 1383 * mode. 1384 */ 1385 if (ISSET(t->c_cflag, CRTSCTS)) { 1386 sc->sc_mcr_dtr = MCR_DTR; 1387 sc->sc_mcr_rts = MCR_RTS; 1388 sc->sc_msr_cts = MSR_CTS; 1389 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1390 SET(sc->sc_mcr, MCR_AFE); 1391 } else { 1392 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1393 } 1394 } else if (ISSET(t->c_cflag, MDMBUF)) { 1395 /* 1396 * For DTR/DCD flow control, make sure we don't toggle DTR for 1397 * carrier detection. 1398 */ 1399 sc->sc_mcr_dtr = 0; 1400 sc->sc_mcr_rts = MCR_DTR; 1401 sc->sc_msr_cts = MSR_DCD; 1402 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1403 CLR(sc->sc_mcr, MCR_AFE); 1404 } else { 1405 sc->sc_efr = 0; 1406 } 1407 } else { 1408 /* 1409 * If no flow control, then always set RTS. This will make 1410 * the other side happy if it mistakenly thinks we're doing 1411 * RTS/CTS flow control. 1412 */ 1413 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1414 sc->sc_mcr_rts = 0; 1415 sc->sc_msr_cts = 0; 1416 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1417 CLR(sc->sc_mcr, MCR_AFE); 1418 } else { 1419 sc->sc_efr = 0; 1420 } 1421 if (ISSET(sc->sc_mcr, MCR_DTR)) 1422 SET(sc->sc_mcr, MCR_RTS); 1423 else 1424 CLR(sc->sc_mcr, MCR_RTS); 1425 } 1426 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1427 1428 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1429 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1430 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1431 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1432 1433 sc->sc_dlbl = ospeed; 1434 sc->sc_dlbh = ospeed >> 8; 1435 1436 /* 1437 * Set the FIFO threshold based on the receive speed. 1438 * 1439 * * If it's a low speed, it's probably a mouse or some other 1440 * interactive device, so set the threshold low. 1441 * * If it's a high speed, trim the trigger level down to prevent 1442 * overflows. 1443 * * Otherwise set it a bit higher. 1444 */ 1445 if (sc->sc_type == COM_TYPE_HAYESP) 1446 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1447 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1448 if (t->c_ospeed <= 1200) 1449 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1450 else if (t->c_ospeed <= 38400) 1451 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1452 else 1453 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1454 } else 1455 sc->sc_fifo = 0; 1456 1457 /* And copy to tty. */ 1458 tp->t_ispeed = t->c_ospeed; 1459 tp->t_ospeed = t->c_ospeed; 1460 tp->t_cflag = t->c_cflag; 1461 1462 if (!sc->sc_heldchange) { 1463 if (sc->sc_tx_busy) { 1464 sc->sc_heldtbc = sc->sc_tbc; 1465 sc->sc_tbc = 0; 1466 sc->sc_heldchange = 1; 1467 } else 1468 com_loadchannelregs(sc); 1469 } 1470 1471 if (!ISSET(t->c_cflag, CHWFLOW)) { 1472 /* Disable the high water mark. */ 1473 sc->sc_r_hiwat = 0; 1474 sc->sc_r_lowat = 0; 1475 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1476 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1477 com_schedrx(sc); 1478 } 1479 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1480 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1481 com_hwiflow(sc); 1482 } 1483 } else { 1484 sc->sc_r_hiwat = com_rbuf_hiwat; 1485 sc->sc_r_lowat = com_rbuf_lowat; 1486 } 1487 1488 mutex_spin_exit(&sc->sc_lock); 1489 1490 /* 1491 * Update the tty layer's idea of the carrier bit, in case we changed 1492 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1493 * explicit request. 1494 */ 1495 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1496 1497 #ifdef COM_DEBUG 1498 if (com_debug) 1499 comstatus(sc, "comparam "); 1500 #endif 1501 1502 if (!ISSET(t->c_cflag, CHWFLOW)) { 1503 if (sc->sc_tx_stopped) { 1504 sc->sc_tx_stopped = 0; 1505 comstart(tp); 1506 } 1507 } 1508 1509 return (0); 1510 } 1511 1512 void 1513 com_iflush(struct com_softc *sc) 1514 { 1515 struct com_regs *regsp = &sc->sc_regs; 1516 #ifdef DIAGNOSTIC 1517 int reg; 1518 #endif 1519 int timo; 1520 1521 #ifdef DIAGNOSTIC 1522 reg = 0xffff; 1523 #endif 1524 timo = 50000; 1525 /* flush any pending I/O */ 1526 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1527 && --timo) 1528 #ifdef DIAGNOSTIC 1529 reg = 1530 #else 1531 (void) 1532 #endif 1533 CSR_READ_1(regsp, COM_REG_RXDATA); 1534 #ifdef DIAGNOSTIC 1535 if (!timo) 1536 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1537 #endif 1538 1539 #ifdef COM_16750 1540 uint8_t fifo; 1541 /* 1542 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1543 * This should prevent triggering busy interrupt while 1544 * manipulating divisors. 1545 */ 1546 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1547 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1548 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1549 FIFO_XMT_RST); 1550 delay(100); 1551 #endif 1552 } 1553 1554 void 1555 com_loadchannelregs(struct com_softc *sc) 1556 { 1557 struct com_regs *regsp = &sc->sc_regs; 1558 1559 /* XXXXX necessary? */ 1560 com_iflush(sc); 1561 1562 if (sc->sc_type == COM_TYPE_PXA2x0) 1563 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1564 else 1565 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1566 1567 if (sc->sc_type == COM_TYPE_OMAP) { 1568 /* disable before changing settings */ 1569 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1570 } 1571 1572 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1573 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1574 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1575 /* no EFR on alchemy */ 1576 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1577 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1578 } 1579 if (sc->sc_type == COM_TYPE_AU1x00) { 1580 /* alchemy has single separate 16-bit clock divisor register */ 1581 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1582 (sc->sc_dlbh << 8)); 1583 } else { 1584 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1585 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1586 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1587 } 1588 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1589 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1590 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1591 #ifdef COM_HAYESP 1592 if (sc->sc_type == COM_TYPE_HAYESP) { 1593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1594 HAYESP_SETPRESCALER); 1595 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1596 sc->sc_prescaler); 1597 } 1598 #endif 1599 if (sc->sc_type == COM_TYPE_OMAP) { 1600 /* setup the fifos. the FCR value is not used as long 1601 as SCR[6] and SCR[7] are 0, which they are at reset 1602 and we never touch the SCR register */ 1603 uint8_t rx_fifo_trig = 40; 1604 uint8_t tx_fifo_trig = 60; 1605 uint8_t rx_start = 8; 1606 uint8_t rx_halt = 60; 1607 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1608 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1609 1610 /* enable access to TCR & TLR */ 1611 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1612 1613 /* write tcr and tlr values */ 1614 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1615 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1616 1617 /* disable access to TCR & TLR */ 1618 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1619 1620 /* enable again, but mode is based on speed */ 1621 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1622 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1623 } else { 1624 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1625 } 1626 } 1627 1628 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1629 } 1630 1631 int 1632 comhwiflow(struct tty *tp, int block) 1633 { 1634 struct com_softc *sc = 1635 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1636 1637 if (COM_ISALIVE(sc) == 0) 1638 return (0); 1639 1640 if (sc->sc_mcr_rts == 0) 1641 return (0); 1642 1643 mutex_spin_enter(&sc->sc_lock); 1644 1645 if (block) { 1646 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1647 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1648 com_hwiflow(sc); 1649 } 1650 } else { 1651 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1652 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1653 com_schedrx(sc); 1654 } 1655 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1656 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1657 com_hwiflow(sc); 1658 } 1659 } 1660 1661 mutex_spin_exit(&sc->sc_lock); 1662 return (1); 1663 } 1664 1665 /* 1666 * (un)block input via hw flowcontrol 1667 */ 1668 void 1669 com_hwiflow(struct com_softc *sc) 1670 { 1671 struct com_regs *regsp= &sc->sc_regs; 1672 1673 if (sc->sc_mcr_rts == 0) 1674 return; 1675 1676 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1677 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1678 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1679 } else { 1680 SET(sc->sc_mcr, sc->sc_mcr_rts); 1681 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1682 } 1683 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1684 } 1685 1686 1687 void 1688 comstart(struct tty *tp) 1689 { 1690 struct com_softc *sc = 1691 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1692 struct com_regs *regsp = &sc->sc_regs; 1693 int s; 1694 1695 if (COM_ISALIVE(sc) == 0) 1696 return; 1697 1698 s = spltty(); 1699 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1700 goto out; 1701 if (sc->sc_tx_stopped) 1702 goto out; 1703 if (!ttypull(tp)) 1704 goto out; 1705 1706 /* Grab the first contiguous region of buffer space. */ 1707 { 1708 u_char *tba; 1709 int tbc; 1710 1711 tba = tp->t_outq.c_cf; 1712 tbc = ndqb(&tp->t_outq, 0); 1713 1714 mutex_spin_enter(&sc->sc_lock); 1715 1716 sc->sc_tba = tba; 1717 sc->sc_tbc = tbc; 1718 } 1719 1720 SET(tp->t_state, TS_BUSY); 1721 sc->sc_tx_busy = 1; 1722 1723 /* Enable transmit completion interrupts if necessary. */ 1724 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1725 SET(sc->sc_ier, IER_ETXRDY); 1726 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1727 } 1728 1729 /* Output the first chunk of the contiguous buffer. */ 1730 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1731 u_int n; 1732 1733 n = sc->sc_tbc; 1734 if (n > sc->sc_fifolen) 1735 n = sc->sc_fifolen; 1736 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1737 sc->sc_tbc -= n; 1738 sc->sc_tba += n; 1739 } 1740 1741 mutex_spin_exit(&sc->sc_lock); 1742 out: 1743 splx(s); 1744 return; 1745 } 1746 1747 /* 1748 * Stop output on a line. 1749 */ 1750 void 1751 comstop(struct tty *tp, int flag) 1752 { 1753 struct com_softc *sc = 1754 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1755 1756 mutex_spin_enter(&sc->sc_lock); 1757 if (ISSET(tp->t_state, TS_BUSY)) { 1758 /* Stop transmitting at the next chunk. */ 1759 sc->sc_tbc = 0; 1760 sc->sc_heldtbc = 0; 1761 if (!ISSET(tp->t_state, TS_TTSTOP)) 1762 SET(tp->t_state, TS_FLUSH); 1763 } 1764 mutex_spin_exit(&sc->sc_lock); 1765 } 1766 1767 void 1768 comdiag(void *arg) 1769 { 1770 struct com_softc *sc = arg; 1771 int overflows, floods; 1772 1773 mutex_spin_enter(&sc->sc_lock); 1774 overflows = sc->sc_overflows; 1775 sc->sc_overflows = 0; 1776 floods = sc->sc_floods; 1777 sc->sc_floods = 0; 1778 sc->sc_errors = 0; 1779 mutex_spin_exit(&sc->sc_lock); 1780 1781 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1782 device_xname(sc->sc_dev), 1783 overflows, overflows == 1 ? "" : "s", 1784 floods, floods == 1 ? "" : "s"); 1785 } 1786 1787 integrate void 1788 com_rxsoft(struct com_softc *sc, struct tty *tp) 1789 { 1790 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1791 u_char *get, *end; 1792 u_int cc, scc; 1793 u_char lsr; 1794 int code; 1795 1796 end = sc->sc_ebuf; 1797 get = sc->sc_rbget; 1798 scc = cc = com_rbuf_size - sc->sc_rbavail; 1799 1800 if (cc == com_rbuf_size) { 1801 sc->sc_floods++; 1802 if (sc->sc_errors++ == 0) 1803 callout_reset(&sc->sc_diag_callout, 60 * hz, 1804 comdiag, sc); 1805 } 1806 1807 /* If not yet open, drop the entire buffer content here */ 1808 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1809 get += cc << 1; 1810 if (get >= end) 1811 get -= com_rbuf_size << 1; 1812 cc = 0; 1813 } 1814 while (cc) { 1815 code = get[0]; 1816 lsr = get[1]; 1817 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1818 if (ISSET(lsr, LSR_OE)) { 1819 sc->sc_overflows++; 1820 if (sc->sc_errors++ == 0) 1821 callout_reset(&sc->sc_diag_callout, 1822 60 * hz, comdiag, sc); 1823 } 1824 if (ISSET(lsr, LSR_BI | LSR_FE)) 1825 SET(code, TTY_FE); 1826 if (ISSET(lsr, LSR_PE)) 1827 SET(code, TTY_PE); 1828 } 1829 if ((*rint)(code, tp) == -1) { 1830 /* 1831 * The line discipline's buffer is out of space. 1832 */ 1833 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1834 /* 1835 * We're either not using flow control, or the 1836 * line discipline didn't tell us to block for 1837 * some reason. Either way, we have no way to 1838 * know when there's more space available, so 1839 * just drop the rest of the data. 1840 */ 1841 get += cc << 1; 1842 if (get >= end) 1843 get -= com_rbuf_size << 1; 1844 cc = 0; 1845 } else { 1846 /* 1847 * Don't schedule any more receive processing 1848 * until the line discipline tells us there's 1849 * space available (through comhwiflow()). 1850 * Leave the rest of the data in the input 1851 * buffer. 1852 */ 1853 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1854 } 1855 break; 1856 } 1857 get += 2; 1858 if (get >= end) 1859 get = sc->sc_rbuf; 1860 cc--; 1861 } 1862 1863 if (cc != scc) { 1864 sc->sc_rbget = get; 1865 mutex_spin_enter(&sc->sc_lock); 1866 1867 cc = sc->sc_rbavail += scc - cc; 1868 /* Buffers should be ok again, release possible block. */ 1869 if (cc >= sc->sc_r_lowat) { 1870 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1871 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1872 SET(sc->sc_ier, IER_ERXRDY); 1873 #ifdef COM_PXA2X0 1874 if (sc->sc_type == COM_TYPE_PXA2x0) 1875 SET(sc->sc_ier, IER_ERXTOUT); 1876 #endif 1877 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1878 } 1879 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1880 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1881 com_hwiflow(sc); 1882 } 1883 } 1884 mutex_spin_exit(&sc->sc_lock); 1885 } 1886 } 1887 1888 integrate void 1889 com_txsoft(struct com_softc *sc, struct tty *tp) 1890 { 1891 1892 CLR(tp->t_state, TS_BUSY); 1893 if (ISSET(tp->t_state, TS_FLUSH)) 1894 CLR(tp->t_state, TS_FLUSH); 1895 else 1896 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1897 (*tp->t_linesw->l_start)(tp); 1898 } 1899 1900 integrate void 1901 com_stsoft(struct com_softc *sc, struct tty *tp) 1902 { 1903 u_char msr, delta; 1904 1905 mutex_spin_enter(&sc->sc_lock); 1906 msr = sc->sc_msr; 1907 delta = sc->sc_msr_delta; 1908 sc->sc_msr_delta = 0; 1909 mutex_spin_exit(&sc->sc_lock); 1910 1911 if (ISSET(delta, sc->sc_msr_dcd)) { 1912 /* 1913 * Inform the tty layer that carrier detect changed. 1914 */ 1915 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1916 } 1917 1918 if (ISSET(delta, sc->sc_msr_cts)) { 1919 /* Block or unblock output according to flow control. */ 1920 if (ISSET(msr, sc->sc_msr_cts)) { 1921 sc->sc_tx_stopped = 0; 1922 (*tp->t_linesw->l_start)(tp); 1923 } else { 1924 sc->sc_tx_stopped = 1; 1925 } 1926 } 1927 1928 #ifdef COM_DEBUG 1929 if (com_debug) 1930 comstatus(sc, "com_stsoft"); 1931 #endif 1932 } 1933 1934 void 1935 comsoft(void *arg) 1936 { 1937 struct com_softc *sc = arg; 1938 struct tty *tp; 1939 1940 if (COM_ISALIVE(sc) == 0) 1941 return; 1942 1943 tp = sc->sc_tty; 1944 1945 if (sc->sc_rx_ready) { 1946 sc->sc_rx_ready = 0; 1947 com_rxsoft(sc, tp); 1948 } 1949 1950 if (sc->sc_st_check) { 1951 sc->sc_st_check = 0; 1952 com_stsoft(sc, tp); 1953 } 1954 1955 if (sc->sc_tx_done) { 1956 sc->sc_tx_done = 0; 1957 com_txsoft(sc, tp); 1958 } 1959 } 1960 1961 int 1962 comintr(void *arg) 1963 { 1964 struct com_softc *sc = arg; 1965 struct com_regs *regsp = &sc->sc_regs; 1966 1967 u_char *put, *end; 1968 u_int cc; 1969 u_char lsr, iir; 1970 1971 if (COM_ISALIVE(sc) == 0) 1972 return (0); 1973 1974 KASSERT(regsp != NULL); 1975 1976 mutex_spin_enter(&sc->sc_lock); 1977 iir = CSR_READ_1(regsp, COM_REG_IIR); 1978 1979 /* Handle ns16750-specific busy interrupt. */ 1980 #ifdef COM_16750 1981 int timeout; 1982 if ((iir & IIR_BUSY) == IIR_BUSY) { 1983 for (timeout = 10000; 1984 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1985 if (timeout <= 0) { 1986 aprint_error_dev(sc->sc_dev, 1987 "timeout while waiting for BUSY interrupt " 1988 "acknowledge\n"); 1989 mutex_spin_exit(&sc->sc_lock); 1990 return (0); 1991 } 1992 1993 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1994 iir = CSR_READ_1(regsp, COM_REG_IIR); 1995 } 1996 #endif /* COM_16750 */ 1997 1998 1999 if (ISSET(iir, IIR_NOPEND)) { 2000 mutex_spin_exit(&sc->sc_lock); 2001 return (0); 2002 } 2003 2004 end = sc->sc_ebuf; 2005 put = sc->sc_rbput; 2006 cc = sc->sc_rbavail; 2007 2008 again: do { 2009 u_char msr, delta; 2010 2011 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2012 if (ISSET(lsr, LSR_BI)) { 2013 int cn_trapped = 0; /* see above: cn_trap() */ 2014 2015 cn_check_magic(sc->sc_tty->t_dev, 2016 CNC_BREAK, com_cnm_state); 2017 if (cn_trapped) 2018 continue; 2019 #if defined(KGDB) && !defined(DDB) 2020 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2021 kgdb_connect(1); 2022 continue; 2023 } 2024 #endif 2025 } 2026 2027 if (ISSET(lsr, LSR_RCV_MASK) && 2028 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2029 while (cc > 0) { 2030 int cn_trapped = 0; 2031 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2032 put[1] = lsr; 2033 cn_check_magic(sc->sc_tty->t_dev, 2034 put[0], com_cnm_state); 2035 if (cn_trapped) 2036 goto next; 2037 put += 2; 2038 if (put >= end) 2039 put = sc->sc_rbuf; 2040 cc--; 2041 next: 2042 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2043 if (!ISSET(lsr, LSR_RCV_MASK)) 2044 break; 2045 } 2046 2047 /* 2048 * Current string of incoming characters ended because 2049 * no more data was available or we ran out of space. 2050 * Schedule a receive event if any data was received. 2051 * If we're out of space, turn off receive interrupts. 2052 */ 2053 sc->sc_rbput = put; 2054 sc->sc_rbavail = cc; 2055 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2056 sc->sc_rx_ready = 1; 2057 2058 /* 2059 * See if we are in danger of overflowing a buffer. If 2060 * so, use hardware flow control to ease the pressure. 2061 */ 2062 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2063 cc < sc->sc_r_hiwat) { 2064 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2065 com_hwiflow(sc); 2066 } 2067 2068 /* 2069 * If we're out of space, disable receive interrupts 2070 * until the queue has drained a bit. 2071 */ 2072 if (!cc) { 2073 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2074 #ifdef COM_PXA2X0 2075 if (sc->sc_type == COM_TYPE_PXA2x0) 2076 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2077 else 2078 #endif 2079 CLR(sc->sc_ier, IER_ERXRDY); 2080 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2081 } 2082 } else { 2083 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2084 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2085 continue; 2086 } 2087 } 2088 2089 msr = CSR_READ_1(regsp, COM_REG_MSR); 2090 delta = msr ^ sc->sc_msr; 2091 sc->sc_msr = msr; 2092 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2093 (delta & MSR_DCD)) { 2094 mutex_spin_enter(&timecounter_lock); 2095 pps_capture(&sc->sc_pps_state); 2096 pps_event(&sc->sc_pps_state, 2097 (msr & MSR_DCD) ? 2098 PPS_CAPTUREASSERT : 2099 PPS_CAPTURECLEAR); 2100 mutex_spin_exit(&timecounter_lock); 2101 } 2102 2103 /* 2104 * Process normal status changes 2105 */ 2106 if (ISSET(delta, sc->sc_msr_mask)) { 2107 SET(sc->sc_msr_delta, delta); 2108 2109 /* 2110 * Stop output immediately if we lose the output 2111 * flow control signal or carrier detect. 2112 */ 2113 if (ISSET(~msr, sc->sc_msr_mask)) { 2114 sc->sc_tbc = 0; 2115 sc->sc_heldtbc = 0; 2116 #ifdef COM_DEBUG 2117 if (com_debug) 2118 comstatus(sc, "comintr "); 2119 #endif 2120 } 2121 2122 sc->sc_st_check = 1; 2123 } 2124 } while (!ISSET((iir = 2125 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2126 /* 2127 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2128 * by IIR read, so we can't do this way: `process all interrupts, 2129 * then do TX if possible'. 2130 */ 2131 (iir & IIR_IMASK) != IIR_TXRDY); 2132 2133 /* 2134 * Read LSR again, since there may be an interrupt between 2135 * the last LSR read and IIR read above. 2136 */ 2137 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2138 2139 /* 2140 * See if data can be transmitted as well. 2141 * Schedule tx done event if no data left 2142 * and tty was marked busy. 2143 */ 2144 if (ISSET(lsr, LSR_TXRDY)) { 2145 /* 2146 * If we've delayed a parameter change, do it now, and restart 2147 * output. 2148 */ 2149 if (sc->sc_heldchange) { 2150 com_loadchannelregs(sc); 2151 sc->sc_heldchange = 0; 2152 sc->sc_tbc = sc->sc_heldtbc; 2153 sc->sc_heldtbc = 0; 2154 } 2155 2156 /* Output the next chunk of the contiguous buffer, if any. */ 2157 if (sc->sc_tbc > 0) { 2158 u_int n; 2159 2160 n = sc->sc_tbc; 2161 if (n > sc->sc_fifolen) 2162 n = sc->sc_fifolen; 2163 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2164 sc->sc_tbc -= n; 2165 sc->sc_tba += n; 2166 } else { 2167 /* Disable transmit completion interrupts if necessary. */ 2168 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2169 CLR(sc->sc_ier, IER_ETXRDY); 2170 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2171 } 2172 if (sc->sc_tx_busy) { 2173 sc->sc_tx_busy = 0; 2174 sc->sc_tx_done = 1; 2175 } 2176 } 2177 } 2178 2179 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2180 goto again; 2181 2182 mutex_spin_exit(&sc->sc_lock); 2183 2184 /* Wake up the poller. */ 2185 softint_schedule(sc->sc_si); 2186 2187 #ifdef RND_COM 2188 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2189 #endif 2190 2191 return (1); 2192 } 2193 2194 /* 2195 * The following functions are polled getc and putc routines, shared 2196 * by the console and kgdb glue. 2197 * 2198 * The read-ahead code is so that you can detect pending in-band 2199 * cn_magic in polled mode while doing output rather than having to 2200 * wait until the kernel decides it needs input. 2201 */ 2202 2203 #define MAX_READAHEAD 20 2204 static int com_readahead[MAX_READAHEAD]; 2205 static int com_readaheadcount = 0; 2206 2207 int 2208 com_common_getc(dev_t dev, struct com_regs *regsp) 2209 { 2210 int s = splserial(); 2211 u_char stat, c; 2212 2213 /* got a character from reading things earlier */ 2214 if (com_readaheadcount > 0) { 2215 int i; 2216 2217 c = com_readahead[0]; 2218 for (i = 1; i < com_readaheadcount; i++) { 2219 com_readahead[i-1] = com_readahead[i]; 2220 } 2221 com_readaheadcount--; 2222 splx(s); 2223 return (c); 2224 } 2225 2226 /* don't block until a character becomes available */ 2227 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2228 splx(s); 2229 return -1; 2230 } 2231 2232 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2233 stat = CSR_READ_1(regsp, COM_REG_IIR); 2234 { 2235 int cn_trapped = 0; /* required by cn_trap, see above */ 2236 #ifdef DDB 2237 extern int db_active; 2238 if (!db_active) 2239 #endif 2240 cn_check_magic(dev, c, com_cnm_state); 2241 } 2242 splx(s); 2243 return (c); 2244 } 2245 2246 static void 2247 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2248 { 2249 int s = splserial(); 2250 int cin, stat, timo; 2251 2252 if (com_readaheadcount < MAX_READAHEAD 2253 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2254 int cn_trapped = 0; 2255 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2256 stat = CSR_READ_1(regsp, COM_REG_IIR); 2257 cn_check_magic(dev, cin, com_cnm_state); 2258 com_readahead[com_readaheadcount++] = cin; 2259 } 2260 2261 /* wait for any pending transmission to finish */ 2262 timo = 150000; 2263 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2264 continue; 2265 2266 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2267 COM_BARRIER(regsp, BR | BW); 2268 2269 splx(s); 2270 } 2271 2272 /* 2273 * Initialize UART for use as console or KGDB line. 2274 */ 2275 int 2276 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2277 tcflag_t cflag) 2278 { 2279 2280 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2281 ®sp->cr_ioh)) 2282 return (ENOMEM); /* ??? */ 2283 2284 if (type == COM_TYPE_OMAP) { 2285 /* disable before changing settings */ 2286 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2287 } 2288 2289 rate = comspeed(rate, frequency, type); 2290 if (__predict_true(rate != -1)) { 2291 if (type == COM_TYPE_AU1x00) { 2292 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2293 } else { 2294 /* no EFR on alchemy */ 2295 if (type != COM_TYPE_16550_NOERS) { 2296 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2297 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2298 } 2299 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2300 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2301 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2302 } 2303 } 2304 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2305 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2306 CSR_WRITE_1(regsp, COM_REG_FIFO, 2307 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2308 2309 if (type == COM_TYPE_OMAP) { 2310 /* setup the fifos. the FCR value is not used as long 2311 as SCR[6] and SCR[7] are 0, which they are at reset 2312 and we never touch the SCR register */ 2313 uint8_t rx_fifo_trig = 40; 2314 uint8_t tx_fifo_trig = 60; 2315 uint8_t rx_start = 8; 2316 uint8_t rx_halt = 60; 2317 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2318 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2319 2320 /* enable access to TCR & TLR */ 2321 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2322 2323 /* write tcr and tlr values */ 2324 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2325 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2326 2327 /* disable access to TCR & TLR */ 2328 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2329 2330 /* enable again, but mode is based on speed */ 2331 if (rate > 230400) { 2332 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2333 } else { 2334 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2335 } 2336 } 2337 2338 #ifdef COM_PXA2X0 2339 if (type == COM_TYPE_PXA2x0) 2340 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2341 else 2342 #endif 2343 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2344 2345 return (0); 2346 } 2347 2348 int 2349 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2350 tcflag_t cflag) 2351 { 2352 int res; 2353 2354 comcons_info.regs = *regsp; 2355 2356 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2357 if (res) 2358 return (res); 2359 2360 cn_tab = &comcons; 2361 cn_init_magic(&com_cnm_state); 2362 cn_set_magic("\047\001"); /* default magic is BREAK */ 2363 2364 comcons_info.frequency = frequency; 2365 comcons_info.type = type; 2366 comcons_info.rate = rate; 2367 comcons_info.cflag = cflag; 2368 2369 return (0); 2370 } 2371 2372 int 2373 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2374 int type, tcflag_t cflag) 2375 { 2376 struct com_regs regs; 2377 2378 memset(®s, 0, sizeof regs); 2379 regs.cr_iot = iot; 2380 regs.cr_iobase = iobase; 2381 regs.cr_nports = COM_NPORTS; 2382 #ifdef COM_REGMAP 2383 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2384 #endif 2385 2386 return comcnattach1(®s, rate, frequency, type, cflag); 2387 } 2388 2389 static int 2390 comcnreattach(void) 2391 { 2392 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2393 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2394 } 2395 2396 int 2397 comcngetc(dev_t dev) 2398 { 2399 2400 return (com_common_getc(dev, &comcons_info.regs)); 2401 } 2402 2403 /* 2404 * Console kernel output character routine. 2405 */ 2406 void 2407 comcnputc(dev_t dev, int c) 2408 { 2409 2410 com_common_putc(dev, &comcons_info.regs, c); 2411 } 2412 2413 void 2414 comcnpollc(dev_t dev, int on) 2415 { 2416 2417 com_readaheadcount = 0; 2418 } 2419 2420 #ifdef KGDB 2421 int 2422 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2423 tcflag_t cflag) 2424 { 2425 int res; 2426 2427 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2428 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2429 #if !defined(DDB) 2430 return (EBUSY); /* cannot share with console */ 2431 #else 2432 comkgdbregs = *regsp; 2433 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2434 #endif 2435 } else { 2436 comkgdbregs = *regsp; 2437 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2438 if (res) 2439 return (res); 2440 2441 /* 2442 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2443 * expects this to be initialized 2444 */ 2445 cn_init_magic(&com_cnm_state); 2446 cn_set_magic("\047\001"); 2447 } 2448 2449 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2450 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2451 2452 return (0); 2453 } 2454 2455 int 2456 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2457 int frequency, int type, tcflag_t cflag) 2458 { 2459 struct com_regs regs; 2460 2461 regs.cr_iot = iot; 2462 regs.cr_nports = COM_NPORTS; 2463 regs.cr_iobase = iobase; 2464 #ifdef COM_REGMAP 2465 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2466 #endif 2467 2468 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2469 } 2470 2471 /* ARGSUSED */ 2472 int 2473 com_kgdb_getc(void *arg) 2474 { 2475 2476 return (com_common_getc(NODEV, &comkgdbregs)); 2477 } 2478 2479 /* ARGSUSED */ 2480 void 2481 com_kgdb_putc(void *arg, int c) 2482 { 2483 2484 com_common_putc(NODEV, &comkgdbregs, c); 2485 } 2486 #endif /* KGDB */ 2487 2488 /* helper function to identify the com ports used by 2489 console or KGDB (and not yet autoconf attached) */ 2490 int 2491 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2492 { 2493 bus_space_handle_t help; 2494 2495 if (!comconsattached && 2496 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2497 iobase == comcons_info.regs.cr_iobase) 2498 help = comcons_info.regs.cr_ioh; 2499 #ifdef KGDB 2500 else if (!com_kgdb_attached && 2501 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2502 iobase == comkgdbregs.cr_iobase) 2503 help = comkgdbregs.cr_ioh; 2504 #endif 2505 else 2506 return (0); 2507 2508 if (ioh) 2509 *ioh = help; 2510 return (1); 2511 } 2512 2513 /* 2514 * this routine exists to serve as a shutdown hook for systems that 2515 * have firmware which doesn't interact properly with a com device in 2516 * FIFO mode. 2517 */ 2518 bool 2519 com_cleanup(device_t self, int how) 2520 { 2521 struct com_softc *sc = device_private(self); 2522 2523 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2524 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2525 2526 return true; 2527 } 2528 2529 bool 2530 com_suspend(device_t self, const pmf_qual_t *qual) 2531 { 2532 struct com_softc *sc = device_private(self); 2533 2534 #if 0 2535 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2536 cn_tab = &comcons_suspend; 2537 #endif 2538 2539 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2540 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2541 2542 return true; 2543 } 2544 2545 bool 2546 com_resume(device_t self, const pmf_qual_t *qual) 2547 { 2548 struct com_softc *sc = device_private(self); 2549 2550 mutex_spin_enter(&sc->sc_lock); 2551 com_loadchannelregs(sc); 2552 mutex_spin_exit(&sc->sc_lock); 2553 2554 return true; 2555 } 2556