1 /* $NetBSD: com.c,v 1.294 2010/01/09 14:15:48 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.294 2010/01/09 14:15:48 tsutsui Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/conf.h> 108 #include <sys/file.h> 109 #include <sys/uio.h> 110 #include <sys/kernel.h> 111 #include <sys/syslog.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/timepps.h> 115 #include <sys/vnode.h> 116 #include <sys/kauth.h> 117 #include <sys/intr.h> 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #ifdef COM_HAYESP 126 #include <dev/ic/hayespreg.h> 127 #endif 128 #define com_lcr com_cfcr 129 #include <dev/cons.h> 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 extern struct cfdriver com_cd; 194 195 dev_type_open(comopen); 196 dev_type_close(comclose); 197 dev_type_read(comread); 198 dev_type_write(comwrite); 199 dev_type_ioctl(comioctl); 200 dev_type_stop(comstop); 201 dev_type_tty(comtty); 202 dev_type_poll(compoll); 203 204 static struct comcons_info comcons_info; 205 206 /* 207 * Following are all routines needed for COM to act as console 208 */ 209 static struct consdev comcons = { 210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 211 NODEV, CN_NORMAL 212 }; 213 214 215 const struct cdevsw com_cdevsw = { 216 comopen, comclose, comread, comwrite, comioctl, 217 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 218 }; 219 220 /* 221 * Make this an option variable one can patch. 222 * But be warned: this must be a power of 2! 223 */ 224 u_int com_rbuf_size = COM_RING_SIZE; 225 226 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 227 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 228 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 229 230 static int comconsattached; 231 static struct cnm_state com_cnm_state; 232 233 #ifdef KGDB 234 #include <sys/kgdb.h> 235 236 static struct com_regs comkgdbregs; 237 static int com_kgdb_attached; 238 239 int com_kgdb_getc(void *); 240 void com_kgdb_putc(void *, int); 241 #endif /* KGDB */ 242 243 #ifdef COM_REGMAP 244 /* initializer for typical 16550-ish hardware */ 245 #define COM_REG_16550 { \ 246 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 247 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 248 249 const bus_size_t com_std_map[16] = COM_REG_16550; 250 #endif /* COM_REGMAP */ 251 252 #define COMUNIT_MASK 0x7ffff 253 #define COMDIALOUT_MASK 0x80000 254 255 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 256 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 257 258 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 259 device_is_active((sc)->sc_dev)) 260 261 #define BR BUS_SPACE_BARRIER_READ 262 #define BW BUS_SPACE_BARRIER_WRITE 263 #define COM_BARRIER(r, f) \ 264 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 265 266 /*ARGSUSED*/ 267 int 268 comspeed(long speed, long frequency, int type) 269 { 270 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 271 272 int x, err; 273 int divisor = 16; 274 275 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 276 divisor = 13; 277 } 278 279 #if 0 280 if (speed == 0) 281 return (0); 282 #endif 283 if (speed <= 0) 284 return (-1); 285 x = divrnd(frequency / divisor, speed); 286 if (x <= 0) 287 return (-1); 288 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 289 if (err < 0) 290 err = -err; 291 if (err > COM_TOLERANCE) 292 return (-1); 293 return (x); 294 295 #undef divrnd 296 } 297 298 #ifdef COM_DEBUG 299 int com_debug = 0; 300 301 void comstatus(struct com_softc *, const char *); 302 void 303 comstatus(struct com_softc *sc, const char *str) 304 { 305 struct tty *tp = sc->sc_tty; 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 309 str, 310 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 312 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 314 sc->sc_tx_stopped ? '+' : '-'); 315 316 aprint_normal_dev(sc->sc_dev, 317 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 318 str, 319 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 320 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 321 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 322 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 323 sc->sc_rx_flags); 324 } 325 #endif 326 327 int 328 com_probe_subr(struct com_regs *regs) 329 { 330 331 /* force access to id reg */ 332 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 333 CSR_WRITE_1(regs, COM_REG_IIR, 0); 334 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 335 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 336 return (0); 337 338 return (1); 339 } 340 341 int 342 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 343 { 344 struct com_regs regs; 345 346 regs.cr_iot = iot; 347 regs.cr_ioh = ioh; 348 #ifdef COM_REGMAP 349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 350 #endif 351 352 return com_probe_subr(®s); 353 } 354 355 /* 356 * No locking in this routine; it is only called during attach, 357 * or with the port already locked. 358 */ 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 363 /* Turn on line break interrupt, set carrier. */ 364 sc->sc_ier = IER_ERXRDY; 365 if (sc->sc_type == COM_TYPE_PXA2x0) 366 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 367 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 368 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 369 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 370 } 371 372 void 373 com_attach_subr(struct com_softc *sc) 374 { 375 struct com_regs *regsp = &sc->sc_regs; 376 struct tty *tp; 377 #ifdef COM_16650 378 u_int8_t lcr; 379 #endif 380 const char *fifo_msg = NULL; 381 382 aprint_naive("\n"); 383 384 callout_init(&sc->sc_diag_callout, 0); 385 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 386 387 /* Disable interrupts before configuring the device. */ 388 if (sc->sc_type == COM_TYPE_PXA2x0) 389 sc->sc_ier = IER_EUART; 390 else 391 sc->sc_ier = 0; 392 393 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 394 395 if (regsp->cr_iot == comcons_info.regs.cr_iot && 396 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 397 comconsattached = 1; 398 399 if (cn_tab == NULL && comcnreattach() != 0) { 400 printf("can't re-init serial console @%lx\n", 401 (u_long)comcons_info.regs.cr_iobase); 402 } 403 404 /* Make sure the console is always "hardwired". */ 405 delay(10000); /* wait for output to finish */ 406 SET(sc->sc_hwflags, COM_HW_CONSOLE); 407 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 408 } 409 410 /* Probe for FIFO */ 411 switch (sc->sc_type) { 412 case COM_TYPE_HAYESP: 413 goto fifodone; 414 415 case COM_TYPE_AU1x00: 416 sc->sc_fifolen = 16; 417 fifo_msg = "Au1X00 UART, working fifo"; 418 SET(sc->sc_hwflags, COM_HW_FIFO); 419 goto fifodelay; 420 421 case COM_TYPE_16550_NOERS: 422 sc->sc_fifolen = 16; 423 fifo_msg = "ns16650, no ERS, working fifo"; 424 SET(sc->sc_hwflags, COM_HW_FIFO); 425 goto fifodelay; 426 427 case COM_TYPE_OMAP: 428 sc->sc_fifolen = 64; 429 fifo_msg = "OMAP UART, working fifo"; 430 SET(sc->sc_hwflags, COM_HW_FIFO); 431 goto fifodelay; 432 } 433 434 sc->sc_fifolen = 1; 435 /* look for a NS 16550AF UART with FIFOs */ 436 CSR_WRITE_1(regsp, COM_REG_FIFO, 437 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 438 delay(100); 439 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 440 == IIR_FIFO_MASK) 441 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 442 == FIFO_TRIGGER_14) { 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 445 #ifdef COM_16650 446 /* 447 * IIR changes into the EFR if LCR is set to LCR_EERS 448 * on 16650s. We also know IIR != 0 at this point. 449 * Write 0 into the EFR, and read it. If the result 450 * is 0, we have a 16650. 451 * 452 * Older 16650s were broken; the test to detect them 453 * is taken from the Linux driver. Apparently 454 * setting DLAB enable gives access to the EFR on 455 * these chips. 456 */ 457 lcr = CSR_READ_1(regsp, COM_REG_LCR); 458 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 459 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 460 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 461 CSR_WRITE_1(regsp, COM_REG_LCR, 462 lcr | LCR_DLAB); 463 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 464 CLR(sc->sc_hwflags, COM_HW_FIFO); 465 sc->sc_fifolen = 0; 466 } else { 467 SET(sc->sc_hwflags, COM_HW_FLOW); 468 sc->sc_fifolen = 32; 469 } 470 } else 471 #endif 472 sc->sc_fifolen = 16; 473 474 #ifdef COM_16650 475 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 476 if (sc->sc_fifolen == 0) 477 fifo_msg = "st16650, broken fifo"; 478 else if (sc->sc_fifolen == 32) 479 fifo_msg = "st16650a, working fifo"; 480 else 481 #endif 482 fifo_msg = "ns16550a, working fifo"; 483 } else 484 fifo_msg = "ns16550, broken fifo"; 485 else 486 fifo_msg = "ns8250 or ns16450, no fifo"; 487 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 488 fifodelay: 489 /* 490 * Some chips will clear down both Tx and Rx FIFOs when zero is 491 * written to com_fifo. If this chip is the console, writing zero 492 * results in some of the chip/FIFO description being lost, so delay 493 * printing it until now. 494 */ 495 delay(10); 496 aprint_normal(": %s\n", fifo_msg); 497 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 498 sc->sc_fifolen = 1; 499 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 500 } 501 502 fifodone: 503 504 tp = ttymalloc(); 505 tp->t_oproc = comstart; 506 tp->t_param = comparam; 507 tp->t_hwiflow = comhwiflow; 508 509 sc->sc_tty = tp; 510 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 511 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 512 sc->sc_rbavail = com_rbuf_size; 513 if (sc->sc_rbuf == NULL) { 514 aprint_error_dev(sc->sc_dev, 515 "unable to allocate ring buffer\n"); 516 return; 517 } 518 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 519 520 tty_attach(tp); 521 522 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 523 SET(sc->sc_mcr, MCR_IENABLE); 524 525 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 526 int maj; 527 528 /* locate the major number */ 529 maj = cdevsw_lookup_major(&com_cdevsw); 530 531 tp->t_dev = cn_tab->cn_dev = makedev(maj, 532 device_unit(sc->sc_dev)); 533 534 aprint_normal_dev(sc->sc_dev, "console\n"); 535 } 536 537 #ifdef KGDB 538 /* 539 * Allow kgdb to "take over" this port. If this is 540 * not the console and is the kgdb device, it has 541 * exclusive use. If it's the console _and_ the 542 * kgdb device, it doesn't. 543 */ 544 if (regsp->cr_iot == comkgdbregs.cr_iot && 545 regsp->cr_iobase == comkgdbregs.cr_iobase) { 546 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 547 com_kgdb_attached = 1; 548 549 SET(sc->sc_hwflags, COM_HW_KGDB); 550 } 551 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 552 } 553 #endif 554 555 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 556 557 #if NRND > 0 && defined(RND_COM) 558 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 559 RND_TYPE_TTY, 0); 560 #endif 561 562 /* if there are no enable/disable functions, assume the device 563 is always enabled */ 564 if (!sc->enable) 565 sc->enabled = 1; 566 567 com_config(sc); 568 569 SET(sc->sc_hwflags, COM_HW_DEV_OK); 570 } 571 572 void 573 com_config(struct com_softc *sc) 574 { 575 struct com_regs *regsp = &sc->sc_regs; 576 577 /* Disable interrupts before configuring the device. */ 578 if (sc->sc_type == COM_TYPE_PXA2x0) 579 sc->sc_ier = IER_EUART; 580 else 581 sc->sc_ier = 0; 582 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 583 (void) CSR_READ_1(regsp, COM_REG_IIR); 584 585 #ifdef COM_HAYESP 586 /* Look for a Hayes ESP board. */ 587 if (sc->sc_type == COM_TYPE_HAYESP) { 588 589 /* Set 16550 compatibility mode */ 590 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 591 HAYESP_SETMODE); 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 593 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 594 HAYESP_MODE_SCALE); 595 596 /* Set RTS/CTS flow control */ 597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 598 HAYESP_SETFLOWTYPE); 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 600 HAYESP_FLOW_RTS); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_FLOW_CTS); 603 604 /* Set flow control levels */ 605 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 606 HAYESP_SETRXFLOW); 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 608 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 613 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 614 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 615 } 616 #endif 617 618 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 619 com_enable_debugport(sc); 620 } 621 622 #if 0 623 static int 624 comcngetc_detached(dev_t dev) 625 { 626 return 0; 627 } 628 629 static void 630 comcnputc_detached(dev_t dev, int c) 631 { 632 } 633 #endif 634 635 int 636 com_detach(device_t self, int flags) 637 { 638 struct com_softc *sc = device_private(self); 639 int maj, mn; 640 641 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 642 return EBUSY; 643 644 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 645 (flags & DETACH_SHUTDOWN) != 0) 646 return EBUSY; 647 648 if (sc->disable != NULL && sc->enabled != 0) { 649 (*sc->disable)(sc); 650 sc->enabled = 0; 651 } 652 653 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 654 comconsattached = 0; 655 cn_tab = NULL; 656 } 657 658 /* locate the major number */ 659 maj = cdevsw_lookup_major(&com_cdevsw); 660 661 /* Nuke the vnodes for any open instances. */ 662 mn = device_unit(self); 663 vdevgone(maj, mn, mn, VCHR); 664 665 mn |= COMDIALOUT_MASK; 666 vdevgone(maj, mn, mn, VCHR); 667 668 if (sc->sc_rbuf == NULL) { 669 /* 670 * Ring buffer allocation failed in the com_attach_subr, 671 * only the tty is allocated, and nothing else. 672 */ 673 ttyfree(sc->sc_tty); 674 return 0; 675 } 676 677 /* Free the receive buffer. */ 678 free(sc->sc_rbuf, M_DEVBUF); 679 680 /* Detach and free the tty. */ 681 tty_detach(sc->sc_tty); 682 ttyfree(sc->sc_tty); 683 684 /* Unhook the soft interrupt handler. */ 685 softint_disestablish(sc->sc_si); 686 687 #if NRND > 0 && defined(RND_COM) 688 /* Unhook the entropy source. */ 689 rnd_detach_source(&sc->rnd_source); 690 #endif 691 callout_destroy(&sc->sc_diag_callout); 692 693 /* Destroy the lock. */ 694 mutex_destroy(&sc->sc_lock); 695 696 return (0); 697 } 698 699 void 700 com_shutdown(struct com_softc *sc) 701 { 702 struct tty *tp = sc->sc_tty; 703 704 mutex_spin_enter(&sc->sc_lock); 705 706 /* If we were asserting flow control, then deassert it. */ 707 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 708 com_hwiflow(sc); 709 710 /* Clear any break condition set with TIOCSBRK. */ 711 com_break(sc, 0); 712 713 /* 714 * Hang up if necessary. Wait a bit, so the other side has time to 715 * notice even if we immediately open the port again. 716 * Avoid tsleeping above splhigh(). 717 */ 718 if (ISSET(tp->t_cflag, HUPCL)) { 719 com_modem(sc, 0); 720 mutex_spin_exit(&sc->sc_lock); 721 /* XXX will only timeout */ 722 (void) kpause(ttclos, false, hz, NULL); 723 mutex_spin_enter(&sc->sc_lock); 724 } 725 726 /* Turn off interrupts. */ 727 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 728 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 729 if (sc->sc_type == COM_TYPE_PXA2x0) 730 sc->sc_ier |= IER_ERXTOUT; 731 } else 732 sc->sc_ier = 0; 733 734 if (sc->sc_type == COM_TYPE_PXA2x0) 735 sc->sc_ier |= IER_EUART; 736 737 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 738 739 mutex_spin_exit(&sc->sc_lock); 740 741 if (sc->disable) { 742 #ifdef DIAGNOSTIC 743 if (!sc->enabled) 744 panic("com_shutdown: not enabled?"); 745 #endif 746 (*sc->disable)(sc); 747 sc->enabled = 0; 748 } 749 } 750 751 int 752 comopen(dev_t dev, int flag, int mode, struct lwp *l) 753 { 754 struct com_softc *sc; 755 struct tty *tp; 756 int s; 757 int error; 758 759 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 760 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 761 sc->sc_rbuf == NULL) 762 return (ENXIO); 763 764 if (!device_is_active(sc->sc_dev)) 765 return (ENXIO); 766 767 #ifdef KGDB 768 /* 769 * If this is the kgdb port, no other use is permitted. 770 */ 771 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 772 return (EBUSY); 773 #endif 774 775 tp = sc->sc_tty; 776 777 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 778 return (EBUSY); 779 780 s = spltty(); 781 782 /* 783 * Do the following iff this is a first open. 784 */ 785 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 786 struct termios t; 787 788 tp->t_dev = dev; 789 790 791 if (sc->enable) { 792 if ((*sc->enable)(sc)) { 793 splx(s); 794 aprint_error_dev(sc->sc_dev, 795 "device enable failed\n"); 796 return (EIO); 797 } 798 mutex_spin_enter(&sc->sc_lock); 799 sc->enabled = 1; 800 com_config(sc); 801 } else { 802 mutex_spin_enter(&sc->sc_lock); 803 } 804 805 /* Turn on interrupts. */ 806 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 807 if (sc->sc_type == COM_TYPE_PXA2x0) 808 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 809 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 810 811 /* Fetch the current modem control status, needed later. */ 812 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 813 814 /* Clear PPS capture state on first open. */ 815 mutex_spin_enter(&timecounter_lock); 816 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 817 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 818 pps_init(&sc->sc_pps_state); 819 mutex_spin_exit(&timecounter_lock); 820 821 mutex_spin_exit(&sc->sc_lock); 822 823 /* 824 * Initialize the termios status to the defaults. Add in the 825 * sticky bits from TIOCSFLAGS. 826 */ 827 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 828 t.c_ospeed = comcons_info.rate; 829 t.c_cflag = comcons_info.cflag; 830 } else { 831 t.c_ospeed = TTYDEF_SPEED; 832 t.c_cflag = TTYDEF_CFLAG; 833 } 834 t.c_ispeed = t.c_ospeed; 835 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 836 SET(t.c_cflag, CLOCAL); 837 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 838 SET(t.c_cflag, CRTSCTS); 839 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 840 SET(t.c_cflag, MDMBUF); 841 /* Make sure comparam() will do something. */ 842 tp->t_ospeed = 0; 843 (void) comparam(tp, &t); 844 tp->t_iflag = TTYDEF_IFLAG; 845 tp->t_oflag = TTYDEF_OFLAG; 846 tp->t_lflag = TTYDEF_LFLAG; 847 ttychars(tp); 848 ttsetwater(tp); 849 850 mutex_spin_enter(&sc->sc_lock); 851 852 /* 853 * Turn on DTR. We must always do this, even if carrier is not 854 * present, because otherwise we'd have to use TIOCSDTR 855 * immediately after setting CLOCAL, which applications do not 856 * expect. We always assert DTR while the device is open 857 * unless explicitly requested to deassert it. 858 */ 859 com_modem(sc, 1); 860 861 /* Clear the input ring, and unblock. */ 862 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 863 sc->sc_rbavail = com_rbuf_size; 864 com_iflush(sc); 865 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 866 com_hwiflow(sc); 867 868 #ifdef COM_DEBUG 869 if (com_debug) 870 comstatus(sc, "comopen "); 871 #endif 872 873 mutex_spin_exit(&sc->sc_lock); 874 } 875 876 splx(s); 877 878 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 879 if (error) 880 goto bad; 881 882 error = (*tp->t_linesw->l_open)(dev, tp); 883 if (error) 884 goto bad; 885 886 return (0); 887 888 bad: 889 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 890 /* 891 * We failed to open the device, and nobody else had it opened. 892 * Clean up the state as appropriate. 893 */ 894 com_shutdown(sc); 895 } 896 897 return (error); 898 } 899 900 int 901 comclose(dev_t dev, int flag, int mode, struct lwp *l) 902 { 903 struct com_softc *sc = 904 device_lookup_private(&com_cd, COMUNIT(dev)); 905 struct tty *tp = sc->sc_tty; 906 907 /* XXX This is for cons.c. */ 908 if (!ISSET(tp->t_state, TS_ISOPEN)) 909 return (0); 910 911 (*tp->t_linesw->l_close)(tp, flag); 912 ttyclose(tp); 913 914 if (COM_ISALIVE(sc) == 0) 915 return (0); 916 917 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 918 /* 919 * Although we got a last close, the device may still be in 920 * use; e.g. if this was the dialout node, and there are still 921 * processes waiting for carrier on the non-dialout node. 922 */ 923 com_shutdown(sc); 924 } 925 926 return (0); 927 } 928 929 int 930 comread(dev_t dev, struct uio *uio, int flag) 931 { 932 struct com_softc *sc = 933 device_lookup_private(&com_cd, COMUNIT(dev)); 934 struct tty *tp = sc->sc_tty; 935 936 if (COM_ISALIVE(sc) == 0) 937 return (EIO); 938 939 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 940 } 941 942 int 943 comwrite(dev_t dev, struct uio *uio, int flag) 944 { 945 struct com_softc *sc = 946 device_lookup_private(&com_cd, COMUNIT(dev)); 947 struct tty *tp = sc->sc_tty; 948 949 if (COM_ISALIVE(sc) == 0) 950 return (EIO); 951 952 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 953 } 954 955 int 956 compoll(dev_t dev, int events, struct lwp *l) 957 { 958 struct com_softc *sc = 959 device_lookup_private(&com_cd, COMUNIT(dev)); 960 struct tty *tp = sc->sc_tty; 961 962 if (COM_ISALIVE(sc) == 0) 963 return (POLLHUP); 964 965 return ((*tp->t_linesw->l_poll)(tp, events, l)); 966 } 967 968 struct tty * 969 comtty(dev_t dev) 970 { 971 struct com_softc *sc = 972 device_lookup_private(&com_cd, COMUNIT(dev)); 973 struct tty *tp = sc->sc_tty; 974 975 return (tp); 976 } 977 978 int 979 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 980 { 981 struct com_softc *sc; 982 struct tty *tp; 983 int error; 984 985 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 986 if (sc == NULL) 987 return ENXIO; 988 if (COM_ISALIVE(sc) == 0) 989 return (EIO); 990 991 tp = sc->sc_tty; 992 993 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 994 if (error != EPASSTHROUGH) 995 return (error); 996 997 error = ttioctl(tp, cmd, data, flag, l); 998 if (error != EPASSTHROUGH) 999 return (error); 1000 1001 error = 0; 1002 switch (cmd) { 1003 case TIOCSFLAGS: 1004 error = kauth_authorize_device_tty(l->l_cred, 1005 KAUTH_DEVICE_TTY_PRIVSET, tp); 1006 break; 1007 default: 1008 /* nothing */ 1009 break; 1010 } 1011 if (error) { 1012 return error; 1013 } 1014 1015 mutex_spin_enter(&sc->sc_lock); 1016 1017 switch (cmd) { 1018 case TIOCSBRK: 1019 com_break(sc, 1); 1020 break; 1021 1022 case TIOCCBRK: 1023 com_break(sc, 0); 1024 break; 1025 1026 case TIOCSDTR: 1027 com_modem(sc, 1); 1028 break; 1029 1030 case TIOCCDTR: 1031 com_modem(sc, 0); 1032 break; 1033 1034 case TIOCGFLAGS: 1035 *(int *)data = sc->sc_swflags; 1036 break; 1037 1038 case TIOCSFLAGS: 1039 sc->sc_swflags = *(int *)data; 1040 break; 1041 1042 case TIOCMSET: 1043 case TIOCMBIS: 1044 case TIOCMBIC: 1045 tiocm_to_com(sc, cmd, *(int *)data); 1046 break; 1047 1048 case TIOCMGET: 1049 *(int *)data = com_to_tiocm(sc); 1050 break; 1051 1052 case PPS_IOC_CREATE: 1053 case PPS_IOC_DESTROY: 1054 case PPS_IOC_GETPARAMS: 1055 case PPS_IOC_SETPARAMS: 1056 case PPS_IOC_GETCAP: 1057 case PPS_IOC_FETCH: 1058 #ifdef PPS_SYNC 1059 case PPS_IOC_KCBIND: 1060 #endif 1061 mutex_spin_enter(&timecounter_lock); 1062 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1063 mutex_spin_exit(&timecounter_lock); 1064 break; 1065 1066 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1067 mutex_spin_enter(&timecounter_lock); 1068 #ifndef PPS_TRAILING_EDGE 1069 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1070 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1071 #else 1072 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1073 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1074 #endif 1075 mutex_spin_exit(&timecounter_lock); 1076 break; 1077 1078 default: 1079 error = EPASSTHROUGH; 1080 break; 1081 } 1082 1083 mutex_spin_exit(&sc->sc_lock); 1084 1085 #ifdef COM_DEBUG 1086 if (com_debug) 1087 comstatus(sc, "comioctl "); 1088 #endif 1089 1090 return (error); 1091 } 1092 1093 integrate void 1094 com_schedrx(struct com_softc *sc) 1095 { 1096 1097 sc->sc_rx_ready = 1; 1098 1099 /* Wake up the poller. */ 1100 softint_schedule(sc->sc_si); 1101 } 1102 1103 void 1104 com_break(struct com_softc *sc, int onoff) 1105 { 1106 1107 if (onoff) 1108 SET(sc->sc_lcr, LCR_SBREAK); 1109 else 1110 CLR(sc->sc_lcr, LCR_SBREAK); 1111 1112 if (!sc->sc_heldchange) { 1113 if (sc->sc_tx_busy) { 1114 sc->sc_heldtbc = sc->sc_tbc; 1115 sc->sc_tbc = 0; 1116 sc->sc_heldchange = 1; 1117 } else 1118 com_loadchannelregs(sc); 1119 } 1120 } 1121 1122 void 1123 com_modem(struct com_softc *sc, int onoff) 1124 { 1125 1126 if (sc->sc_mcr_dtr == 0) 1127 return; 1128 1129 if (onoff) 1130 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1131 else 1132 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1133 1134 if (!sc->sc_heldchange) { 1135 if (sc->sc_tx_busy) { 1136 sc->sc_heldtbc = sc->sc_tbc; 1137 sc->sc_tbc = 0; 1138 sc->sc_heldchange = 1; 1139 } else 1140 com_loadchannelregs(sc); 1141 } 1142 } 1143 1144 void 1145 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1146 { 1147 u_char combits; 1148 1149 combits = 0; 1150 if (ISSET(ttybits, TIOCM_DTR)) 1151 SET(combits, MCR_DTR); 1152 if (ISSET(ttybits, TIOCM_RTS)) 1153 SET(combits, MCR_RTS); 1154 1155 switch (how) { 1156 case TIOCMBIC: 1157 CLR(sc->sc_mcr, combits); 1158 break; 1159 1160 case TIOCMBIS: 1161 SET(sc->sc_mcr, combits); 1162 break; 1163 1164 case TIOCMSET: 1165 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1166 SET(sc->sc_mcr, combits); 1167 break; 1168 } 1169 1170 if (!sc->sc_heldchange) { 1171 if (sc->sc_tx_busy) { 1172 sc->sc_heldtbc = sc->sc_tbc; 1173 sc->sc_tbc = 0; 1174 sc->sc_heldchange = 1; 1175 } else 1176 com_loadchannelregs(sc); 1177 } 1178 } 1179 1180 int 1181 com_to_tiocm(struct com_softc *sc) 1182 { 1183 u_char combits; 1184 int ttybits = 0; 1185 1186 combits = sc->sc_mcr; 1187 if (ISSET(combits, MCR_DTR)) 1188 SET(ttybits, TIOCM_DTR); 1189 if (ISSET(combits, MCR_RTS)) 1190 SET(ttybits, TIOCM_RTS); 1191 1192 combits = sc->sc_msr; 1193 if (ISSET(combits, MSR_DCD)) 1194 SET(ttybits, TIOCM_CD); 1195 if (ISSET(combits, MSR_CTS)) 1196 SET(ttybits, TIOCM_CTS); 1197 if (ISSET(combits, MSR_DSR)) 1198 SET(ttybits, TIOCM_DSR); 1199 if (ISSET(combits, MSR_RI | MSR_TERI)) 1200 SET(ttybits, TIOCM_RI); 1201 1202 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1203 SET(ttybits, TIOCM_LE); 1204 1205 return (ttybits); 1206 } 1207 1208 static u_char 1209 cflag2lcr(tcflag_t cflag) 1210 { 1211 u_char lcr = 0; 1212 1213 switch (ISSET(cflag, CSIZE)) { 1214 case CS5: 1215 SET(lcr, LCR_5BITS); 1216 break; 1217 case CS6: 1218 SET(lcr, LCR_6BITS); 1219 break; 1220 case CS7: 1221 SET(lcr, LCR_7BITS); 1222 break; 1223 case CS8: 1224 SET(lcr, LCR_8BITS); 1225 break; 1226 } 1227 if (ISSET(cflag, PARENB)) { 1228 SET(lcr, LCR_PENAB); 1229 if (!ISSET(cflag, PARODD)) 1230 SET(lcr, LCR_PEVEN); 1231 } 1232 if (ISSET(cflag, CSTOPB)) 1233 SET(lcr, LCR_STOPB); 1234 1235 return (lcr); 1236 } 1237 1238 int 1239 comparam(struct tty *tp, struct termios *t) 1240 { 1241 struct com_softc *sc = 1242 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1243 int ospeed; 1244 u_char lcr; 1245 1246 if (COM_ISALIVE(sc) == 0) 1247 return (EIO); 1248 1249 #ifdef COM_HAYESP 1250 if (sc->sc_type == COM_TYPE_HAYESP) { 1251 int prescaler, speed; 1252 1253 /* 1254 * Calculate UART clock prescaler. It should be in 1255 * range of 0 .. 3. 1256 */ 1257 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1258 prescaler++, speed /= 2) 1259 if ((ospeed = comspeed(speed, sc->sc_frequency, 1260 sc->sc_type)) > 0) 1261 break; 1262 1263 if (prescaler == 4) 1264 return (EINVAL); 1265 sc->sc_prescaler = prescaler; 1266 } else 1267 #endif 1268 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1269 1270 /* Check requested parameters. */ 1271 if (ospeed < 0) 1272 return (EINVAL); 1273 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1274 return (EINVAL); 1275 1276 /* 1277 * For the console, always force CLOCAL and !HUPCL, so that the port 1278 * is always active. 1279 */ 1280 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1281 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1282 SET(t->c_cflag, CLOCAL); 1283 CLR(t->c_cflag, HUPCL); 1284 } 1285 1286 /* 1287 * If there were no changes, don't do anything. This avoids dropping 1288 * input and improves performance when all we did was frob things like 1289 * VMIN and VTIME. 1290 */ 1291 if (tp->t_ospeed == t->c_ospeed && 1292 tp->t_cflag == t->c_cflag) 1293 return (0); 1294 1295 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1296 1297 mutex_spin_enter(&sc->sc_lock); 1298 1299 sc->sc_lcr = lcr; 1300 1301 /* 1302 * If we're not in a mode that assumes a connection is present, then 1303 * ignore carrier changes. 1304 */ 1305 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1306 sc->sc_msr_dcd = 0; 1307 else 1308 sc->sc_msr_dcd = MSR_DCD; 1309 /* 1310 * Set the flow control pins depending on the current flow control 1311 * mode. 1312 */ 1313 if (ISSET(t->c_cflag, CRTSCTS)) { 1314 sc->sc_mcr_dtr = MCR_DTR; 1315 sc->sc_mcr_rts = MCR_RTS; 1316 sc->sc_msr_cts = MSR_CTS; 1317 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1318 } else if (ISSET(t->c_cflag, MDMBUF)) { 1319 /* 1320 * For DTR/DCD flow control, make sure we don't toggle DTR for 1321 * carrier detection. 1322 */ 1323 sc->sc_mcr_dtr = 0; 1324 sc->sc_mcr_rts = MCR_DTR; 1325 sc->sc_msr_cts = MSR_DCD; 1326 sc->sc_efr = 0; 1327 } else { 1328 /* 1329 * If no flow control, then always set RTS. This will make 1330 * the other side happy if it mistakenly thinks we're doing 1331 * RTS/CTS flow control. 1332 */ 1333 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1334 sc->sc_mcr_rts = 0; 1335 sc->sc_msr_cts = 0; 1336 sc->sc_efr = 0; 1337 if (ISSET(sc->sc_mcr, MCR_DTR)) 1338 SET(sc->sc_mcr, MCR_RTS); 1339 else 1340 CLR(sc->sc_mcr, MCR_RTS); 1341 } 1342 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1343 1344 #if 0 1345 if (ospeed == 0) 1346 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1347 else 1348 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1349 #endif 1350 1351 sc->sc_dlbl = ospeed; 1352 sc->sc_dlbh = ospeed >> 8; 1353 1354 /* 1355 * Set the FIFO threshold based on the receive speed. 1356 * 1357 * * If it's a low speed, it's probably a mouse or some other 1358 * interactive device, so set the threshold low. 1359 * * If it's a high speed, trim the trigger level down to prevent 1360 * overflows. 1361 * * Otherwise set it a bit higher. 1362 */ 1363 if (sc->sc_type == COM_TYPE_HAYESP) 1364 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1365 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1366 if (t->c_ospeed <= 1200) 1367 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1368 else if (t->c_ospeed <= 38400) 1369 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1370 else 1371 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1372 } else 1373 sc->sc_fifo = 0; 1374 1375 /* And copy to tty. */ 1376 tp->t_ispeed = t->c_ospeed; 1377 tp->t_ospeed = t->c_ospeed; 1378 tp->t_cflag = t->c_cflag; 1379 1380 if (!sc->sc_heldchange) { 1381 if (sc->sc_tx_busy) { 1382 sc->sc_heldtbc = sc->sc_tbc; 1383 sc->sc_tbc = 0; 1384 sc->sc_heldchange = 1; 1385 } else 1386 com_loadchannelregs(sc); 1387 } 1388 1389 if (!ISSET(t->c_cflag, CHWFLOW)) { 1390 /* Disable the high water mark. */ 1391 sc->sc_r_hiwat = 0; 1392 sc->sc_r_lowat = 0; 1393 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1394 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1395 com_schedrx(sc); 1396 } 1397 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1398 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1399 com_hwiflow(sc); 1400 } 1401 } else { 1402 sc->sc_r_hiwat = com_rbuf_hiwat; 1403 sc->sc_r_lowat = com_rbuf_lowat; 1404 } 1405 1406 mutex_spin_exit(&sc->sc_lock); 1407 1408 /* 1409 * Update the tty layer's idea of the carrier bit, in case we changed 1410 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1411 * explicit request. 1412 */ 1413 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1414 1415 #ifdef COM_DEBUG 1416 if (com_debug) 1417 comstatus(sc, "comparam "); 1418 #endif 1419 1420 if (!ISSET(t->c_cflag, CHWFLOW)) { 1421 if (sc->sc_tx_stopped) { 1422 sc->sc_tx_stopped = 0; 1423 comstart(tp); 1424 } 1425 } 1426 1427 return (0); 1428 } 1429 1430 void 1431 com_iflush(struct com_softc *sc) 1432 { 1433 struct com_regs *regsp = &sc->sc_regs; 1434 #ifdef DIAGNOSTIC 1435 int reg; 1436 #endif 1437 int timo; 1438 1439 #ifdef DIAGNOSTIC 1440 reg = 0xffff; 1441 #endif 1442 timo = 50000; 1443 /* flush any pending I/O */ 1444 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1445 && --timo) 1446 #ifdef DIAGNOSTIC 1447 reg = 1448 #else 1449 (void) 1450 #endif 1451 CSR_READ_1(regsp, COM_REG_RXDATA); 1452 #ifdef DIAGNOSTIC 1453 if (!timo) 1454 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1455 #endif 1456 } 1457 1458 void 1459 com_loadchannelregs(struct com_softc *sc) 1460 { 1461 struct com_regs *regsp = &sc->sc_regs; 1462 1463 /* XXXXX necessary? */ 1464 com_iflush(sc); 1465 1466 if (sc->sc_type == COM_TYPE_PXA2x0) 1467 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1468 else 1469 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1470 1471 if (sc->sc_type == COM_TYPE_OMAP) { 1472 /* disable before changing settings */ 1473 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1474 } 1475 1476 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1477 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1478 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1479 /* no EFR on alchemy */ 1480 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1481 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1482 } 1483 if (sc->sc_type == COM_TYPE_AU1x00) { 1484 /* alchemy has single separate 16-bit clock divisor register */ 1485 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1486 (sc->sc_dlbh << 8)); 1487 } else { 1488 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1489 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1490 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1491 } 1492 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1493 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1494 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1495 #ifdef COM_HAYESP 1496 if (sc->sc_type == COM_TYPE_HAYESP) { 1497 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1498 HAYESP_SETPRESCALER); 1499 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1500 sc->sc_prescaler); 1501 } 1502 #endif 1503 if (sc->sc_type == COM_TYPE_OMAP) { 1504 /* setup the fifos. the FCR value is not used as long 1505 as SCR[6] and SCR[7] are 0, which they are at reset 1506 and we never touch the SCR register */ 1507 uint8_t rx_fifo_trig = 40; 1508 uint8_t tx_fifo_trig = 60; 1509 uint8_t rx_start = 8; 1510 uint8_t rx_halt = 60; 1511 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1512 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1513 1514 /* enable access to TCR & TLR */ 1515 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1516 1517 /* write tcr and tlr values */ 1518 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1519 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1520 1521 /* disable access to TCR & TLR */ 1522 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1523 1524 /* enable again, but mode is based on speed */ 1525 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1526 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1527 } else { 1528 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1529 } 1530 } 1531 1532 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1533 } 1534 1535 int 1536 comhwiflow(struct tty *tp, int block) 1537 { 1538 struct com_softc *sc = 1539 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1540 1541 if (COM_ISALIVE(sc) == 0) 1542 return (0); 1543 1544 if (sc->sc_mcr_rts == 0) 1545 return (0); 1546 1547 mutex_spin_enter(&sc->sc_lock); 1548 1549 if (block) { 1550 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1551 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1552 com_hwiflow(sc); 1553 } 1554 } else { 1555 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1556 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1557 com_schedrx(sc); 1558 } 1559 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1560 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1561 com_hwiflow(sc); 1562 } 1563 } 1564 1565 mutex_spin_exit(&sc->sc_lock); 1566 return (1); 1567 } 1568 1569 /* 1570 * (un)block input via hw flowcontrol 1571 */ 1572 void 1573 com_hwiflow(struct com_softc *sc) 1574 { 1575 struct com_regs *regsp= &sc->sc_regs; 1576 1577 if (sc->sc_mcr_rts == 0) 1578 return; 1579 1580 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1581 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1582 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1583 } else { 1584 SET(sc->sc_mcr, sc->sc_mcr_rts); 1585 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1586 } 1587 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1588 } 1589 1590 1591 void 1592 comstart(struct tty *tp) 1593 { 1594 struct com_softc *sc = 1595 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1596 struct com_regs *regsp = &sc->sc_regs; 1597 int s; 1598 1599 if (COM_ISALIVE(sc) == 0) 1600 return; 1601 1602 s = spltty(); 1603 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1604 goto out; 1605 if (sc->sc_tx_stopped) 1606 goto out; 1607 if (!ttypull(tp)) 1608 goto out; 1609 1610 /* Grab the first contiguous region of buffer space. */ 1611 { 1612 u_char *tba; 1613 int tbc; 1614 1615 tba = tp->t_outq.c_cf; 1616 tbc = ndqb(&tp->t_outq, 0); 1617 1618 mutex_spin_enter(&sc->sc_lock); 1619 1620 sc->sc_tba = tba; 1621 sc->sc_tbc = tbc; 1622 } 1623 1624 SET(tp->t_state, TS_BUSY); 1625 sc->sc_tx_busy = 1; 1626 1627 /* Enable transmit completion interrupts if necessary. */ 1628 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1629 SET(sc->sc_ier, IER_ETXRDY); 1630 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1631 } 1632 1633 /* Output the first chunk of the contiguous buffer. */ 1634 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1635 u_int n; 1636 1637 n = sc->sc_tbc; 1638 if (n > sc->sc_fifolen) 1639 n = sc->sc_fifolen; 1640 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1641 sc->sc_tbc -= n; 1642 sc->sc_tba += n; 1643 } 1644 1645 mutex_spin_exit(&sc->sc_lock); 1646 out: 1647 splx(s); 1648 return; 1649 } 1650 1651 /* 1652 * Stop output on a line. 1653 */ 1654 void 1655 comstop(struct tty *tp, int flag) 1656 { 1657 struct com_softc *sc = 1658 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1659 1660 mutex_spin_enter(&sc->sc_lock); 1661 if (ISSET(tp->t_state, TS_BUSY)) { 1662 /* Stop transmitting at the next chunk. */ 1663 sc->sc_tbc = 0; 1664 sc->sc_heldtbc = 0; 1665 if (!ISSET(tp->t_state, TS_TTSTOP)) 1666 SET(tp->t_state, TS_FLUSH); 1667 } 1668 mutex_spin_exit(&sc->sc_lock); 1669 } 1670 1671 void 1672 comdiag(void *arg) 1673 { 1674 struct com_softc *sc = arg; 1675 int overflows, floods; 1676 1677 mutex_spin_enter(&sc->sc_lock); 1678 overflows = sc->sc_overflows; 1679 sc->sc_overflows = 0; 1680 floods = sc->sc_floods; 1681 sc->sc_floods = 0; 1682 sc->sc_errors = 0; 1683 mutex_spin_exit(&sc->sc_lock); 1684 1685 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1686 device_xname(sc->sc_dev), 1687 overflows, overflows == 1 ? "" : "s", 1688 floods, floods == 1 ? "" : "s"); 1689 } 1690 1691 integrate void 1692 com_rxsoft(struct com_softc *sc, struct tty *tp) 1693 { 1694 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1695 u_char *get, *end; 1696 u_int cc, scc; 1697 u_char lsr; 1698 int code; 1699 1700 end = sc->sc_ebuf; 1701 get = sc->sc_rbget; 1702 scc = cc = com_rbuf_size - sc->sc_rbavail; 1703 1704 if (cc == com_rbuf_size) { 1705 sc->sc_floods++; 1706 if (sc->sc_errors++ == 0) 1707 callout_reset(&sc->sc_diag_callout, 60 * hz, 1708 comdiag, sc); 1709 } 1710 1711 /* If not yet open, drop the entire buffer content here */ 1712 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1713 get += cc << 1; 1714 if (get >= end) 1715 get -= com_rbuf_size << 1; 1716 cc = 0; 1717 } 1718 while (cc) { 1719 code = get[0]; 1720 lsr = get[1]; 1721 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1722 if (ISSET(lsr, LSR_OE)) { 1723 sc->sc_overflows++; 1724 if (sc->sc_errors++ == 0) 1725 callout_reset(&sc->sc_diag_callout, 1726 60 * hz, comdiag, sc); 1727 } 1728 if (ISSET(lsr, LSR_BI | LSR_FE)) 1729 SET(code, TTY_FE); 1730 if (ISSET(lsr, LSR_PE)) 1731 SET(code, TTY_PE); 1732 } 1733 if ((*rint)(code, tp) == -1) { 1734 /* 1735 * The line discipline's buffer is out of space. 1736 */ 1737 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1738 /* 1739 * We're either not using flow control, or the 1740 * line discipline didn't tell us to block for 1741 * some reason. Either way, we have no way to 1742 * know when there's more space available, so 1743 * just drop the rest of the data. 1744 */ 1745 get += cc << 1; 1746 if (get >= end) 1747 get -= com_rbuf_size << 1; 1748 cc = 0; 1749 } else { 1750 /* 1751 * Don't schedule any more receive processing 1752 * until the line discipline tells us there's 1753 * space available (through comhwiflow()). 1754 * Leave the rest of the data in the input 1755 * buffer. 1756 */ 1757 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1758 } 1759 break; 1760 } 1761 get += 2; 1762 if (get >= end) 1763 get = sc->sc_rbuf; 1764 cc--; 1765 } 1766 1767 if (cc != scc) { 1768 sc->sc_rbget = get; 1769 mutex_spin_enter(&sc->sc_lock); 1770 1771 cc = sc->sc_rbavail += scc - cc; 1772 /* Buffers should be ok again, release possible block. */ 1773 if (cc >= sc->sc_r_lowat) { 1774 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1775 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1776 SET(sc->sc_ier, IER_ERXRDY); 1777 #ifdef COM_PXA2X0 1778 if (sc->sc_type == COM_TYPE_PXA2x0) 1779 SET(sc->sc_ier, IER_ERXTOUT); 1780 #endif 1781 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1782 } 1783 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1784 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1785 com_hwiflow(sc); 1786 } 1787 } 1788 mutex_spin_exit(&sc->sc_lock); 1789 } 1790 } 1791 1792 integrate void 1793 com_txsoft(struct com_softc *sc, struct tty *tp) 1794 { 1795 1796 CLR(tp->t_state, TS_BUSY); 1797 if (ISSET(tp->t_state, TS_FLUSH)) 1798 CLR(tp->t_state, TS_FLUSH); 1799 else 1800 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1801 (*tp->t_linesw->l_start)(tp); 1802 } 1803 1804 integrate void 1805 com_stsoft(struct com_softc *sc, struct tty *tp) 1806 { 1807 u_char msr, delta; 1808 1809 mutex_spin_enter(&sc->sc_lock); 1810 msr = sc->sc_msr; 1811 delta = sc->sc_msr_delta; 1812 sc->sc_msr_delta = 0; 1813 mutex_spin_exit(&sc->sc_lock); 1814 1815 if (ISSET(delta, sc->sc_msr_dcd)) { 1816 /* 1817 * Inform the tty layer that carrier detect changed. 1818 */ 1819 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1820 } 1821 1822 if (ISSET(delta, sc->sc_msr_cts)) { 1823 /* Block or unblock output according to flow control. */ 1824 if (ISSET(msr, sc->sc_msr_cts)) { 1825 sc->sc_tx_stopped = 0; 1826 (*tp->t_linesw->l_start)(tp); 1827 } else { 1828 sc->sc_tx_stopped = 1; 1829 } 1830 } 1831 1832 #ifdef COM_DEBUG 1833 if (com_debug) 1834 comstatus(sc, "com_stsoft"); 1835 #endif 1836 } 1837 1838 void 1839 comsoft(void *arg) 1840 { 1841 struct com_softc *sc = arg; 1842 struct tty *tp; 1843 1844 if (COM_ISALIVE(sc) == 0) 1845 return; 1846 1847 tp = sc->sc_tty; 1848 1849 if (sc->sc_rx_ready) { 1850 sc->sc_rx_ready = 0; 1851 com_rxsoft(sc, tp); 1852 } 1853 1854 if (sc->sc_st_check) { 1855 sc->sc_st_check = 0; 1856 com_stsoft(sc, tp); 1857 } 1858 1859 if (sc->sc_tx_done) { 1860 sc->sc_tx_done = 0; 1861 com_txsoft(sc, tp); 1862 } 1863 } 1864 1865 int 1866 comintr(void *arg) 1867 { 1868 struct com_softc *sc = arg; 1869 struct com_regs *regsp = &sc->sc_regs; 1870 1871 u_char *put, *end; 1872 u_int cc; 1873 u_char lsr, iir; 1874 1875 if (COM_ISALIVE(sc) == 0) 1876 return (0); 1877 1878 KASSERT(regsp != NULL); 1879 1880 mutex_spin_enter(&sc->sc_lock); 1881 iir = CSR_READ_1(regsp, COM_REG_IIR); 1882 if (ISSET(iir, IIR_NOPEND)) { 1883 mutex_spin_exit(&sc->sc_lock); 1884 return (0); 1885 } 1886 1887 end = sc->sc_ebuf; 1888 put = sc->sc_rbput; 1889 cc = sc->sc_rbavail; 1890 1891 again: do { 1892 u_char msr, delta; 1893 1894 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1895 if (ISSET(lsr, LSR_BI)) { 1896 int cn_trapped = 0; 1897 1898 cn_check_magic(sc->sc_tty->t_dev, 1899 CNC_BREAK, com_cnm_state); 1900 if (cn_trapped) 1901 continue; 1902 #if defined(KGDB) && !defined(DDB) 1903 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1904 kgdb_connect(1); 1905 continue; 1906 } 1907 #endif 1908 } 1909 1910 if (ISSET(lsr, LSR_RCV_MASK) && 1911 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1912 while (cc > 0) { 1913 int cn_trapped = 0; 1914 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1915 put[1] = lsr; 1916 cn_check_magic(sc->sc_tty->t_dev, 1917 put[0], com_cnm_state); 1918 if (cn_trapped) 1919 goto next; 1920 put += 2; 1921 if (put >= end) 1922 put = sc->sc_rbuf; 1923 cc--; 1924 next: 1925 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1926 if (!ISSET(lsr, LSR_RCV_MASK)) 1927 break; 1928 } 1929 1930 /* 1931 * Current string of incoming characters ended because 1932 * no more data was available or we ran out of space. 1933 * Schedule a receive event if any data was received. 1934 * If we're out of space, turn off receive interrupts. 1935 */ 1936 sc->sc_rbput = put; 1937 sc->sc_rbavail = cc; 1938 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1939 sc->sc_rx_ready = 1; 1940 1941 /* 1942 * See if we are in danger of overflowing a buffer. If 1943 * so, use hardware flow control to ease the pressure. 1944 */ 1945 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1946 cc < sc->sc_r_hiwat) { 1947 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1948 com_hwiflow(sc); 1949 } 1950 1951 /* 1952 * If we're out of space, disable receive interrupts 1953 * until the queue has drained a bit. 1954 */ 1955 if (!cc) { 1956 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1957 #ifdef COM_PXA2X0 1958 if (sc->sc_type == COM_TYPE_PXA2x0) 1959 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1960 else 1961 #endif 1962 CLR(sc->sc_ier, IER_ERXRDY); 1963 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1964 } 1965 } else { 1966 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1967 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1968 continue; 1969 } 1970 } 1971 1972 msr = CSR_READ_1(regsp, COM_REG_MSR); 1973 delta = msr ^ sc->sc_msr; 1974 sc->sc_msr = msr; 1975 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1976 (delta & MSR_DCD)) { 1977 mutex_spin_enter(&timecounter_lock); 1978 pps_capture(&sc->sc_pps_state); 1979 pps_event(&sc->sc_pps_state, 1980 (msr & MSR_DCD) ? 1981 PPS_CAPTUREASSERT : 1982 PPS_CAPTURECLEAR); 1983 mutex_spin_exit(&timecounter_lock); 1984 } 1985 1986 /* 1987 * Process normal status changes 1988 */ 1989 if (ISSET(delta, sc->sc_msr_mask)) { 1990 SET(sc->sc_msr_delta, delta); 1991 1992 /* 1993 * Stop output immediately if we lose the output 1994 * flow control signal or carrier detect. 1995 */ 1996 if (ISSET(~msr, sc->sc_msr_mask)) { 1997 sc->sc_tbc = 0; 1998 sc->sc_heldtbc = 0; 1999 #ifdef COM_DEBUG 2000 if (com_debug) 2001 comstatus(sc, "comintr "); 2002 #endif 2003 } 2004 2005 sc->sc_st_check = 1; 2006 } 2007 } while (!ISSET((iir = 2008 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2009 /* 2010 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2011 * by IIR read, so we can't do this way: `process all interrupts, 2012 * then do TX if possble'. 2013 */ 2014 (iir & IIR_IMASK) != IIR_TXRDY); 2015 2016 /* 2017 * Read LSR again, since there may be an interrupt between 2018 * the last LSR read and IIR read above. 2019 */ 2020 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2021 2022 /* 2023 * See if data can be transmitted as well. 2024 * Schedule tx done event if no data left 2025 * and tty was marked busy. 2026 */ 2027 if (ISSET(lsr, LSR_TXRDY)) { 2028 /* 2029 * If we've delayed a parameter change, do it now, and restart 2030 * output. 2031 */ 2032 if (sc->sc_heldchange) { 2033 com_loadchannelregs(sc); 2034 sc->sc_heldchange = 0; 2035 sc->sc_tbc = sc->sc_heldtbc; 2036 sc->sc_heldtbc = 0; 2037 } 2038 2039 /* Output the next chunk of the contiguous buffer, if any. */ 2040 if (sc->sc_tbc > 0) { 2041 u_int n; 2042 2043 n = sc->sc_tbc; 2044 if (n > sc->sc_fifolen) 2045 n = sc->sc_fifolen; 2046 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2047 sc->sc_tbc -= n; 2048 sc->sc_tba += n; 2049 } else { 2050 /* Disable transmit completion interrupts if necessary. */ 2051 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2052 CLR(sc->sc_ier, IER_ETXRDY); 2053 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2054 } 2055 if (sc->sc_tx_busy) { 2056 sc->sc_tx_busy = 0; 2057 sc->sc_tx_done = 1; 2058 } 2059 } 2060 } 2061 2062 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2063 goto again; 2064 2065 mutex_spin_exit(&sc->sc_lock); 2066 2067 /* Wake up the poller. */ 2068 softint_schedule(sc->sc_si); 2069 2070 #if NRND > 0 && defined(RND_COM) 2071 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2072 #endif 2073 2074 return (1); 2075 } 2076 2077 /* 2078 * The following functions are polled getc and putc routines, shared 2079 * by the console and kgdb glue. 2080 * 2081 * The read-ahead code is so that you can detect pending in-band 2082 * cn_magic in polled mode while doing output rather than having to 2083 * wait until the kernel decides it needs input. 2084 */ 2085 2086 #define MAX_READAHEAD 20 2087 static int com_readahead[MAX_READAHEAD]; 2088 static int com_readaheadcount = 0; 2089 2090 int 2091 com_common_getc(dev_t dev, struct com_regs *regsp) 2092 { 2093 int s = splserial(); 2094 u_char stat, c; 2095 2096 /* got a character from reading things earlier */ 2097 if (com_readaheadcount > 0) { 2098 int i; 2099 2100 c = com_readahead[0]; 2101 for (i = 1; i < com_readaheadcount; i++) { 2102 com_readahead[i-1] = com_readahead[i]; 2103 } 2104 com_readaheadcount--; 2105 splx(s); 2106 return (c); 2107 } 2108 2109 /* block until a character becomes available */ 2110 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2111 ; 2112 2113 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2114 stat = CSR_READ_1(regsp, COM_REG_IIR); 2115 { 2116 int cn_trapped = 0; /* unused */ 2117 #ifdef DDB 2118 extern int db_active; 2119 if (!db_active) 2120 #endif 2121 cn_check_magic(dev, c, com_cnm_state); 2122 } 2123 splx(s); 2124 return (c); 2125 } 2126 2127 static void 2128 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2129 { 2130 int s = splserial(); 2131 int cin, stat, timo; 2132 2133 if (com_readaheadcount < MAX_READAHEAD 2134 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2135 int cn_trapped = 0; 2136 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2137 stat = CSR_READ_1(regsp, COM_REG_IIR); 2138 cn_check_magic(dev, cin, com_cnm_state); 2139 com_readahead[com_readaheadcount++] = cin; 2140 } 2141 2142 /* wait for any pending transmission to finish */ 2143 timo = 150000; 2144 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2145 continue; 2146 2147 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2148 COM_BARRIER(regsp, BR | BW); 2149 2150 splx(s); 2151 } 2152 2153 /* 2154 * Initialize UART for use as console or KGDB line. 2155 */ 2156 int 2157 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2158 tcflag_t cflag) 2159 { 2160 2161 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2162 ®sp->cr_ioh)) 2163 return (ENOMEM); /* ??? */ 2164 2165 if (type == COM_TYPE_OMAP) { 2166 /* disable before changing settings */ 2167 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2168 } 2169 2170 rate = comspeed(rate, frequency, type); 2171 if (type != COM_TYPE_AU1x00) { 2172 /* no EFR on alchemy */ 2173 if (type != COM_TYPE_16550_NOERS) { 2174 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2175 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2176 } 2177 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2178 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2179 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2180 } else { 2181 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2182 } 2183 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2184 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2185 CSR_WRITE_1(regsp, COM_REG_FIFO, 2186 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2187 2188 if (type == COM_TYPE_OMAP) { 2189 /* setup the fifos. the FCR value is not used as long 2190 as SCR[6] and SCR[7] are 0, which they are at reset 2191 and we never touch the SCR register */ 2192 uint8_t rx_fifo_trig = 40; 2193 uint8_t tx_fifo_trig = 60; 2194 uint8_t rx_start = 8; 2195 uint8_t rx_halt = 60; 2196 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2197 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2198 2199 /* enable access to TCR & TLR */ 2200 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2201 2202 /* write tcr and tlr values */ 2203 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2204 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2205 2206 /* disable access to TCR & TLR */ 2207 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2208 2209 /* enable again, but mode is based on speed */ 2210 if (rate > 230400) { 2211 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2212 } else { 2213 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2214 } 2215 } 2216 2217 #ifdef COM_PXA2X0 2218 if (type == COM_TYPE_PXA2x0) 2219 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2220 else 2221 #endif 2222 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2223 2224 return (0); 2225 } 2226 2227 int 2228 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2229 tcflag_t cflag) 2230 { 2231 int res; 2232 2233 comcons_info.regs = *regsp; 2234 2235 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2236 if (res) 2237 return (res); 2238 2239 cn_tab = &comcons; 2240 cn_init_magic(&com_cnm_state); 2241 cn_set_magic("\047\001"); /* default magic is BREAK */ 2242 2243 comcons_info.frequency = frequency; 2244 comcons_info.type = type; 2245 comcons_info.rate = rate; 2246 comcons_info.cflag = cflag; 2247 2248 return (0); 2249 } 2250 2251 int 2252 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2253 int type, tcflag_t cflag) 2254 { 2255 struct com_regs regs; 2256 2257 memset(®s, 0, sizeof regs); 2258 regs.cr_iot = iot; 2259 regs.cr_iobase = iobase; 2260 regs.cr_nports = COM_NPORTS; 2261 #ifdef COM_REGMAP 2262 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2263 #endif 2264 2265 return comcnattach1(®s, rate, frequency, type, cflag); 2266 } 2267 2268 static int 2269 comcnreattach(void) 2270 { 2271 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2272 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2273 } 2274 2275 int 2276 comcngetc(dev_t dev) 2277 { 2278 2279 return (com_common_getc(dev, &comcons_info.regs)); 2280 } 2281 2282 /* 2283 * Console kernel output character routine. 2284 */ 2285 void 2286 comcnputc(dev_t dev, int c) 2287 { 2288 2289 com_common_putc(dev, &comcons_info.regs, c); 2290 } 2291 2292 void 2293 comcnpollc(dev_t dev, int on) 2294 { 2295 2296 } 2297 2298 #ifdef KGDB 2299 int 2300 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2301 tcflag_t cflag) 2302 { 2303 int res; 2304 2305 if (regsp->cr_iot == comcons_info.regs.cr_iot && 2306 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2307 #if !defined(DDB) 2308 return (EBUSY); /* cannot share with console */ 2309 #else 2310 comkgdbregs = *regsp; 2311 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2312 #endif 2313 } else { 2314 comkgdbregs = *regsp; 2315 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2316 if (res) 2317 return (res); 2318 2319 /* 2320 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2321 * expects this to be initialized 2322 */ 2323 cn_init_magic(&com_cnm_state); 2324 cn_set_magic("\047\001"); 2325 } 2326 2327 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2328 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2329 2330 return (0); 2331 } 2332 2333 int 2334 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2335 int frequency, int type, tcflag_t cflag) 2336 { 2337 struct com_regs regs; 2338 2339 regs.cr_iot = iot; 2340 regs.cr_nports = COM_NPORTS; 2341 regs.cr_iobase = iobase; 2342 #ifdef COM_REGMAP 2343 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2344 #endif 2345 2346 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2347 } 2348 2349 /* ARGSUSED */ 2350 int 2351 com_kgdb_getc(void *arg) 2352 { 2353 2354 return (com_common_getc(NODEV, &comkgdbregs)); 2355 } 2356 2357 /* ARGSUSED */ 2358 void 2359 com_kgdb_putc(void *arg, int c) 2360 { 2361 2362 com_common_putc(NODEV, &comkgdbregs, c); 2363 } 2364 #endif /* KGDB */ 2365 2366 /* helper function to identify the com ports used by 2367 console or KGDB (and not yet autoconf attached) */ 2368 int 2369 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2370 { 2371 bus_space_handle_t help; 2372 2373 if (!comconsattached && 2374 iot == comcons_info.regs.cr_iot && 2375 iobase == comcons_info.regs.cr_iobase) 2376 help = comcons_info.regs.cr_ioh; 2377 #ifdef KGDB 2378 else if (!com_kgdb_attached && 2379 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2380 help = comkgdbregs.cr_ioh; 2381 #endif 2382 else 2383 return (0); 2384 2385 if (ioh) 2386 *ioh = help; 2387 return (1); 2388 } 2389 2390 /* 2391 * this routine exists to serve as a shutdown hook for systems that 2392 * have firmware which doesn't interact properly with a com device in 2393 * FIFO mode. 2394 */ 2395 bool 2396 com_cleanup(device_t self, int how) 2397 { 2398 struct com_softc *sc = device_private(self); 2399 2400 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2401 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2402 2403 return true; 2404 } 2405 2406 bool 2407 com_suspend(device_t self, pmf_qual_t qual) 2408 { 2409 struct com_softc *sc = device_private(self); 2410 2411 #if 0 2412 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2413 cn_tab = &comcons_suspend; 2414 #endif 2415 2416 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2417 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2418 2419 return true; 2420 } 2421 2422 bool 2423 com_resume(device_t self, pmf_qual_t qual) 2424 { 2425 struct com_softc *sc = device_private(self); 2426 2427 mutex_spin_enter(&sc->sc_lock); 2428 com_loadchannelregs(sc); 2429 mutex_spin_exit(&sc->sc_lock); 2430 2431 return true; 2432 } 2433