1 /* $NetBSD: atwvar.h,v 1.17 2005/12/11 12:21:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_IC_ATWVAR_H_ 39 #define _DEV_IC_ATWVAR_H_ 40 41 #include <sys/queue.h> 42 #include <sys/callout.h> 43 #include <sys/time.h> 44 45 /* 46 * Some misc. statics, useful for debugging. 47 */ 48 struct atw_stats { 49 u_long ts_tx_tuf; /* transmit underflow errors */ 50 u_long ts_tx_tro; /* transmit jabber timeouts */ 51 u_long ts_tx_trt; /* retry count exceeded */ 52 u_long ts_tx_tlt; /* lifetime exceeded */ 53 u_long ts_tx_sofbr; /* packet size mismatch */ 54 }; 55 56 /* 57 * Transmit descriptor list size. This is arbitrary, but allocate 58 * enough descriptors for 64 pending transmissions and 16 segments 59 * per packet. Since a descriptor holds 2 buffer addresses, that's 60 * 8 descriptors per packet. This MUST work out to a power of 2. 61 */ 62 #define ATW_NTXSEGS 16 63 64 #define ATW_TXQUEUELEN 64 65 #define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS) 66 #define ATW_NTXDESC_MASK (ATW_NTXDESC - 1) 67 #define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK) 68 69 /* 70 * Receive descriptor list size. We have one Rx buffer per incoming 71 * packet, so this logic is a little simpler. 72 */ 73 #define ATW_NRXDESC 64 74 #define ATW_NRXDESC_MASK (ATW_NRXDESC - 1) 75 #define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK) 76 77 /* 78 * Control structures are DMA'd to the ADM8211 chip. We allocate them in 79 * a single clump that maps to a single DMA segment to make several things 80 * easier. 81 */ 82 struct atw_control_data { 83 /* 84 * The transmit descriptors. 85 */ 86 struct atw_txdesc acd_txdescs[ATW_NTXDESC]; 87 88 /* 89 * The receive descriptors. 90 */ 91 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC]; 92 }; 93 94 #define ATW_CDOFF(x) offsetof(struct atw_control_data, x) 95 #define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)]) 96 #define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)]) 97 /* 98 * Software state for transmit jobs. 99 */ 100 struct atw_txsoft { 101 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 102 bus_dmamap_t txs_dmamap; /* our DMA map */ 103 int txs_firstdesc; /* first descriptor in packet */ 104 int txs_lastdesc; /* last descriptor in packet */ 105 int txs_ndescs; /* number of descriptors */ 106 SIMPLEQ_ENTRY(atw_txsoft) txs_q; 107 }; 108 109 SIMPLEQ_HEAD(atw_txsq, atw_txsoft); 110 111 /* 112 * Software state for receive jobs. 113 */ 114 struct atw_rxsoft { 115 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 116 bus_dmamap_t rxs_dmamap; /* our DMA map */ 117 }; 118 119 /* 120 * Table which describes the transmit threshold mode. We generally 121 * start at index 0. Whenever we get a transmit underrun, we increment 122 * our index, falling back if we encounter the NULL terminator. 123 */ 124 struct atw_txthresh_tab { 125 u_int32_t txth_opmode; /* OPMODE bits */ 126 const char *txth_name; /* name of mode */ 127 }; 128 129 #define ATW_TXTHRESH_TAB_LO_RATE { \ 130 { ATW_NAR_TR_L64, "64 bytes" }, \ 131 { ATW_NAR_TR_L160, "160 bytes" }, \ 132 { ATW_NAR_TR_L192, "192 bytes" }, \ 133 { ATW_NAR_SF, "store and forward" }, \ 134 { 0, NULL }, \ 135 } 136 137 #define ATW_TXTHRESH_TAB_HI_RATE { \ 138 { ATW_NAR_TR_H96, "96 bytes" }, \ 139 { ATW_NAR_TR_H288, "288 bytes" }, \ 140 { ATW_NAR_TR_H544, "544 bytes" }, \ 141 { ATW_NAR_SF, "store and forward" }, \ 142 { 0, NULL }, \ 143 } 144 145 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1, 146 ATW_RFTYPE_MARVEL = 2 }; 147 148 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1, 149 ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD = 5 }; 150 151 /* Radio capture format for ADMtek. */ 152 153 #define ATW_RX_RADIOTAP_PRESENT \ 154 ((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \ 155 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 156 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) 157 158 struct atw_rx_radiotap_header { 159 struct ieee80211_radiotap_header ar_ihdr; 160 u_int8_t ar_flags; 161 u_int8_t ar_rate; 162 u_int16_t ar_chan_freq; 163 u_int16_t ar_chan_flags; 164 u_int8_t ar_antsignal; 165 } __attribute__((__packed__)); 166 167 #define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 168 (1 << IEEE80211_RADIOTAP_RATE) | \ 169 (1 << IEEE80211_RADIOTAP_CHANNEL)) 170 171 struct atw_tx_radiotap_header { 172 struct ieee80211_radiotap_header at_ihdr; 173 u_int8_t at_flags; 174 u_int8_t at_rate; 175 u_int16_t at_chan_freq; 176 u_int16_t at_chan_flags; 177 } __attribute__((__packed__)); 178 179 enum atw_revision { 180 ATW_REVISION_AB = 0x11, /* ADM8211A */ 181 ATW_REVISION_AF = 0x15, /* ADM8211A? */ 182 ATW_REVISION_BA = 0x20, /* ADM8211B */ 183 ATW_REVISION_CA = 0x30 /* ADM8211C/CR */ 184 }; 185 186 struct atw_softc { 187 struct device sc_dev; 188 struct ethercom sc_ec; 189 struct ieee80211com sc_ic; 190 int (*sc_enable)(struct atw_softc *); 191 void (*sc_disable)(struct atw_softc *); 192 void (*sc_power)(struct atw_softc *, int); 193 int (*sc_newstate)(struct ieee80211com *, 194 enum ieee80211_state, int); 195 void (*sc_recv_mgmt)(struct ieee80211com *, 196 struct mbuf *, struct ieee80211_node *, 197 int, int, u_int32_t); 198 struct ieee80211_node *(*sc_node_alloc)(struct ieee80211_node_table*); 199 void (*sc_node_free)(struct ieee80211_node *); 200 201 struct atw_stats sc_stats; /* debugging stats */ 202 203 int sc_tx_timer; 204 int sc_rescan_timer; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_dma_tag_t sc_dmat; /* bus dma tag */ 209 void *sc_sdhook; /* shutdown hook */ 210 void *sc_powerhook; /* power management hook */ 211 u_int32_t sc_cacheline; /* cache line size */ 212 u_int32_t sc_maxburst; /* maximum burst length */ 213 214 const struct atw_txthresh_tab *sc_txth; 215 int sc_txthresh; /* current tx threshold */ 216 217 u_int sc_cur_chan; /* current channel */ 218 219 int sc_flags; 220 221 u_int16_t *sc_srom; 222 u_int16_t sc_sromsz; 223 224 caddr_t sc_radiobpf; 225 226 bus_dma_segment_t sc_cdseg; /* control data memory */ 227 int sc_cdnseg; /* number of segments */ 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN]; 235 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct atw_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->acd_txdescs 242 #define sc_rxdescs sc_control_data->acd_rxdescs 243 #define sc_setup_desc sc_control_data->acd_setup_desc 244 245 int sc_txfree; /* number of free Tx descriptors */ 246 int sc_txnext; /* next ready Tx descriptor */ 247 int sc_ntxsegs; /* number of transmit segs per pkt */ 248 249 struct atw_txsq sc_txfreeq; /* free Tx descsofts */ 250 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */ 251 252 int sc_rxptr; /* next ready RX descriptor/descsoft */ 253 254 u_int32_t sc_busmode; /* copy of ATW_PAR */ 255 u_int32_t sc_opmode; /* copy of ATW_NAR */ 256 u_int32_t sc_inten; /* copy of ATW_IER */ 257 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */ 258 259 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 260 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 261 u_int32_t sc_linkint_mask;/* link-state interrupts mask */ 262 263 /* interrupt acknowledge hook */ 264 void (*sc_intr_ack)(struct atw_softc *); 265 266 enum atw_rftype sc_rftype; 267 enum atw_bbptype sc_bbptype; 268 u_int32_t sc_synctl_rd; 269 u_int32_t sc_synctl_wr; 270 u_int32_t sc_bbpctl_rd; 271 u_int32_t sc_bbpctl_wr; 272 273 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *, 274 int, u_int32_t); 275 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *, 276 int, u_int32_t); 277 278 /* ADM8211 state variables. */ 279 u_int8_t sc_sram[ATW_SRAM_MAXSIZE]; 280 u_int sc_sramlen; 281 u_int8_t sc_bssid[IEEE80211_ADDR_LEN]; 282 uint8_t sc_rev; 283 uint8_t sc_rf3000_options1; 284 uint8_t sc_rf3000_options2; 285 286 struct callout sc_scan_ch; 287 union { 288 struct atw_rx_radiotap_header tap; 289 u_int8_t pad[64]; 290 } sc_rxtapu; 291 union { 292 struct atw_tx_radiotap_header tap; 293 u_int8_t pad[64]; 294 } sc_txtapu; 295 }; 296 297 #define sc_if sc_ec.ec_if 298 #define sc_rxtap sc_rxtapu.tap 299 #define sc_txtap sc_txtapu.tap 300 301 /* XXX this is fragile. try not to introduce any u_int32_t's. */ 302 struct atw_frame { 303 /*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN]; 304 /*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */ 305 /*07*/ u_int8_t atw_service; /* 0 */ 306 /*08*/ u_int16_t atw_paylen; /* payload length */ 307 /*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame 308 * Control 309 */ 310 /* 802.11 PLCP Length for first & last fragment */ 311 /*0c*/ u_int16_t atw_tail_plcplen; 312 /*0e*/ u_int16_t atw_head_plcplen; 313 /* 802.11 Duration for first & last fragment */ 314 /*10*/ u_int16_t atw_tail_dur; 315 /*12*/ u_int16_t atw_head_dur; 316 /*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN]; 317 union { 318 struct { 319 /*1a*/ u_int16_t hdrctl; /*transmission control*/ 320 /*1c*/ u_int16_t fragthr;/* fragmentation threshold 321 * [0:11], zero [12:15]. 322 */ 323 /*1e*/ u_int8_t fragnum;/* fragment number [4:7], 324 * zero [0:3]. 325 */ 326 /*1f*/ u_int8_t rtylmt; /* retry limit */ 327 /*20*/ u_int8_t wepkey0[4];/* ??? */ 328 /*24*/ u_int8_t wepkey1[4];/* ??? */ 329 /*28*/ u_int8_t wepkey2[4];/* ??? */ 330 /*2c*/ u_int8_t wepkey3[4];/* ??? */ 331 /*30*/ u_int8_t keyid; 332 /*31*/ u_int8_t reserved0[7]; 333 } s1; 334 struct { 335 u_int8_t pad[6]; 336 struct ieee80211_frame ihdr; 337 } s2; 338 } u; 339 } __attribute__((__packed__)); 340 341 #define atw_hdrctl u.s1.hdrctl 342 #define atw_fragthr u.s1.fragthr 343 #define atw_fragnum u.s1.fragnum 344 #define atw_rtylmt u.s1.rtylmt 345 #define atw_keyid u.s1.keyid 346 #define atw_ihdr u.s2.ihdr 347 348 #define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */ 349 #define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */ 350 #define ATW_HDRCTL_WEP BIT(5) 351 #define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */ 352 #define ATW_HDRCTL_UNKNOWN2 BIT(8) 353 354 #define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11) 355 #define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7) 356 357 /* Values for sc_flags. */ 358 #define ATWF_MRL 0x00000010 /* memory read line okay */ 359 #define ATWF_MRM 0x00000020 /* memory read multi okay */ 360 #define ATWF_MWI 0x00000040 /* memory write inval okay */ 361 #define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */ 362 #define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */ 363 #define ATWF_ATTACHED 0x00000800 /* attach has succeeded */ 364 #define ATWF_ENABLED 0x00001000 /* chip is enabled */ 365 #define ATWF_WEP_SRAM_VALID 0x00002000 /* SRAM matches s/w state */ 366 367 #define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED) 368 369 #define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x))) 370 #define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x))) 371 372 #define ATW_CDTXSYNC(sc, x, n, ops) \ 373 do { \ 374 int __x, __n; \ 375 \ 376 __x = (x); \ 377 __n = (n); \ 378 \ 379 /* If it will wrap around, sync to the end of the ring. */ \ 380 if ((__x + __n) > ATW_NTXDESC) { \ 381 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 382 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \ 383 (ATW_NTXDESC - __x), (ops)); \ 384 __n -= (ATW_NTXDESC - __x); \ 385 __x = 0; \ 386 } \ 387 \ 388 /* Now sync whatever is left. */ \ 389 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 390 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \ 391 } while (0) 392 393 #define ATW_CDRXSYNC(sc, x, ops) \ 394 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 395 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops)) 396 397 /* 398 * Note we rely on MCLBYTES being a power of two. Because the `length' 399 * field is only 11 bits, we must subtract 1 from the length to avoid 400 * having it truncated to 0! 401 */ 402 #define ATW_INIT_RXDESC(sc, x) \ 403 do { \ 404 struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 405 struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \ 406 struct mbuf *__m = __rxs->rxs_mbuf; \ 407 \ 408 __rxd->ar_buf1 = \ 409 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 410 __rxd->ar_buf2 = /* for descriptor chaining */ \ 411 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \ 412 __rxd->ar_ctl = \ 413 htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \ 414 ATW_RXCTL_RBS1_MASK) | \ 415 0 /* ATW_RXCTL_RCH */ | \ 416 ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \ 417 __rxd->ar_stat = htole32(ATW_RXSTAT_OWN); \ 418 \ 419 ATW_CDRXSYNC((sc), (x), \ 420 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 421 } while (0) 422 423 /* country codes from ADM8211 SROM */ 424 #define ATW_COUNTRY_FCC 0 /* USA 1-11 */ 425 #define ATW_COUNTRY_IC 1 /* Canada 1-11 */ 426 #define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */ 427 #define ATW_COUNTRY_SPAIN 3 /* 10-11 */ 428 #define ATW_COUNTRY_FRANCE 4 /* 10-13 */ 429 #define ATW_COUNTRY_MKK 5 /* Japan: 14 */ 430 #define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */ 431 432 /* 433 * register space access macros 434 */ 435 #define ATW_READ(sc, reg) \ 436 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 437 438 #define ATW_WRITE(sc, reg, val) \ 439 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 440 441 #define ATW_SET(sc, reg, mask) \ 442 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask)) 443 444 #define ATW_CLR(sc, reg, mask) \ 445 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask)) 446 447 #define ATW_ISSET(sc, reg, mask) \ 448 (ATW_READ((sc), (reg)) & (mask)) 449 450 void atw_attach(struct atw_softc *); 451 int atw_detach(struct atw_softc *); 452 int atw_activate(struct device *, enum devact); 453 int atw_intr(void *arg); 454 void atw_power(int, void *); 455 void atw_shutdown(void *); 456 457 #endif /* _DEV_IC_ATWVAR_H_ */ 458