1 /* $NetBSD: atwvar.h,v 1.1 2003/07/06 22:58:09 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_IC_ATWVAR_H_ 39 #define _DEV_IC_ATWVAR_H_ 40 41 #include <sys/queue.h> 42 #include <sys/callout.h> 43 #include <sys/time.h> 44 #if 0 45 #endif 46 47 /* 48 * Some misc. statics, useful for debugging. 49 */ 50 struct atw_stats { 51 u_long ts_tx_tuf; /* transmit underflow errors */ 52 u_long ts_tx_tro; /* transmit jabber timeouts */ 53 u_long ts_tx_trt; /* retry count exceeded */ 54 u_long ts_tx_tlt; /* lifetime exceeded */ 55 u_long ts_tx_sofbr; /* packet size mismatch */ 56 }; 57 58 /* 59 * Transmit descriptor list size. This is arbitrary, but allocate 60 * enough descriptors for 64 pending transmissions and 16 segments 61 * per packet. Since a descriptor holds 2 buffer addresses, that's 62 * 8 descriptors per packet. This MUST work out to a power of 2. 63 */ 64 #define ATW_NTXSEGS 16 65 66 #define ATW_TXQUEUELEN 64 67 #define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS) 68 #define ATW_NTXDESC_MASK (ATW_NTXDESC - 1) 69 #define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK) 70 71 /* 72 * Receive descriptor list size. We have one Rx buffer per incoming 73 * packet, so this logic is a little simpler. 74 */ 75 #define ATW_NRXDESC 64 76 #define ATW_NRXDESC_MASK (ATW_NRXDESC - 1) 77 #define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK) 78 79 /* 80 * Control structures are DMA'd to the ADM8211 chip. We allocate them in 81 * a single clump that maps to a single DMA segment to make several things 82 * easier. 83 */ 84 struct atw_control_data { 85 /* 86 * The transmit descriptors. 87 */ 88 struct atw_txdesc acd_txdescs[ATW_NTXDESC]; 89 90 /* 91 * The receive descriptors. 92 */ 93 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC]; 94 }; 95 96 #define ATW_CDOFF(x) offsetof(struct atw_control_data, x) 97 #define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)]) 98 #define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)]) 99 /* 100 * Software state for transmit jobs. 101 */ 102 struct atw_txsoft { 103 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 104 bus_dmamap_t txs_dmamap; /* our DMA map */ 105 int txs_firstdesc; /* first descriptor in packet */ 106 int txs_lastdesc; /* last descriptor in packet */ 107 int txs_ndescs; /* number of descriptors */ 108 SIMPLEQ_ENTRY(atw_txsoft) txs_q; 109 }; 110 111 SIMPLEQ_HEAD(atw_txsq, atw_txsoft); 112 113 /* 114 * Software state for receive jobs. 115 */ 116 struct atw_rxsoft { 117 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t rxs_dmamap; /* our DMA map */ 119 }; 120 121 /* 122 * Table which describes the transmit threshold mode. We generally 123 * start at index 0. Whenever we get a transmit underrun, we increment 124 * our index, falling back if we encounter the NULL terminator. 125 */ 126 struct atw_txthresh_tab { 127 u_int32_t txth_opmode; /* OPMODE bits */ 128 const char *txth_name; /* name of mode */ 129 }; 130 131 #define ATW_TXTHRESH_TAB_LO_RATE { \ 132 { ATW_NAR_TR_L64, "64 bytes" }, \ 133 { ATW_NAR_TR_L160, "160 bytes" }, \ 134 { ATW_NAR_TR_L192, "192 bytes" }, \ 135 { ATW_NAR_SF, "store and forward" }, \ 136 { 0, NULL }, \ 137 } 138 139 #define ATW_TXTHRESH_TAB_HI_RATE { \ 140 { ATW_NAR_TR_H96, "96 bytes" }, \ 141 { ATW_NAR_TR_H288, "288 bytes" }, \ 142 { ATW_NAR_TR_H544, "544 bytes" }, \ 143 { ATW_NAR_SF, "store and forward" }, \ 144 { 0, NULL }, \ 145 } 146 147 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1, 148 ATW_RFTYPE_MARVEL = 2 }; 149 150 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1, 151 ATW_BBPTYPE_MARVEL = 2 }; 152 153 struct atw_softc { 154 struct device sc_dev; 155 struct ieee80211com sc_ic; 156 void *sc_ih; /* interrupt handler */ 157 int (*sc_enable)(struct atw_softc *); 158 void (*sc_disable)(struct atw_softc *); 159 void (*sc_power)(struct atw_softc *, int); 160 161 int sc_pci; /* attach to PCI-Bus */ 162 163 struct atw_stats sc_stats; /* debugging stats */ 164 165 int sc_tx_timer; 166 int sc_rescan_timer; 167 168 bus_space_tag_t sc_st; /* bus space tag */ 169 bus_space_handle_t sc_sh; /* bus space handle */ 170 bus_dma_tag_t sc_dmat; /* bus dma tag */ 171 void *sc_sdhook; /* shutdown hook */ 172 void *sc_powerhook; /* power management hook */ 173 u_int32_t sc_cacheline; /* cache line size */ 174 u_int32_t sc_maxburst; /* maximum burst length */ 175 176 const struct atw_txthresh_tab *sc_txth; 177 int sc_txthresh; /* current tx threshold */ 178 179 u_int sc_cur_chan; /* current channel */ 180 181 int sc_flags; 182 183 u_int16_t *sc_srom; 184 u_int16_t sc_sromsz; 185 186 caddr_t sc_radiobpf; 187 188 bus_dma_segment_t sc_cdseg; /* control data memory */ 189 int sc_cdnseg; /* number of segments */ 190 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 191 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 192 193 /* 194 * Software state for transmit and receive descriptors. 195 */ 196 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN]; 197 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC]; 198 199 /* 200 * Control data structures. 201 */ 202 struct atw_control_data *sc_control_data; 203 #define sc_txdescs sc_control_data->acd_txdescs 204 #define sc_rxdescs sc_control_data->acd_rxdescs 205 #define sc_setup_desc sc_control_data->acd_setup_desc 206 207 int sc_txfree; /* number of free Tx descriptors */ 208 int sc_txnext; /* next ready Tx descriptor */ 209 int sc_ntxsegs; /* number of transmit segs per pkt */ 210 211 struct atw_txsq sc_txfreeq; /* free Tx descsofts */ 212 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */ 213 214 int sc_rxptr; /* next ready RX descriptor/descsoft */ 215 216 u_int32_t sc_busmode; /* copy of ATW_PAR */ 217 u_int32_t sc_opmode; /* copy of ATW_NAR */ 218 u_int32_t sc_inten; /* copy of ATW_IER */ 219 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */ 220 221 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 222 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 223 u_int32_t sc_linkint_mask;/* link-state interrupts mask */ 224 225 /* interrupt acknowledge hook */ 226 void (*sc_intr_ack) __P((struct atw_softc *)); 227 228 enum atw_rftype sc_rftype; 229 enum atw_bbptype sc_bbptype; 230 u_int32_t sc_synctl_rd; 231 u_int32_t sc_synctl_wr; 232 u_int32_t sc_bbpctl_rd; 233 u_int32_t sc_bbpctl_wr; 234 235 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *, 236 int, u_int32_t); 237 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *, 238 int, u_int32_t); 239 240 /* ADM8211 state variables. */ 241 u_int8_t sc_sram[ATW_SRAM_SIZE]; 242 u_int8_t sc_bssid[IEEE80211_ADDR_LEN]; 243 u_int8_t sc_lost_bcn_thresh; 244 245 struct timeval sc_last_beacon; 246 struct callout sc_scan_timer; 247 }; 248 249 #define sc_if sc_ic.ic_if 250 251 /* XXX this is fragile. try not to introduce any u_int32_t's. */ 252 struct atw_frame { 253 /*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN]; 254 /*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */ 255 /*07*/ u_int8_t atw_service; /* 0 */ 256 /*08*/ u_int16_t atw_paylen; /* payload length */ 257 /*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame 258 * Control 259 */ 260 /* 802.11 PLCP Length for first & last fragment */ 261 /*0c*/ u_int16_t atw_tail_plcplen; 262 /*0e*/ u_int16_t atw_head_plcplen; 263 /* 802.11 Duration for first & last fragment */ 264 /*10*/ u_int16_t atw_tail_dur; 265 /*12*/ u_int16_t atw_head_dur; 266 /*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN]; 267 union { 268 struct { 269 /*1a*/ u_int16_t hdrctl; /*transmission control*/ 270 /*1c*/ u_int16_t fragthr;/* fragmentation threshold 271 * [0:11], zero [12:15]. 272 */ 273 /*1e*/ u_int8_t fragnum;/* fragment number [4:7], 274 * zero [0:3]. 275 */ 276 /*1f*/ u_int8_t rtylmt; /* retry limit */ 277 /*20*/ u_int8_t wepkey0[4];/* ??? */ 278 /*24*/ u_int8_t wepkey1[4];/* ??? */ 279 /*28*/ u_int8_t wepkey2[4];/* ??? */ 280 /*2c*/ u_int8_t wepkey3[4];/* ??? */ 281 /*30*/ u_int8_t keyid; 282 /*31*/ u_int8_t reserved0[7]; 283 } s; 284 struct ieee80211_frame_addr4 ihdr; 285 } u; 286 } __attribute__((__packed__)); 287 288 #define atw_hdrctl u.s.hdrctl 289 #define atw_fragthr u.s.fragthr 290 #define atw_fragnum u.s.fragnum 291 #define atw_rtylmt u.s.rtylmt 292 #define atw_keyid u.s.keyid 293 #define atw_ihdr u.ihdr 294 295 #define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */ 296 #define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */ 297 #define ATW_HDRCTL_WEP BIT(5) 298 #define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */ 299 #define ATW_HDRCTL_UNKNOWN2 BIT(8) 300 301 #define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11) 302 #define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7) 303 304 /* Values for sc_flags. */ 305 #define ATWF_MRL 0x00000010 /* memory read line okay */ 306 #define ATWF_MRM 0x00000020 /* memory read multi okay */ 307 #define ATWF_MWI 0x00000040 /* memory write inval okay */ 308 #define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */ 309 #define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */ 310 #define ATWF_ATTACHED 0x00000800 /* attach has succeeded */ 311 #define ATWF_ENABLED 0x00001000 /* chip is enabled */ 312 313 #define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED) 314 315 #define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x))) 316 #define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x))) 317 318 #define ATW_CDTXSYNC(sc, x, n, ops) \ 319 do { \ 320 int __x, __n; \ 321 \ 322 __x = (x); \ 323 __n = (n); \ 324 \ 325 /* If it will wrap around, sync to the end of the ring. */ \ 326 if ((__x + __n) > ATW_NTXDESC) { \ 327 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 328 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \ 329 (ATW_NTXDESC - __x), (ops)); \ 330 __n -= (ATW_NTXDESC - __x); \ 331 __x = 0; \ 332 } \ 333 \ 334 /* Now sync whatever is left. */ \ 335 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 336 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \ 337 } while (0) 338 339 #define ATW_CDRXSYNC(sc, x, ops) \ 340 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 341 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops)) 342 343 /* 344 * Note we rely on MCLBYTES being a power of two. Because the `length' 345 * field is only 11 bits, we must subtract 1 from the length to avoid 346 * having it truncated to 0! 347 * 348 * Apparently we have to set ATW_RXSTAT_SQL to make the ADM8211 tell 349 * us RSSI. 350 */ 351 #define ATW_INIT_RXDESC(sc, x) \ 352 do { \ 353 struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 354 struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \ 355 struct mbuf *__m = __rxs->rxs_mbuf; \ 356 \ 357 __m->m_data = __m->m_ext.ext_buf; \ 358 __rxd->ar_buf1 = \ 359 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 360 __rxd->ar_buf2 = /* for descriptor chaining */ \ 361 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \ 362 __rxd->ar_ctl = \ 363 htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \ 364 ATW_RXCTL_RBS1_MASK) | \ 365 0 /* ATW_RXCTL_RCH */ | \ 366 ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \ 367 __rxd->ar_stat = \ 368 htole32(ATW_RXSTAT_OWN|ATW_RXSTAT_SQL|ATW_RXSTAT_FS| \ 369 ATW_RXSTAT_LS); \ 370 ATW_CDRXSYNC((sc), (x), \ 371 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 372 } while (0) 373 374 /* country codes from ADM8211 SROM */ 375 #define ATW_COUNTRY_FCC 0 /* USA 1-11 */ 376 #define ATW_COUNTRY_IC 1 /* Canada 1-11 */ 377 #define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */ 378 #define ATW_COUNTRY_SPAIN 3 /* 10-11 */ 379 #define ATW_COUNTRY_FRANCE 4 /* 10-13 */ 380 #define ATW_COUNTRY_MKK 5 /* Japan: 14 */ 381 #define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */ 382 383 /* 384 * register space access macros 385 */ 386 #define ATW_READ(sc, reg) \ 387 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 388 389 #define ATW_WRITE(sc, reg, val) \ 390 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 391 392 #define ATW_SET(sc, reg, mask) \ 393 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask)) 394 395 #define ATW_CLR(sc, reg, mask) \ 396 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask)) 397 398 #define ATW_ISSET(sc, reg, mask) \ 399 (ATW_READ((sc), (reg)) & (mask)) 400 401 void atw_attach __P((struct atw_softc *)); 402 int atw_detach __P((struct atw_softc *)); 403 int atw_activate __P((struct device *, enum devact)); 404 int atw_intr __P((void *arg)); 405 void atw_power __P((int, void *)); 406 void atw_shutdown __P((void *)); 407 408 #endif /* _DEV_IC_ATWVAR_H_ */ 409