1 /* $NetBSD: atwvar.h,v 1.26 2007/11/16 23:51:02 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_IC_ATWVAR_H_ 39 #define _DEV_IC_ATWVAR_H_ 40 41 #include <sys/queue.h> 42 #include <sys/callout.h> 43 #include <sys/time.h> 44 45 /* 46 * Some misc. statics, useful for debugging. 47 */ 48 struct atw_stats { 49 u_long ts_tx_tuf; /* transmit underflow errors */ 50 u_long ts_tx_tro; /* transmit jabber timeouts */ 51 u_long ts_tx_trt; /* retry count exceeded */ 52 u_long ts_tx_tlt; /* lifetime exceeded */ 53 u_long ts_tx_sofbr; /* packet size mismatch */ 54 }; 55 56 /* 57 * Transmit descriptor list size. This is arbitrary, but allocate 58 * enough descriptors for 64 pending transmissions and 16 segments 59 * per packet. Since a descriptor holds 2 buffer addresses, that's 60 * 8 descriptors per packet. This MUST work out to a power of 2. 61 */ 62 #define ATW_NTXSEGS 16 63 64 #define ATW_TXQUEUELEN 64 65 #define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS) 66 #define ATW_NTXDESC_MASK (ATW_NTXDESC - 1) 67 #define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK) 68 69 /* 70 * Receive descriptor list size. We have one Rx buffer per incoming 71 * packet, so this logic is a little simpler. 72 */ 73 #define ATW_NRXDESC 64 74 #define ATW_NRXDESC_MASK (ATW_NRXDESC - 1) 75 #define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK) 76 77 /* 78 * Control structures are DMA'd to the ADM8211 chip. We allocate them in 79 * a single clump that maps to a single DMA segment to make several things 80 * easier. 81 */ 82 struct atw_control_data { 83 /* 84 * The transmit descriptors. 85 */ 86 struct atw_txdesc acd_txdescs[ATW_NTXDESC]; 87 88 /* 89 * The receive descriptors. 90 */ 91 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC]; 92 }; 93 94 #define ATW_CDOFF(x) offsetof(struct atw_control_data, x) 95 #define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)]) 96 #define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)]) 97 /* 98 * Software state for transmit jobs. 99 */ 100 struct atw_txsoft { 101 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 102 bus_dmamap_t txs_dmamap; /* our DMA map */ 103 int txs_firstdesc; /* first descriptor in packet */ 104 int txs_lastdesc; /* last descriptor in packet */ 105 int txs_ndescs; /* number of descriptors */ 106 struct ieee80211_duration txs_d0; 107 struct ieee80211_duration txs_dn; 108 SIMPLEQ_ENTRY(atw_txsoft) txs_q; 109 }; 110 111 SIMPLEQ_HEAD(atw_txsq, atw_txsoft); 112 113 /* 114 * Software state for receive jobs. 115 */ 116 struct atw_rxsoft { 117 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t rxs_dmamap; /* our DMA map */ 119 }; 120 121 /* 122 * Table which describes the transmit threshold mode. We generally 123 * start at index 0. Whenever we get a transmit underrun, we increment 124 * our index, falling back if we encounter the NULL terminator. 125 */ 126 struct atw_txthresh_tab { 127 u_int32_t txth_opmode; /* OPMODE bits */ 128 const char *txth_name; /* name of mode */ 129 }; 130 131 #define ATW_TXTHRESH_TAB_LO_RATE { \ 132 { ATW_NAR_TR_L64, "64 bytes" }, \ 133 { ATW_NAR_TR_L160, "160 bytes" }, \ 134 { ATW_NAR_TR_L192, "192 bytes" }, \ 135 { ATW_NAR_SF, "store and forward" }, \ 136 { 0, NULL }, \ 137 } 138 139 #define ATW_TXTHRESH_TAB_HI_RATE { \ 140 { ATW_NAR_TR_H96, "96 bytes" }, \ 141 { ATW_NAR_TR_H288, "288 bytes" }, \ 142 { ATW_NAR_TR_H544, "544 bytes" }, \ 143 { ATW_NAR_SF, "store and forward" }, \ 144 { 0, NULL }, \ 145 } 146 147 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1, 148 ATW_RFTYPE_MARVEL = 2 }; 149 150 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1, 151 ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD = 5 }; 152 153 /* Radio capture format for ADMtek. */ 154 155 #define ATW_RX_RADIOTAP_PRESENT \ 156 ((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \ 157 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 158 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) 159 160 struct atw_rx_radiotap_header { 161 struct ieee80211_radiotap_header ar_ihdr; 162 uint8_t ar_flags; 163 uint8_t ar_rate; 164 uint16_t ar_chan_freq; 165 uint16_t ar_chan_flags; 166 uint8_t ar_antsignal; 167 } __attribute__((__packed__)); 168 169 #define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_RATE) | \ 170 (1 << IEEE80211_RADIOTAP_CHANNEL)) 171 172 struct atw_tx_radiotap_header { 173 struct ieee80211_radiotap_header at_ihdr; 174 uint8_t at_rate; 175 uint8_t at_pad; 176 uint16_t at_chan_freq; 177 uint16_t at_chan_flags; 178 } __attribute__((__packed__)); 179 180 enum atw_revision { 181 ATW_REVISION_AB = 0x11, /* ADM8211A */ 182 ATW_REVISION_AF = 0x15, /* ADM8211A? */ 183 ATW_REVISION_BA = 0x20, /* ADM8211B */ 184 ATW_REVISION_CA = 0x30 /* ADM8211C/CR */ 185 }; 186 187 struct atw_softc { 188 struct device sc_dev; 189 struct ethercom sc_ec; 190 struct ieee80211com sc_ic; 191 int (*sc_enable)(struct atw_softc *); 192 void (*sc_disable)(struct atw_softc *); 193 void (*sc_power)(struct atw_softc *, int); 194 int (*sc_newstate)(struct ieee80211com *, 195 enum ieee80211_state, int); 196 void (*sc_recv_mgmt)(struct ieee80211com *, 197 struct mbuf *, struct ieee80211_node *, 198 int, int, u_int32_t); 199 struct ieee80211_node *(*sc_node_alloc)(struct ieee80211_node_table*); 200 void (*sc_node_free)(struct ieee80211_node *); 201 202 struct atw_stats sc_stats; /* debugging stats */ 203 204 int sc_tx_timer; 205 int sc_rescan_timer; 206 207 bus_space_tag_t sc_st; /* bus space tag */ 208 bus_space_handle_t sc_sh; /* bus space handle */ 209 bus_dma_tag_t sc_dmat; /* bus dma tag */ 210 void *sc_sdhook; /* shutdown hook */ 211 void *sc_powerhook; /* power management hook */ 212 u_int32_t sc_cacheline; /* cache line size */ 213 u_int32_t sc_maxburst; /* maximum burst length */ 214 215 const struct atw_txthresh_tab *sc_txth; 216 int sc_txthresh; /* current tx threshold */ 217 218 u_int sc_cur_chan; /* current channel */ 219 220 int sc_flags; 221 222 u_int16_t *sc_srom; 223 u_int16_t sc_sromsz; 224 225 void * sc_radiobpf; 226 227 bus_dma_segment_t sc_cdseg; /* control data memory */ 228 int sc_cdnseg; /* number of segments */ 229 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 230 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 231 232 /* 233 * Software state for transmit and receive descriptors. 234 */ 235 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN]; 236 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC]; 237 238 /* 239 * Control data structures. 240 */ 241 struct atw_control_data *sc_control_data; 242 #define sc_txdescs sc_control_data->acd_txdescs 243 #define sc_rxdescs sc_control_data->acd_rxdescs 244 #define sc_setup_desc sc_control_data->acd_setup_desc 245 246 int sc_txfree; /* number of free Tx descriptors */ 247 int sc_txnext; /* next ready Tx descriptor */ 248 int sc_ntxsegs; /* number of transmit segs per pkt */ 249 250 struct atw_txsq sc_txfreeq; /* free Tx descsofts */ 251 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */ 252 253 int sc_rxptr; /* next ready RX descriptor/descsoft */ 254 255 u_int32_t sc_busmode; /* copy of ATW_PAR */ 256 u_int32_t sc_opmode; /* copy of ATW_NAR */ 257 u_int32_t sc_inten; /* copy of ATW_IER */ 258 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */ 259 260 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 261 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 262 u_int32_t sc_linkint_mask;/* link-state interrupts mask */ 263 264 /* interrupt acknowledge hook */ 265 void (*sc_intr_ack)(struct atw_softc *); 266 267 enum atw_rftype sc_rftype; 268 enum atw_bbptype sc_bbptype; 269 u_int32_t sc_synctl_rd; 270 u_int32_t sc_synctl_wr; 271 u_int32_t sc_bbpctl_rd; 272 u_int32_t sc_bbpctl_wr; 273 274 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *, 275 int, u_int32_t); 276 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *, 277 int, u_int32_t); 278 279 /* ADM8211 state variables. */ 280 u_int8_t sc_sram[ATW_SRAM_MAXSIZE]; 281 u_int sc_sramlen; 282 u_int8_t sc_bssid[IEEE80211_ADDR_LEN]; 283 uint8_t sc_rev; 284 uint8_t sc_rf3000_options1; 285 uint8_t sc_rf3000_options2; 286 287 struct evcnt sc_recv_ev; 288 struct evcnt sc_crc16e_ev; 289 struct evcnt sc_crc32e_ev; 290 struct evcnt sc_icve_ev; 291 struct evcnt sc_sfde_ev; 292 struct evcnt sc_sige_ev; 293 294 struct callout sc_scan_ch; 295 union { 296 struct atw_rx_radiotap_header tap; 297 u_int8_t pad[64]; 298 } sc_rxtapu; 299 union { 300 struct atw_tx_radiotap_header tap; 301 u_int8_t pad[64]; 302 } sc_txtapu; 303 }; 304 305 #define sc_if sc_ec.ec_if 306 #define sc_rxtap sc_rxtapu.tap 307 #define sc_txtap sc_txtapu.tap 308 309 /* XXX this is fragile. try not to introduce any u_int32_t's. */ 310 struct atw_frame { 311 /*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN]; 312 /*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */ 313 /*07*/ u_int8_t atw_service; /* 0 */ 314 /*08*/ u_int16_t atw_paylen; /* payload length */ 315 /*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame 316 * Control 317 */ 318 /* 802.11 PLCP Length for first & last fragment */ 319 /*0c*/ u_int16_t atw_tail_plcplen; 320 /*0e*/ u_int16_t atw_head_plcplen; 321 /* 802.11 Duration for first & last fragment */ 322 /*10*/ u_int16_t atw_tail_dur; 323 /*12*/ u_int16_t atw_head_dur; 324 /*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN]; 325 union { 326 struct { 327 /*1a*/ u_int16_t hdrctl; /*transmission control*/ 328 /*1c*/ u_int16_t fragthr;/* fragmentation threshold 329 * [0:11], zero [12:15]. 330 */ 331 /*1e*/ u_int8_t fragnum;/* fragment number [4:7], 332 * zero [0:3]. 333 */ 334 /*1f*/ u_int8_t rtylmt; /* retry limit */ 335 /*20*/ u_int8_t wepkey0[4];/* ??? */ 336 /*24*/ u_int8_t wepkey1[4];/* ??? */ 337 /*28*/ u_int8_t wepkey2[4];/* ??? */ 338 /*2c*/ u_int8_t wepkey3[4];/* ??? */ 339 /*30*/ u_int8_t keyid; 340 /*31*/ u_int8_t reserved0[7]; 341 } s1; 342 struct { 343 u_int8_t pad[6]; 344 struct ieee80211_frame ihdr; 345 } s2; 346 } u; 347 } __attribute__((__packed__)); 348 349 #define atw_hdrctl u.s1.hdrctl 350 #define atw_fragthr u.s1.fragthr 351 #define atw_fragnum u.s1.fragnum 352 #define atw_rtylmt u.s1.rtylmt 353 #define atw_keyid u.s1.keyid 354 #define atw_ihdr u.s2.ihdr 355 356 #define ATW_HDRCTL_SHORT_PREAMBLE __BIT(0) /* use short preamble */ 357 #define ATW_HDRCTL_RTSCTS __BIT(4) /* send RTS */ 358 #define ATW_HDRCTL_WEP __BIT(5) 359 #define ATW_HDRCTL_UNKNOWN1 __BIT(15) /* MAC adds FCS? */ 360 #define ATW_HDRCTL_UNKNOWN2 __BIT(8) 361 362 #define ATW_FRAGTHR_FRAGTHR_MASK __BITS(0, 11) 363 #define ATW_FRAGNUM_FRAGNUM_MASK __BITS(4, 7) 364 365 /* Values for sc_flags. */ 366 #define ATWF_MRL 0x00000001 /* memory read line okay */ 367 #define ATWF_MRM 0x00000002 /* memory read multi okay */ 368 #define ATWF_MWI 0x00000004 /* memory write inval okay */ 369 #define ATWF_SHORT_PREAMBLE 0x00000008 /* short preamble enabled */ 370 #define ATWF_RTSCTS 0x00000010 /* RTS/CTS enabled */ 371 #define ATWF_ATTACHED 0x00000020 /* attach has succeeded */ 372 #define ATWF_ENABLED 0x00000040 /* chip is enabled */ 373 #define ATWF_WEP_SRAM_VALID 0x00000080 /* SRAM matches s/w state */ 374 375 #define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED) 376 377 #define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x))) 378 #define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x))) 379 380 #define ATW_CDTXSYNC(sc, x, n, ops) \ 381 do { \ 382 int __x, __n; \ 383 \ 384 __x = (x); \ 385 __n = (n); \ 386 \ 387 /* If it will wrap around, sync to the end of the ring. */ \ 388 if ((__x + __n) > ATW_NTXDESC) { \ 389 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 390 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \ 391 (ATW_NTXDESC - __x), (ops)); \ 392 __n -= (ATW_NTXDESC - __x); \ 393 __x = 0; \ 394 } \ 395 \ 396 /* Now sync whatever is left. */ \ 397 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 398 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \ 399 } while (0) 400 401 #define ATW_CDRXSYNC(sc, x, ops) \ 402 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 403 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops)) 404 405 /* 406 * Note we rely on MCLBYTES being a power of two. Because the `length' 407 * field is only 11 bits, we must subtract 1 from the length to avoid 408 * having it truncated to 0! 409 */ 410 static inline void 411 atw_init_rxdesc(struct atw_softc *sc, int x) 412 { 413 struct atw_rxsoft *rxs = &sc->sc_rxsoft[x]; 414 struct atw_rxdesc *rxd = &sc->sc_rxdescs[x]; 415 struct mbuf *m = rxs->rxs_mbuf; 416 417 rxd->ar_buf1 = 418 htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 419 rxd->ar_buf2 = /* for descriptor chaining */ 420 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX(x))); 421 rxd->ar_ctlrssi = 422 htole32(__SHIFTIN(((m->m_ext.ext_size - 1) & ~0x3U), 423 ATW_RXCTL_RBS1_MASK) | 424 0 /* ATW_RXCTL_RCH */ | 425 (x == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); 426 rxd->ar_stat = htole32(ATW_RXSTAT_OWN); 427 428 ATW_CDRXSYNC((sc), x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 429 } 430 431 /* country codes from ADM8211 SROM */ 432 #define ATW_COUNTRY_FCC 0 /* USA 1-11 */ 433 #define ATW_COUNTRY_IC 1 /* Canada 1-11 */ 434 #define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */ 435 #define ATW_COUNTRY_SPAIN 3 /* 10-11 */ 436 #define ATW_COUNTRY_FRANCE 4 /* 10-13 */ 437 #define ATW_COUNTRY_MKK 5 /* Japan: 14 */ 438 #define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */ 439 440 /* 441 * register space access macros 442 */ 443 #define ATW_READ(sc, reg) \ 444 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 445 446 #define ATW_WRITE(sc, reg, val) \ 447 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 448 449 #define ATW_SET(sc, reg, mask) \ 450 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask)) 451 452 #define ATW_CLR(sc, reg, mask) \ 453 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask)) 454 455 #define ATW_ISSET(sc, reg, mask) \ 456 (ATW_READ((sc), (reg)) & (mask)) 457 458 void atw_attach(struct atw_softc *); 459 int atw_detach(struct atw_softc *); 460 int atw_activate(struct device *, enum devact); 461 int atw_intr(void *arg); 462 void atw_power(int, void *); 463 void atw_shutdown(void *); 464 465 #endif /* _DEV_IC_ATWVAR_H_ */ 466