1 /* $NetBSD: athn.c,v 1.15 2017/02/02 10:05:35 nonaka Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.15 2017/02/02 10:05:35 nonaka Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 Static void athn_set_multi(struct athn_softc *); 140 #endif /* notyet */ 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } 253 else { 254 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 255 athn_get_rf_name(sc)); 256 aprint_verbose_dev(sc->sc_dev, 257 "rev %d (%dT%dR), ROM rev %d, address %s\n", 258 sc->sc_mac_rev, 259 sc->sc_ntxchains, sc->sc_nrxchains, 260 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 261 } 262 263 callout_init(&sc->sc_scan_to, 0); 264 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 265 callout_init(&sc->sc_calib_to, 0); 266 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 267 268 sc->sc_amrr.amrr_min_success_threshold = 1; 269 sc->sc_amrr.amrr_max_success_threshold = 15; 270 271 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 272 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 273 ic->ic_state = IEEE80211_S_INIT; 274 275 /* Set device capabilities. */ 276 ic->ic_caps = 277 IEEE80211_C_WPA | /* 802.11i */ 278 #ifndef IEEE80211_STA_ONLY 279 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 280 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 281 #endif 282 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 283 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 284 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 285 IEEE80211_C_PMGT; /* Power saving supported. */ 286 287 #ifndef IEEE80211_NO_HT 288 if (sc->sc_flags & ATHN_FLAG_11N) { 289 int i, ntxstreams, nrxstreams; 290 291 /* Set HT capabilities. */ 292 ic->ic_htcaps = 293 IEEE80211_HTCAP_SMPS_DIS | 294 IEEE80211_HTCAP_CBW20_40 | 295 IEEE80211_HTCAP_SGI40 | 296 IEEE80211_HTCAP_DSSSCCK40; 297 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 298 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 299 if (AR_SREV_9380_10_OR_LATER(sc)) 300 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 301 if (AR_SREV_9280_10_OR_LATER(sc)) { 302 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 303 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 304 } 305 ntxstreams = sc->sc_ntxchains; 306 nrxstreams = sc->sc_nrxchains; 307 if (!AR_SREV_9380_10_OR_LATER(sc)) { 308 ntxstreams = MIN(ntxstreams, 2); 309 nrxstreams = MIN(nrxstreams, 2); 310 } 311 /* Set supported HT rates. */ 312 for (i = 0; i < nrxstreams; i++) 313 ic->ic_sup_mcs[i] = 0xff; 314 /* Set the "Tx MCS Set Defined" bit. */ 315 ic->ic_sup_mcs[12] |= 0x01; 316 if (ntxstreams != nrxstreams) { 317 /* Set "Tx Rx MCS Set Not Equal" bit. */ 318 ic->ic_sup_mcs[12] |= 0x02; 319 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 320 } 321 } 322 #endif 323 324 /* Set supported rates. */ 325 if (sc->sc_flags & ATHN_FLAG_11G) { 326 ic->ic_sup_rates[IEEE80211_MODE_11B] = 327 ieee80211_std_rateset_11b; 328 ic->ic_sup_rates[IEEE80211_MODE_11G] = 329 ieee80211_std_rateset_11g; 330 } 331 if (sc->sc_flags & ATHN_FLAG_11A) { 332 ic->ic_sup_rates[IEEE80211_MODE_11A] = 333 ieee80211_std_rateset_11a; 334 } 335 336 /* Get the list of authorized/supported channels. */ 337 athn_get_chanlist(sc); 338 339 ifp->if_softc = sc; 340 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 341 if (!ifp->if_init) 342 ifp->if_init = athn_init; 343 if (!ifp->if_ioctl) 344 ifp->if_ioctl = athn_ioctl; 345 if (!ifp->if_start) 346 ifp->if_start = athn_start; 347 if (!ifp->if_watchdog) 348 ifp->if_watchdog = athn_watchdog; 349 IFQ_SET_READY(&ifp->if_snd); 350 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 351 352 if_initialize(ifp); 353 ieee80211_ifattach(ic); 354 /* Use common softint-based if_input */ 355 ifp->if_percpuq = if_percpuq_create(ifp); 356 if_register(ifp); 357 358 ic->ic_node_alloc = athn_node_alloc; 359 ic->ic_newassoc = athn_newassoc; 360 if (ic->ic_updateslot == NULL) 361 ic->ic_updateslot = athn_updateslot; 362 #ifdef notyet_edca 363 ic->ic_updateedca = athn_updateedca; 364 #endif 365 #ifdef notyet 366 ic->ic_set_key = athn_set_key; 367 ic->ic_delete_key = athn_delete_key; 368 #endif 369 370 /* Override 802.11 state transition machine. */ 371 sc->sc_newstate = ic->ic_newstate; 372 ic->ic_newstate = athn_newstate; 373 374 if (sc->sc_media_change == NULL) 375 sc->sc_media_change = athn_media_change; 376 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 377 378 athn_radiotap_attach(sc); 379 return 0; 380 } 381 382 PUBLIC void 383 athn_detach(struct athn_softc *sc) 384 { 385 struct ifnet *ifp = &sc->sc_if; 386 int qid; 387 388 callout_halt(&sc->sc_scan_to, NULL); 389 callout_halt(&sc->sc_calib_to, NULL); 390 391 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 392 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 393 athn_tx_reclaim(sc, qid); 394 395 /* Free Tx/Rx DMA resources. */ 396 sc->sc_ops.dma_free(sc); 397 398 if (sc->sc_soft_ih != NULL) { 399 softint_disestablish(sc->sc_soft_ih); 400 sc->sc_soft_ih = NULL; 401 } 402 } 403 /* Free ROM copy. */ 404 if (sc->sc_eep != NULL) { 405 free(sc->sc_eep, M_DEVBUF); 406 sc->sc_eep = NULL; 407 } 408 409 bpf_detach(ifp); 410 ieee80211_ifdetach(&sc->sc_ic); 411 if_detach(ifp); 412 413 callout_destroy(&sc->sc_scan_to); 414 callout_destroy(&sc->sc_calib_to); 415 } 416 417 /* 418 * Attach the interface to 802.11 radiotap. 419 */ 420 Static void 421 athn_radiotap_attach(struct athn_softc *sc) 422 { 423 424 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 425 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 426 &sc->sc_drvbpf); 427 428 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 429 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 430 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 431 432 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 433 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 434 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 435 } 436 437 Static void 438 athn_get_chanlist(struct athn_softc *sc) 439 { 440 struct ieee80211com *ic = &sc->sc_ic; 441 uint8_t chan; 442 size_t i; 443 444 if (sc->sc_flags & ATHN_FLAG_11G) { 445 for (i = 1; i <= 14; i++) { 446 chan = i; 447 ic->ic_channels[chan].ic_freq = 448 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 449 ic->ic_channels[chan].ic_flags = 450 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 451 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 452 } 453 } 454 if (sc->sc_flags & ATHN_FLAG_11A) { 455 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 456 chan = athn_5ghz_chans[i]; 457 ic->ic_channels[chan].ic_freq = 458 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 459 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 460 } 461 } 462 } 463 464 PUBLIC void 465 athn_rx_start(struct athn_softc *sc) 466 { 467 struct ieee80211com *ic = &sc->sc_ic; 468 uint32_t rfilt; 469 470 /* Setup Rx DMA descriptors. */ 471 sc->sc_ops.rx_enable(sc); 472 473 /* Set Rx filter. */ 474 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 475 #ifndef IEEE80211_NO_HT 476 /* Want Compressed Block Ack Requests. */ 477 rfilt |= AR_RX_FILTER_COMPR_BAR; 478 #endif 479 rfilt |= AR_RX_FILTER_BEACON; 480 if (ic->ic_opmode != IEEE80211_M_STA) { 481 rfilt |= AR_RX_FILTER_PROBEREQ; 482 if (ic->ic_opmode == IEEE80211_M_MONITOR) 483 rfilt |= AR_RX_FILTER_PROM; 484 #ifndef IEEE80211_STA_ONLY 485 if (AR_SREV_9280_10_OR_LATER(sc) && 486 ic->ic_opmode == IEEE80211_M_HOSTAP) 487 rfilt |= AR_RX_FILTER_PSPOLL; 488 #endif 489 } 490 athn_set_rxfilter(sc, rfilt); 491 492 /* Set BSSID mask. */ 493 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 494 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 495 496 athn_set_opmode(sc); 497 498 /* Set multicast filter. */ 499 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 500 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 501 502 AR_WRITE(sc, AR_FILT_OFDM, 0); 503 AR_WRITE(sc, AR_FILT_CCK, 0); 504 AR_WRITE(sc, AR_MIBC, 0); 505 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 506 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 507 508 /* XXX ANI. */ 509 AR_WRITE(sc, AR_PHY_ERR_1, 0); 510 AR_WRITE(sc, AR_PHY_ERR_2, 0); 511 512 /* Disable HW crypto for now. */ 513 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 514 515 /* Start PCU Rx. */ 516 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 517 AR_WRITE_BARRIER(sc); 518 } 519 520 PUBLIC void 521 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 522 { 523 524 AR_WRITE(sc, AR_RX_FILTER, rfilt); 525 #ifdef notyet 526 reg = AR_READ(sc, AR_PHY_ERR); 527 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 528 AR_PHY_ERR_CCK_TIMING); 529 AR_WRITE(sc, AR_PHY_ERR, reg); 530 if (reg != 0) 531 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 532 else 533 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 534 #else 535 AR_WRITE(sc, AR_PHY_ERR, 0); 536 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 537 #endif 538 AR_WRITE_BARRIER(sc); 539 } 540 541 PUBLIC int 542 athn_intr(void *xsc) 543 { 544 struct athn_softc *sc = xsc; 545 struct ifnet *ifp = &sc->sc_if; 546 547 if (!IS_UP_AND_RUNNING(ifp)) 548 return 0; 549 550 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 551 /* 552 * The hardware is not ready/present, don't touch anything. 553 * Note this can happen early on if the IRQ is shared. 554 */ 555 return 0; 556 557 if (!sc->sc_ops.intr_status(sc)) 558 return 0; 559 560 softint_schedule(sc->sc_soft_ih); 561 return 1; 562 } 563 564 Static void 565 athn_softintr(void *xsc) 566 { 567 struct athn_softc *sc = xsc; 568 struct ifnet *ifp = &sc->sc_if; 569 570 if (!IS_UP_AND_RUNNING(ifp)) 571 return; 572 573 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 574 /* 575 * The hardware is not ready/present, don't touch anything. 576 * Note this can happen early on if the IRQ is shared. 577 */ 578 return; 579 580 sc->sc_ops.intr(sc); 581 } 582 583 Static void 584 athn_get_chipid(struct athn_softc *sc) 585 { 586 uint32_t reg; 587 588 reg = AR_READ(sc, AR_SREV); 589 if (MS(reg, AR_SREV_ID) == 0xff) { 590 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 591 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 592 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 593 sc->sc_flags |= ATHN_FLAG_PCIE; 594 } 595 else { 596 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 597 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 598 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 599 sc->sc_flags |= ATHN_FLAG_PCIE; 600 } 601 } 602 603 Static const char * 604 athn_get_mac_name(struct athn_softc *sc) 605 { 606 607 switch (sc->sc_mac_ver) { 608 case AR_SREV_VERSION_5416_PCI: 609 return "AR5416"; 610 case AR_SREV_VERSION_5416_PCIE: 611 return "AR5418"; 612 case AR_SREV_VERSION_9160: 613 return "AR9160"; 614 case AR_SREV_VERSION_9280: 615 return "AR9280"; 616 case AR_SREV_VERSION_9285: 617 return "AR9285"; 618 case AR_SREV_VERSION_9271: 619 return "AR9271"; 620 case AR_SREV_VERSION_9287: 621 return "AR9287"; 622 case AR_SREV_VERSION_9380: 623 return "AR9380"; 624 case AR_SREV_VERSION_9485: 625 return "AR9485"; 626 default: 627 return "unknown"; 628 } 629 } 630 631 /* 632 * Return RF chip name (not for single-chip solutions). 633 */ 634 Static const char * 635 athn_get_rf_name(struct athn_softc *sc) 636 { 637 638 KASSERT(!AR_SINGLE_CHIP(sc)); 639 640 switch (sc->sc_rf_rev) { 641 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 642 return "AR5133"; 643 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 644 return "AR2133"; 645 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 646 return "AR5122"; 647 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 648 return "AR2122"; 649 default: 650 return "unknown"; 651 } 652 } 653 654 PUBLIC int 655 athn_reset_power_on(struct athn_softc *sc) 656 { 657 int ntries; 658 659 /* Set force wake. */ 660 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 661 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 662 663 if (!AR_SREV_9380_10_OR_LATER(sc)) { 664 /* Make sure no DMA is active by doing an AHB reset. */ 665 AR_WRITE(sc, AR_RC, AR_RC_AHB); 666 } 667 /* RTC reset and clear. */ 668 AR_WRITE(sc, AR_RTC_RESET, 0); 669 AR_WRITE_BARRIER(sc); 670 DELAY(2); 671 if (!AR_SREV_9380_10_OR_LATER(sc)) 672 AR_WRITE(sc, AR_RC, 0); 673 AR_WRITE(sc, AR_RTC_RESET, 1); 674 675 /* Poll until RTC is ON. */ 676 for (ntries = 0; ntries < 1000; ntries++) { 677 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 678 AR_RTC_STATUS_ON) 679 break; 680 DELAY(10); 681 } 682 if (ntries == 1000) { 683 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 684 return ETIMEDOUT; 685 } 686 return athn_reset(sc, 0); 687 } 688 689 PUBLIC int 690 athn_reset(struct athn_softc *sc, int cold_reset) 691 { 692 int ntries; 693 694 /* Set force wake. */ 695 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 696 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 697 698 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 699 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 700 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 701 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 702 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 703 } 704 else if (!AR_SREV_9380_10_OR_LATER(sc)) 705 AR_WRITE(sc, AR_RC, AR_RC_AHB); 706 707 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 708 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 709 AR_WRITE_BARRIER(sc); 710 DELAY(50); 711 AR_WRITE(sc, AR_RTC_RC, 0); 712 for (ntries = 0; ntries < 1000; ntries++) { 713 if (!(AR_READ(sc, AR_RTC_RC) & 714 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 715 break; 716 DELAY(10); 717 } 718 if (ntries == 1000) { 719 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 720 return ETIMEDOUT; 721 } 722 AR_WRITE(sc, AR_RC, 0); 723 AR_WRITE_BARRIER(sc); 724 return 0; 725 } 726 727 PUBLIC int 728 athn_set_power_awake(struct athn_softc *sc) 729 { 730 int ntries, error; 731 732 /* Do a Power-On-Reset if shutdown. */ 733 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 734 AR_RTC_STATUS_SHUTDOWN) { 735 if ((error = athn_reset_power_on(sc)) != 0) 736 return error; 737 if (!AR_SREV_9380_10_OR_LATER(sc)) 738 athn_init_pll(sc, NULL); 739 } 740 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 741 AR_WRITE_BARRIER(sc); 742 DELAY(50); /* Give chip the chance to awake. */ 743 744 /* Poll until RTC is ON. */ 745 for (ntries = 0; ntries < 4000; ntries++) { 746 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 747 AR_RTC_STATUS_ON) 748 break; 749 DELAY(50); 750 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 751 } 752 if (ntries == 4000) { 753 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 754 return ETIMEDOUT; 755 } 756 757 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 758 AR_WRITE_BARRIER(sc); 759 return 0; 760 } 761 762 PUBLIC void 763 athn_set_power_sleep(struct athn_softc *sc) 764 { 765 766 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 767 /* Allow the MAC to go to sleep. */ 768 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 769 if (!AR_SREV_9380_10_OR_LATER(sc)) 770 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 771 /* 772 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 773 * results in high power consumption on AR5416 chipsets. 774 */ 775 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 776 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 777 AR_WRITE_BARRIER(sc); 778 } 779 780 PUBLIC void 781 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 782 { 783 uint32_t pll; 784 785 if (AR_SREV_9380_10_OR_LATER(sc)) { 786 if (AR_SREV_9485(sc)) 787 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 788 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 789 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 790 } 791 else if (AR_SREV_9280_10_OR_LATER(sc)) { 792 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 793 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 794 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 795 pll = 0x142c; 796 else if (AR_SREV_9280_20(sc)) 797 pll = 0x2850; 798 else 799 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 800 } 801 else 802 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 803 } 804 else if (AR_SREV_9160_10_OR_LATER(sc)) { 805 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 806 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 807 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 808 else 809 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 810 } 811 else { 812 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 813 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 814 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 815 else 816 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 817 } 818 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 819 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 820 if (AR_SREV_9271(sc)) { 821 /* Switch core clock to 117MHz. */ 822 AR_WRITE_BARRIER(sc); 823 DELAY(500); 824 AR_WRITE(sc, 0x50050, 0x304); 825 } 826 AR_WRITE_BARRIER(sc); 827 DELAY(100); 828 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 829 AR_WRITE_BARRIER(sc); 830 } 831 832 Static void 833 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 834 { 835 int i; 836 837 /* Write sequence to Serializer/Deserializer. */ 838 for (i = 0; i < serdes->nvals; i++) 839 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 840 AR_WRITE_BARRIER(sc); 841 } 842 843 PUBLIC void 844 athn_config_pcie(struct athn_softc *sc) 845 { 846 847 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 848 athn_write_serdes(sc, sc->sc_serdes); 849 850 DELAY(1000); 851 /* Allow forcing of PCIe core into L1 state. */ 852 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 853 854 #ifndef ATHN_PCIE_WAEN 855 AR_WRITE(sc, AR_WA, sc->sc_workaround); 856 #else 857 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 858 #endif 859 AR_WRITE_BARRIER(sc); 860 } 861 862 /* 863 * Serializer/Deserializer programming for non-PCIe devices. 864 */ 865 static const uint32_t ar_nonpcie_serdes_regs[] = { 866 AR_PCIE_SERDES, 867 AR_PCIE_SERDES, 868 AR_PCIE_SERDES, 869 AR_PCIE_SERDES, 870 AR_PCIE_SERDES, 871 AR_PCIE_SERDES, 872 AR_PCIE_SERDES, 873 AR_PCIE_SERDES, 874 AR_PCIE_SERDES, 875 AR_PCIE_SERDES2, 876 }; 877 878 static const uint32_t ar_nonpcie_serdes_vals[] = { 879 0x9248fc00, 880 0x24924924, 881 0x28000029, 882 0x57160824, 883 0x25980579, 884 0x00000000, 885 0x1aaabe40, 886 0xbe105554, 887 0x000e1007, 888 0x00000000 889 }; 890 891 static const struct athn_serdes ar_nonpcie_serdes = { 892 __arraycount(ar_nonpcie_serdes_vals), 893 ar_nonpcie_serdes_regs, 894 ar_nonpcie_serdes_vals 895 }; 896 897 PUBLIC void 898 athn_config_nonpcie(struct athn_softc *sc) 899 { 900 901 athn_write_serdes(sc, &ar_nonpcie_serdes); 902 } 903 904 PUBLIC int 905 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 906 struct ieee80211_channel *extchan) 907 { 908 struct athn_ops *ops = &sc->sc_ops; 909 int error, qid; 910 911 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 912 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 913 if (athn_tx_pending(sc, qid)) 914 return EBUSY; 915 916 /* Request RF Bus grant. */ 917 if ((error = ops->rf_bus_request(sc)) != 0) 918 return error; 919 920 ops->set_phy(sc, curchan, extchan); 921 922 /* Change the synthesizer. */ 923 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 924 return error; 925 926 sc->sc_curchan = curchan; 927 sc->sc_curchanext = extchan; 928 929 /* Set transmit power values for new channel. */ 930 ops->set_txpower(sc, curchan, extchan); 931 932 /* Release the RF Bus grant. */ 933 ops->rf_bus_release(sc); 934 935 /* Write delta slope coeffs for modes where OFDM may be used. */ 936 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 937 ops->set_delta_slope(sc, curchan, extchan); 938 939 ops->spur_mitigate(sc, curchan, extchan); 940 /* XXX Load noisefloor values and start calibration. */ 941 942 return 0; 943 } 944 945 Static int 946 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 947 struct ieee80211_channel *extchan) 948 { 949 int error, qid; 950 951 /* Disable interrupts. */ 952 athn_disable_interrupts(sc); 953 954 /* Stop all Tx queues. */ 955 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 956 athn_stop_tx_dma(sc, qid); 957 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 958 athn_tx_reclaim(sc, qid); 959 960 /* Stop Rx. */ 961 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 962 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 963 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 964 AR_WRITE(sc, AR_FILT_OFDM, 0); 965 AR_WRITE(sc, AR_FILT_CCK, 0); 966 athn_set_rxfilter(sc, 0); 967 error = athn_stop_rx_dma(sc); 968 if (error != 0) 969 goto reset; 970 971 #ifdef notyet 972 /* AR9280 needs a full reset. */ 973 if (AR_SREV_9280(sc)) 974 #endif 975 goto reset; 976 977 /* If band or bandwidth changes, we need to do a full reset. */ 978 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 979 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 980 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 981 goto reset; 982 } 983 error = athn_set_power_awake(sc); 984 if (error != 0) 985 goto reset; 986 987 error = athn_set_chan(sc, curchan, extchan); 988 if (error != 0) { 989 reset: /* Error found, try a full reset. */ 990 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 991 error = athn_hw_reset(sc, curchan, extchan, 0); 992 if (error != 0) /* Hopeless case. */ 993 return error; 994 } 995 athn_rx_start(sc); 996 997 /* Re-enable interrupts. */ 998 athn_enable_interrupts(sc); 999 return 0; 1000 } 1001 1002 PUBLIC void 1003 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1004 { 1005 #define COEFF_SCALE_SHIFT 24 1006 uint32_t exp, man; 1007 1008 /* exponent = 14 - floor(log2(coeff)) */ 1009 for (exp = 31; exp > 0; exp--) 1010 if (coeff & (1 << exp)) 1011 break; 1012 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1013 1014 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1015 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1016 1017 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1018 *exponent = exp - 16; 1019 #undef COEFF_SCALE_SHIFT 1020 } 1021 1022 PUBLIC void 1023 athn_reset_key(struct athn_softc *sc, int entry) 1024 { 1025 1026 /* 1027 * NB: Key cache registers access special memory area that requires 1028 * two 32-bit writes to actually update the values in the internal 1029 * memory. Consequently, writes must be grouped by pair. 1030 */ 1031 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1032 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1033 1034 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1035 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1036 1037 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1038 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1039 1040 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1041 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1042 1043 AR_WRITE_BARRIER(sc); 1044 } 1045 1046 #ifdef notyet 1047 Static int 1048 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1049 struct ieee80211_key *k) 1050 { 1051 struct athn_softc *sc = ic->ic_ifp->if_softc; 1052 const uint8_t *txmic, *rxmic, *key, *addr; 1053 uintptr_t entry, micentry; 1054 uint32_t type, lo, hi; 1055 1056 switch (k->k_cipher) { 1057 case IEEE80211_CIPHER_WEP40: 1058 type = AR_KEYTABLE_TYPE_40; 1059 break; 1060 case IEEE80211_CIPHER_WEP104: 1061 type = AR_KEYTABLE_TYPE_104; 1062 break; 1063 case IEEE80211_CIPHER_TKIP: 1064 type = AR_KEYTABLE_TYPE_TKIP; 1065 break; 1066 case IEEE80211_CIPHER_CCMP: 1067 type = AR_KEYTABLE_TYPE_CCM; 1068 break; 1069 default: 1070 /* Fallback to software crypto for other ciphers. */ 1071 return ieee80211_set_key(ic, ni, k); 1072 } 1073 1074 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1075 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1076 else 1077 entry = k->k_id; 1078 k->k_priv = (void *)entry; 1079 1080 /* NB: See note about key cache registers access above. */ 1081 key = k->k_key; 1082 if (type == AR_KEYTABLE_TYPE_TKIP) { 1083 #ifndef IEEE80211_STA_ONLY 1084 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1085 txmic = &key[16]; 1086 rxmic = &key[24]; 1087 } 1088 else 1089 #endif 1090 { 1091 rxmic = &key[16]; 1092 txmic = &key[24]; 1093 } 1094 /* Tx+Rx MIC key is at entry + 64. */ 1095 micentry = entry + 64; 1096 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1097 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1098 1099 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1100 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1101 1102 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1103 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1104 } 1105 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1106 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1107 1108 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1109 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1110 1111 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1112 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1113 1114 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1115 addr = ni->ni_macaddr; 1116 lo = LE_READ_4(&addr[0]); 1117 hi = LE_READ_2(&addr[4]); 1118 lo = lo >> 1 | hi << 31; 1119 hi = hi >> 1; 1120 } 1121 else 1122 lo = hi = 0; 1123 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1124 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1125 AR_WRITE_BARRIER(sc); 1126 return 0; 1127 } 1128 1129 Static void 1130 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1131 struct ieee80211_key *k) 1132 { 1133 struct athn_softc *sc = ic->ic_ifp->if_softc; 1134 uintptr_t entry; 1135 1136 switch (k->k_cipher) { 1137 case IEEE80211_CIPHER_WEP40: 1138 case IEEE80211_CIPHER_WEP104: 1139 case IEEE80211_CIPHER_CCMP: 1140 entry = (uintptr_t)k->k_priv; 1141 athn_reset_key(sc, entry); 1142 break; 1143 case IEEE80211_CIPHER_TKIP: 1144 entry = (uintptr_t)k->k_priv; 1145 athn_reset_key(sc, entry); 1146 athn_reset_key(sc, entry + 64); 1147 break; 1148 default: 1149 /* Fallback to software crypto for other ciphers. */ 1150 ieee80211_delete_key(ic, ni, k); 1151 } 1152 } 1153 #endif /* notyet */ 1154 1155 PUBLIC void 1156 athn_led_init(struct athn_softc *sc) 1157 { 1158 struct athn_ops *ops = &sc->sc_ops; 1159 1160 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1161 /* LED off, active low. */ 1162 athn_set_led(sc, 0); 1163 } 1164 1165 PUBLIC void 1166 athn_set_led(struct athn_softc *sc, int on) 1167 { 1168 struct athn_ops *ops = &sc->sc_ops; 1169 1170 sc->sc_led_state = on; 1171 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1172 } 1173 1174 #ifdef ATHN_BT_COEXISTENCE 1175 Static void 1176 athn_btcoex_init(struct athn_softc *sc) 1177 { 1178 struct athn_ops *ops = &sc->sc_ops; 1179 uint32_t reg; 1180 1181 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1182 /* Connect bt_active to baseband. */ 1183 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1184 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1185 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1186 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1187 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1188 1189 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1190 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1191 AR_GPIO_BTACTIVE_PIN); 1192 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1193 AR_WRITE_BARRIER(sc); 1194 1195 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1196 } 1197 else { /* 3-wire. */ 1198 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1199 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1200 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1201 1202 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1203 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1204 AR_GPIO_BTACTIVE_PIN); 1205 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1206 AR_GPIO_BTPRIORITY_PIN); 1207 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1208 AR_WRITE_BARRIER(sc); 1209 1210 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1211 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1212 } 1213 } 1214 1215 Static void 1216 athn_btcoex_enable(struct athn_softc *sc) 1217 { 1218 struct athn_ops *ops = &sc->sc_ops; 1219 uint32_t reg; 1220 1221 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1222 AR_WRITE(sc, AR_BT_COEX_MODE, 1223 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1224 SM(AR_BT_PRIORITY_TIME, 2) | 1225 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1226 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1227 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1228 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1229 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1230 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1231 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1232 AR_WRITE(sc, AR_BT_COEX_MODE2, 1233 SM(AR_BT_BCN_MISS_THRESH, 50) | 1234 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1235 1236 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1237 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1238 AR_WRITE_BARRIER(sc); 1239 1240 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1241 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1242 1243 } 1244 else { /* 2-wire. */ 1245 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1246 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1247 } 1248 reg = AR_READ(sc, AR_GPIO_PDPU); 1249 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1250 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1251 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1252 AR_WRITE_BARRIER(sc); 1253 1254 /* Disable PCIe Active State Power Management (ASPM). */ 1255 if (sc->sc_disable_aspm != NULL) 1256 sc->sc_disable_aspm(sc); 1257 1258 /* XXX Start periodic timer. */ 1259 } 1260 1261 Static void 1262 athn_btcoex_disable(struct athn_softc *sc) 1263 { 1264 struct athn_ops *ops = &sc->sc_ops; 1265 1266 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1267 1268 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1269 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1270 1271 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1272 AR_WRITE(sc, AR_BT_COEX_MODE, 1273 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1274 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1275 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1276 /* XXX Stop periodic timer. */ 1277 } 1278 AR_WRITE_BARRIER(sc); 1279 /* XXX Restore ASPM setting? */ 1280 } 1281 #endif 1282 1283 Static void 1284 athn_iter_func(void *arg, struct ieee80211_node *ni) 1285 { 1286 struct athn_softc *sc = arg; 1287 struct athn_node *an = (struct athn_node *)ni; 1288 1289 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1290 } 1291 1292 Static void 1293 athn_calib_to(void *arg) 1294 { 1295 extern int ticks; 1296 struct athn_softc *sc = arg; 1297 struct athn_ops *ops = &sc->sc_ops; 1298 struct ieee80211com *ic = &sc->sc_ic; 1299 int s; 1300 1301 s = splnet(); 1302 1303 /* Do periodic (every 4 minutes) PA calibration. */ 1304 if (AR_SREV_9285_11_OR_LATER(sc) && 1305 !AR_SREV_9380_10_OR_LATER(sc) && 1306 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1307 sc->sc_pa_calib_ticks = ticks; 1308 if (AR_SREV_9271(sc)) 1309 ar9271_pa_calib(sc); 1310 else 1311 ar9285_pa_calib(sc); 1312 } 1313 1314 /* Do periodic (every 30 seconds) temperature compensation. */ 1315 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1316 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1317 sc->sc_olpc_ticks = ticks; 1318 ops->olpc_temp_compensation(sc); 1319 } 1320 1321 #ifdef notyet 1322 /* XXX ANI. */ 1323 athn_ani_monitor(sc); 1324 1325 ops->next_calib(sc); 1326 #endif 1327 if (ic->ic_fixed_rate == -1) { 1328 if (ic->ic_opmode == IEEE80211_M_STA) 1329 athn_iter_func(sc, ic->ic_bss); 1330 else 1331 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1332 } 1333 callout_schedule(&sc->sc_calib_to, hz / 2); 1334 splx(s); 1335 } 1336 1337 Static int 1338 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1339 struct ieee80211_channel *extchan) 1340 { 1341 struct athn_ops *ops = &sc->sc_ops; 1342 int error; 1343 1344 if (AR_SREV_9380_10_OR_LATER(sc)) 1345 error = ar9003_init_calib(sc); 1346 else if (AR_SREV_9285_10_OR_LATER(sc)) 1347 error = ar9285_init_calib(sc, curchan, extchan); 1348 else 1349 error = ar5416_init_calib(sc, curchan, extchan); 1350 if (error != 0) 1351 return error; 1352 1353 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1354 /* Do PA calibration. */ 1355 if (AR_SREV_9285_11_OR_LATER(sc)) { 1356 extern int ticks; 1357 sc->sc_pa_calib_ticks = ticks; 1358 if (AR_SREV_9271(sc)) 1359 ar9271_pa_calib(sc); 1360 else 1361 ar9285_pa_calib(sc); 1362 } 1363 /* Do noisefloor calibration. */ 1364 ops->noisefloor_calib(sc); 1365 } 1366 if (AR_SREV_9160_10_OR_LATER(sc)) { 1367 /* Support IQ calibration. */ 1368 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1369 if (AR_SREV_9380_10_OR_LATER(sc)) { 1370 /* Support temperature compensation calibration. */ 1371 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1372 } 1373 else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1374 /* 1375 * ADC gain calibration causes uplink throughput 1376 * drops in HT40 mode on AR9287. 1377 */ 1378 if (!AR_SREV_9287(sc)) { 1379 /* Support ADC gain calibration. */ 1380 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1381 } 1382 /* Support ADC DC offset calibration. */ 1383 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1384 } 1385 } 1386 return 0; 1387 } 1388 1389 /* 1390 * Adaptive noise immunity. 1391 */ 1392 #ifdef notyet 1393 Static int32_t 1394 athn_ani_get_rssi(struct athn_softc *sc) 1395 { 1396 1397 return 0; /* XXX */ 1398 } 1399 #endif /* notyet */ 1400 1401 #ifdef notyet 1402 Static void 1403 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1404 { 1405 struct athn_ani *ani = &sc->sc_ani; 1406 struct athn_ops *ops = &sc->sc_ops; 1407 int32_t rssi; 1408 1409 /* First, raise noise immunity level, up to max. */ 1410 if (ani->noise_immunity_level < 4) { 1411 ani->noise_immunity_level++; 1412 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1413 return; 1414 } 1415 1416 /* Then, raise our spur immunity level, up to max. */ 1417 if (ani->spur_immunity_level < 7) { 1418 ani->spur_immunity_level++; 1419 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1420 return; 1421 } 1422 1423 #ifndef IEEE80211_STA_ONLY 1424 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1425 if (ani->firstep_level < 2) { 1426 ani->firstep_level++; 1427 ops->set_firstep_level(sc, ani->firstep_level); 1428 } 1429 return; 1430 } 1431 #endif 1432 rssi = athn_ani_get_rssi(sc); 1433 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1434 /* 1435 * Beacon RSSI is high, turn off OFDM weak signal detection 1436 * or raise first step level as last resort. 1437 */ 1438 if (ani->ofdm_weak_signal) { 1439 ani->ofdm_weak_signal = 0; 1440 ops->disable_ofdm_weak_signal(sc); 1441 ani->spur_immunity_level = 0; 1442 ops->set_spur_immunity_level(sc, 0); 1443 } 1444 else if (ani->firstep_level < 2) { 1445 ani->firstep_level++; 1446 ops->set_firstep_level(sc, ani->firstep_level); 1447 } 1448 } 1449 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1450 /* 1451 * Beacon RSSI is in mid range, we need OFDM weak signal 1452 * detection but we can raise first step level. 1453 */ 1454 if (!ani->ofdm_weak_signal) { 1455 ani->ofdm_weak_signal = 1; 1456 ops->enable_ofdm_weak_signal(sc); 1457 } 1458 if (ani->firstep_level < 2) { 1459 ani->firstep_level++; 1460 ops->set_firstep_level(sc, ani->firstep_level); 1461 } 1462 } 1463 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1464 /* 1465 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1466 * signal detection and zero first step level to maximize 1467 * CCK sensitivity. 1468 */ 1469 if (ani->ofdm_weak_signal) { 1470 ani->ofdm_weak_signal = 0; 1471 ops->disable_ofdm_weak_signal(sc); 1472 } 1473 if (ani->firstep_level > 0) { 1474 ani->firstep_level = 0; 1475 ops->set_firstep_level(sc, 0); 1476 } 1477 } 1478 } 1479 #endif /* notyet */ 1480 1481 #ifdef notyet 1482 Static void 1483 athn_ani_cck_err_trigger(struct athn_softc *sc) 1484 { 1485 struct athn_ani *ani = &sc->sc_ani; 1486 struct athn_ops *ops = &sc->sc_ops; 1487 int32_t rssi; 1488 1489 /* Raise noise immunity level, up to max. */ 1490 if (ani->noise_immunity_level < 4) { 1491 ani->noise_immunity_level++; 1492 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1493 return; 1494 } 1495 1496 #ifndef IEEE80211_STA_ONLY 1497 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1498 if (ani->firstep_level < 2) { 1499 ani->firstep_level++; 1500 ops->set_firstep_level(sc, ani->firstep_level); 1501 } 1502 return; 1503 } 1504 #endif 1505 rssi = athn_ani_get_rssi(sc); 1506 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1507 /* 1508 * Beacon RSSI is in mid or high range, raise first step 1509 * level. 1510 */ 1511 if (ani->firstep_level < 2) { 1512 ani->firstep_level++; 1513 ops->set_firstep_level(sc, ani->firstep_level); 1514 } 1515 } 1516 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1517 /* 1518 * Beacon RSSI is low, zero first step level to maximize 1519 * CCK sensitivity. 1520 */ 1521 if (ani->firstep_level > 0) { 1522 ani->firstep_level = 0; 1523 ops->set_firstep_level(sc, 0); 1524 } 1525 } 1526 } 1527 #endif /* notyet */ 1528 1529 #ifdef notyet 1530 Static void 1531 athn_ani_lower_immunity(struct athn_softc *sc) 1532 { 1533 struct athn_ani *ani = &sc->sc_ani; 1534 struct athn_ops *ops = &sc->sc_ops; 1535 int32_t rssi; 1536 1537 #ifndef IEEE80211_STA_ONLY 1538 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1539 if (ani->firstep_level > 0) { 1540 ani->firstep_level--; 1541 ops->set_firstep_level(sc, ani->firstep_level); 1542 } 1543 return; 1544 } 1545 #endif 1546 rssi = athn_ani_get_rssi(sc); 1547 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1548 /* 1549 * Beacon RSSI is high, leave OFDM weak signal detection 1550 * off or it may oscillate. 1551 */ 1552 } 1553 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1554 /* 1555 * Beacon RSSI is in mid range, turn on OFDM weak signal 1556 * detection or lower first step level. 1557 */ 1558 if (!ani->ofdm_weak_signal) { 1559 ani->ofdm_weak_signal = 1; 1560 ops->enable_ofdm_weak_signal(sc); 1561 return; 1562 } 1563 if (ani->firstep_level > 0) { 1564 ani->firstep_level--; 1565 ops->set_firstep_level(sc, ani->firstep_level); 1566 return; 1567 } 1568 } 1569 else { 1570 /* Beacon RSSI is low, lower first step level. */ 1571 if (ani->firstep_level > 0) { 1572 ani->firstep_level--; 1573 ops->set_firstep_level(sc, ani->firstep_level); 1574 return; 1575 } 1576 } 1577 /* 1578 * Lower spur immunity level down to zero, or if all else fails, 1579 * lower noise immunity level down to zero. 1580 */ 1581 if (ani->spur_immunity_level > 0) { 1582 ani->spur_immunity_level--; 1583 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1584 } 1585 else if (ani->noise_immunity_level > 0) { 1586 ani->noise_immunity_level--; 1587 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1588 } 1589 } 1590 #endif /* notyet */ 1591 1592 #ifdef notyet 1593 Static void 1594 athn_ani_restart(struct athn_softc *sc) 1595 { 1596 struct athn_ani *ani = &sc->sc_ani; 1597 1598 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1599 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1600 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1601 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1602 AR_WRITE_BARRIER(sc); 1603 1604 ani->listen_time = 0; 1605 ani->ofdm_phy_err_count = 0; 1606 ani->cck_phy_err_count = 0; 1607 } 1608 #endif /* notyet */ 1609 1610 #ifdef notyet 1611 Static void 1612 athn_ani_monitor(struct athn_softc *sc) 1613 { 1614 struct athn_ani *ani = &sc->sc_ani; 1615 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1616 int32_t cycdelta, txfdelta, rxfdelta; 1617 int32_t listen_time; 1618 1619 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1620 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1621 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1622 1623 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1624 cycdelta = cyccnt - ani->cyccnt; 1625 txfdelta = txfcnt - ani->txfcnt; 1626 rxfdelta = rxfcnt - ani->rxfcnt; 1627 1628 listen_time = (cycdelta - txfdelta - rxfdelta) / 1629 (athn_clock_rate(sc) * 1000); 1630 } 1631 else 1632 listen_time = 0; 1633 1634 ani->cyccnt = cyccnt; 1635 ani->txfcnt = txfcnt; 1636 ani->rxfcnt = rxfcnt; 1637 1638 if (listen_time < 0) { 1639 athn_ani_restart(sc); 1640 return; 1641 } 1642 ani->listen_time += listen_time; 1643 1644 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1645 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1646 1647 if (phy1 < ani->ofdm_phy_err_base) { 1648 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1649 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1650 } 1651 if (phy2 < ani->cck_phy_err_base) { 1652 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1653 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1654 } 1655 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1656 AR_WRITE_BARRIER(sc); 1657 return; 1658 } 1659 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1660 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1661 1662 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1663 /* Check to see if we need to lower immunity. */ 1664 if (ani->ofdm_phy_err_count <= 1665 ani->listen_time * ani->ofdm_trig_low / 1000 && 1666 ani->cck_phy_err_count <= 1667 ani->listen_time * ani->cck_trig_low / 1000) 1668 athn_ani_lower_immunity(sc); 1669 athn_ani_restart(sc); 1670 1671 } 1672 else if (ani->listen_time > ATHN_ANI_PERIOD) { 1673 /* Check to see if we need to raise immunity. */ 1674 if (ani->ofdm_phy_err_count > 1675 ani->listen_time * ani->ofdm_trig_high / 1000) { 1676 athn_ani_ofdm_err_trigger(sc); 1677 athn_ani_restart(sc); 1678 } 1679 else if (ani->cck_phy_err_count > 1680 ani->listen_time * ani->cck_trig_high / 1000) { 1681 athn_ani_cck_err_trigger(sc); 1682 athn_ani_restart(sc); 1683 } 1684 } 1685 } 1686 #endif /* notyet */ 1687 1688 PUBLIC uint8_t 1689 athn_chan2fbin(struct ieee80211_channel *c) 1690 { 1691 1692 if (IEEE80211_IS_CHAN_2GHZ(c)) 1693 return c->ic_freq - 2300; 1694 else 1695 return (c->ic_freq - 4800) / 5; 1696 } 1697 1698 PUBLIC int 1699 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1700 { 1701 1702 if (x1 == x2) /* Prevents division by zero. */ 1703 return y1; 1704 /* Linear interpolation. */ 1705 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1706 } 1707 1708 PUBLIC void 1709 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1710 int *lo, int *hi) 1711 { 1712 int i; 1713 1714 for (i = 0; i < npiers; i++) 1715 if (pierfreq[i] == AR_BCHAN_UNUSED || 1716 pierfreq[i] > fbin) 1717 break; 1718 *hi = i; 1719 *lo = *hi - 1; 1720 if (*lo == -1) 1721 *lo = *hi; 1722 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1723 *hi = *lo; 1724 } 1725 1726 Static void 1727 athn_init_dma(struct athn_softc *sc) 1728 { 1729 uint32_t reg; 1730 1731 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1732 /* Set AHB not to do cacheline prefetches. */ 1733 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1734 } 1735 reg = AR_READ(sc, AR_TXCFG); 1736 /* Let MAC DMA reads be in 128-byte chunks. */ 1737 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1738 1739 /* Set initial Tx trigger level. */ 1740 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1741 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1742 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1743 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1744 AR_WRITE(sc, AR_TXCFG, reg); 1745 1746 /* Let MAC DMA writes be in 128-byte chunks. */ 1747 reg = AR_READ(sc, AR_RXCFG); 1748 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1749 AR_WRITE(sc, AR_RXCFG, reg); 1750 1751 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1752 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1753 1754 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1755 if (AR_SREV_9285(sc)) { 1756 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1757 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1758 } 1759 else if (!AR_SREV_9271(sc)) { 1760 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1761 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1762 } 1763 AR_WRITE_BARRIER(sc); 1764 1765 /* Reset Tx status ring. */ 1766 if (AR_SREV_9380_10_OR_LATER(sc)) 1767 ar9003_reset_txsring(sc); 1768 } 1769 1770 PUBLIC void 1771 athn_inc_tx_trigger_level(struct athn_softc *sc) 1772 { 1773 uint32_t reg, ftrig; 1774 1775 reg = AR_READ(sc, AR_TXCFG); 1776 ftrig = MS(reg, AR_TXCFG_FTRIG); 1777 /* 1778 * NB: The AR9285 and all single-stream parts have an issue that 1779 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1780 */ 1781 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1782 return; /* Already at max. */ 1783 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1784 AR_WRITE(sc, AR_TXCFG, reg); 1785 AR_WRITE_BARRIER(sc); 1786 } 1787 1788 PUBLIC int 1789 athn_stop_rx_dma(struct athn_softc *sc) 1790 { 1791 int ntries; 1792 1793 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1794 /* Wait for Rx enable bit to go low. */ 1795 for (ntries = 0; ntries < 100; ntries++) { 1796 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1797 return 0; 1798 DELAY(100); 1799 } 1800 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1801 return ETIMEDOUT; 1802 } 1803 1804 #ifdef unused 1805 Static int 1806 athn_rx_abort(struct athn_softc *sc) 1807 { 1808 int ntries; 1809 1810 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1811 for (ntries = 0; ntries < 1000; ntries++) { 1812 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1813 return 0; 1814 DELAY(10); 1815 } 1816 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1817 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1818 AR_WRITE_BARRIER(sc); 1819 return ETIMEDOUT; 1820 } 1821 #endif /* unused */ 1822 1823 Static void 1824 athn_tx_reclaim(struct athn_softc *sc, int qid) 1825 { 1826 struct athn_txq *txq = &sc->sc_txq[qid]; 1827 struct athn_tx_buf *bf; 1828 1829 /* Reclaim all buffers queued in the specified Tx queue. */ 1830 /* NB: Tx DMA must be stopped. */ 1831 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1832 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1833 1834 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1835 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1836 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1837 m_freem(bf->bf_m); 1838 bf->bf_m = NULL; 1839 bf->bf_ni = NULL; /* Nodes already freed! */ 1840 1841 /* Link Tx buffer back to global free list. */ 1842 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1843 } 1844 } 1845 1846 PUBLIC int 1847 athn_tx_pending(struct athn_softc *sc, int qid) 1848 { 1849 1850 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1851 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1852 } 1853 1854 PUBLIC void 1855 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1856 { 1857 uint32_t tsflo; 1858 int ntries, i; 1859 1860 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1861 for (ntries = 0; ntries < 40; ntries++) { 1862 if (!athn_tx_pending(sc, qid)) 1863 break; 1864 DELAY(100); 1865 } 1866 if (ntries == 40) { 1867 for (i = 0; i < 2; i++) { 1868 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1869 AR_WRITE(sc, AR_QUIET2, 1870 SM(AR_QUIET2_QUIET_DUR, 10)); 1871 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1872 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1873 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1874 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1875 break; 1876 } 1877 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1878 AR_WRITE_BARRIER(sc); 1879 DELAY(200); 1880 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1881 AR_WRITE_BARRIER(sc); 1882 1883 for (ntries = 0; ntries < 40; ntries++) { 1884 if (!athn_tx_pending(sc, qid)) 1885 break; 1886 DELAY(100); 1887 } 1888 1889 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1890 } 1891 AR_WRITE(sc, AR_Q_TXD, 0); 1892 AR_WRITE_BARRIER(sc); 1893 } 1894 1895 PUBLIC int 1896 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1897 { 1898 #define divround(a, b) (((a) + (b) - 1) / (b)) 1899 int txtime; 1900 1901 /* XXX HT. */ 1902 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1903 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1904 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1905 txtime = 16 + 4 + 4 * txtime + 16; 1906 } 1907 else { 1908 txtime = divround(16 * len, athn_rates[ridx].rate); 1909 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1910 txtime += 72 + 24; 1911 else 1912 txtime += 144 + 48; 1913 txtime += 10; /* 10us SIFS. */ 1914 } 1915 return txtime; 1916 #undef divround 1917 } 1918 1919 PUBLIC void 1920 athn_init_tx_queues(struct athn_softc *sc) 1921 { 1922 int qid; 1923 1924 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1925 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1926 sc->sc_txq[qid].lastds = NULL; 1927 sc->sc_txq[qid].wait = NULL; 1928 sc->sc_txq[qid].queued = 0; 1929 1930 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1931 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1932 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1933 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1934 AR_WRITE(sc, AR_QMISC(qid), 1935 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1936 AR_WRITE(sc, AR_DMISC(qid), 1937 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1938 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1939 } 1940 1941 /* Init beacon queue. */ 1942 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1943 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1944 AR_Q_MISC_CBR_INCR_DIS1); 1945 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1946 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1947 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1948 AR_D_MISC_BEACON_USE | 1949 AR_D_MISC_POST_FR_BKOFF_DIS); 1950 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1951 SM(AR_D_LCL_IFS_CWMIN, 0) | 1952 SM(AR_D_LCL_IFS_CWMAX, 0) | 1953 SM(AR_D_LCL_IFS_AIFS, 1)); 1954 1955 /* Init CAB (Content After Beacon) queue. */ 1956 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1957 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1958 AR_Q_MISC_CBR_INCR_DIS0); 1959 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1960 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1961 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1962 1963 /* Init PS-Poll queue. */ 1964 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1965 AR_Q_MISC_CBR_INCR_DIS1); 1966 1967 /* Init UAPSD queue. */ 1968 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1969 AR_D_MISC_POST_FR_BKOFF_DIS); 1970 1971 if (AR_SREV_9380_10_OR_LATER(sc)) { 1972 /* Enable MAC descriptor CRC check. */ 1973 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1974 } 1975 /* Enable DESC interrupts for all Tx queues. */ 1976 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1977 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1978 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1979 AR_WRITE_BARRIER(sc); 1980 } 1981 1982 PUBLIC void 1983 athn_set_sta_timers(struct athn_softc *sc) 1984 { 1985 struct ieee80211com *ic = &sc->sc_ic; 1986 uint32_t tsfhi, tsflo, tsftu, reg; 1987 uint32_t intval, next_tbtt, next_dtim; 1988 int dtim_period, rem_dtim_count; 1989 1990 tsfhi = AR_READ(sc, AR_TSF_U32); 1991 tsflo = AR_READ(sc, AR_TSF_L32); 1992 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1993 1994 /* Beacon interval in TU. */ 1995 intval = ic->ic_bss->ni_intval; 1996 1997 next_tbtt = roundup(tsftu, intval); 1998 #ifdef notyet 1999 dtim_period = ic->ic_dtim_period; 2000 if (dtim_period <= 0) 2001 #endif 2002 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2003 2004 #ifdef notyet 2005 int dtim_count = ic->ic_dtim_count; 2006 if (dtim_count >= dtim_period) /* Should not happen. */ 2007 dtim_count = 0; /* Assume last TIM was a DTIM. */ 2008 #endif 2009 2010 /* Compute number of remaining TIMs until next DTIM. */ 2011 rem_dtim_count = 0; /* XXX */ 2012 next_dtim = next_tbtt + rem_dtim_count * intval; 2013 2014 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2015 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2016 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2017 2018 /* 2019 * Set the number of consecutive beacons to miss before raising 2020 * a BMISS interrupt to 10. 2021 */ 2022 reg = AR_READ(sc, AR_RSSI_THR); 2023 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2024 AR_WRITE(sc, AR_RSSI_THR, reg); 2025 2026 AR_WRITE(sc, AR_NEXT_DTIM, 2027 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2028 AR_WRITE(sc, AR_NEXT_TIM, 2029 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2030 2031 /* CAB timeout is in 1/8 TU. */ 2032 AR_WRITE(sc, AR_SLEEP1, 2033 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2034 AR_SLEEP1_ASSUME_DTIM); 2035 AR_WRITE(sc, AR_SLEEP2, 2036 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2037 2038 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2039 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2040 2041 AR_SETBITS(sc, AR_TIMER_MODE, 2042 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2043 2044 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2045 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2046 2047 AR_WRITE_BARRIER(sc); 2048 } 2049 2050 #ifndef IEEE80211_STA_ONLY 2051 PUBLIC void 2052 athn_set_hostap_timers(struct athn_softc *sc) 2053 { 2054 struct ieee80211com *ic = &sc->sc_ic; 2055 uint32_t intval, next_tbtt; 2056 2057 /* Beacon interval in TU. */ 2058 intval = ic->ic_bss->ni_intval; 2059 next_tbtt = intval; 2060 2061 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2062 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2063 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2064 AR_WRITE(sc, AR_NEXT_CFP, 2065 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2066 2067 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2068 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2069 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2070 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2071 2072 AR_WRITE(sc, AR_TIMER_MODE, 2073 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2074 2075 AR_WRITE_BARRIER(sc); 2076 } 2077 #endif 2078 2079 PUBLIC void 2080 athn_set_opmode(struct athn_softc *sc) 2081 { 2082 uint32_t reg; 2083 2084 switch (sc->sc_ic.ic_opmode) { 2085 #ifndef IEEE80211_STA_ONLY 2086 case IEEE80211_M_HOSTAP: 2087 reg = AR_READ(sc, AR_STA_ID1); 2088 reg &= ~AR_STA_ID1_ADHOC; 2089 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2090 AR_WRITE(sc, AR_STA_ID1, reg); 2091 2092 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2093 break; 2094 case IEEE80211_M_IBSS: 2095 case IEEE80211_M_AHDEMO: 2096 reg = AR_READ(sc, AR_STA_ID1); 2097 reg &= ~AR_STA_ID1_STA_AP; 2098 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2099 AR_WRITE(sc, AR_STA_ID1, reg); 2100 2101 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2102 break; 2103 #endif 2104 default: 2105 reg = AR_READ(sc, AR_STA_ID1); 2106 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2107 reg |= AR_STA_ID1_KSRCH_MODE; 2108 AR_WRITE(sc, AR_STA_ID1, reg); 2109 break; 2110 } 2111 AR_WRITE_BARRIER(sc); 2112 } 2113 2114 PUBLIC void 2115 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2116 { 2117 const uint8_t *bssid = ni->ni_bssid; 2118 2119 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2120 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2121 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2122 AR_WRITE_BARRIER(sc); 2123 } 2124 2125 Static void 2126 athn_enable_interrupts(struct athn_softc *sc) 2127 { 2128 uint32_t mask2; 2129 2130 athn_disable_interrupts(sc); /* XXX */ 2131 2132 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2133 2134 mask2 = AR_READ(sc, AR_IMR_S2); 2135 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2136 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2137 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2138 AR_WRITE(sc, AR_IMR_S2, mask2); 2139 2140 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2141 2142 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2143 2144 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2145 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2146 2147 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2148 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2149 AR_WRITE_BARRIER(sc); 2150 } 2151 2152 Static void 2153 athn_disable_interrupts(struct athn_softc *sc) 2154 { 2155 2156 AR_WRITE(sc, AR_IER, 0); 2157 (void)AR_READ(sc, AR_IER); 2158 2159 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2160 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2161 2162 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2163 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2164 2165 AR_WRITE(sc, AR_IMR, 0); 2166 2167 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2168 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2169 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2170 2171 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2172 AR_WRITE_BARRIER(sc); 2173 } 2174 2175 Static void 2176 athn_init_qos(struct athn_softc *sc) 2177 { 2178 2179 /* Initialize QoS settings. */ 2180 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2181 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2182 AR_WRITE(sc, AR_QOS_NO_ACK, 2183 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2184 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2185 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2186 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2187 /* Initialize TXOP for all TIDs. */ 2188 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2189 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2190 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2191 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2192 AR_WRITE_BARRIER(sc); 2193 } 2194 2195 PUBLIC int 2196 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2197 struct ieee80211_channel *extchan, int init) 2198 { 2199 struct ieee80211com *ic = &sc->sc_ic; 2200 struct athn_ops *ops = &sc->sc_ops; 2201 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2202 int i, error; 2203 2204 /* XXX not if already awake */ 2205 if ((error = athn_set_power_awake(sc)) != 0) { 2206 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2207 return error; 2208 } 2209 2210 /* Preserve the antenna on a channel switch. */ 2211 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2212 def_ant = 1; 2213 /* Preserve other registers. */ 2214 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2215 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2216 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2217 AR_CFG_LED_BLINK_SLOW); 2218 2219 /* Mark PHY as inactive. */ 2220 ops->disable_phy(sc); 2221 2222 if (init && AR_SREV_9271(sc)) { 2223 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2224 AR9271_RADIO_RF_RST); 2225 DELAY(50); 2226 } 2227 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2228 /* Save TSF before it gets cleared. */ 2229 tsfhi = AR_READ(sc, AR_TSF_U32); 2230 tsflo = AR_READ(sc, AR_TSF_L32); 2231 2232 /* NB: RTC reset clears TSF. */ 2233 error = athn_reset_power_on(sc); 2234 } 2235 else { 2236 tsfhi = tsflo = 0; /* XXX: gcc */ 2237 error = athn_reset(sc, 0); 2238 } 2239 if (error != 0) { 2240 aprint_error_dev(sc->sc_dev, 2241 "could not reset chip (error=%d)\n", error); 2242 return error; 2243 } 2244 2245 /* XXX not if already awake */ 2246 if ((error = athn_set_power_awake(sc)) != 0) { 2247 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2248 return error; 2249 } 2250 2251 athn_init_pll(sc, curchan); 2252 ops->set_rf_mode(sc, curchan); 2253 2254 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2255 /* Check that the radio is not disabled by hardware switch. */ 2256 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2257 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2258 reg = !reg; 2259 if (!reg) { 2260 aprint_error_dev(sc->sc_dev, 2261 "radio is disabled by hardware switch\n"); 2262 return EPERM; 2263 } 2264 } 2265 if (init && AR_SREV_9271(sc)) { 2266 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2267 AR9271_GATE_MAC_CTL); 2268 DELAY(50); 2269 } 2270 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2271 /* Restore TSF if it got cleared. */ 2272 AR_WRITE(sc, AR_TSF_L32, tsflo); 2273 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2274 } 2275 2276 if (AR_SREV_9280_10_OR_LATER(sc)) 2277 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2278 2279 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2280 ar9287_1_3_enable_async_fifo(sc); 2281 2282 /* Write init values to hardware. */ 2283 ops->hw_init(sc, curchan, extchan); 2284 2285 /* 2286 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2287 * management frames using CCMP. 2288 */ 2289 if (AR_SREV_9280_20_OR_LATER(sc)) { 2290 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2291 /* Do not mask the subtype field in management frames. */ 2292 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2293 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2294 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2295 IEEE80211_FC1_MORE_DATA)); 2296 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2297 } 2298 else if (AR_SREV_9160_10_OR_LATER(sc)) { 2299 /* Disable hardware crypto for management frames. */ 2300 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2301 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2302 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2303 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2304 } 2305 2306 if (ic->ic_curmode != IEEE80211_MODE_11B) 2307 ops->set_delta_slope(sc, curchan, extchan); 2308 2309 ops->spur_mitigate(sc, curchan, extchan); 2310 ops->init_from_rom(sc, curchan, extchan); 2311 2312 /* XXX */ 2313 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2314 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2315 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2316 2317 athn_set_opmode(sc); 2318 2319 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2320 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2321 2322 /* Restore previous antenna. */ 2323 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2324 2325 AR_WRITE(sc, AR_BSS_ID0, 0); 2326 AR_WRITE(sc, AR_BSS_ID1, 0); 2327 2328 AR_WRITE(sc, AR_ISR, 0xffffffff); 2329 2330 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2331 2332 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2333 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2334 return error; 2335 } 2336 sc->sc_curchan = curchan; 2337 sc->sc_curchanext = extchan; 2338 2339 for (i = 0; i < AR_NUM_DCU; i++) 2340 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2341 2342 athn_init_tx_queues(sc); 2343 2344 /* Initialize interrupt mask. */ 2345 sc->sc_imask = 2346 AR_IMR_TXDESC | AR_IMR_TXEOL | 2347 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2348 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2349 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2350 if (AR_SREV_9380_10_OR_LATER(sc)) 2351 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2352 #ifndef IEEE80211_STA_ONLY 2353 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2354 sc->sc_imask |= AR_IMR_MIB; 2355 #endif 2356 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2357 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2358 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2359 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2360 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2361 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2362 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2363 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2364 if (AR_SREV_9380_10_OR_LATER(sc)) { 2365 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2366 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2367 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2368 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2369 } 2370 2371 athn_init_qos(sc); 2372 2373 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2374 2375 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2376 ar9287_1_3_setup_async_fifo(sc); 2377 2378 /* Disable sequence number generation in hardware. */ 2379 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2380 2381 athn_init_dma(sc); 2382 2383 /* Program observation bus to see MAC interrupts. */ 2384 AR_WRITE(sc, sc->sc_obs_off, 8); 2385 2386 /* Setup Rx interrupt mitigation. */ 2387 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2388 2389 ops->init_baseband(sc); 2390 2391 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2392 aprint_error_dev(sc->sc_dev, 2393 "could not initialize calibration\n"); 2394 return error; 2395 } 2396 2397 ops->set_rxchains(sc); 2398 2399 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2400 2401 if (sc->sc_flags & ATHN_FLAG_USB) { 2402 if (AR_SREV_9271(sc)) 2403 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2404 else 2405 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2406 } 2407 #if BYTE_ORDER == BIG_ENDIAN 2408 else { 2409 /* Default is LE, turn on swapping for BE. */ 2410 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2411 } 2412 #endif 2413 AR_WRITE_BARRIER(sc); 2414 2415 return 0; 2416 } 2417 2418 Static struct ieee80211_node * 2419 athn_node_alloc(struct ieee80211_node_table *ntp) 2420 { 2421 2422 return malloc(sizeof(struct athn_node), M_DEVBUF, 2423 M_NOWAIT | M_ZERO); 2424 } 2425 2426 Static void 2427 athn_newassoc(struct ieee80211_node *ni, int isnew) 2428 { 2429 struct ieee80211com *ic = ni->ni_ic; 2430 struct athn_softc *sc = ic->ic_ifp->if_softc; 2431 struct athn_node *an = (void *)ni; 2432 struct ieee80211_rateset *rs = &ni->ni_rates; 2433 uint8_t rate; 2434 int ridx, i, j; 2435 2436 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2437 /* Start at lowest available bit-rate, AMRR will raise. */ 2438 ni->ni_txrate = 0; 2439 2440 for (i = 0; i < rs->rs_nrates; i++) { 2441 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2442 2443 /* Map 802.11 rate to HW rate index. */ 2444 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2445 if (athn_rates[ridx].rate == rate) 2446 break; 2447 an->ridx[i] = ridx; 2448 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2449 2450 /* Compute fallback rate for retries. */ 2451 an->fallback[i] = i; 2452 for (j = i - 1; j >= 0; j--) { 2453 if (athn_rates[an->ridx[j]].phy == 2454 athn_rates[an->ridx[i]].phy) { 2455 an->fallback[i] = j; 2456 break; 2457 } 2458 } 2459 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2460 i, an->fallback[i]); 2461 } 2462 } 2463 2464 Static int 2465 athn_media_change(struct ifnet *ifp) 2466 { 2467 struct athn_softc *sc = ifp->if_softc; 2468 struct ieee80211com *ic = &sc->sc_ic; 2469 uint8_t rate, ridx; 2470 int error; 2471 2472 error = ieee80211_media_change(ifp); 2473 if (error != ENETRESET) 2474 return error; 2475 2476 if (ic->ic_fixed_rate != -1) { 2477 rate = ic->ic_sup_rates[ic->ic_curmode]. 2478 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2479 /* Map 802.11 rate to HW rate index. */ 2480 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2481 if (athn_rates[ridx].rate == rate) 2482 break; 2483 sc->sc_fixed_ridx = ridx; 2484 } 2485 if (IS_UP_AND_RUNNING(ifp)) { 2486 athn_stop(ifp, 0); 2487 error = athn_init(ifp); 2488 } 2489 return error; 2490 } 2491 2492 Static void 2493 athn_next_scan(void *arg) 2494 { 2495 struct athn_softc *sc = arg; 2496 struct ieee80211com *ic = &sc->sc_ic; 2497 int s; 2498 2499 s = splnet(); 2500 if (ic->ic_state == IEEE80211_S_SCAN) 2501 ieee80211_next_scan(ic); 2502 splx(s); 2503 } 2504 2505 Static int 2506 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2507 { 2508 struct ifnet *ifp = ic->ic_ifp; 2509 struct athn_softc *sc = ifp->if_softc; 2510 uint32_t reg; 2511 int error; 2512 2513 callout_stop(&sc->sc_calib_to); 2514 2515 switch (nstate) { 2516 case IEEE80211_S_INIT: 2517 athn_set_led(sc, 0); 2518 break; 2519 case IEEE80211_S_SCAN: 2520 /* Make the LED blink while scanning. */ 2521 athn_set_led(sc, !sc->sc_led_state); 2522 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2523 if (error != 0) 2524 return error; 2525 callout_schedule(&sc->sc_scan_to, hz / 5); 2526 break; 2527 case IEEE80211_S_AUTH: 2528 athn_set_led(sc, 0); 2529 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2530 if (error != 0) 2531 return error; 2532 break; 2533 case IEEE80211_S_ASSOC: 2534 break; 2535 case IEEE80211_S_RUN: 2536 athn_set_led(sc, 1); 2537 2538 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2539 break; 2540 2541 /* Fake a join to initialize the Tx rate. */ 2542 athn_newassoc(ic->ic_bss, 1); 2543 2544 athn_set_bss(sc, ic->ic_bss); 2545 athn_disable_interrupts(sc); 2546 #ifndef IEEE80211_STA_ONLY 2547 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2548 athn_set_hostap_timers(sc); 2549 /* Enable software beacon alert interrupts. */ 2550 sc->sc_imask |= AR_IMR_SWBA; 2551 } 2552 else 2553 #endif 2554 { 2555 athn_set_sta_timers(sc); 2556 /* Enable beacon miss interrupts. */ 2557 sc->sc_imask |= AR_IMR_BMISS; 2558 2559 /* Stop receiving beacons from other BSS. */ 2560 reg = AR_READ(sc, AR_RX_FILTER); 2561 reg = (reg & ~AR_RX_FILTER_BEACON) | 2562 AR_RX_FILTER_MYBEACON; 2563 AR_WRITE(sc, AR_RX_FILTER, reg); 2564 AR_WRITE_BARRIER(sc); 2565 } 2566 athn_enable_interrupts(sc); 2567 2568 if (sc->sc_sup_calib_mask != 0) { 2569 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2570 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2571 /* ops->do_calib(sc); */ 2572 } 2573 /* XXX Start ANI. */ 2574 2575 callout_schedule(&sc->sc_calib_to, hz / 2); 2576 break; 2577 } 2578 2579 return sc->sc_newstate(ic, nstate, arg); 2580 } 2581 2582 #ifdef notyet_edca 2583 PUBLIC void 2584 athn_updateedca(struct ieee80211com *ic) 2585 { 2586 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2587 struct athn_softc *sc = ic->ic_ifp->if_softc; 2588 const struct ieee80211_edca_ac_params *ac; 2589 int aci, qid; 2590 2591 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2592 ac = &ic->ic_edca_ac[aci]; 2593 qid = athn_ac2qid[aci]; 2594 2595 AR_WRITE(sc, AR_DLCL_IFS(qid), 2596 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2597 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2598 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2599 if (ac->ac_txoplimit != 0) { 2600 AR_WRITE(sc, AR_DCHNTIME(qid), 2601 SM(AR_D_CHNTIME_DUR, 2602 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2603 AR_D_CHNTIME_EN); 2604 } 2605 else 2606 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2607 } 2608 AR_WRITE_BARRIER(sc); 2609 #undef ATHN_EXP2 2610 } 2611 #endif /* notyet_edca */ 2612 2613 Static int 2614 athn_clock_rate(struct athn_softc *sc) 2615 { 2616 struct ieee80211com *ic = &sc->sc_ic; 2617 int clockrate; /* MHz. */ 2618 2619 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2620 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2621 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2622 else 2623 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2624 } 2625 else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2626 clockrate = AR_CLOCK_RATE_CCK; 2627 } 2628 else 2629 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2630 #ifndef IEEE80211_NO_HT 2631 if (sc->sc_curchanext != NULL) 2632 clockrate *= 2; 2633 #endif 2634 return clockrate; 2635 } 2636 2637 PUBLIC void 2638 athn_updateslot(struct ifnet *ifp) 2639 { 2640 struct athn_softc *sc = ifp->if_softc; 2641 struct ieee80211com *ic = &sc->sc_ic; 2642 int slot; 2643 2644 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2645 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2646 AR_WRITE_BARRIER(sc); 2647 } 2648 2649 Static void 2650 athn_start(struct ifnet *ifp) 2651 { 2652 struct athn_softc *sc = ifp->if_softc; 2653 struct ieee80211com *ic = &sc->sc_ic; 2654 struct ether_header *eh; 2655 struct ieee80211_node *ni; 2656 struct mbuf *m; 2657 2658 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2659 || !device_is_active(sc->sc_dev)) 2660 return; 2661 2662 for (;;) { 2663 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2664 ifp->if_flags |= IFF_OACTIVE; 2665 break; 2666 } 2667 /* Send pending management frames first. */ 2668 IF_DEQUEUE(&ic->ic_mgtq, m); 2669 if (m != NULL) { 2670 ni = M_GETCTX(m, struct ieee80211_node *); 2671 goto sendit; 2672 } 2673 if (ic->ic_state != IEEE80211_S_RUN) 2674 break; 2675 2676 /* Encapsulate and send data frames. */ 2677 IFQ_DEQUEUE(&ifp->if_snd, m); 2678 if (m == NULL) 2679 break; 2680 2681 if (m->m_len < (int)sizeof(*eh) && 2682 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2683 ifp->if_oerrors++; 2684 continue; 2685 } 2686 eh = mtod(m, struct ether_header *); 2687 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2688 if (ni == NULL) { 2689 m_freem(m); 2690 ifp->if_oerrors++; 2691 continue; 2692 } 2693 2694 bpf_mtap(ifp, m); 2695 2696 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2697 continue; 2698 sendit: 2699 bpf_mtap3(ic->ic_rawbpf, m); 2700 2701 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2702 ieee80211_free_node(ni); 2703 ifp->if_oerrors++; 2704 continue; 2705 } 2706 2707 sc->sc_tx_timer = 5; 2708 ifp->if_timer = 1; 2709 } 2710 } 2711 2712 Static void 2713 athn_watchdog(struct ifnet *ifp) 2714 { 2715 struct athn_softc *sc = ifp->if_softc; 2716 2717 ifp->if_timer = 0; 2718 2719 if (sc->sc_tx_timer > 0) { 2720 if (--sc->sc_tx_timer == 0) { 2721 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2722 /* see athn_init, no need to call athn_stop here */ 2723 /* athn_stop(ifp, 0); */ 2724 (void)athn_init(ifp); 2725 ifp->if_oerrors++; 2726 return; 2727 } 2728 ifp->if_timer = 1; 2729 } 2730 ieee80211_watchdog(&sc->sc_ic); 2731 } 2732 2733 #ifdef notyet 2734 Static void 2735 athn_set_multi(struct athn_softc *sc) 2736 { 2737 struct arpcom *ac = &sc->sc_ic.ic_ac; 2738 struct ifnet *ifp = &ac->ac_if; 2739 struct ether_multi *enm; 2740 struct ether_multistep step; 2741 const uint8_t *addr; 2742 uint32_t val, lo, hi; 2743 uint8_t bit; 2744 2745 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2746 lo = hi = 0xffffffff; 2747 goto done; 2748 } 2749 lo = hi = 0; 2750 ETHER_FIRST_MULTI(step, ac, enm); 2751 while (enm != NULL) { 2752 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2753 ifp->if_flags |= IFF_ALLMULTI; 2754 lo = hi = 0xffffffff; 2755 goto done; 2756 } 2757 addr = enm->enm_addrlo; 2758 /* Calculate the XOR value of all eight 6-bit words. */ 2759 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2760 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2761 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2762 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2763 bit &= 0x3f; 2764 if (bit < 32) 2765 lo |= 1 << bit; 2766 else 2767 hi |= 1 << (bit - 32); 2768 ETHER_NEXT_MULTI(step, enm); 2769 } 2770 done: 2771 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2772 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2773 AR_WRITE_BARRIER(sc); 2774 } 2775 #endif /* notyet */ 2776 2777 Static int 2778 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2779 { 2780 struct athn_softc *sc = ifp->if_softc; 2781 struct ieee80211com *ic = &sc->sc_ic; 2782 int s, error = 0; 2783 2784 s = splnet(); 2785 2786 switch (cmd) { 2787 case SIOCSIFFLAGS: 2788 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2789 break; 2790 2791 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2792 case IFF_UP | IFF_RUNNING: 2793 #ifdef notyet 2794 if (((ifp->if_flags ^ sc->sc_if_flags) & 2795 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2796 /* XXX: setup multi */ 2797 #endif 2798 break; 2799 case IFF_UP: 2800 athn_init(ifp); 2801 break; 2802 2803 case IFF_RUNNING: 2804 athn_stop(ifp, 1); 2805 break; 2806 case 0: 2807 default: 2808 break; 2809 } 2810 sc->sc_if_flags = ifp->if_flags; 2811 break; 2812 2813 case SIOCADDMULTI: 2814 case SIOCDELMULTI: 2815 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2816 /* setup multicast filter, etc */ 2817 #ifdef notyet 2818 athn_set_multi(sc); 2819 #endif 2820 error = 0; 2821 } 2822 break; 2823 2824 case SIOCS80211CHANNEL: 2825 error = ieee80211_ioctl(ic, cmd, data); 2826 if (error == ENETRESET && 2827 ic->ic_opmode == IEEE80211_M_MONITOR) { 2828 if (IS_UP_AND_RUNNING(ifp)) 2829 athn_switch_chan(sc, ic->ic_curchan, NULL); 2830 error = 0; 2831 } 2832 break; 2833 2834 default: 2835 error = ieee80211_ioctl(ic, cmd, data); 2836 } 2837 2838 if (error == ENETRESET) { 2839 error = 0; 2840 if (IS_UP_AND_RUNNING(ifp) && 2841 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2842 athn_stop(ifp, 0); 2843 error = athn_init(ifp); 2844 } 2845 } 2846 2847 splx(s); 2848 return error; 2849 } 2850 2851 Static int 2852 athn_init(struct ifnet *ifp) 2853 { 2854 struct athn_softc *sc = ifp->if_softc; 2855 struct athn_ops *ops = &sc->sc_ops; 2856 struct ieee80211com *ic = &sc->sc_ic; 2857 struct ieee80211_channel *curchan, *extchan; 2858 size_t i; 2859 int error; 2860 2861 KASSERT(!cpu_intr_p()); 2862 2863 if (device_is_active(sc->sc_dev)) { 2864 athn_stop(ifp, 0); /* see athn_watchdog() */ 2865 } else { 2866 short flags = ifp->if_flags; 2867 ifp->if_flags &= ~IFF_UP; 2868 /* avoid recursion in athn_resume */ 2869 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2870 !device_is_active(sc->sc_dev)) { 2871 printf("%s: failed to power up device\n", 2872 device_xname(sc->sc_dev)); 2873 return 0; 2874 } 2875 ifp->if_flags = flags; 2876 } 2877 2878 curchan = ic->ic_curchan; 2879 extchan = NULL; 2880 2881 /* In case a new MAC address has been configured. */ 2882 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2883 2884 #ifdef openbsd_power_management 2885 /* For CardBus, power on the socket. */ 2886 if (sc->sc_enable != NULL) { 2887 if ((error = sc->sc_enable(sc)) != 0) { 2888 aprint_error_dev(sc->sc_dev, 2889 "could not enable device\n"); 2890 goto fail; 2891 } 2892 if ((error = athn_reset_power_on(sc)) != 0) { 2893 aprint_error_dev(sc->sc_dev, 2894 "could not power on device\n"); 2895 goto fail; 2896 } 2897 } 2898 #endif 2899 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2900 athn_config_nonpcie(sc); 2901 else 2902 athn_config_pcie(sc); 2903 2904 /* Reset HW key cache entries. */ 2905 for (i = 0; i < sc->sc_kc_entries; i++) 2906 athn_reset_key(sc, i); 2907 2908 ops->enable_antenna_diversity(sc); 2909 2910 #ifdef ATHN_BT_COEXISTENCE 2911 /* Configure bluetooth coexistence for combo chips. */ 2912 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2913 athn_btcoex_init(sc); 2914 #endif 2915 2916 /* Configure LED. */ 2917 athn_led_init(sc); 2918 2919 /* Configure hardware radio switch. */ 2920 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2921 ops->rfsilent_init(sc); 2922 2923 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2924 aprint_error_dev(sc->sc_dev, 2925 "unable to reset hardware; reset status %d\n", error); 2926 goto fail; 2927 } 2928 2929 /* Enable Rx. */ 2930 athn_rx_start(sc); 2931 2932 /* Enable interrupts. */ 2933 athn_enable_interrupts(sc); 2934 2935 #ifdef ATHN_BT_COEXISTENCE 2936 /* Enable bluetooth coexistence for combo chips. */ 2937 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2938 athn_btcoex_enable(sc); 2939 #endif 2940 2941 ifp->if_flags &= ~IFF_OACTIVE; 2942 ifp->if_flags |= IFF_RUNNING; 2943 2944 #ifdef notyet 2945 if (ic->ic_flags & IEEE80211_F_WEPON) { 2946 /* Configure WEP keys. */ 2947 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2948 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2949 } 2950 #endif 2951 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2952 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2953 else 2954 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2955 2956 return 0; 2957 fail: 2958 athn_stop(ifp, 1); 2959 return error; 2960 } 2961 2962 PUBLIC void 2963 athn_stop(struct ifnet *ifp, int disable) 2964 { 2965 struct athn_softc *sc = ifp->if_softc; 2966 struct ieee80211com *ic = &sc->sc_ic; 2967 int qid; 2968 2969 ifp->if_timer = sc->sc_tx_timer = 0; 2970 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2971 2972 callout_stop(&sc->sc_scan_to); 2973 /* In case we were scanning, release the scan "lock". */ 2974 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2975 2976 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2977 2978 #ifdef ATHN_BT_COEXISTENCE 2979 /* Disable bluetooth coexistence for combo chips. */ 2980 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2981 athn_btcoex_disable(sc); 2982 #endif 2983 2984 /* Disable interrupts. */ 2985 athn_disable_interrupts(sc); 2986 /* Acknowledge interrupts (avoids interrupt storms). */ 2987 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2988 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2989 2990 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2991 athn_stop_tx_dma(sc, qid); 2992 /* XXX call athn_hw_reset if Tx still pending? */ 2993 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2994 athn_tx_reclaim(sc, qid); 2995 2996 /* Stop Rx. */ 2997 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2998 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2999 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 3000 AR_WRITE(sc, AR_FILT_OFDM, 0); 3001 AR_WRITE(sc, AR_FILT_CCK, 0); 3002 AR_WRITE_BARRIER(sc); 3003 athn_set_rxfilter(sc, 0); 3004 athn_stop_rx_dma(sc); 3005 3006 athn_reset(sc, 0); 3007 athn_init_pll(sc, NULL); 3008 athn_set_power_awake(sc); 3009 athn_reset(sc, 1); 3010 athn_init_pll(sc, NULL); 3011 3012 athn_set_power_sleep(sc); 3013 3014 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3015 /* For CardBus, power down the socket. */ 3016 if (disable && sc->sc_disable != NULL) 3017 sc->sc_disable(sc); 3018 #endif 3019 if (disable) 3020 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3021 } 3022 3023 Static void 3024 athn_pmf_wlan_off(device_t self) 3025 { 3026 struct athn_softc *sc = device_private(self); 3027 struct ifnet *ifp = &sc->sc_if; 3028 3029 /* Turn the interface down. */ 3030 ifp->if_flags &= ~IFF_UP; 3031 athn_stop(ifp, 1); 3032 } 3033 3034 PUBLIC void 3035 athn_suspend(struct athn_softc *sc) 3036 { 3037 struct ifnet *ifp = &sc->sc_if; 3038 3039 if (ifp->if_flags & IFF_RUNNING) 3040 athn_stop(ifp, 1); 3041 } 3042 3043 PUBLIC bool 3044 athn_resume(struct athn_softc *sc) 3045 { 3046 struct ifnet *ifp = &sc->sc_if; 3047 3048 if (ifp->if_flags & IFF_UP) 3049 athn_init(ifp); 3050 3051 return true; 3052 } 3053