1 /* $NetBSD: athn.c,v 1.18 2018/06/26 06:48:00 msaitoh Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.18 2018/06/26 06:48:00 msaitoh Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 Static void athn_set_multi(struct athn_softc *); 140 #endif /* notyet */ 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } 253 else { 254 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 255 athn_get_rf_name(sc)); 256 aprint_verbose_dev(sc->sc_dev, 257 "rev %d (%dT%dR), ROM rev %d, address %s\n", 258 sc->sc_mac_rev, 259 sc->sc_ntxchains, sc->sc_nrxchains, 260 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 261 } 262 263 callout_init(&sc->sc_scan_to, 0); 264 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 265 callout_init(&sc->sc_calib_to, 0); 266 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 267 268 sc->sc_amrr.amrr_min_success_threshold = 1; 269 sc->sc_amrr.amrr_max_success_threshold = 15; 270 271 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 272 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 273 ic->ic_state = IEEE80211_S_INIT; 274 275 /* Set device capabilities. */ 276 ic->ic_caps = 277 IEEE80211_C_WPA | /* 802.11i */ 278 #ifndef IEEE80211_STA_ONLY 279 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 280 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 281 #endif 282 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 283 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 284 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 285 IEEE80211_C_PMGT; /* Power saving supported. */ 286 287 #ifndef IEEE80211_NO_HT 288 if (sc->sc_flags & ATHN_FLAG_11N) { 289 int i, ntxstreams, nrxstreams; 290 291 /* Set HT capabilities. */ 292 ic->ic_htcaps = 293 IEEE80211_HTCAP_SMPS_DIS | 294 IEEE80211_HTCAP_CBW20_40 | 295 IEEE80211_HTCAP_SGI40 | 296 IEEE80211_HTCAP_DSSSCCK40; 297 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 298 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 299 if (AR_SREV_9380_10_OR_LATER(sc)) 300 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 301 if (AR_SREV_9280_10_OR_LATER(sc)) { 302 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 303 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 304 } 305 ntxstreams = sc->sc_ntxchains; 306 nrxstreams = sc->sc_nrxchains; 307 if (!AR_SREV_9380_10_OR_LATER(sc)) { 308 ntxstreams = MIN(ntxstreams, 2); 309 nrxstreams = MIN(nrxstreams, 2); 310 } 311 /* Set supported HT rates. */ 312 for (i = 0; i < nrxstreams; i++) 313 ic->ic_sup_mcs[i] = 0xff; 314 /* Set the "Tx MCS Set Defined" bit. */ 315 ic->ic_sup_mcs[12] |= 0x01; 316 if (ntxstreams != nrxstreams) { 317 /* Set "Tx Rx MCS Set Not Equal" bit. */ 318 ic->ic_sup_mcs[12] |= 0x02; 319 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 320 } 321 } 322 #endif 323 324 /* Set supported rates. */ 325 if (sc->sc_flags & ATHN_FLAG_11G) { 326 ic->ic_sup_rates[IEEE80211_MODE_11B] = 327 ieee80211_std_rateset_11b; 328 ic->ic_sup_rates[IEEE80211_MODE_11G] = 329 ieee80211_std_rateset_11g; 330 } 331 if (sc->sc_flags & ATHN_FLAG_11A) { 332 ic->ic_sup_rates[IEEE80211_MODE_11A] = 333 ieee80211_std_rateset_11a; 334 } 335 336 /* Get the list of authorized/supported channels. */ 337 athn_get_chanlist(sc); 338 339 ifp->if_softc = sc; 340 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 341 if (!ifp->if_init) 342 ifp->if_init = athn_init; 343 if (!ifp->if_ioctl) 344 ifp->if_ioctl = athn_ioctl; 345 if (!ifp->if_start) 346 ifp->if_start = athn_start; 347 if (!ifp->if_watchdog) 348 ifp->if_watchdog = athn_watchdog; 349 IFQ_SET_READY(&ifp->if_snd); 350 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 351 352 error = if_initialize(ifp); 353 if (error != 0) { 354 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 355 error); 356 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, 357 athn_pmf_wlan_off, false); 358 callout_destroy(&sc->sc_scan_to); 359 callout_destroy(&sc->sc_calib_to); 360 return error; 361 } 362 ieee80211_ifattach(ic); 363 /* Use common softint-based if_input */ 364 ifp->if_percpuq = if_percpuq_create(ifp); 365 if_register(ifp); 366 367 ic->ic_node_alloc = athn_node_alloc; 368 ic->ic_newassoc = athn_newassoc; 369 if (ic->ic_updateslot == NULL) 370 ic->ic_updateslot = athn_updateslot; 371 #ifdef notyet_edca 372 ic->ic_updateedca = athn_updateedca; 373 #endif 374 #ifdef notyet 375 ic->ic_set_key = athn_set_key; 376 ic->ic_delete_key = athn_delete_key; 377 #endif 378 379 /* Override 802.11 state transition machine. */ 380 sc->sc_newstate = ic->ic_newstate; 381 ic->ic_newstate = athn_newstate; 382 383 if (sc->sc_media_change == NULL) 384 sc->sc_media_change = athn_media_change; 385 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 386 387 athn_radiotap_attach(sc); 388 return 0; 389 } 390 391 PUBLIC void 392 athn_detach(struct athn_softc *sc) 393 { 394 struct ifnet *ifp = &sc->sc_if; 395 int qid; 396 397 callout_halt(&sc->sc_scan_to, NULL); 398 callout_halt(&sc->sc_calib_to, NULL); 399 400 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 401 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 402 athn_tx_reclaim(sc, qid); 403 404 /* Free Tx/Rx DMA resources. */ 405 sc->sc_ops.dma_free(sc); 406 407 if (sc->sc_soft_ih != NULL) { 408 softint_disestablish(sc->sc_soft_ih); 409 sc->sc_soft_ih = NULL; 410 } 411 } 412 /* Free ROM copy. */ 413 if (sc->sc_eep != NULL) { 414 free(sc->sc_eep, M_DEVBUF); 415 sc->sc_eep = NULL; 416 } 417 418 bpf_detach(ifp); 419 ieee80211_ifdetach(&sc->sc_ic); 420 if_detach(ifp); 421 422 callout_destroy(&sc->sc_scan_to); 423 callout_destroy(&sc->sc_calib_to); 424 425 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 426 false); 427 } 428 429 /* 430 * Attach the interface to 802.11 radiotap. 431 */ 432 Static void 433 athn_radiotap_attach(struct athn_softc *sc) 434 { 435 436 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 437 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 438 &sc->sc_drvbpf); 439 440 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 441 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 442 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 443 444 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 445 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 446 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 447 } 448 449 Static void 450 athn_get_chanlist(struct athn_softc *sc) 451 { 452 struct ieee80211com *ic = &sc->sc_ic; 453 uint8_t chan; 454 size_t i; 455 456 if (sc->sc_flags & ATHN_FLAG_11G) { 457 for (i = 1; i <= 14; i++) { 458 chan = i; 459 ic->ic_channels[chan].ic_freq = 460 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 461 ic->ic_channels[chan].ic_flags = 462 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 463 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 464 } 465 } 466 if (sc->sc_flags & ATHN_FLAG_11A) { 467 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 468 chan = athn_5ghz_chans[i]; 469 ic->ic_channels[chan].ic_freq = 470 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 471 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 472 } 473 } 474 } 475 476 PUBLIC void 477 athn_rx_start(struct athn_softc *sc) 478 { 479 struct ieee80211com *ic = &sc->sc_ic; 480 uint32_t rfilt; 481 482 /* Setup Rx DMA descriptors. */ 483 sc->sc_ops.rx_enable(sc); 484 485 /* Set Rx filter. */ 486 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 487 #ifndef IEEE80211_NO_HT 488 /* Want Compressed Block Ack Requests. */ 489 rfilt |= AR_RX_FILTER_COMPR_BAR; 490 #endif 491 rfilt |= AR_RX_FILTER_BEACON; 492 if (ic->ic_opmode != IEEE80211_M_STA) { 493 rfilt |= AR_RX_FILTER_PROBEREQ; 494 if (ic->ic_opmode == IEEE80211_M_MONITOR) 495 rfilt |= AR_RX_FILTER_PROM; 496 #ifndef IEEE80211_STA_ONLY 497 if (AR_SREV_9280_10_OR_LATER(sc) && 498 ic->ic_opmode == IEEE80211_M_HOSTAP) 499 rfilt |= AR_RX_FILTER_PSPOLL; 500 #endif 501 } 502 athn_set_rxfilter(sc, rfilt); 503 504 /* Set BSSID mask. */ 505 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 506 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 507 508 athn_set_opmode(sc); 509 510 /* Set multicast filter. */ 511 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 512 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 513 514 AR_WRITE(sc, AR_FILT_OFDM, 0); 515 AR_WRITE(sc, AR_FILT_CCK, 0); 516 AR_WRITE(sc, AR_MIBC, 0); 517 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 518 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 519 520 /* XXX ANI. */ 521 AR_WRITE(sc, AR_PHY_ERR_1, 0); 522 AR_WRITE(sc, AR_PHY_ERR_2, 0); 523 524 /* Disable HW crypto for now. */ 525 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 526 527 /* Start PCU Rx. */ 528 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 529 AR_WRITE_BARRIER(sc); 530 } 531 532 PUBLIC void 533 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 534 { 535 536 AR_WRITE(sc, AR_RX_FILTER, rfilt); 537 #ifdef notyet 538 reg = AR_READ(sc, AR_PHY_ERR); 539 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 540 AR_PHY_ERR_CCK_TIMING); 541 AR_WRITE(sc, AR_PHY_ERR, reg); 542 if (reg != 0) 543 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 544 else 545 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 546 #else 547 AR_WRITE(sc, AR_PHY_ERR, 0); 548 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 549 #endif 550 AR_WRITE_BARRIER(sc); 551 } 552 553 PUBLIC int 554 athn_intr(void *xsc) 555 { 556 struct athn_softc *sc = xsc; 557 struct ifnet *ifp = &sc->sc_if; 558 559 if (!IS_UP_AND_RUNNING(ifp)) 560 return 0; 561 562 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 563 /* 564 * The hardware is not ready/present, don't touch anything. 565 * Note this can happen early on if the IRQ is shared. 566 */ 567 return 0; 568 569 if (!sc->sc_ops.intr_status(sc)) 570 return 0; 571 572 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 573 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 574 AR_WRITE_BARRIER(sc); 575 576 softint_schedule(sc->sc_soft_ih); 577 578 return 1; 579 } 580 581 Static void 582 athn_softintr(void *xsc) 583 { 584 struct athn_softc *sc = xsc; 585 struct ifnet *ifp = &sc->sc_if; 586 587 if (!IS_UP_AND_RUNNING(ifp)) 588 return; 589 590 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 591 /* 592 * The hardware is not ready/present, don't touch anything. 593 * Note this can happen early on if the IRQ is shared. 594 */ 595 return; 596 597 sc->sc_ops.intr(sc); 598 599 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 600 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 601 AR_WRITE_BARRIER(sc); 602 } 603 604 Static void 605 athn_get_chipid(struct athn_softc *sc) 606 { 607 uint32_t reg; 608 609 reg = AR_READ(sc, AR_SREV); 610 if (MS(reg, AR_SREV_ID) == 0xff) { 611 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 612 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 613 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 614 sc->sc_flags |= ATHN_FLAG_PCIE; 615 } 616 else { 617 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 618 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 619 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 620 sc->sc_flags |= ATHN_FLAG_PCIE; 621 } 622 } 623 624 Static const char * 625 athn_get_mac_name(struct athn_softc *sc) 626 { 627 628 switch (sc->sc_mac_ver) { 629 case AR_SREV_VERSION_5416_PCI: 630 return "AR5416"; 631 case AR_SREV_VERSION_5416_PCIE: 632 return "AR5418"; 633 case AR_SREV_VERSION_9160: 634 return "AR9160"; 635 case AR_SREV_VERSION_9280: 636 return "AR9280"; 637 case AR_SREV_VERSION_9285: 638 return "AR9285"; 639 case AR_SREV_VERSION_9271: 640 return "AR9271"; 641 case AR_SREV_VERSION_9287: 642 return "AR9287"; 643 case AR_SREV_VERSION_9380: 644 return "AR9380"; 645 case AR_SREV_VERSION_9485: 646 return "AR9485"; 647 default: 648 return "unknown"; 649 } 650 } 651 652 /* 653 * Return RF chip name (not for single-chip solutions). 654 */ 655 Static const char * 656 athn_get_rf_name(struct athn_softc *sc) 657 { 658 659 KASSERT(!AR_SINGLE_CHIP(sc)); 660 661 switch (sc->sc_rf_rev) { 662 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 663 return "AR5133"; 664 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 665 return "AR2133"; 666 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 667 return "AR5122"; 668 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 669 return "AR2122"; 670 default: 671 return "unknown"; 672 } 673 } 674 675 PUBLIC int 676 athn_reset_power_on(struct athn_softc *sc) 677 { 678 int ntries; 679 680 /* Set force wake. */ 681 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 682 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 683 684 if (!AR_SREV_9380_10_OR_LATER(sc)) { 685 /* Make sure no DMA is active by doing an AHB reset. */ 686 AR_WRITE(sc, AR_RC, AR_RC_AHB); 687 } 688 /* RTC reset and clear. */ 689 AR_WRITE(sc, AR_RTC_RESET, 0); 690 AR_WRITE_BARRIER(sc); 691 DELAY(2); 692 if (!AR_SREV_9380_10_OR_LATER(sc)) 693 AR_WRITE(sc, AR_RC, 0); 694 AR_WRITE(sc, AR_RTC_RESET, 1); 695 696 /* Poll until RTC is ON. */ 697 for (ntries = 0; ntries < 1000; ntries++) { 698 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 699 AR_RTC_STATUS_ON) 700 break; 701 DELAY(10); 702 } 703 if (ntries == 1000) { 704 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 705 return ETIMEDOUT; 706 } 707 return athn_reset(sc, 0); 708 } 709 710 PUBLIC int 711 athn_reset(struct athn_softc *sc, int cold_reset) 712 { 713 int ntries; 714 715 /* Set force wake. */ 716 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 717 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 718 719 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 720 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 721 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 722 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 723 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 724 } 725 else if (!AR_SREV_9380_10_OR_LATER(sc)) 726 AR_WRITE(sc, AR_RC, AR_RC_AHB); 727 728 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 729 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 730 AR_WRITE_BARRIER(sc); 731 DELAY(50); 732 AR_WRITE(sc, AR_RTC_RC, 0); 733 for (ntries = 0; ntries < 1000; ntries++) { 734 if (!(AR_READ(sc, AR_RTC_RC) & 735 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 736 break; 737 DELAY(10); 738 } 739 if (ntries == 1000) { 740 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 741 return ETIMEDOUT; 742 } 743 AR_WRITE(sc, AR_RC, 0); 744 AR_WRITE_BARRIER(sc); 745 return 0; 746 } 747 748 PUBLIC int 749 athn_set_power_awake(struct athn_softc *sc) 750 { 751 int ntries, error; 752 753 /* Do a Power-On-Reset if shutdown. */ 754 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 755 AR_RTC_STATUS_SHUTDOWN) { 756 if ((error = athn_reset_power_on(sc)) != 0) 757 return error; 758 if (!AR_SREV_9380_10_OR_LATER(sc)) 759 athn_init_pll(sc, NULL); 760 } 761 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 762 AR_WRITE_BARRIER(sc); 763 DELAY(50); /* Give chip the chance to awake. */ 764 765 /* Poll until RTC is ON. */ 766 for (ntries = 0; ntries < 4000; ntries++) { 767 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 768 AR_RTC_STATUS_ON) 769 break; 770 DELAY(50); 771 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 772 } 773 if (ntries == 4000) { 774 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 775 return ETIMEDOUT; 776 } 777 778 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 779 AR_WRITE_BARRIER(sc); 780 return 0; 781 } 782 783 PUBLIC void 784 athn_set_power_sleep(struct athn_softc *sc) 785 { 786 787 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 788 /* Allow the MAC to go to sleep. */ 789 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 790 if (!AR_SREV_9380_10_OR_LATER(sc)) 791 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 792 /* 793 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 794 * results in high power consumption on AR5416 chipsets. 795 */ 796 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 797 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 798 AR_WRITE_BARRIER(sc); 799 } 800 801 PUBLIC void 802 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 803 { 804 uint32_t pll; 805 806 if (AR_SREV_9380_10_OR_LATER(sc)) { 807 if (AR_SREV_9485(sc)) 808 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 809 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 810 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 811 } 812 else if (AR_SREV_9280_10_OR_LATER(sc)) { 813 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 814 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 815 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 816 pll = 0x142c; 817 else if (AR_SREV_9280_20(sc)) 818 pll = 0x2850; 819 else 820 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 821 } 822 else 823 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 824 } 825 else if (AR_SREV_9160_10_OR_LATER(sc)) { 826 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 827 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 828 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 829 else 830 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 831 } 832 else { 833 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 834 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 835 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 836 else 837 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 838 } 839 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 840 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 841 if (AR_SREV_9271(sc)) { 842 /* Switch core clock to 117MHz. */ 843 AR_WRITE_BARRIER(sc); 844 DELAY(500); 845 AR_WRITE(sc, 0x50050, 0x304); 846 } 847 AR_WRITE_BARRIER(sc); 848 DELAY(100); 849 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 850 AR_WRITE_BARRIER(sc); 851 } 852 853 Static void 854 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 855 { 856 int i; 857 858 /* Write sequence to Serializer/Deserializer. */ 859 for (i = 0; i < serdes->nvals; i++) 860 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 861 AR_WRITE_BARRIER(sc); 862 } 863 864 PUBLIC void 865 athn_config_pcie(struct athn_softc *sc) 866 { 867 868 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 869 athn_write_serdes(sc, sc->sc_serdes); 870 871 DELAY(1000); 872 /* Allow forcing of PCIe core into L1 state. */ 873 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 874 875 #ifndef ATHN_PCIE_WAEN 876 AR_WRITE(sc, AR_WA, sc->sc_workaround); 877 #else 878 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 879 #endif 880 AR_WRITE_BARRIER(sc); 881 } 882 883 /* 884 * Serializer/Deserializer programming for non-PCIe devices. 885 */ 886 static const uint32_t ar_nonpcie_serdes_regs[] = { 887 AR_PCIE_SERDES, 888 AR_PCIE_SERDES, 889 AR_PCIE_SERDES, 890 AR_PCIE_SERDES, 891 AR_PCIE_SERDES, 892 AR_PCIE_SERDES, 893 AR_PCIE_SERDES, 894 AR_PCIE_SERDES, 895 AR_PCIE_SERDES, 896 AR_PCIE_SERDES2, 897 }; 898 899 static const uint32_t ar_nonpcie_serdes_vals[] = { 900 0x9248fc00, 901 0x24924924, 902 0x28000029, 903 0x57160824, 904 0x25980579, 905 0x00000000, 906 0x1aaabe40, 907 0xbe105554, 908 0x000e1007, 909 0x00000000 910 }; 911 912 static const struct athn_serdes ar_nonpcie_serdes = { 913 __arraycount(ar_nonpcie_serdes_vals), 914 ar_nonpcie_serdes_regs, 915 ar_nonpcie_serdes_vals 916 }; 917 918 PUBLIC void 919 athn_config_nonpcie(struct athn_softc *sc) 920 { 921 922 athn_write_serdes(sc, &ar_nonpcie_serdes); 923 } 924 925 PUBLIC int 926 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 927 struct ieee80211_channel *extchan) 928 { 929 struct athn_ops *ops = &sc->sc_ops; 930 int error, qid; 931 932 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 933 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 934 if (athn_tx_pending(sc, qid)) 935 return EBUSY; 936 937 /* Request RF Bus grant. */ 938 if ((error = ops->rf_bus_request(sc)) != 0) 939 return error; 940 941 ops->set_phy(sc, curchan, extchan); 942 943 /* Change the synthesizer. */ 944 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 945 return error; 946 947 sc->sc_curchan = curchan; 948 sc->sc_curchanext = extchan; 949 950 /* Set transmit power values for new channel. */ 951 ops->set_txpower(sc, curchan, extchan); 952 953 /* Release the RF Bus grant. */ 954 ops->rf_bus_release(sc); 955 956 /* Write delta slope coeffs for modes where OFDM may be used. */ 957 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 958 ops->set_delta_slope(sc, curchan, extchan); 959 960 ops->spur_mitigate(sc, curchan, extchan); 961 /* XXX Load noisefloor values and start calibration. */ 962 963 return 0; 964 } 965 966 Static int 967 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 968 struct ieee80211_channel *extchan) 969 { 970 int error, qid; 971 972 /* Disable interrupts. */ 973 athn_disable_interrupts(sc); 974 975 /* Stop all Tx queues. */ 976 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 977 athn_stop_tx_dma(sc, qid); 978 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 979 athn_tx_reclaim(sc, qid); 980 981 /* Stop Rx. */ 982 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 983 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 984 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 985 AR_WRITE(sc, AR_FILT_OFDM, 0); 986 AR_WRITE(sc, AR_FILT_CCK, 0); 987 athn_set_rxfilter(sc, 0); 988 error = athn_stop_rx_dma(sc); 989 if (error != 0) 990 goto reset; 991 992 #ifdef notyet 993 /* AR9280 needs a full reset. */ 994 if (AR_SREV_9280(sc)) 995 #endif 996 goto reset; 997 998 /* If band or bandwidth changes, we need to do a full reset. */ 999 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 1000 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 1001 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 1002 goto reset; 1003 } 1004 error = athn_set_power_awake(sc); 1005 if (error != 0) 1006 goto reset; 1007 1008 error = athn_set_chan(sc, curchan, extchan); 1009 if (error != 0) { 1010 reset: /* Error found, try a full reset. */ 1011 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 1012 error = athn_hw_reset(sc, curchan, extchan, 0); 1013 if (error != 0) /* Hopeless case. */ 1014 return error; 1015 } 1016 athn_rx_start(sc); 1017 1018 /* Re-enable interrupts. */ 1019 athn_enable_interrupts(sc); 1020 return 0; 1021 } 1022 1023 PUBLIC void 1024 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1025 { 1026 #define COEFF_SCALE_SHIFT 24 1027 uint32_t exp, man; 1028 1029 /* exponent = 14 - floor(log2(coeff)) */ 1030 for (exp = 31; exp > 0; exp--) 1031 if (coeff & (1 << exp)) 1032 break; 1033 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1034 1035 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1036 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1037 1038 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1039 *exponent = exp - 16; 1040 #undef COEFF_SCALE_SHIFT 1041 } 1042 1043 PUBLIC void 1044 athn_reset_key(struct athn_softc *sc, int entry) 1045 { 1046 1047 /* 1048 * NB: Key cache registers access special memory area that requires 1049 * two 32-bit writes to actually update the values in the internal 1050 * memory. Consequently, writes must be grouped by pair. 1051 */ 1052 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1053 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1054 1055 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1056 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1057 1058 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1059 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1060 1061 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1062 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1063 1064 AR_WRITE_BARRIER(sc); 1065 } 1066 1067 #ifdef notyet 1068 Static int 1069 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1070 struct ieee80211_key *k) 1071 { 1072 struct athn_softc *sc = ic->ic_ifp->if_softc; 1073 const uint8_t *txmic, *rxmic, *key, *addr; 1074 uintptr_t entry, micentry; 1075 uint32_t type, lo, hi; 1076 1077 switch (k->k_cipher) { 1078 case IEEE80211_CIPHER_WEP40: 1079 type = AR_KEYTABLE_TYPE_40; 1080 break; 1081 case IEEE80211_CIPHER_WEP104: 1082 type = AR_KEYTABLE_TYPE_104; 1083 break; 1084 case IEEE80211_CIPHER_TKIP: 1085 type = AR_KEYTABLE_TYPE_TKIP; 1086 break; 1087 case IEEE80211_CIPHER_CCMP: 1088 type = AR_KEYTABLE_TYPE_CCM; 1089 break; 1090 default: 1091 /* Fallback to software crypto for other ciphers. */ 1092 return ieee80211_set_key(ic, ni, k); 1093 } 1094 1095 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1096 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1097 else 1098 entry = k->k_id; 1099 k->k_priv = (void *)entry; 1100 1101 /* NB: See note about key cache registers access above. */ 1102 key = k->k_key; 1103 if (type == AR_KEYTABLE_TYPE_TKIP) { 1104 #ifndef IEEE80211_STA_ONLY 1105 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1106 txmic = &key[16]; 1107 rxmic = &key[24]; 1108 } 1109 else 1110 #endif 1111 { 1112 rxmic = &key[16]; 1113 txmic = &key[24]; 1114 } 1115 /* Tx+Rx MIC key is at entry + 64. */ 1116 micentry = entry + 64; 1117 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1118 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1119 1120 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1121 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1122 1123 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1124 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1125 } 1126 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1127 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1128 1129 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1130 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1131 1132 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1133 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1134 1135 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1136 addr = ni->ni_macaddr; 1137 lo = LE_READ_4(&addr[0]); 1138 hi = LE_READ_2(&addr[4]); 1139 lo = lo >> 1 | hi << 31; 1140 hi = hi >> 1; 1141 } 1142 else 1143 lo = hi = 0; 1144 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1145 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1146 AR_WRITE_BARRIER(sc); 1147 return 0; 1148 } 1149 1150 Static void 1151 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1152 struct ieee80211_key *k) 1153 { 1154 struct athn_softc *sc = ic->ic_ifp->if_softc; 1155 uintptr_t entry; 1156 1157 switch (k->k_cipher) { 1158 case IEEE80211_CIPHER_WEP40: 1159 case IEEE80211_CIPHER_WEP104: 1160 case IEEE80211_CIPHER_CCMP: 1161 entry = (uintptr_t)k->k_priv; 1162 athn_reset_key(sc, entry); 1163 break; 1164 case IEEE80211_CIPHER_TKIP: 1165 entry = (uintptr_t)k->k_priv; 1166 athn_reset_key(sc, entry); 1167 athn_reset_key(sc, entry + 64); 1168 break; 1169 default: 1170 /* Fallback to software crypto for other ciphers. */ 1171 ieee80211_delete_key(ic, ni, k); 1172 } 1173 } 1174 #endif /* notyet */ 1175 1176 PUBLIC void 1177 athn_led_init(struct athn_softc *sc) 1178 { 1179 struct athn_ops *ops = &sc->sc_ops; 1180 1181 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1182 /* LED off, active low. */ 1183 athn_set_led(sc, 0); 1184 } 1185 1186 PUBLIC void 1187 athn_set_led(struct athn_softc *sc, int on) 1188 { 1189 struct athn_ops *ops = &sc->sc_ops; 1190 1191 sc->sc_led_state = on; 1192 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1193 } 1194 1195 #ifdef ATHN_BT_COEXISTENCE 1196 Static void 1197 athn_btcoex_init(struct athn_softc *sc) 1198 { 1199 struct athn_ops *ops = &sc->sc_ops; 1200 uint32_t reg; 1201 1202 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1203 /* Connect bt_active to baseband. */ 1204 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1205 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1206 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1207 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1208 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1209 1210 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1211 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1212 AR_GPIO_BTACTIVE_PIN); 1213 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1214 AR_WRITE_BARRIER(sc); 1215 1216 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1217 } 1218 else { /* 3-wire. */ 1219 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1220 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1221 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1222 1223 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1224 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1225 AR_GPIO_BTACTIVE_PIN); 1226 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1227 AR_GPIO_BTPRIORITY_PIN); 1228 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1229 AR_WRITE_BARRIER(sc); 1230 1231 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1232 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1233 } 1234 } 1235 1236 Static void 1237 athn_btcoex_enable(struct athn_softc *sc) 1238 { 1239 struct athn_ops *ops = &sc->sc_ops; 1240 uint32_t reg; 1241 1242 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1243 AR_WRITE(sc, AR_BT_COEX_MODE, 1244 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1245 SM(AR_BT_PRIORITY_TIME, 2) | 1246 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1247 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1248 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1249 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1250 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1251 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1252 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1253 AR_WRITE(sc, AR_BT_COEX_MODE2, 1254 SM(AR_BT_BCN_MISS_THRESH, 50) | 1255 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1256 1257 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1258 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1259 AR_WRITE_BARRIER(sc); 1260 1261 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1262 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1263 1264 } 1265 else { /* 2-wire. */ 1266 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1267 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1268 } 1269 reg = AR_READ(sc, AR_GPIO_PDPU); 1270 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1271 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1272 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1273 AR_WRITE_BARRIER(sc); 1274 1275 /* Disable PCIe Active State Power Management (ASPM). */ 1276 if (sc->sc_disable_aspm != NULL) 1277 sc->sc_disable_aspm(sc); 1278 1279 /* XXX Start periodic timer. */ 1280 } 1281 1282 Static void 1283 athn_btcoex_disable(struct athn_softc *sc) 1284 { 1285 struct athn_ops *ops = &sc->sc_ops; 1286 1287 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1288 1289 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1290 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1291 1292 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1293 AR_WRITE(sc, AR_BT_COEX_MODE, 1294 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1295 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1296 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1297 /* XXX Stop periodic timer. */ 1298 } 1299 AR_WRITE_BARRIER(sc); 1300 /* XXX Restore ASPM setting? */ 1301 } 1302 #endif 1303 1304 Static void 1305 athn_iter_func(void *arg, struct ieee80211_node *ni) 1306 { 1307 struct athn_softc *sc = arg; 1308 struct athn_node *an = (struct athn_node *)ni; 1309 1310 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1311 } 1312 1313 Static void 1314 athn_calib_to(void *arg) 1315 { 1316 extern int ticks; 1317 struct athn_softc *sc = arg; 1318 struct athn_ops *ops = &sc->sc_ops; 1319 struct ieee80211com *ic = &sc->sc_ic; 1320 int s; 1321 1322 s = splnet(); 1323 1324 /* Do periodic (every 4 minutes) PA calibration. */ 1325 if (AR_SREV_9285_11_OR_LATER(sc) && 1326 !AR_SREV_9380_10_OR_LATER(sc) && 1327 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1328 sc->sc_pa_calib_ticks = ticks; 1329 if (AR_SREV_9271(sc)) 1330 ar9271_pa_calib(sc); 1331 else 1332 ar9285_pa_calib(sc); 1333 } 1334 1335 /* Do periodic (every 30 seconds) temperature compensation. */ 1336 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1337 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1338 sc->sc_olpc_ticks = ticks; 1339 ops->olpc_temp_compensation(sc); 1340 } 1341 1342 #ifdef notyet 1343 /* XXX ANI. */ 1344 athn_ani_monitor(sc); 1345 1346 ops->next_calib(sc); 1347 #endif 1348 if (ic->ic_fixed_rate == -1) { 1349 if (ic->ic_opmode == IEEE80211_M_STA) 1350 athn_iter_func(sc, ic->ic_bss); 1351 else 1352 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1353 } 1354 callout_schedule(&sc->sc_calib_to, hz / 2); 1355 splx(s); 1356 } 1357 1358 Static int 1359 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1360 struct ieee80211_channel *extchan) 1361 { 1362 struct athn_ops *ops = &sc->sc_ops; 1363 int error; 1364 1365 if (AR_SREV_9380_10_OR_LATER(sc)) 1366 error = ar9003_init_calib(sc); 1367 else if (AR_SREV_9285_10_OR_LATER(sc)) 1368 error = ar9285_init_calib(sc, curchan, extchan); 1369 else 1370 error = ar5416_init_calib(sc, curchan, extchan); 1371 if (error != 0) 1372 return error; 1373 1374 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1375 /* Do PA calibration. */ 1376 if (AR_SREV_9285_11_OR_LATER(sc)) { 1377 extern int ticks; 1378 sc->sc_pa_calib_ticks = ticks; 1379 if (AR_SREV_9271(sc)) 1380 ar9271_pa_calib(sc); 1381 else 1382 ar9285_pa_calib(sc); 1383 } 1384 /* Do noisefloor calibration. */ 1385 ops->noisefloor_calib(sc); 1386 } 1387 if (AR_SREV_9160_10_OR_LATER(sc)) { 1388 /* Support IQ calibration. */ 1389 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1390 if (AR_SREV_9380_10_OR_LATER(sc)) { 1391 /* Support temperature compensation calibration. */ 1392 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1393 } 1394 else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1395 /* 1396 * ADC gain calibration causes uplink throughput 1397 * drops in HT40 mode on AR9287. 1398 */ 1399 if (!AR_SREV_9287(sc)) { 1400 /* Support ADC gain calibration. */ 1401 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1402 } 1403 /* Support ADC DC offset calibration. */ 1404 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1405 } 1406 } 1407 return 0; 1408 } 1409 1410 /* 1411 * Adaptive noise immunity. 1412 */ 1413 #ifdef notyet 1414 Static int32_t 1415 athn_ani_get_rssi(struct athn_softc *sc) 1416 { 1417 1418 return 0; /* XXX */ 1419 } 1420 #endif /* notyet */ 1421 1422 #ifdef notyet 1423 Static void 1424 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1425 { 1426 struct athn_ani *ani = &sc->sc_ani; 1427 struct athn_ops *ops = &sc->sc_ops; 1428 int32_t rssi; 1429 1430 /* First, raise noise immunity level, up to max. */ 1431 if (ani->noise_immunity_level < 4) { 1432 ani->noise_immunity_level++; 1433 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1434 return; 1435 } 1436 1437 /* Then, raise our spur immunity level, up to max. */ 1438 if (ani->spur_immunity_level < 7) { 1439 ani->spur_immunity_level++; 1440 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1441 return; 1442 } 1443 1444 #ifndef IEEE80211_STA_ONLY 1445 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1446 if (ani->firstep_level < 2) { 1447 ani->firstep_level++; 1448 ops->set_firstep_level(sc, ani->firstep_level); 1449 } 1450 return; 1451 } 1452 #endif 1453 rssi = athn_ani_get_rssi(sc); 1454 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1455 /* 1456 * Beacon RSSI is high, turn off OFDM weak signal detection 1457 * or raise first step level as last resort. 1458 */ 1459 if (ani->ofdm_weak_signal) { 1460 ani->ofdm_weak_signal = 0; 1461 ops->disable_ofdm_weak_signal(sc); 1462 ani->spur_immunity_level = 0; 1463 ops->set_spur_immunity_level(sc, 0); 1464 } 1465 else if (ani->firstep_level < 2) { 1466 ani->firstep_level++; 1467 ops->set_firstep_level(sc, ani->firstep_level); 1468 } 1469 } 1470 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1471 /* 1472 * Beacon RSSI is in mid range, we need OFDM weak signal 1473 * detection but we can raise first step level. 1474 */ 1475 if (!ani->ofdm_weak_signal) { 1476 ani->ofdm_weak_signal = 1; 1477 ops->enable_ofdm_weak_signal(sc); 1478 } 1479 if (ani->firstep_level < 2) { 1480 ani->firstep_level++; 1481 ops->set_firstep_level(sc, ani->firstep_level); 1482 } 1483 } 1484 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1485 /* 1486 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1487 * signal detection and zero first step level to maximize 1488 * CCK sensitivity. 1489 */ 1490 if (ani->ofdm_weak_signal) { 1491 ani->ofdm_weak_signal = 0; 1492 ops->disable_ofdm_weak_signal(sc); 1493 } 1494 if (ani->firstep_level > 0) { 1495 ani->firstep_level = 0; 1496 ops->set_firstep_level(sc, 0); 1497 } 1498 } 1499 } 1500 #endif /* notyet */ 1501 1502 #ifdef notyet 1503 Static void 1504 athn_ani_cck_err_trigger(struct athn_softc *sc) 1505 { 1506 struct athn_ani *ani = &sc->sc_ani; 1507 struct athn_ops *ops = &sc->sc_ops; 1508 int32_t rssi; 1509 1510 /* Raise noise immunity level, up to max. */ 1511 if (ani->noise_immunity_level < 4) { 1512 ani->noise_immunity_level++; 1513 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1514 return; 1515 } 1516 1517 #ifndef IEEE80211_STA_ONLY 1518 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1519 if (ani->firstep_level < 2) { 1520 ani->firstep_level++; 1521 ops->set_firstep_level(sc, ani->firstep_level); 1522 } 1523 return; 1524 } 1525 #endif 1526 rssi = athn_ani_get_rssi(sc); 1527 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1528 /* 1529 * Beacon RSSI is in mid or high range, raise first step 1530 * level. 1531 */ 1532 if (ani->firstep_level < 2) { 1533 ani->firstep_level++; 1534 ops->set_firstep_level(sc, ani->firstep_level); 1535 } 1536 } 1537 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1538 /* 1539 * Beacon RSSI is low, zero first step level to maximize 1540 * CCK sensitivity. 1541 */ 1542 if (ani->firstep_level > 0) { 1543 ani->firstep_level = 0; 1544 ops->set_firstep_level(sc, 0); 1545 } 1546 } 1547 } 1548 #endif /* notyet */ 1549 1550 #ifdef notyet 1551 Static void 1552 athn_ani_lower_immunity(struct athn_softc *sc) 1553 { 1554 struct athn_ani *ani = &sc->sc_ani; 1555 struct athn_ops *ops = &sc->sc_ops; 1556 int32_t rssi; 1557 1558 #ifndef IEEE80211_STA_ONLY 1559 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1560 if (ani->firstep_level > 0) { 1561 ani->firstep_level--; 1562 ops->set_firstep_level(sc, ani->firstep_level); 1563 } 1564 return; 1565 } 1566 #endif 1567 rssi = athn_ani_get_rssi(sc); 1568 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1569 /* 1570 * Beacon RSSI is high, leave OFDM weak signal detection 1571 * off or it may oscillate. 1572 */ 1573 } 1574 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1575 /* 1576 * Beacon RSSI is in mid range, turn on OFDM weak signal 1577 * detection or lower first step level. 1578 */ 1579 if (!ani->ofdm_weak_signal) { 1580 ani->ofdm_weak_signal = 1; 1581 ops->enable_ofdm_weak_signal(sc); 1582 return; 1583 } 1584 if (ani->firstep_level > 0) { 1585 ani->firstep_level--; 1586 ops->set_firstep_level(sc, ani->firstep_level); 1587 return; 1588 } 1589 } 1590 else { 1591 /* Beacon RSSI is low, lower first step level. */ 1592 if (ani->firstep_level > 0) { 1593 ani->firstep_level--; 1594 ops->set_firstep_level(sc, ani->firstep_level); 1595 return; 1596 } 1597 } 1598 /* 1599 * Lower spur immunity level down to zero, or if all else fails, 1600 * lower noise immunity level down to zero. 1601 */ 1602 if (ani->spur_immunity_level > 0) { 1603 ani->spur_immunity_level--; 1604 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1605 } 1606 else if (ani->noise_immunity_level > 0) { 1607 ani->noise_immunity_level--; 1608 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1609 } 1610 } 1611 #endif /* notyet */ 1612 1613 #ifdef notyet 1614 Static void 1615 athn_ani_restart(struct athn_softc *sc) 1616 { 1617 struct athn_ani *ani = &sc->sc_ani; 1618 1619 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1620 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1621 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1622 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1623 AR_WRITE_BARRIER(sc); 1624 1625 ani->listen_time = 0; 1626 ani->ofdm_phy_err_count = 0; 1627 ani->cck_phy_err_count = 0; 1628 } 1629 #endif /* notyet */ 1630 1631 #ifdef notyet 1632 Static void 1633 athn_ani_monitor(struct athn_softc *sc) 1634 { 1635 struct athn_ani *ani = &sc->sc_ani; 1636 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1637 int32_t cycdelta, txfdelta, rxfdelta; 1638 int32_t listen_time; 1639 1640 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1641 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1642 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1643 1644 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1645 cycdelta = cyccnt - ani->cyccnt; 1646 txfdelta = txfcnt - ani->txfcnt; 1647 rxfdelta = rxfcnt - ani->rxfcnt; 1648 1649 listen_time = (cycdelta - txfdelta - rxfdelta) / 1650 (athn_clock_rate(sc) * 1000); 1651 } 1652 else 1653 listen_time = 0; 1654 1655 ani->cyccnt = cyccnt; 1656 ani->txfcnt = txfcnt; 1657 ani->rxfcnt = rxfcnt; 1658 1659 if (listen_time < 0) { 1660 athn_ani_restart(sc); 1661 return; 1662 } 1663 ani->listen_time += listen_time; 1664 1665 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1666 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1667 1668 if (phy1 < ani->ofdm_phy_err_base) { 1669 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1670 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1671 } 1672 if (phy2 < ani->cck_phy_err_base) { 1673 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1674 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1675 } 1676 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1677 AR_WRITE_BARRIER(sc); 1678 return; 1679 } 1680 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1681 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1682 1683 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1684 /* Check to see if we need to lower immunity. */ 1685 if (ani->ofdm_phy_err_count <= 1686 ani->listen_time * ani->ofdm_trig_low / 1000 && 1687 ani->cck_phy_err_count <= 1688 ani->listen_time * ani->cck_trig_low / 1000) 1689 athn_ani_lower_immunity(sc); 1690 athn_ani_restart(sc); 1691 1692 } 1693 else if (ani->listen_time > ATHN_ANI_PERIOD) { 1694 /* Check to see if we need to raise immunity. */ 1695 if (ani->ofdm_phy_err_count > 1696 ani->listen_time * ani->ofdm_trig_high / 1000) { 1697 athn_ani_ofdm_err_trigger(sc); 1698 athn_ani_restart(sc); 1699 } 1700 else if (ani->cck_phy_err_count > 1701 ani->listen_time * ani->cck_trig_high / 1000) { 1702 athn_ani_cck_err_trigger(sc); 1703 athn_ani_restart(sc); 1704 } 1705 } 1706 } 1707 #endif /* notyet */ 1708 1709 PUBLIC uint8_t 1710 athn_chan2fbin(struct ieee80211_channel *c) 1711 { 1712 1713 if (IEEE80211_IS_CHAN_2GHZ(c)) 1714 return c->ic_freq - 2300; 1715 else 1716 return (c->ic_freq - 4800) / 5; 1717 } 1718 1719 PUBLIC int 1720 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1721 { 1722 1723 if (x1 == x2) /* Prevents division by zero. */ 1724 return y1; 1725 /* Linear interpolation. */ 1726 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1727 } 1728 1729 PUBLIC void 1730 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1731 int *lo, int *hi) 1732 { 1733 int i; 1734 1735 for (i = 0; i < npiers; i++) 1736 if (pierfreq[i] == AR_BCHAN_UNUSED || 1737 pierfreq[i] > fbin) 1738 break; 1739 *hi = i; 1740 *lo = *hi - 1; 1741 if (*lo == -1) 1742 *lo = *hi; 1743 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1744 *hi = *lo; 1745 } 1746 1747 Static void 1748 athn_init_dma(struct athn_softc *sc) 1749 { 1750 uint32_t reg; 1751 1752 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1753 /* Set AHB not to do cacheline prefetches. */ 1754 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1755 } 1756 reg = AR_READ(sc, AR_TXCFG); 1757 /* Let MAC DMA reads be in 128-byte chunks. */ 1758 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1759 1760 /* Set initial Tx trigger level. */ 1761 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1762 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1763 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1764 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1765 AR_WRITE(sc, AR_TXCFG, reg); 1766 1767 /* Let MAC DMA writes be in 128-byte chunks. */ 1768 reg = AR_READ(sc, AR_RXCFG); 1769 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1770 AR_WRITE(sc, AR_RXCFG, reg); 1771 1772 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1773 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1774 1775 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1776 if (AR_SREV_9285(sc)) { 1777 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1778 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1779 } 1780 else if (!AR_SREV_9271(sc)) { 1781 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1782 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1783 } 1784 AR_WRITE_BARRIER(sc); 1785 1786 /* Reset Tx status ring. */ 1787 if (AR_SREV_9380_10_OR_LATER(sc)) 1788 ar9003_reset_txsring(sc); 1789 } 1790 1791 PUBLIC void 1792 athn_inc_tx_trigger_level(struct athn_softc *sc) 1793 { 1794 uint32_t reg, ftrig; 1795 1796 reg = AR_READ(sc, AR_TXCFG); 1797 ftrig = MS(reg, AR_TXCFG_FTRIG); 1798 /* 1799 * NB: The AR9285 and all single-stream parts have an issue that 1800 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1801 */ 1802 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1803 return; /* Already at max. */ 1804 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1805 AR_WRITE(sc, AR_TXCFG, reg); 1806 AR_WRITE_BARRIER(sc); 1807 } 1808 1809 PUBLIC int 1810 athn_stop_rx_dma(struct athn_softc *sc) 1811 { 1812 int ntries; 1813 1814 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1815 /* Wait for Rx enable bit to go low. */ 1816 for (ntries = 0; ntries < 100; ntries++) { 1817 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1818 return 0; 1819 DELAY(100); 1820 } 1821 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1822 return ETIMEDOUT; 1823 } 1824 1825 #ifdef unused 1826 Static int 1827 athn_rx_abort(struct athn_softc *sc) 1828 { 1829 int ntries; 1830 1831 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1832 for (ntries = 0; ntries < 1000; ntries++) { 1833 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1834 return 0; 1835 DELAY(10); 1836 } 1837 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1838 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1839 AR_WRITE_BARRIER(sc); 1840 return ETIMEDOUT; 1841 } 1842 #endif /* unused */ 1843 1844 Static void 1845 athn_tx_reclaim(struct athn_softc *sc, int qid) 1846 { 1847 struct athn_txq *txq = &sc->sc_txq[qid]; 1848 struct athn_tx_buf *bf; 1849 1850 /* Reclaim all buffers queued in the specified Tx queue. */ 1851 /* NB: Tx DMA must be stopped. */ 1852 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1853 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1854 1855 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1856 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1857 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1858 m_freem(bf->bf_m); 1859 bf->bf_m = NULL; 1860 bf->bf_ni = NULL; /* Nodes already freed! */ 1861 1862 /* Link Tx buffer back to global free list. */ 1863 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1864 } 1865 } 1866 1867 PUBLIC int 1868 athn_tx_pending(struct athn_softc *sc, int qid) 1869 { 1870 1871 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1872 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1873 } 1874 1875 PUBLIC void 1876 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1877 { 1878 uint32_t tsflo; 1879 int ntries, i; 1880 1881 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1882 for (ntries = 0; ntries < 40; ntries++) { 1883 if (!athn_tx_pending(sc, qid)) 1884 break; 1885 DELAY(100); 1886 } 1887 if (ntries == 40) { 1888 for (i = 0; i < 2; i++) { 1889 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1890 AR_WRITE(sc, AR_QUIET2, 1891 SM(AR_QUIET2_QUIET_DUR, 10)); 1892 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1893 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1894 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1895 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1896 break; 1897 } 1898 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1899 AR_WRITE_BARRIER(sc); 1900 DELAY(200); 1901 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1902 AR_WRITE_BARRIER(sc); 1903 1904 for (ntries = 0; ntries < 40; ntries++) { 1905 if (!athn_tx_pending(sc, qid)) 1906 break; 1907 DELAY(100); 1908 } 1909 1910 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1911 } 1912 AR_WRITE(sc, AR_Q_TXD, 0); 1913 AR_WRITE_BARRIER(sc); 1914 } 1915 1916 PUBLIC int 1917 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1918 { 1919 #define divround(a, b) (((a) + (b) - 1) / (b)) 1920 int txtime; 1921 1922 /* XXX HT. */ 1923 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1924 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1925 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1926 txtime = 16 + 4 + 4 * txtime + 16; 1927 } 1928 else { 1929 txtime = divround(16 * len, athn_rates[ridx].rate); 1930 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1931 txtime += 72 + 24; 1932 else 1933 txtime += 144 + 48; 1934 txtime += 10; /* 10us SIFS. */ 1935 } 1936 return txtime; 1937 #undef divround 1938 } 1939 1940 PUBLIC void 1941 athn_init_tx_queues(struct athn_softc *sc) 1942 { 1943 int qid; 1944 1945 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1946 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1947 sc->sc_txq[qid].lastds = NULL; 1948 sc->sc_txq[qid].wait = NULL; 1949 sc->sc_txq[qid].queued = 0; 1950 1951 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1952 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1953 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1954 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1955 AR_WRITE(sc, AR_QMISC(qid), 1956 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1957 AR_WRITE(sc, AR_DMISC(qid), 1958 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1959 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1960 } 1961 1962 /* Init beacon queue. */ 1963 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1964 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1965 AR_Q_MISC_CBR_INCR_DIS1); 1966 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1967 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1968 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1969 AR_D_MISC_BEACON_USE | 1970 AR_D_MISC_POST_FR_BKOFF_DIS); 1971 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1972 SM(AR_D_LCL_IFS_CWMIN, 0) | 1973 SM(AR_D_LCL_IFS_CWMAX, 0) | 1974 SM(AR_D_LCL_IFS_AIFS, 1)); 1975 1976 /* Init CAB (Content After Beacon) queue. */ 1977 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1978 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1979 AR_Q_MISC_CBR_INCR_DIS0); 1980 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1981 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1982 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1983 1984 /* Init PS-Poll queue. */ 1985 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1986 AR_Q_MISC_CBR_INCR_DIS1); 1987 1988 /* Init UAPSD queue. */ 1989 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1990 AR_D_MISC_POST_FR_BKOFF_DIS); 1991 1992 if (AR_SREV_9380_10_OR_LATER(sc)) { 1993 /* Enable MAC descriptor CRC check. */ 1994 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1995 } 1996 /* Enable DESC interrupts for all Tx queues. */ 1997 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1998 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1999 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 2000 AR_WRITE_BARRIER(sc); 2001 } 2002 2003 PUBLIC void 2004 athn_set_sta_timers(struct athn_softc *sc) 2005 { 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 uint32_t tsfhi, tsflo, tsftu, reg; 2008 uint32_t intval, next_tbtt, next_dtim; 2009 int dtim_period, rem_dtim_count; 2010 2011 tsfhi = AR_READ(sc, AR_TSF_U32); 2012 tsflo = AR_READ(sc, AR_TSF_L32); 2013 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 2014 2015 /* Beacon interval in TU. */ 2016 intval = ic->ic_bss->ni_intval; 2017 2018 next_tbtt = roundup(tsftu, intval); 2019 #ifdef notyet 2020 dtim_period = ic->ic_dtim_period; 2021 if (dtim_period <= 0) 2022 #endif 2023 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 2024 2025 #ifdef notyet 2026 int dtim_count = ic->ic_dtim_count; 2027 if (dtim_count >= dtim_period) /* Should not happen. */ 2028 dtim_count = 0; /* Assume last TIM was a DTIM. */ 2029 #endif 2030 2031 /* Compute number of remaining TIMs until next DTIM. */ 2032 rem_dtim_count = 0; /* XXX */ 2033 next_dtim = next_tbtt + rem_dtim_count * intval; 2034 2035 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2036 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2037 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2038 2039 /* 2040 * Set the number of consecutive beacons to miss before raising 2041 * a BMISS interrupt to 10. 2042 */ 2043 reg = AR_READ(sc, AR_RSSI_THR); 2044 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2045 AR_WRITE(sc, AR_RSSI_THR, reg); 2046 2047 AR_WRITE(sc, AR_NEXT_DTIM, 2048 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2049 AR_WRITE(sc, AR_NEXT_TIM, 2050 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2051 2052 /* CAB timeout is in 1/8 TU. */ 2053 AR_WRITE(sc, AR_SLEEP1, 2054 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2055 AR_SLEEP1_ASSUME_DTIM); 2056 AR_WRITE(sc, AR_SLEEP2, 2057 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2058 2059 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2060 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2061 2062 AR_SETBITS(sc, AR_TIMER_MODE, 2063 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2064 2065 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2066 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2067 2068 AR_WRITE_BARRIER(sc); 2069 } 2070 2071 #ifndef IEEE80211_STA_ONLY 2072 PUBLIC void 2073 athn_set_hostap_timers(struct athn_softc *sc) 2074 { 2075 struct ieee80211com *ic = &sc->sc_ic; 2076 uint32_t intval, next_tbtt; 2077 2078 /* Beacon interval in TU. */ 2079 intval = ic->ic_bss->ni_intval; 2080 next_tbtt = intval; 2081 2082 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2083 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2084 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2085 AR_WRITE(sc, AR_NEXT_CFP, 2086 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2087 2088 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2089 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2090 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2091 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2092 2093 AR_WRITE(sc, AR_TIMER_MODE, 2094 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2095 2096 AR_WRITE_BARRIER(sc); 2097 } 2098 #endif 2099 2100 PUBLIC void 2101 athn_set_opmode(struct athn_softc *sc) 2102 { 2103 uint32_t reg; 2104 2105 switch (sc->sc_ic.ic_opmode) { 2106 #ifndef IEEE80211_STA_ONLY 2107 case IEEE80211_M_HOSTAP: 2108 reg = AR_READ(sc, AR_STA_ID1); 2109 reg &= ~AR_STA_ID1_ADHOC; 2110 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2111 AR_WRITE(sc, AR_STA_ID1, reg); 2112 2113 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2114 break; 2115 case IEEE80211_M_IBSS: 2116 case IEEE80211_M_AHDEMO: 2117 reg = AR_READ(sc, AR_STA_ID1); 2118 reg &= ~AR_STA_ID1_STA_AP; 2119 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2120 AR_WRITE(sc, AR_STA_ID1, reg); 2121 2122 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2123 break; 2124 #endif 2125 default: 2126 reg = AR_READ(sc, AR_STA_ID1); 2127 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2128 reg |= AR_STA_ID1_KSRCH_MODE; 2129 AR_WRITE(sc, AR_STA_ID1, reg); 2130 break; 2131 } 2132 AR_WRITE_BARRIER(sc); 2133 } 2134 2135 PUBLIC void 2136 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2137 { 2138 const uint8_t *bssid = ni->ni_bssid; 2139 2140 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2141 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2142 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2143 AR_WRITE_BARRIER(sc); 2144 } 2145 2146 Static void 2147 athn_enable_interrupts(struct athn_softc *sc) 2148 { 2149 uint32_t mask2; 2150 2151 athn_disable_interrupts(sc); /* XXX */ 2152 2153 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2154 2155 mask2 = AR_READ(sc, AR_IMR_S2); 2156 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2157 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2158 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2159 AR_WRITE(sc, AR_IMR_S2, mask2); 2160 2161 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2162 2163 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2164 2165 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2166 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2167 2168 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2169 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2170 AR_WRITE_BARRIER(sc); 2171 } 2172 2173 Static void 2174 athn_disable_interrupts(struct athn_softc *sc) 2175 { 2176 2177 AR_WRITE(sc, AR_IER, 0); 2178 (void)AR_READ(sc, AR_IER); 2179 2180 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2181 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2182 2183 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2184 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2185 2186 AR_WRITE(sc, AR_IMR, 0); 2187 2188 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2189 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2190 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2191 2192 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2193 AR_WRITE_BARRIER(sc); 2194 } 2195 2196 Static void 2197 athn_init_qos(struct athn_softc *sc) 2198 { 2199 2200 /* Initialize QoS settings. */ 2201 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2202 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2203 AR_WRITE(sc, AR_QOS_NO_ACK, 2204 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2205 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2206 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2207 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2208 /* Initialize TXOP for all TIDs. */ 2209 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2210 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2211 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2212 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2213 AR_WRITE_BARRIER(sc); 2214 } 2215 2216 PUBLIC int 2217 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2218 struct ieee80211_channel *extchan, int init) 2219 { 2220 struct ieee80211com *ic = &sc->sc_ic; 2221 struct athn_ops *ops = &sc->sc_ops; 2222 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2223 int i, error; 2224 2225 /* XXX not if already awake */ 2226 if ((error = athn_set_power_awake(sc)) != 0) { 2227 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2228 return error; 2229 } 2230 2231 /* Preserve the antenna on a channel switch. */ 2232 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2233 def_ant = 1; 2234 /* Preserve other registers. */ 2235 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2236 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2237 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2238 AR_CFG_LED_BLINK_SLOW); 2239 2240 /* Mark PHY as inactive. */ 2241 ops->disable_phy(sc); 2242 2243 if (init && AR_SREV_9271(sc)) { 2244 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2245 AR9271_RADIO_RF_RST); 2246 DELAY(50); 2247 } 2248 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2249 /* Save TSF before it gets cleared. */ 2250 tsfhi = AR_READ(sc, AR_TSF_U32); 2251 tsflo = AR_READ(sc, AR_TSF_L32); 2252 2253 /* NB: RTC reset clears TSF. */ 2254 error = athn_reset_power_on(sc); 2255 } 2256 else { 2257 tsfhi = tsflo = 0; /* XXX: gcc */ 2258 error = athn_reset(sc, 0); 2259 } 2260 if (error != 0) { 2261 aprint_error_dev(sc->sc_dev, 2262 "could not reset chip (error=%d)\n", error); 2263 return error; 2264 } 2265 2266 /* XXX not if already awake */ 2267 if ((error = athn_set_power_awake(sc)) != 0) { 2268 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2269 return error; 2270 } 2271 2272 athn_init_pll(sc, curchan); 2273 ops->set_rf_mode(sc, curchan); 2274 2275 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2276 /* Check that the radio is not disabled by hardware switch. */ 2277 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2278 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2279 reg = !reg; 2280 if (!reg) { 2281 aprint_error_dev(sc->sc_dev, 2282 "radio is disabled by hardware switch\n"); 2283 return EPERM; 2284 } 2285 } 2286 if (init && AR_SREV_9271(sc)) { 2287 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2288 AR9271_GATE_MAC_CTL); 2289 DELAY(50); 2290 } 2291 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2292 /* Restore TSF if it got cleared. */ 2293 AR_WRITE(sc, AR_TSF_L32, tsflo); 2294 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2295 } 2296 2297 if (AR_SREV_9280_10_OR_LATER(sc)) 2298 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2299 2300 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2301 ar9287_1_3_enable_async_fifo(sc); 2302 2303 /* Write init values to hardware. */ 2304 ops->hw_init(sc, curchan, extchan); 2305 2306 /* 2307 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2308 * management frames using CCMP. 2309 */ 2310 if (AR_SREV_9280_20_OR_LATER(sc)) { 2311 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2312 /* Do not mask the subtype field in management frames. */ 2313 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2314 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2315 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2316 IEEE80211_FC1_MORE_DATA)); 2317 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2318 } 2319 else if (AR_SREV_9160_10_OR_LATER(sc)) { 2320 /* Disable hardware crypto for management frames. */ 2321 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2322 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2323 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2324 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2325 } 2326 2327 if (ic->ic_curmode != IEEE80211_MODE_11B) 2328 ops->set_delta_slope(sc, curchan, extchan); 2329 2330 ops->spur_mitigate(sc, curchan, extchan); 2331 ops->init_from_rom(sc, curchan, extchan); 2332 2333 /* XXX */ 2334 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2335 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2336 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2337 2338 athn_set_opmode(sc); 2339 2340 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2341 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2342 2343 /* Restore previous antenna. */ 2344 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2345 2346 AR_WRITE(sc, AR_BSS_ID0, 0); 2347 AR_WRITE(sc, AR_BSS_ID1, 0); 2348 2349 AR_WRITE(sc, AR_ISR, 0xffffffff); 2350 2351 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2352 2353 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2354 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2355 return error; 2356 } 2357 sc->sc_curchan = curchan; 2358 sc->sc_curchanext = extchan; 2359 2360 for (i = 0; i < AR_NUM_DCU; i++) 2361 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2362 2363 athn_init_tx_queues(sc); 2364 2365 /* Initialize interrupt mask. */ 2366 sc->sc_imask = 2367 AR_IMR_TXDESC | AR_IMR_TXEOL | 2368 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2369 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2370 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2371 if (AR_SREV_9380_10_OR_LATER(sc)) 2372 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2373 #ifndef IEEE80211_STA_ONLY 2374 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2375 sc->sc_imask |= AR_IMR_MIB; 2376 #endif 2377 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2378 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2379 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2380 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2381 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2382 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2383 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2384 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2385 if (AR_SREV_9380_10_OR_LATER(sc)) { 2386 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2387 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2388 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2389 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2390 } 2391 2392 athn_init_qos(sc); 2393 2394 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2395 2396 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2397 ar9287_1_3_setup_async_fifo(sc); 2398 2399 /* Disable sequence number generation in hardware. */ 2400 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2401 2402 athn_init_dma(sc); 2403 2404 /* Program observation bus to see MAC interrupts. */ 2405 AR_WRITE(sc, sc->sc_obs_off, 8); 2406 2407 /* Setup Rx interrupt mitigation. */ 2408 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2409 2410 ops->init_baseband(sc); 2411 2412 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2413 aprint_error_dev(sc->sc_dev, 2414 "could not initialize calibration\n"); 2415 return error; 2416 } 2417 2418 ops->set_rxchains(sc); 2419 2420 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2421 2422 if (sc->sc_flags & ATHN_FLAG_USB) { 2423 if (AR_SREV_9271(sc)) 2424 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2425 else 2426 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2427 } 2428 #if BYTE_ORDER == BIG_ENDIAN 2429 else { 2430 /* Default is LE, turn on swapping for BE. */ 2431 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2432 } 2433 #endif 2434 AR_WRITE_BARRIER(sc); 2435 2436 return 0; 2437 } 2438 2439 Static struct ieee80211_node * 2440 athn_node_alloc(struct ieee80211_node_table *ntp) 2441 { 2442 2443 return malloc(sizeof(struct athn_node), M_DEVBUF, 2444 M_NOWAIT | M_ZERO); 2445 } 2446 2447 Static void 2448 athn_newassoc(struct ieee80211_node *ni, int isnew) 2449 { 2450 struct ieee80211com *ic = ni->ni_ic; 2451 struct athn_softc *sc = ic->ic_ifp->if_softc; 2452 struct athn_node *an = (void *)ni; 2453 struct ieee80211_rateset *rs = &ni->ni_rates; 2454 uint8_t rate; 2455 int ridx, i, j; 2456 2457 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2458 /* Start at lowest available bit-rate, AMRR will raise. */ 2459 ni->ni_txrate = 0; 2460 2461 for (i = 0; i < rs->rs_nrates; i++) { 2462 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2463 2464 /* Map 802.11 rate to HW rate index. */ 2465 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2466 if (athn_rates[ridx].rate == rate) 2467 break; 2468 an->ridx[i] = ridx; 2469 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2470 2471 /* Compute fallback rate for retries. */ 2472 an->fallback[i] = i; 2473 for (j = i - 1; j >= 0; j--) { 2474 if (athn_rates[an->ridx[j]].phy == 2475 athn_rates[an->ridx[i]].phy) { 2476 an->fallback[i] = j; 2477 break; 2478 } 2479 } 2480 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2481 i, an->fallback[i]); 2482 } 2483 } 2484 2485 Static int 2486 athn_media_change(struct ifnet *ifp) 2487 { 2488 struct athn_softc *sc = ifp->if_softc; 2489 struct ieee80211com *ic = &sc->sc_ic; 2490 uint8_t rate, ridx; 2491 int error; 2492 2493 error = ieee80211_media_change(ifp); 2494 if (error != ENETRESET) 2495 return error; 2496 2497 if (ic->ic_fixed_rate != -1) { 2498 rate = ic->ic_sup_rates[ic->ic_curmode]. 2499 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2500 /* Map 802.11 rate to HW rate index. */ 2501 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2502 if (athn_rates[ridx].rate == rate) 2503 break; 2504 sc->sc_fixed_ridx = ridx; 2505 } 2506 if (IS_UP_AND_RUNNING(ifp)) { 2507 athn_stop(ifp, 0); 2508 error = athn_init(ifp); 2509 } 2510 return error; 2511 } 2512 2513 Static void 2514 athn_next_scan(void *arg) 2515 { 2516 struct athn_softc *sc = arg; 2517 struct ieee80211com *ic = &sc->sc_ic; 2518 int s; 2519 2520 s = splnet(); 2521 if (ic->ic_state == IEEE80211_S_SCAN) 2522 ieee80211_next_scan(ic); 2523 splx(s); 2524 } 2525 2526 Static int 2527 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2528 { 2529 struct ifnet *ifp = ic->ic_ifp; 2530 struct athn_softc *sc = ifp->if_softc; 2531 uint32_t reg; 2532 int error; 2533 2534 callout_stop(&sc->sc_calib_to); 2535 2536 switch (nstate) { 2537 case IEEE80211_S_INIT: 2538 athn_set_led(sc, 0); 2539 break; 2540 case IEEE80211_S_SCAN: 2541 /* Make the LED blink while scanning. */ 2542 athn_set_led(sc, !sc->sc_led_state); 2543 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2544 if (error != 0) 2545 return error; 2546 callout_schedule(&sc->sc_scan_to, hz / 5); 2547 break; 2548 case IEEE80211_S_AUTH: 2549 athn_set_led(sc, 0); 2550 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2551 if (error != 0) 2552 return error; 2553 break; 2554 case IEEE80211_S_ASSOC: 2555 break; 2556 case IEEE80211_S_RUN: 2557 athn_set_led(sc, 1); 2558 2559 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2560 break; 2561 2562 /* Fake a join to initialize the Tx rate. */ 2563 athn_newassoc(ic->ic_bss, 1); 2564 2565 athn_set_bss(sc, ic->ic_bss); 2566 athn_disable_interrupts(sc); 2567 #ifndef IEEE80211_STA_ONLY 2568 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2569 athn_set_hostap_timers(sc); 2570 /* Enable software beacon alert interrupts. */ 2571 sc->sc_imask |= AR_IMR_SWBA; 2572 } 2573 else 2574 #endif 2575 { 2576 athn_set_sta_timers(sc); 2577 /* Enable beacon miss interrupts. */ 2578 sc->sc_imask |= AR_IMR_BMISS; 2579 2580 /* Stop receiving beacons from other BSS. */ 2581 reg = AR_READ(sc, AR_RX_FILTER); 2582 reg = (reg & ~AR_RX_FILTER_BEACON) | 2583 AR_RX_FILTER_MYBEACON; 2584 AR_WRITE(sc, AR_RX_FILTER, reg); 2585 AR_WRITE_BARRIER(sc); 2586 } 2587 athn_enable_interrupts(sc); 2588 2589 if (sc->sc_sup_calib_mask != 0) { 2590 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2591 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2592 /* ops->do_calib(sc); */ 2593 } 2594 /* XXX Start ANI. */ 2595 2596 callout_schedule(&sc->sc_calib_to, hz / 2); 2597 break; 2598 } 2599 2600 return sc->sc_newstate(ic, nstate, arg); 2601 } 2602 2603 #ifdef notyet_edca 2604 PUBLIC void 2605 athn_updateedca(struct ieee80211com *ic) 2606 { 2607 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2608 struct athn_softc *sc = ic->ic_ifp->if_softc; 2609 const struct ieee80211_edca_ac_params *ac; 2610 int aci, qid; 2611 2612 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2613 ac = &ic->ic_edca_ac[aci]; 2614 qid = athn_ac2qid[aci]; 2615 2616 AR_WRITE(sc, AR_DLCL_IFS(qid), 2617 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2618 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2619 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2620 if (ac->ac_txoplimit != 0) { 2621 AR_WRITE(sc, AR_DCHNTIME(qid), 2622 SM(AR_D_CHNTIME_DUR, 2623 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2624 AR_D_CHNTIME_EN); 2625 } 2626 else 2627 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2628 } 2629 AR_WRITE_BARRIER(sc); 2630 #undef ATHN_EXP2 2631 } 2632 #endif /* notyet_edca */ 2633 2634 Static int 2635 athn_clock_rate(struct athn_softc *sc) 2636 { 2637 struct ieee80211com *ic = &sc->sc_ic; 2638 int clockrate; /* MHz. */ 2639 2640 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2641 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2642 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2643 else 2644 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2645 } 2646 else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2647 clockrate = AR_CLOCK_RATE_CCK; 2648 } 2649 else 2650 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2651 #ifndef IEEE80211_NO_HT 2652 if (sc->sc_curchanext != NULL) 2653 clockrate *= 2; 2654 #endif 2655 return clockrate; 2656 } 2657 2658 PUBLIC void 2659 athn_updateslot(struct ifnet *ifp) 2660 { 2661 struct athn_softc *sc = ifp->if_softc; 2662 struct ieee80211com *ic = &sc->sc_ic; 2663 int slot; 2664 2665 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2666 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2667 AR_WRITE_BARRIER(sc); 2668 } 2669 2670 Static void 2671 athn_start(struct ifnet *ifp) 2672 { 2673 struct athn_softc *sc = ifp->if_softc; 2674 struct ieee80211com *ic = &sc->sc_ic; 2675 struct ether_header *eh; 2676 struct ieee80211_node *ni; 2677 struct mbuf *m; 2678 2679 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2680 || !device_is_active(sc->sc_dev)) 2681 return; 2682 2683 for (;;) { 2684 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2685 ifp->if_flags |= IFF_OACTIVE; 2686 break; 2687 } 2688 /* Send pending management frames first. */ 2689 IF_DEQUEUE(&ic->ic_mgtq, m); 2690 if (m != NULL) { 2691 ni = M_GETCTX(m, struct ieee80211_node *); 2692 goto sendit; 2693 } 2694 if (ic->ic_state != IEEE80211_S_RUN) 2695 break; 2696 2697 /* Encapsulate and send data frames. */ 2698 IFQ_DEQUEUE(&ifp->if_snd, m); 2699 if (m == NULL) 2700 break; 2701 2702 if (m->m_len < (int)sizeof(*eh) && 2703 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2704 ifp->if_oerrors++; 2705 continue; 2706 } 2707 eh = mtod(m, struct ether_header *); 2708 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2709 if (ni == NULL) { 2710 m_freem(m); 2711 ifp->if_oerrors++; 2712 continue; 2713 } 2714 2715 bpf_mtap(ifp, m, BPF_D_OUT); 2716 2717 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2718 continue; 2719 sendit: 2720 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2721 2722 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2723 ieee80211_free_node(ni); 2724 ifp->if_oerrors++; 2725 continue; 2726 } 2727 2728 sc->sc_tx_timer = 5; 2729 ifp->if_timer = 1; 2730 } 2731 } 2732 2733 Static void 2734 athn_watchdog(struct ifnet *ifp) 2735 { 2736 struct athn_softc *sc = ifp->if_softc; 2737 2738 ifp->if_timer = 0; 2739 2740 if (sc->sc_tx_timer > 0) { 2741 if (--sc->sc_tx_timer == 0) { 2742 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2743 /* see athn_init, no need to call athn_stop here */ 2744 /* athn_stop(ifp, 0); */ 2745 (void)athn_init(ifp); 2746 ifp->if_oerrors++; 2747 return; 2748 } 2749 ifp->if_timer = 1; 2750 } 2751 ieee80211_watchdog(&sc->sc_ic); 2752 } 2753 2754 #ifdef notyet 2755 Static void 2756 athn_set_multi(struct athn_softc *sc) 2757 { 2758 struct arpcom *ac = &sc->sc_ic.ic_ac; 2759 struct ifnet *ifp = &ac->ac_if; 2760 struct ether_multi *enm; 2761 struct ether_multistep step; 2762 const uint8_t *addr; 2763 uint32_t val, lo, hi; 2764 uint8_t bit; 2765 2766 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2767 lo = hi = 0xffffffff; 2768 goto done; 2769 } 2770 lo = hi = 0; 2771 ETHER_FIRST_MULTI(step, ac, enm); 2772 while (enm != NULL) { 2773 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2774 ifp->if_flags |= IFF_ALLMULTI; 2775 lo = hi = 0xffffffff; 2776 goto done; 2777 } 2778 addr = enm->enm_addrlo; 2779 /* Calculate the XOR value of all eight 6-bit words. */ 2780 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2781 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2782 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2783 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2784 bit &= 0x3f; 2785 if (bit < 32) 2786 lo |= 1 << bit; 2787 else 2788 hi |= 1 << (bit - 32); 2789 ETHER_NEXT_MULTI(step, enm); 2790 } 2791 done: 2792 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2793 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2794 AR_WRITE_BARRIER(sc); 2795 } 2796 #endif /* notyet */ 2797 2798 Static int 2799 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2800 { 2801 struct athn_softc *sc = ifp->if_softc; 2802 struct ieee80211com *ic = &sc->sc_ic; 2803 int s, error = 0; 2804 2805 s = splnet(); 2806 2807 switch (cmd) { 2808 case SIOCSIFFLAGS: 2809 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2810 break; 2811 2812 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2813 case IFF_UP | IFF_RUNNING: 2814 #ifdef notyet 2815 if (((ifp->if_flags ^ sc->sc_if_flags) & 2816 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2817 /* XXX: setup multi */ 2818 #endif 2819 break; 2820 case IFF_UP: 2821 athn_init(ifp); 2822 break; 2823 2824 case IFF_RUNNING: 2825 athn_stop(ifp, 1); 2826 break; 2827 case 0: 2828 default: 2829 break; 2830 } 2831 sc->sc_if_flags = ifp->if_flags; 2832 break; 2833 2834 case SIOCADDMULTI: 2835 case SIOCDELMULTI: 2836 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2837 /* setup multicast filter, etc */ 2838 #ifdef notyet 2839 athn_set_multi(sc); 2840 #endif 2841 error = 0; 2842 } 2843 break; 2844 2845 case SIOCS80211CHANNEL: 2846 error = ieee80211_ioctl(ic, cmd, data); 2847 if (error == ENETRESET && 2848 ic->ic_opmode == IEEE80211_M_MONITOR) { 2849 if (IS_UP_AND_RUNNING(ifp)) 2850 athn_switch_chan(sc, ic->ic_curchan, NULL); 2851 error = 0; 2852 } 2853 break; 2854 2855 default: 2856 error = ieee80211_ioctl(ic, cmd, data); 2857 } 2858 2859 if (error == ENETRESET) { 2860 error = 0; 2861 if (IS_UP_AND_RUNNING(ifp) && 2862 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2863 athn_stop(ifp, 0); 2864 error = athn_init(ifp); 2865 } 2866 } 2867 2868 splx(s); 2869 return error; 2870 } 2871 2872 Static int 2873 athn_init(struct ifnet *ifp) 2874 { 2875 struct athn_softc *sc = ifp->if_softc; 2876 struct athn_ops *ops = &sc->sc_ops; 2877 struct ieee80211com *ic = &sc->sc_ic; 2878 struct ieee80211_channel *curchan, *extchan; 2879 size_t i; 2880 int error; 2881 2882 KASSERT(!cpu_intr_p()); 2883 2884 if (device_is_active(sc->sc_dev)) { 2885 athn_stop(ifp, 0); /* see athn_watchdog() */ 2886 } else { 2887 short flags = ifp->if_flags; 2888 ifp->if_flags &= ~IFF_UP; 2889 /* avoid recursion in athn_resume */ 2890 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2891 !device_is_active(sc->sc_dev)) { 2892 printf("%s: failed to power up device\n", 2893 device_xname(sc->sc_dev)); 2894 return 0; 2895 } 2896 ifp->if_flags = flags; 2897 } 2898 2899 curchan = ic->ic_curchan; 2900 extchan = NULL; 2901 2902 /* In case a new MAC address has been configured. */ 2903 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2904 2905 #ifdef openbsd_power_management 2906 /* For CardBus, power on the socket. */ 2907 if (sc->sc_enable != NULL) { 2908 if ((error = sc->sc_enable(sc)) != 0) { 2909 aprint_error_dev(sc->sc_dev, 2910 "could not enable device\n"); 2911 goto fail; 2912 } 2913 if ((error = athn_reset_power_on(sc)) != 0) { 2914 aprint_error_dev(sc->sc_dev, 2915 "could not power on device\n"); 2916 goto fail; 2917 } 2918 } 2919 #endif 2920 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2921 athn_config_nonpcie(sc); 2922 else 2923 athn_config_pcie(sc); 2924 2925 /* Reset HW key cache entries. */ 2926 for (i = 0; i < sc->sc_kc_entries; i++) 2927 athn_reset_key(sc, i); 2928 2929 ops->enable_antenna_diversity(sc); 2930 2931 #ifdef ATHN_BT_COEXISTENCE 2932 /* Configure bluetooth coexistence for combo chips. */ 2933 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2934 athn_btcoex_init(sc); 2935 #endif 2936 2937 /* Configure LED. */ 2938 athn_led_init(sc); 2939 2940 /* Configure hardware radio switch. */ 2941 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2942 ops->rfsilent_init(sc); 2943 2944 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2945 aprint_error_dev(sc->sc_dev, 2946 "unable to reset hardware; reset status %d\n", error); 2947 goto fail; 2948 } 2949 2950 /* Enable Rx. */ 2951 athn_rx_start(sc); 2952 2953 /* Enable interrupts. */ 2954 athn_enable_interrupts(sc); 2955 2956 #ifdef ATHN_BT_COEXISTENCE 2957 /* Enable bluetooth coexistence for combo chips. */ 2958 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2959 athn_btcoex_enable(sc); 2960 #endif 2961 2962 ifp->if_flags &= ~IFF_OACTIVE; 2963 ifp->if_flags |= IFF_RUNNING; 2964 2965 #ifdef notyet 2966 if (ic->ic_flags & IEEE80211_F_WEPON) { 2967 /* Configure WEP keys. */ 2968 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2969 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2970 } 2971 #endif 2972 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2973 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2974 else 2975 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2976 2977 return 0; 2978 fail: 2979 athn_stop(ifp, 1); 2980 return error; 2981 } 2982 2983 PUBLIC void 2984 athn_stop(struct ifnet *ifp, int disable) 2985 { 2986 struct athn_softc *sc = ifp->if_softc; 2987 struct ieee80211com *ic = &sc->sc_ic; 2988 int qid; 2989 2990 ifp->if_timer = sc->sc_tx_timer = 0; 2991 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2992 2993 callout_stop(&sc->sc_scan_to); 2994 /* In case we were scanning, release the scan "lock". */ 2995 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2996 2997 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2998 2999 #ifdef ATHN_BT_COEXISTENCE 3000 /* Disable bluetooth coexistence for combo chips. */ 3001 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 3002 athn_btcoex_disable(sc); 3003 #endif 3004 3005 /* Disable interrupts. */ 3006 athn_disable_interrupts(sc); 3007 /* Acknowledge interrupts (avoids interrupt storms). */ 3008 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 3009 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 3010 3011 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3012 athn_stop_tx_dma(sc, qid); 3013 /* XXX call athn_hw_reset if Tx still pending? */ 3014 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 3015 athn_tx_reclaim(sc, qid); 3016 3017 /* Stop Rx. */ 3018 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3019 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 3020 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 3021 AR_WRITE(sc, AR_FILT_OFDM, 0); 3022 AR_WRITE(sc, AR_FILT_CCK, 0); 3023 AR_WRITE_BARRIER(sc); 3024 athn_set_rxfilter(sc, 0); 3025 athn_stop_rx_dma(sc); 3026 3027 athn_reset(sc, 0); 3028 athn_init_pll(sc, NULL); 3029 athn_set_power_awake(sc); 3030 athn_reset(sc, 1); 3031 athn_init_pll(sc, NULL); 3032 3033 athn_set_power_sleep(sc); 3034 3035 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 3036 /* For CardBus, power down the socket. */ 3037 if (disable && sc->sc_disable != NULL) 3038 sc->sc_disable(sc); 3039 #endif 3040 if (disable) 3041 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3042 } 3043 3044 Static void 3045 athn_pmf_wlan_off(device_t self) 3046 { 3047 struct athn_softc *sc = device_private(self); 3048 struct ifnet *ifp = &sc->sc_if; 3049 3050 /* Turn the interface down. */ 3051 ifp->if_flags &= ~IFF_UP; 3052 athn_stop(ifp, 1); 3053 } 3054 3055 PUBLIC void 3056 athn_suspend(struct athn_softc *sc) 3057 { 3058 struct ifnet *ifp = &sc->sc_if; 3059 3060 if (ifp->if_flags & IFF_RUNNING) 3061 athn_stop(ifp, 1); 3062 } 3063 3064 PUBLIC bool 3065 athn_resume(struct athn_softc *sc) 3066 { 3067 struct ifnet *ifp = &sc->sc_if; 3068 3069 if (ifp->if_flags & IFF_UP) 3070 athn_init(ifp); 3071 3072 return true; 3073 } 3074