1 /* $NetBSD: athn.c,v 1.8 2014/02/23 15:29:12 christos Exp $ */ 2 /* $OpenBSD: athn.c,v 1.75 2013/01/14 09:50:31 jsing Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.8 2014/02/23 15:29:12 christos Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 122 #ifdef ATHN_BT_COEXISTENCE 123 Static void athn_btcoex_disable(struct athn_softc *); 124 Static void athn_btcoex_enable(struct athn_softc *); 125 #endif 126 127 #ifdef unused 128 Static int32_t athn_ani_get_rssi(struct athn_softc *); 129 Static int athn_rx_abort(struct athn_softc *); 130 #endif 131 132 #ifdef notyet 133 Static void athn_ani_cck_err_trigger(struct athn_softc *); 134 Static void athn_ani_lower_immunity(struct athn_softc *); 135 Static void athn_ani_monitor(struct athn_softc *); 136 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 137 Static void athn_ani_restart(struct athn_softc *); 138 Static void athn_set_multi(struct athn_softc *); 139 #endif /* notyet */ 140 141 PUBLIC int 142 athn_attach(struct athn_softc *sc) 143 { 144 struct ieee80211com *ic = &sc->sc_ic; 145 struct ifnet *ifp = &sc->sc_if; 146 size_t max_nnodes; 147 int error; 148 149 /* Read hardware revision. */ 150 athn_get_chipid(sc); 151 152 if ((error = athn_reset_power_on(sc)) != 0) { 153 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 154 return error; 155 } 156 157 if ((error = athn_set_power_awake(sc)) != 0) { 158 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 159 return error; 160 } 161 162 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 163 error = ar5416_attach(sc); 164 else if (AR_SREV_9280(sc)) 165 error = ar9280_attach(sc); 166 else if (AR_SREV_9285(sc)) 167 error = ar9285_attach(sc); 168 #if NATHN_USB > 0 169 else if (AR_SREV_9271(sc)) 170 error = ar9285_attach(sc); 171 #endif 172 else if (AR_SREV_9287(sc)) 173 error = ar9287_attach(sc); 174 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 175 error = ar9380_attach(sc); 176 else 177 error = ENOTSUP; 178 if (error != 0) { 179 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 180 return error; 181 } 182 183 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 184 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 185 false); 186 187 /* We can put the chip in sleep state now. */ 188 athn_set_power_sleep(sc); 189 190 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 191 error = sc->sc_ops.dma_alloc(sc); 192 if (error != 0) { 193 aprint_error_dev(sc->sc_dev, 194 "could not allocate DMA resources\n"); 195 return error; 196 } 197 /* Steal one Tx buffer for beacons. */ 198 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 199 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 200 } 201 202 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 203 DPRINTFN(DBG_INIT, sc, 204 "found RF switch connected to GPIO pin %d\n", 205 sc->sc_rfsilent_pin); 206 } 207 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 208 209 /* 210 * In HostAP mode, the number of STAs that we can handle is 211 * limited by the number of entries in the HW key cache. 212 * TKIP keys consume 2 entries in the cache. 213 */ 214 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 215 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 216 if (sc->sc_max_aid != 0) /* we have an override */ 217 ic->ic_max_aid = sc->sc_max_aid; 218 if (ic->ic_max_aid > max_nnodes) 219 ic->ic_max_aid = max_nnodes; 220 221 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 222 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 223 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 224 sc->sc_txchainmask, sc->sc_rxchainmask); 225 226 /* Count the number of bits set (in lowest 3 bits). */ 227 sc->sc_ntxchains = 228 ((sc->sc_txchainmask >> 2) & 1) + 229 ((sc->sc_txchainmask >> 1) & 1) + 230 ((sc->sc_txchainmask >> 0) & 1); 231 sc->sc_nrxchains = 232 ((sc->sc_rxchainmask >> 2) & 1) + 233 ((sc->sc_rxchainmask >> 1) & 1) + 234 ((sc->sc_rxchainmask >> 0) & 1); 235 236 if (AR_SINGLE_CHIP(sc)) { 237 aprint_normal_dev(sc->sc_dev, 238 "Atheros %s\n", athn_get_mac_name(sc)); 239 aprint_verbose_dev(sc->sc_dev, 240 "rev %d (%dT%dR), ROM rev %d, address %s\n", 241 sc->sc_mac_rev, 242 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 243 ether_sprintf(ic->ic_myaddr)); 244 } else { 245 aprint_normal_dev(sc->sc_dev, 246 "Atheros %s, RF %s\n", athn_get_mac_name(sc), 247 athn_get_rf_name(sc)); 248 aprint_verbose_dev(sc->sc_dev, 249 "rev %d (%dT%dR), ROM rev %d, address %s\n", 250 sc->sc_mac_rev, 251 sc->sc_ntxchains, sc->sc_nrxchains, 252 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 253 } 254 255 callout_init(&sc->sc_scan_to, 0); 256 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 257 callout_init(&sc->sc_calib_to, 0); 258 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 259 260 sc->sc_amrr.amrr_min_success_threshold = 1; 261 sc->sc_amrr.amrr_max_success_threshold = 15; 262 263 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 264 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 265 ic->ic_state = IEEE80211_S_INIT; 266 267 /* Set device capabilities. */ 268 ic->ic_caps = 269 IEEE80211_C_WPA | /* 802.11i */ 270 #ifndef IEEE80211_STA_ONLY 271 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 272 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 273 #endif 274 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 275 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 276 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 277 IEEE80211_C_PMGT; /* Power saving supported. */ 278 279 #ifndef IEEE80211_NO_HT 280 if (sc->sc_flags & ATHN_FLAG_11N) { 281 int i, ntxstreams, nrxstreams; 282 283 /* Set HT capabilities. */ 284 ic->ic_htcaps = 285 IEEE80211_HTCAP_SMPS_DIS | 286 IEEE80211_HTCAP_CBW20_40 | 287 IEEE80211_HTCAP_SGI40 | 288 IEEE80211_HTCAP_DSSSCCK40; 289 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 290 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 291 if (AR_SREV_9380_10_OR_LATER(sc)) 292 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 293 if (AR_SREV_9280_10_OR_LATER(sc)) { 294 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 295 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 296 } 297 ntxstreams = sc->sc_ntxchains; 298 nrxstreams = sc->sc_nrxchains; 299 if (!AR_SREV_9380_10_OR_LATER(sc)) { 300 ntxstreams = MIN(ntxstreams, 2); 301 nrxstreams = MIN(nrxstreams, 2); 302 } 303 /* Set supported HT rates. */ 304 for (i = 0; i < nrxstreams; i++) 305 ic->ic_sup_mcs[i] = 0xff; 306 /* Set the "Tx MCS Set Defined" bit. */ 307 ic->ic_sup_mcs[12] |= 0x01; 308 if (ntxstreams != nrxstreams) { 309 /* Set "Tx Rx MCS Set Not Equal" bit. */ 310 ic->ic_sup_mcs[12] |= 0x02; 311 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 312 } 313 } 314 #endif 315 316 /* Set supported rates. */ 317 if (sc->sc_flags & ATHN_FLAG_11G) { 318 ic->ic_sup_rates[IEEE80211_MODE_11B] = 319 ieee80211_std_rateset_11b; 320 ic->ic_sup_rates[IEEE80211_MODE_11G] = 321 ieee80211_std_rateset_11g; 322 } 323 if (sc->sc_flags & ATHN_FLAG_11A) { 324 ic->ic_sup_rates[IEEE80211_MODE_11A] = 325 ieee80211_std_rateset_11a; 326 } 327 328 /* Get the list of authorized/supported channels. */ 329 athn_get_chanlist(sc); 330 331 ifp->if_softc = sc; 332 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 ifp->if_init = athn_init; 334 ifp->if_ioctl = athn_ioctl; 335 ifp->if_start = athn_start; 336 ifp->if_watchdog = athn_watchdog; 337 IFQ_SET_READY(&ifp->if_snd); 338 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 339 340 if_attach(ifp); 341 ieee80211_ifattach(ic); 342 343 ic->ic_node_alloc = athn_node_alloc; 344 ic->ic_newassoc = athn_newassoc; 345 if (ic->ic_updateslot == NULL) 346 ic->ic_updateslot = athn_updateslot; 347 #ifdef notyet_edca 348 ic->ic_updateedca = athn_updateedca; 349 #endif 350 #ifdef notyet 351 ic->ic_set_key = athn_set_key; 352 ic->ic_delete_key = athn_delete_key; 353 #endif 354 355 /* Override 802.11 state transition machine. */ 356 sc->sc_newstate = ic->ic_newstate; 357 ic->ic_newstate = athn_newstate; 358 359 if (sc->sc_media_change == NULL) 360 sc->sc_media_change = athn_media_change; 361 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 362 363 athn_radiotap_attach(sc); 364 return 0; 365 } 366 367 PUBLIC void 368 athn_detach(struct athn_softc *sc) 369 { 370 struct ifnet *ifp = &sc->sc_if; 371 int qid; 372 373 callout_halt(&sc->sc_scan_to, NULL); 374 callout_halt(&sc->sc_calib_to, NULL); 375 376 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 377 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 378 athn_tx_reclaim(sc, qid); 379 380 /* Free Tx/Rx DMA resources. */ 381 sc->sc_ops.dma_free(sc); 382 } 383 /* Free ROM copy. */ 384 if (sc->sc_eep != NULL) { 385 free(sc->sc_eep, M_DEVBUF); 386 sc->sc_eep = NULL; 387 } 388 389 bpf_detach(ifp); 390 ieee80211_ifdetach(&sc->sc_ic); 391 if_detach(ifp); 392 393 callout_destroy(&sc->sc_scan_to); 394 callout_destroy(&sc->sc_calib_to); 395 } 396 397 /* 398 * Attach the interface to 802.11 radiotap. 399 */ 400 Static void 401 athn_radiotap_attach(struct athn_softc *sc) 402 { 403 404 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 405 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 406 &sc->sc_drvbpf); 407 408 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 409 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 410 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 411 412 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 413 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 414 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 415 } 416 417 Static void 418 athn_get_chanlist(struct athn_softc *sc) 419 { 420 struct ieee80211com *ic = &sc->sc_ic; 421 uint8_t chan; 422 size_t i; 423 424 if (sc->sc_flags & ATHN_FLAG_11G) { 425 for (i = 1; i <= 14; i++) { 426 chan = i; 427 ic->ic_channels[chan].ic_freq = 428 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 429 ic->ic_channels[chan].ic_flags = 430 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 431 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 432 } 433 } 434 if (sc->sc_flags & ATHN_FLAG_11A) { 435 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 436 chan = athn_5ghz_chans[i]; 437 ic->ic_channels[chan].ic_freq = 438 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 439 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 440 } 441 } 442 } 443 444 PUBLIC void 445 athn_rx_start(struct athn_softc *sc) 446 { 447 struct ieee80211com *ic = &sc->sc_ic; 448 uint32_t rfilt; 449 450 /* Setup Rx DMA descriptors. */ 451 sc->sc_ops.rx_enable(sc); 452 453 /* Set Rx filter. */ 454 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 455 #ifndef IEEE80211_NO_HT 456 /* Want Compressed Block Ack Requests. */ 457 rfilt |= AR_RX_FILTER_COMPR_BAR; 458 #endif 459 rfilt |= AR_RX_FILTER_BEACON; 460 if (ic->ic_opmode != IEEE80211_M_STA) { 461 rfilt |= AR_RX_FILTER_PROBEREQ; 462 if (ic->ic_opmode == IEEE80211_M_MONITOR) 463 rfilt |= AR_RX_FILTER_PROM; 464 #ifndef IEEE80211_STA_ONLY 465 if (AR_SREV_9280_10_OR_LATER(sc) && 466 ic->ic_opmode == IEEE80211_M_HOSTAP) 467 rfilt |= AR_RX_FILTER_PSPOLL; 468 #endif 469 } 470 athn_set_rxfilter(sc, rfilt); 471 472 /* Set BSSID mask. */ 473 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 474 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 475 476 athn_set_opmode(sc); 477 478 /* Set multicast filter. */ 479 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 480 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 481 482 AR_WRITE(sc, AR_FILT_OFDM, 0); 483 AR_WRITE(sc, AR_FILT_CCK, 0); 484 AR_WRITE(sc, AR_MIBC, 0); 485 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 486 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 487 488 /* XXX ANI. */ 489 AR_WRITE(sc, AR_PHY_ERR_1, 0); 490 AR_WRITE(sc, AR_PHY_ERR_2, 0); 491 492 /* Disable HW crypto for now. */ 493 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 494 495 /* Start PCU Rx. */ 496 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 497 AR_WRITE_BARRIER(sc); 498 } 499 500 PUBLIC void 501 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 502 { 503 504 AR_WRITE(sc, AR_RX_FILTER, rfilt); 505 #ifdef notyet 506 reg = AR_READ(sc, AR_PHY_ERR); 507 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 508 AR_PHY_ERR_CCK_TIMING); 509 AR_WRITE(sc, AR_PHY_ERR, reg); 510 if (reg != 0) 511 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 512 else 513 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 514 #else 515 AR_WRITE(sc, AR_PHY_ERR, 0); 516 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 517 #endif 518 AR_WRITE_BARRIER(sc); 519 } 520 521 PUBLIC int 522 athn_intr(void *xsc) 523 { 524 struct athn_softc *sc = xsc; 525 struct ifnet *ifp = &sc->sc_if; 526 527 if (!IS_UP_AND_RUNNING(ifp)) 528 return 0; 529 530 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 531 /* 532 * The hardware is not ready/present, don't touch anything. 533 * Note this can happen early on if the IRQ is shared. 534 */ 535 return 0; 536 537 return sc->sc_ops.intr(sc); 538 } 539 540 Static void 541 athn_get_chipid(struct athn_softc *sc) 542 { 543 uint32_t reg; 544 545 reg = AR_READ(sc, AR_SREV); 546 if (MS(reg, AR_SREV_ID) == 0xff) { 547 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 548 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 549 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 550 sc->sc_flags |= ATHN_FLAG_PCIE; 551 } 552 else { 553 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 554 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 555 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 556 sc->sc_flags |= ATHN_FLAG_PCIE; 557 } 558 } 559 560 Static const char * 561 athn_get_mac_name(struct athn_softc *sc) 562 { 563 564 switch (sc->sc_mac_ver) { 565 case AR_SREV_VERSION_5416_PCI: 566 return "AR5416"; 567 case AR_SREV_VERSION_5416_PCIE: 568 return "AR5418"; 569 case AR_SREV_VERSION_9160: 570 return "AR9160"; 571 case AR_SREV_VERSION_9280: 572 return "AR9280"; 573 case AR_SREV_VERSION_9285: 574 return "AR9285"; 575 case AR_SREV_VERSION_9271: 576 return "AR9271"; 577 case AR_SREV_VERSION_9287: 578 return "AR9287"; 579 case AR_SREV_VERSION_9380: 580 return "AR9380"; 581 case AR_SREV_VERSION_9485: 582 return "AR9485"; 583 default: 584 return "unknown"; 585 } 586 } 587 588 /* 589 * Return RF chip name (not for single-chip solutions). 590 */ 591 Static const char * 592 athn_get_rf_name(struct athn_softc *sc) 593 { 594 595 KASSERT(!AR_SINGLE_CHIP(sc)); 596 597 switch (sc->sc_rf_rev) { 598 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 599 return "AR5133"; 600 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 601 return "AR2133"; 602 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 603 return "AR5122"; 604 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 605 return "AR2122"; 606 default: 607 return "unknown"; 608 } 609 } 610 611 PUBLIC int 612 athn_reset_power_on(struct athn_softc *sc) 613 { 614 int ntries; 615 616 /* Set force wake. */ 617 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 618 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 619 620 if (!AR_SREV_9380_10_OR_LATER(sc)) { 621 /* Make sure no DMA is active by doing an AHB reset. */ 622 AR_WRITE(sc, AR_RC, AR_RC_AHB); 623 } 624 /* RTC reset and clear. */ 625 AR_WRITE(sc, AR_RTC_RESET, 0); 626 AR_WRITE_BARRIER(sc); 627 DELAY(2); 628 if (!AR_SREV_9380_10_OR_LATER(sc)) 629 AR_WRITE(sc, AR_RC, 0); 630 AR_WRITE(sc, AR_RTC_RESET, 1); 631 632 /* Poll until RTC is ON. */ 633 for (ntries = 0; ntries < 1000; ntries++) { 634 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 635 AR_RTC_STATUS_ON) 636 break; 637 DELAY(10); 638 } 639 if (ntries == 1000) { 640 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 641 return ETIMEDOUT; 642 } 643 return athn_reset(sc, 0); 644 } 645 646 PUBLIC int 647 athn_reset(struct athn_softc *sc, int cold_reset) 648 { 649 int ntries; 650 651 /* Set force wake. */ 652 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 653 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 654 655 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 656 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 657 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 658 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 659 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 660 } 661 else if (!AR_SREV_9380_10_OR_LATER(sc)) 662 AR_WRITE(sc, AR_RC, AR_RC_AHB); 663 664 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 665 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 666 AR_WRITE_BARRIER(sc); 667 DELAY(50); 668 AR_WRITE(sc, AR_RTC_RC, 0); 669 for (ntries = 0; ntries < 1000; ntries++) { 670 if (!(AR_READ(sc, AR_RTC_RC) & 671 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 672 break; 673 DELAY(10); 674 } 675 if (ntries == 1000) { 676 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 677 return ETIMEDOUT; 678 } 679 AR_WRITE(sc, AR_RC, 0); 680 AR_WRITE_BARRIER(sc); 681 return 0; 682 } 683 684 PUBLIC int 685 athn_set_power_awake(struct athn_softc *sc) 686 { 687 int ntries, error; 688 689 /* Do a Power-On-Reset if shutdown. */ 690 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 691 AR_RTC_STATUS_SHUTDOWN) { 692 if ((error = athn_reset_power_on(sc)) != 0) 693 return error; 694 if (!AR_SREV_9380_10_OR_LATER(sc)) 695 athn_init_pll(sc, NULL); 696 } 697 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 698 AR_WRITE_BARRIER(sc); 699 DELAY(50); /* Give chip the chance to awake. */ 700 701 /* Poll until RTC is ON. */ 702 for (ntries = 0; ntries < 4000; ntries++) { 703 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 704 AR_RTC_STATUS_ON) 705 break; 706 DELAY(50); 707 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 708 } 709 if (ntries == 4000) { 710 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 711 return ETIMEDOUT; 712 } 713 714 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 715 AR_WRITE_BARRIER(sc); 716 return 0; 717 } 718 719 PUBLIC void 720 athn_set_power_sleep(struct athn_softc *sc) 721 { 722 723 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 724 /* Allow the MAC to go to sleep. */ 725 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 726 if (!AR_SREV_9380_10_OR_LATER(sc)) 727 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 728 /* 729 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 730 * results in high power consumption on AR5416 chipsets. 731 */ 732 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 733 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 734 AR_WRITE_BARRIER(sc); 735 } 736 737 PUBLIC void 738 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 739 { 740 uint32_t pll; 741 742 if (AR_SREV_9380_10_OR_LATER(sc)) { 743 if (AR_SREV_9485(sc)) 744 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 745 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 746 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 747 } 748 else if (AR_SREV_9280_10_OR_LATER(sc)) { 749 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 750 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 751 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 752 pll = 0x142c; 753 else if (AR_SREV_9280_20(sc)) 754 pll = 0x2850; 755 else 756 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 757 } 758 else 759 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 760 } 761 else if (AR_SREV_9160_10_OR_LATER(sc)) { 762 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 763 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 764 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 765 else 766 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 767 } 768 else { 769 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 770 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 771 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 772 else 773 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 774 } 775 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 776 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 777 if (AR_SREV_9271(sc)) { 778 /* Switch core clock to 117MHz. */ 779 AR_WRITE_BARRIER(sc); 780 DELAY(500); 781 AR_WRITE(sc, 0x50050, 0x304); 782 } 783 AR_WRITE_BARRIER(sc); 784 DELAY(100); 785 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 786 AR_WRITE_BARRIER(sc); 787 } 788 789 Static void 790 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 791 { 792 int i; 793 794 /* Write sequence to Serializer/Deserializer. */ 795 for (i = 0; i < serdes->nvals; i++) 796 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 797 AR_WRITE_BARRIER(sc); 798 } 799 800 PUBLIC void 801 athn_config_pcie(struct athn_softc *sc) 802 { 803 804 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 805 athn_write_serdes(sc, sc->sc_serdes); 806 807 DELAY(1000); 808 /* Allow forcing of PCIe core into L1 state. */ 809 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 810 811 #ifndef ATHN_PCIE_WAEN 812 AR_WRITE(sc, AR_WA, sc->sc_workaround); 813 #else 814 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 815 #endif 816 AR_WRITE_BARRIER(sc); 817 } 818 819 /* 820 * Serializer/Deserializer programming for non-PCIe devices. 821 */ 822 static const uint32_t ar_nonpcie_serdes_regs[] = { 823 AR_PCIE_SERDES, 824 AR_PCIE_SERDES, 825 AR_PCIE_SERDES, 826 AR_PCIE_SERDES, 827 AR_PCIE_SERDES, 828 AR_PCIE_SERDES, 829 AR_PCIE_SERDES, 830 AR_PCIE_SERDES, 831 AR_PCIE_SERDES, 832 AR_PCIE_SERDES2, 833 }; 834 835 static const uint32_t ar_nonpcie_serdes_vals[] = { 836 0x9248fc00, 837 0x24924924, 838 0x28000029, 839 0x57160824, 840 0x25980579, 841 0x00000000, 842 0x1aaabe40, 843 0xbe105554, 844 0x000e1007, 845 0x00000000 846 }; 847 848 static const struct athn_serdes ar_nonpcie_serdes = { 849 __arraycount(ar_nonpcie_serdes_vals), 850 ar_nonpcie_serdes_regs, 851 ar_nonpcie_serdes_vals 852 }; 853 854 PUBLIC void 855 athn_config_nonpcie(struct athn_softc *sc) 856 { 857 858 athn_write_serdes(sc, &ar_nonpcie_serdes); 859 } 860 861 PUBLIC int 862 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 863 struct ieee80211_channel *extchan) 864 { 865 struct athn_ops *ops = &sc->sc_ops; 866 int error, qid; 867 868 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 869 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 870 if (athn_tx_pending(sc, qid)) 871 return EBUSY; 872 873 /* Request RF Bus grant. */ 874 if ((error = ops->rf_bus_request(sc)) != 0) 875 return error; 876 877 ops->set_phy(sc, curchan, extchan); 878 879 /* Change the synthesizer. */ 880 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 881 return error; 882 883 sc->sc_curchan = curchan; 884 sc->sc_curchanext = extchan; 885 886 /* Set transmit power values for new channel. */ 887 ops->set_txpower(sc, curchan, extchan); 888 889 /* Release the RF Bus grant. */ 890 ops->rf_bus_release(sc); 891 892 /* Write delta slope coeffs for modes where OFDM may be used. */ 893 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 894 ops->set_delta_slope(sc, curchan, extchan); 895 896 ops->spur_mitigate(sc, curchan, extchan); 897 /* XXX Load noisefloor values and start calibration. */ 898 899 return 0; 900 } 901 902 Static int 903 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 904 struct ieee80211_channel *extchan) 905 { 906 int error, qid; 907 908 /* Disable interrupts. */ 909 athn_disable_interrupts(sc); 910 911 /* Stop all Tx queues. */ 912 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 913 athn_stop_tx_dma(sc, qid); 914 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 915 athn_tx_reclaim(sc, qid); 916 917 /* Stop Rx. */ 918 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 919 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 920 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 921 AR_WRITE(sc, AR_FILT_OFDM, 0); 922 AR_WRITE(sc, AR_FILT_CCK, 0); 923 athn_set_rxfilter(sc, 0); 924 error = athn_stop_rx_dma(sc); 925 if (error != 0) 926 goto reset; 927 928 #ifdef notyet 929 /* AR9280 needs a full reset. */ 930 if (AR_SREV_9280(sc)) 931 #endif 932 goto reset; 933 934 /* If band or bandwidth changes, we need to do a full reset. */ 935 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 936 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 937 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 938 goto reset; 939 } 940 error = athn_set_power_awake(sc); 941 if (error != 0) 942 goto reset; 943 944 error = athn_set_chan(sc, curchan, extchan); 945 if (error != 0) { 946 reset: /* Error found, try a full reset. */ 947 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 948 error = athn_hw_reset(sc, curchan, extchan, 0); 949 if (error != 0) /* Hopeless case. */ 950 return error; 951 } 952 athn_rx_start(sc); 953 954 /* Re-enable interrupts. */ 955 athn_enable_interrupts(sc); 956 return 0; 957 } 958 959 PUBLIC void 960 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 961 { 962 #define COEFF_SCALE_SHIFT 24 963 uint32_t exp, man; 964 965 /* exponent = 14 - floor(log2(coeff)) */ 966 for (exp = 31; exp > 0; exp--) 967 if (coeff & (1 << exp)) 968 break; 969 exp = 14 - (exp - COEFF_SCALE_SHIFT); 970 971 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 972 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 973 974 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 975 *exponent = exp - 16; 976 #undef COEFF_SCALE_SHIFT 977 } 978 979 PUBLIC void 980 athn_reset_key(struct athn_softc *sc, int entry) 981 { 982 983 /* 984 * NB: Key cache registers access special memory area that requires 985 * two 32-bit writes to actually update the values in the internal 986 * memory. Consequently, writes must be grouped by pair. 987 */ 988 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 989 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 990 991 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 992 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 993 994 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 995 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 996 997 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 998 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 999 1000 AR_WRITE_BARRIER(sc); 1001 } 1002 1003 #ifdef notyet 1004 Static int 1005 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1006 struct ieee80211_key *k) 1007 { 1008 struct athn_softc *sc = ic->ic_ifp->if_softc; 1009 const uint8_t *txmic, *rxmic, *key, *addr; 1010 uintptr_t entry, micentry; 1011 uint32_t type, lo, hi; 1012 1013 switch (k->k_cipher) { 1014 case IEEE80211_CIPHER_WEP40: 1015 type = AR_KEYTABLE_TYPE_40; 1016 break; 1017 case IEEE80211_CIPHER_WEP104: 1018 type = AR_KEYTABLE_TYPE_104; 1019 break; 1020 case IEEE80211_CIPHER_TKIP: 1021 type = AR_KEYTABLE_TYPE_TKIP; 1022 break; 1023 case IEEE80211_CIPHER_CCMP: 1024 type = AR_KEYTABLE_TYPE_CCM; 1025 break; 1026 default: 1027 /* Fallback to software crypto for other ciphers. */ 1028 return ieee80211_set_key(ic, ni, k); 1029 } 1030 1031 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1032 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1033 else 1034 entry = k->k_id; 1035 k->k_priv = (void *)entry; 1036 1037 /* NB: See note about key cache registers access above. */ 1038 key = k->k_key; 1039 if (type == AR_KEYTABLE_TYPE_TKIP) { 1040 #ifndef IEEE80211_STA_ONLY 1041 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1042 txmic = &key[16]; 1043 rxmic = &key[24]; 1044 } 1045 else 1046 #endif 1047 { 1048 rxmic = &key[16]; 1049 txmic = &key[24]; 1050 } 1051 /* Tx+Rx MIC key is at entry + 64. */ 1052 micentry = entry + 64; 1053 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1054 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1055 1056 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1057 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1058 1059 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1060 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1061 } 1062 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1063 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1064 1065 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1066 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1067 1068 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1069 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1070 1071 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1072 addr = ni->ni_macaddr; 1073 lo = LE_READ_4(&addr[0]); 1074 hi = LE_READ_2(&addr[4]); 1075 lo = lo >> 1 | hi << 31; 1076 hi = hi >> 1; 1077 } 1078 else 1079 lo = hi = 0; 1080 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1081 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1082 AR_WRITE_BARRIER(sc); 1083 return 0; 1084 } 1085 1086 Static void 1087 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1088 struct ieee80211_key *k) 1089 { 1090 struct athn_softc *sc = ic->ic_ifp->if_softc; 1091 uintptr_t entry; 1092 1093 switch (k->k_cipher) { 1094 case IEEE80211_CIPHER_WEP40: 1095 case IEEE80211_CIPHER_WEP104: 1096 case IEEE80211_CIPHER_CCMP: 1097 entry = (uintptr_t)k->k_priv; 1098 athn_reset_key(sc, entry); 1099 break; 1100 case IEEE80211_CIPHER_TKIP: 1101 entry = (uintptr_t)k->k_priv; 1102 athn_reset_key(sc, entry); 1103 athn_reset_key(sc, entry + 64); 1104 break; 1105 default: 1106 /* Fallback to software crypto for other ciphers. */ 1107 ieee80211_delete_key(ic, ni, k); 1108 } 1109 } 1110 #endif /* notyet */ 1111 1112 PUBLIC void 1113 athn_led_init(struct athn_softc *sc) 1114 { 1115 struct athn_ops *ops = &sc->sc_ops; 1116 1117 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1118 /* LED off, active low. */ 1119 athn_set_led(sc, 0); 1120 } 1121 1122 PUBLIC void 1123 athn_set_led(struct athn_softc *sc, int on) 1124 { 1125 struct athn_ops *ops = &sc->sc_ops; 1126 1127 sc->sc_led_state = on; 1128 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1129 } 1130 1131 #ifdef ATHN_BT_COEXISTENCE 1132 Static void 1133 athn_btcoex_init(struct athn_softc *sc) 1134 { 1135 struct athn_ops *ops = &sc->sc_ops; 1136 uint32_t reg; 1137 1138 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1139 /* Connect bt_active to baseband. */ 1140 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1141 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1142 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1143 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1144 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1145 1146 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1147 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1148 AR_GPIO_BTACTIVE_PIN); 1149 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1150 AR_WRITE_BARRIER(sc); 1151 1152 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1153 } 1154 else { /* 3-wire. */ 1155 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1156 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1157 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1158 1159 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1160 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1161 AR_GPIO_BTACTIVE_PIN); 1162 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1163 AR_GPIO_BTPRIORITY_PIN); 1164 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1165 AR_WRITE_BARRIER(sc); 1166 1167 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1168 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1169 } 1170 } 1171 1172 Static void 1173 athn_btcoex_enable(struct athn_softc *sc) 1174 { 1175 struct athn_ops *ops = &sc->sc_ops; 1176 uint32_t reg; 1177 1178 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1179 AR_WRITE(sc, AR_BT_COEX_MODE, 1180 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1181 SM(AR_BT_PRIORITY_TIME, 2) | 1182 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1183 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1184 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1185 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1186 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1187 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1188 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1189 AR_WRITE(sc, AR_BT_COEX_MODE2, 1190 SM(AR_BT_BCN_MISS_THRESH, 50) | 1191 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1192 1193 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1194 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1195 AR_WRITE_BARRIER(sc); 1196 1197 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1198 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1199 1200 } 1201 else { /* 2-wire. */ 1202 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1203 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1204 } 1205 reg = AR_READ(sc, AR_GPIO_PDPU); 1206 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1207 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1208 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1209 AR_WRITE_BARRIER(sc); 1210 1211 /* Disable PCIe Active State Power Management (ASPM). */ 1212 if (sc->sc_disable_aspm != NULL) 1213 sc->sc_disable_aspm(sc); 1214 1215 /* XXX Start periodic timer. */ 1216 } 1217 1218 Static void 1219 athn_btcoex_disable(struct athn_softc *sc) 1220 { 1221 struct athn_ops *ops = &sc->sc_ops; 1222 1223 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1224 1225 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1226 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1227 1228 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1229 AR_WRITE(sc, AR_BT_COEX_MODE, 1230 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1231 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1232 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1233 /* XXX Stop periodic timer. */ 1234 } 1235 AR_WRITE_BARRIER(sc); 1236 /* XXX Restore ASPM setting? */ 1237 } 1238 #endif 1239 1240 Static void 1241 athn_iter_func(void *arg, struct ieee80211_node *ni) 1242 { 1243 struct athn_softc *sc = arg; 1244 struct athn_node *an = (struct athn_node *)ni; 1245 1246 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1247 } 1248 1249 Static void 1250 athn_calib_to(void *arg) 1251 { 1252 extern int ticks; 1253 struct athn_softc *sc = arg; 1254 struct athn_ops *ops = &sc->sc_ops; 1255 struct ieee80211com *ic = &sc->sc_ic; 1256 int s; 1257 1258 s = splnet(); 1259 1260 /* Do periodic (every 4 minutes) PA calibration. */ 1261 if (AR_SREV_9285_11_OR_LATER(sc) && 1262 !AR_SREV_9380_10_OR_LATER(sc) && 1263 ticks >= sc->sc_pa_calib_ticks + 240 * hz) { 1264 sc->sc_pa_calib_ticks = ticks; 1265 if (AR_SREV_9271(sc)) 1266 ar9271_pa_calib(sc); 1267 else 1268 ar9285_pa_calib(sc); 1269 } 1270 1271 /* Do periodic (every 30 seconds) temperature compensation. */ 1272 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1273 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1274 sc->sc_olpc_ticks = ticks; 1275 ops->olpc_temp_compensation(sc); 1276 } 1277 1278 #ifdef notyet 1279 /* XXX ANI. */ 1280 athn_ani_monitor(sc); 1281 1282 ops->next_calib(sc); 1283 #endif 1284 if (ic->ic_fixed_rate == -1) { 1285 if (ic->ic_opmode == IEEE80211_M_STA) 1286 athn_iter_func(sc, ic->ic_bss); 1287 else 1288 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1289 } 1290 callout_schedule(&sc->sc_calib_to, hz / 2); 1291 splx(s); 1292 } 1293 1294 Static int 1295 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1296 struct ieee80211_channel *extchan) 1297 { 1298 struct athn_ops *ops = &sc->sc_ops; 1299 int error; 1300 1301 if (AR_SREV_9380_10_OR_LATER(sc)) 1302 error = ar9003_init_calib(sc); 1303 else if (AR_SREV_9285_10_OR_LATER(sc)) 1304 error = ar9285_init_calib(sc, curchan, extchan); 1305 else 1306 error = ar5416_init_calib(sc, curchan, extchan); 1307 if (error != 0) 1308 return error; 1309 1310 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1311 /* Do PA calibration. */ 1312 if (AR_SREV_9285_11_OR_LATER(sc)) { 1313 extern int ticks; 1314 sc->sc_pa_calib_ticks = ticks; 1315 if (AR_SREV_9271(sc)) 1316 ar9271_pa_calib(sc); 1317 else 1318 ar9285_pa_calib(sc); 1319 } 1320 /* Do noisefloor calibration. */ 1321 ops->noisefloor_calib(sc); 1322 } 1323 if (AR_SREV_9160_10_OR_LATER(sc)) { 1324 /* Support IQ calibration. */ 1325 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1326 if (AR_SREV_9380_10_OR_LATER(sc)) { 1327 /* Support temperature compensation calibration. */ 1328 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1329 } 1330 else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1331 /* 1332 * ADC gain calibration causes uplink throughput 1333 * drops in HT40 mode on AR9287. 1334 */ 1335 if (!AR_SREV_9287(sc)) { 1336 /* Support ADC gain calibration. */ 1337 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1338 } 1339 /* Support ADC DC offset calibration. */ 1340 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1341 } 1342 } 1343 return 0; 1344 } 1345 1346 /* 1347 * Adaptive noise immunity. 1348 */ 1349 #ifdef notyet 1350 Static int32_t 1351 athn_ani_get_rssi(struct athn_softc *sc) 1352 { 1353 1354 return 0; /* XXX */ 1355 } 1356 #endif /* notyet */ 1357 1358 #ifdef notyet 1359 Static void 1360 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1361 { 1362 struct athn_ani *ani = &sc->sc_ani; 1363 struct athn_ops *ops = &sc->sc_ops; 1364 int32_t rssi; 1365 1366 /* First, raise noise immunity level, up to max. */ 1367 if (ani->noise_immunity_level < 4) { 1368 ani->noise_immunity_level++; 1369 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1370 return; 1371 } 1372 1373 /* Then, raise our spur immunity level, up to max. */ 1374 if (ani->spur_immunity_level < 7) { 1375 ani->spur_immunity_level++; 1376 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1377 return; 1378 } 1379 1380 #ifndef IEEE80211_STA_ONLY 1381 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1382 if (ani->firstep_level < 2) { 1383 ani->firstep_level++; 1384 ops->set_firstep_level(sc, ani->firstep_level); 1385 } 1386 return; 1387 } 1388 #endif 1389 rssi = athn_ani_get_rssi(sc); 1390 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1391 /* 1392 * Beacon RSSI is high, turn off OFDM weak signal detection 1393 * or raise first step level as last resort. 1394 */ 1395 if (ani->ofdm_weak_signal) { 1396 ani->ofdm_weak_signal = 0; 1397 ops->disable_ofdm_weak_signal(sc); 1398 ani->spur_immunity_level = 0; 1399 ops->set_spur_immunity_level(sc, 0); 1400 } 1401 else if (ani->firstep_level < 2) { 1402 ani->firstep_level++; 1403 ops->set_firstep_level(sc, ani->firstep_level); 1404 } 1405 } 1406 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1407 /* 1408 * Beacon RSSI is in mid range, we need OFDM weak signal 1409 * detection but we can raise first step level. 1410 */ 1411 if (!ani->ofdm_weak_signal) { 1412 ani->ofdm_weak_signal = 1; 1413 ops->enable_ofdm_weak_signal(sc); 1414 } 1415 if (ani->firstep_level < 2) { 1416 ani->firstep_level++; 1417 ops->set_firstep_level(sc, ani->firstep_level); 1418 } 1419 } 1420 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1421 /* 1422 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1423 * signal detection and zero first step level to maximize 1424 * CCK sensitivity. 1425 */ 1426 if (ani->ofdm_weak_signal) { 1427 ani->ofdm_weak_signal = 0; 1428 ops->disable_ofdm_weak_signal(sc); 1429 } 1430 if (ani->firstep_level > 0) { 1431 ani->firstep_level = 0; 1432 ops->set_firstep_level(sc, 0); 1433 } 1434 } 1435 } 1436 #endif /* notyet */ 1437 1438 #ifdef notyet 1439 Static void 1440 athn_ani_cck_err_trigger(struct athn_softc *sc) 1441 { 1442 struct athn_ani *ani = &sc->sc_ani; 1443 struct athn_ops *ops = &sc->sc_ops; 1444 int32_t rssi; 1445 1446 /* Raise noise immunity level, up to max. */ 1447 if (ani->noise_immunity_level < 4) { 1448 ani->noise_immunity_level++; 1449 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1450 return; 1451 } 1452 1453 #ifndef IEEE80211_STA_ONLY 1454 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1455 if (ani->firstep_level < 2) { 1456 ani->firstep_level++; 1457 ops->set_firstep_level(sc, ani->firstep_level); 1458 } 1459 return; 1460 } 1461 #endif 1462 rssi = athn_ani_get_rssi(sc); 1463 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1464 /* 1465 * Beacon RSSI is in mid or high range, raise first step 1466 * level. 1467 */ 1468 if (ani->firstep_level < 2) { 1469 ani->firstep_level++; 1470 ops->set_firstep_level(sc, ani->firstep_level); 1471 } 1472 } 1473 else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1474 /* 1475 * Beacon RSSI is low, zero first step level to maximize 1476 * CCK sensitivity. 1477 */ 1478 if (ani->firstep_level > 0) { 1479 ani->firstep_level = 0; 1480 ops->set_firstep_level(sc, 0); 1481 } 1482 } 1483 } 1484 #endif /* notyet */ 1485 1486 #ifdef notyet 1487 Static void 1488 athn_ani_lower_immunity(struct athn_softc *sc) 1489 { 1490 struct athn_ani *ani = &sc->sc_ani; 1491 struct athn_ops *ops = &sc->sc_ops; 1492 int32_t rssi; 1493 1494 #ifndef IEEE80211_STA_ONLY 1495 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1496 if (ani->firstep_level > 0) { 1497 ani->firstep_level--; 1498 ops->set_firstep_level(sc, ani->firstep_level); 1499 } 1500 return; 1501 } 1502 #endif 1503 rssi = athn_ani_get_rssi(sc); 1504 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1505 /* 1506 * Beacon RSSI is high, leave OFDM weak signal detection 1507 * off or it may oscillate. 1508 */ 1509 } 1510 else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1511 /* 1512 * Beacon RSSI is in mid range, turn on OFDM weak signal 1513 * detection or lower first step level. 1514 */ 1515 if (!ani->ofdm_weak_signal) { 1516 ani->ofdm_weak_signal = 1; 1517 ops->enable_ofdm_weak_signal(sc); 1518 return; 1519 } 1520 if (ani->firstep_level > 0) { 1521 ani->firstep_level--; 1522 ops->set_firstep_level(sc, ani->firstep_level); 1523 return; 1524 } 1525 } 1526 else { 1527 /* Beacon RSSI is low, lower first step level. */ 1528 if (ani->firstep_level > 0) { 1529 ani->firstep_level--; 1530 ops->set_firstep_level(sc, ani->firstep_level); 1531 return; 1532 } 1533 } 1534 /* 1535 * Lower spur immunity level down to zero, or if all else fails, 1536 * lower noise immunity level down to zero. 1537 */ 1538 if (ani->spur_immunity_level > 0) { 1539 ani->spur_immunity_level--; 1540 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1541 } 1542 else if (ani->noise_immunity_level > 0) { 1543 ani->noise_immunity_level--; 1544 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1545 } 1546 } 1547 #endif /* notyet */ 1548 1549 #ifdef notyet 1550 Static void 1551 athn_ani_restart(struct athn_softc *sc) 1552 { 1553 struct athn_ani *ani = &sc->sc_ani; 1554 1555 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1556 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1557 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1558 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1559 AR_WRITE_BARRIER(sc); 1560 1561 ani->listen_time = 0; 1562 ani->ofdm_phy_err_count = 0; 1563 ani->cck_phy_err_count = 0; 1564 } 1565 #endif /* notyet */ 1566 1567 #ifdef notyet 1568 Static void 1569 athn_ani_monitor(struct athn_softc *sc) 1570 { 1571 struct athn_ani *ani = &sc->sc_ani; 1572 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1573 int32_t cycdelta, txfdelta, rxfdelta; 1574 int32_t listen_time; 1575 1576 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1577 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1578 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1579 1580 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1581 cycdelta = cyccnt - ani->cyccnt; 1582 txfdelta = txfcnt - ani->txfcnt; 1583 rxfdelta = rxfcnt - ani->rxfcnt; 1584 1585 listen_time = (cycdelta - txfdelta - rxfdelta) / 1586 (athn_clock_rate(sc) * 1000); 1587 } 1588 else 1589 listen_time = 0; 1590 1591 ani->cyccnt = cyccnt; 1592 ani->txfcnt = txfcnt; 1593 ani->rxfcnt = rxfcnt; 1594 1595 if (listen_time < 0) { 1596 athn_ani_restart(sc); 1597 return; 1598 } 1599 ani->listen_time += listen_time; 1600 1601 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1602 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1603 1604 if (phy1 < ani->ofdm_phy_err_base) { 1605 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1606 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1607 } 1608 if (phy2 < ani->cck_phy_err_base) { 1609 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1610 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1611 } 1612 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1613 AR_WRITE_BARRIER(sc); 1614 return; 1615 } 1616 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1617 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1618 1619 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1620 /* Check to see if we need to lower immunity. */ 1621 if (ani->ofdm_phy_err_count <= 1622 ani->listen_time * ani->ofdm_trig_low / 1000 && 1623 ani->cck_phy_err_count <= 1624 ani->listen_time * ani->cck_trig_low / 1000) 1625 athn_ani_lower_immunity(sc); 1626 athn_ani_restart(sc); 1627 1628 } 1629 else if (ani->listen_time > ATHN_ANI_PERIOD) { 1630 /* Check to see if we need to raise immunity. */ 1631 if (ani->ofdm_phy_err_count > 1632 ani->listen_time * ani->ofdm_trig_high / 1000) { 1633 athn_ani_ofdm_err_trigger(sc); 1634 athn_ani_restart(sc); 1635 } 1636 else if (ani->cck_phy_err_count > 1637 ani->listen_time * ani->cck_trig_high / 1000) { 1638 athn_ani_cck_err_trigger(sc); 1639 athn_ani_restart(sc); 1640 } 1641 } 1642 } 1643 #endif /* notyet */ 1644 1645 PUBLIC uint8_t 1646 athn_chan2fbin(struct ieee80211_channel *c) 1647 { 1648 1649 if (IEEE80211_IS_CHAN_2GHZ(c)) 1650 return c->ic_freq - 2300; 1651 else 1652 return (c->ic_freq - 4800) / 5; 1653 } 1654 1655 PUBLIC int 1656 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1657 { 1658 1659 if (x1 == x2) /* Prevents division by zero. */ 1660 return y1; 1661 /* Linear interpolation. */ 1662 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1663 } 1664 1665 PUBLIC void 1666 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1667 int *lo, int *hi) 1668 { 1669 int i; 1670 1671 for (i = 0; i < npiers; i++) 1672 if (pierfreq[i] == AR_BCHAN_UNUSED || 1673 pierfreq[i] > fbin) 1674 break; 1675 *hi = i; 1676 *lo = *hi - 1; 1677 if (*lo == -1) 1678 *lo = *hi; 1679 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1680 *hi = *lo; 1681 } 1682 1683 Static void 1684 athn_init_dma(struct athn_softc *sc) 1685 { 1686 uint32_t reg; 1687 1688 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1689 /* Set AHB not to do cacheline prefetches. */ 1690 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1691 } 1692 reg = AR_READ(sc, AR_TXCFG); 1693 /* Let MAC DMA reads be in 128-byte chunks. */ 1694 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1695 1696 /* Set initial Tx trigger level. */ 1697 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1698 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1699 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1700 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1701 AR_WRITE(sc, AR_TXCFG, reg); 1702 1703 /* Let MAC DMA writes be in 128-byte chunks. */ 1704 reg = AR_READ(sc, AR_RXCFG); 1705 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1706 AR_WRITE(sc, AR_RXCFG, reg); 1707 1708 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1709 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1710 1711 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1712 if (AR_SREV_9285(sc)) { 1713 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1714 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1715 } 1716 else if (!AR_SREV_9271(sc)) { 1717 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1718 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1719 } 1720 AR_WRITE_BARRIER(sc); 1721 1722 /* Reset Tx status ring. */ 1723 if (AR_SREV_9380_10_OR_LATER(sc)) 1724 ar9003_reset_txsring(sc); 1725 } 1726 1727 PUBLIC void 1728 athn_inc_tx_trigger_level(struct athn_softc *sc) 1729 { 1730 uint32_t reg, ftrig; 1731 1732 reg = AR_READ(sc, AR_TXCFG); 1733 ftrig = MS(reg, AR_TXCFG_FTRIG); 1734 /* 1735 * NB: The AR9285 and all single-stream parts have an issue that 1736 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1737 */ 1738 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1739 return; /* Already at max. */ 1740 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1741 AR_WRITE(sc, AR_TXCFG, reg); 1742 AR_WRITE_BARRIER(sc); 1743 } 1744 1745 PUBLIC int 1746 athn_stop_rx_dma(struct athn_softc *sc) 1747 { 1748 int ntries; 1749 1750 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1751 /* Wait for Rx enable bit to go low. */ 1752 for (ntries = 0; ntries < 100; ntries++) { 1753 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1754 return 0; 1755 DELAY(100); 1756 } 1757 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1758 return ETIMEDOUT; 1759 } 1760 1761 #ifdef unused 1762 Static int 1763 athn_rx_abort(struct athn_softc *sc) 1764 { 1765 int ntries; 1766 1767 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1768 for (ntries = 0; ntries < 1000; ntries++) { 1769 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1770 return 0; 1771 DELAY(10); 1772 } 1773 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1774 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1775 AR_WRITE_BARRIER(sc); 1776 return ETIMEDOUT; 1777 } 1778 #endif /* unused */ 1779 1780 Static void 1781 athn_tx_reclaim(struct athn_softc *sc, int qid) 1782 { 1783 struct athn_txq *txq = &sc->sc_txq[qid]; 1784 struct athn_tx_buf *bf; 1785 1786 /* Reclaim all buffers queued in the specified Tx queue. */ 1787 /* NB: Tx DMA must be stopped. */ 1788 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1789 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1790 1791 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1792 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1793 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1794 m_freem(bf->bf_m); 1795 bf->bf_m = NULL; 1796 bf->bf_ni = NULL; /* Nodes already freed! */ 1797 1798 /* Link Tx buffer back to global free list. */ 1799 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1800 } 1801 } 1802 1803 PUBLIC int 1804 athn_tx_pending(struct athn_softc *sc, int qid) 1805 { 1806 1807 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1808 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1809 } 1810 1811 PUBLIC void 1812 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1813 { 1814 uint32_t tsflo; 1815 int ntries, i; 1816 1817 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1818 for (ntries = 0; ntries < 40; ntries++) { 1819 if (!athn_tx_pending(sc, qid)) 1820 break; 1821 DELAY(100); 1822 } 1823 if (ntries == 40) { 1824 for (i = 0; i < 2; i++) { 1825 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1826 AR_WRITE(sc, AR_QUIET2, 1827 SM(AR_QUIET2_QUIET_DUR, 10)); 1828 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1829 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1830 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1831 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1832 break; 1833 } 1834 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1835 AR_WRITE_BARRIER(sc); 1836 DELAY(200); 1837 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1838 AR_WRITE_BARRIER(sc); 1839 1840 for (ntries = 0; ntries < 40; ntries++) { 1841 if (!athn_tx_pending(sc, qid)) 1842 break; 1843 DELAY(100); 1844 } 1845 1846 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1847 } 1848 AR_WRITE(sc, AR_Q_TXD, 0); 1849 AR_WRITE_BARRIER(sc); 1850 } 1851 1852 PUBLIC int 1853 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1854 { 1855 #define divround(a, b) (((a) + (b) - 1) / (b)) 1856 int txtime; 1857 1858 /* XXX HT. */ 1859 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1860 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1861 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1862 txtime = 16 + 4 + 4 * txtime + 16; 1863 } 1864 else { 1865 txtime = divround(16 * len, athn_rates[ridx].rate); 1866 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1867 txtime += 72 + 24; 1868 else 1869 txtime += 144 + 48; 1870 txtime += 10; /* 10us SIFS. */ 1871 } 1872 return txtime; 1873 #undef divround 1874 } 1875 1876 PUBLIC void 1877 athn_init_tx_queues(struct athn_softc *sc) 1878 { 1879 int qid; 1880 1881 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1882 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1883 sc->sc_txq[qid].lastds = NULL; 1884 sc->sc_txq[qid].wait = NULL; 1885 sc->sc_txq[qid].queued = 0; 1886 1887 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1888 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1889 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1890 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1891 AR_WRITE(sc, AR_QMISC(qid), 1892 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1893 AR_WRITE(sc, AR_DMISC(qid), 1894 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1895 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1896 } 1897 1898 /* Init beacon queue. */ 1899 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1900 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1901 AR_Q_MISC_CBR_INCR_DIS1); 1902 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1903 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1904 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1905 AR_D_MISC_BEACON_USE | 1906 AR_D_MISC_POST_FR_BKOFF_DIS); 1907 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1908 SM(AR_D_LCL_IFS_CWMIN, 0) | 1909 SM(AR_D_LCL_IFS_CWMAX, 0) | 1910 SM(AR_D_LCL_IFS_AIFS, 1)); 1911 1912 /* Init CAB (Content After Beacon) queue. */ 1913 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1914 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1915 AR_Q_MISC_CBR_INCR_DIS0); 1916 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1917 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1918 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1919 1920 /* Init PS-Poll queue. */ 1921 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1922 AR_Q_MISC_CBR_INCR_DIS1); 1923 1924 /* Init UAPSD queue. */ 1925 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1926 AR_D_MISC_POST_FR_BKOFF_DIS); 1927 1928 if (AR_SREV_9380_10_OR_LATER(sc)) { 1929 /* Enable MAC descriptor CRC check. */ 1930 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1931 } 1932 /* Enable DESC interrupts for all Tx queues. */ 1933 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1934 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1935 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1936 AR_WRITE_BARRIER(sc); 1937 } 1938 1939 PUBLIC void 1940 athn_set_sta_timers(struct athn_softc *sc) 1941 { 1942 struct ieee80211com *ic = &sc->sc_ic; 1943 uint32_t tsfhi, tsflo, tsftu, reg; 1944 uint32_t intval, next_tbtt, next_dtim; 1945 int dtim_period, rem_dtim_count; 1946 1947 tsfhi = AR_READ(sc, AR_TSF_U32); 1948 tsflo = AR_READ(sc, AR_TSF_L32); 1949 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1950 1951 /* Beacon interval in TU. */ 1952 intval = ic->ic_bss->ni_intval; 1953 1954 next_tbtt = roundup(tsftu, intval); 1955 #ifdef notyet 1956 dtim_period = ic->ic_dtim_period; 1957 if (dtim_period <= 0) 1958 #endif 1959 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1960 1961 #ifdef notyet 1962 int dtim_count = ic->ic_dtim_count; 1963 if (dtim_count >= dtim_period) /* Should not happen. */ 1964 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1965 #endif 1966 1967 /* Compute number of remaining TIMs until next DTIM. */ 1968 rem_dtim_count = 0; /* XXX */ 1969 next_dtim = next_tbtt + rem_dtim_count * intval; 1970 1971 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1972 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1973 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1974 1975 /* 1976 * Set the number of consecutive beacons to miss before raising 1977 * a BMISS interrupt to 10. 1978 */ 1979 reg = AR_READ(sc, AR_RSSI_THR); 1980 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 1981 AR_WRITE(sc, AR_RSSI_THR, reg); 1982 1983 AR_WRITE(sc, AR_NEXT_DTIM, 1984 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1985 AR_WRITE(sc, AR_NEXT_TIM, 1986 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1987 1988 /* CAB timeout is in 1/8 TU. */ 1989 AR_WRITE(sc, AR_SLEEP1, 1990 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 1991 AR_SLEEP1_ASSUME_DTIM); 1992 AR_WRITE(sc, AR_SLEEP2, 1993 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 1994 1995 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 1996 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 1997 1998 AR_SETBITS(sc, AR_TIMER_MODE, 1999 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2000 2001 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2002 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2003 2004 AR_WRITE_BARRIER(sc); 2005 } 2006 2007 #ifndef IEEE80211_STA_ONLY 2008 PUBLIC void 2009 athn_set_hostap_timers(struct athn_softc *sc) 2010 { 2011 struct ieee80211com *ic = &sc->sc_ic; 2012 uint32_t intval, next_tbtt; 2013 2014 /* Beacon interval in TU. */ 2015 intval = ic->ic_bss->ni_intval; 2016 next_tbtt = intval; 2017 2018 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2019 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2020 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2021 AR_WRITE(sc, AR_NEXT_CFP, 2022 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2023 2024 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2025 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2026 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2027 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2028 2029 AR_WRITE(sc, AR_TIMER_MODE, 2030 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2031 2032 AR_WRITE_BARRIER(sc); 2033 } 2034 #endif 2035 2036 PUBLIC void 2037 athn_set_opmode(struct athn_softc *sc) 2038 { 2039 uint32_t reg; 2040 2041 switch (sc->sc_ic.ic_opmode) { 2042 #ifndef IEEE80211_STA_ONLY 2043 case IEEE80211_M_HOSTAP: 2044 reg = AR_READ(sc, AR_STA_ID1); 2045 reg &= ~AR_STA_ID1_ADHOC; 2046 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2047 AR_WRITE(sc, AR_STA_ID1, reg); 2048 2049 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2050 break; 2051 case IEEE80211_M_IBSS: 2052 case IEEE80211_M_AHDEMO: 2053 reg = AR_READ(sc, AR_STA_ID1); 2054 reg &= ~AR_STA_ID1_STA_AP; 2055 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2056 AR_WRITE(sc, AR_STA_ID1, reg); 2057 2058 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2059 break; 2060 #endif 2061 default: 2062 reg = AR_READ(sc, AR_STA_ID1); 2063 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2064 reg |= AR_STA_ID1_KSRCH_MODE; 2065 AR_WRITE(sc, AR_STA_ID1, reg); 2066 break; 2067 } 2068 AR_WRITE_BARRIER(sc); 2069 } 2070 2071 PUBLIC void 2072 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2073 { 2074 const uint8_t *bssid = ni->ni_bssid; 2075 2076 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2077 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2078 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2079 AR_WRITE_BARRIER(sc); 2080 } 2081 2082 Static void 2083 athn_enable_interrupts(struct athn_softc *sc) 2084 { 2085 uint32_t mask2; 2086 2087 athn_disable_interrupts(sc); /* XXX */ 2088 2089 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2090 2091 mask2 = AR_READ(sc, AR_IMR_S2); 2092 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2093 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2094 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2095 AR_WRITE(sc, AR_IMR_S2, mask2); 2096 2097 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2098 2099 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2100 2101 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2102 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2103 2104 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2105 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2106 AR_WRITE_BARRIER(sc); 2107 } 2108 2109 Static void 2110 athn_disable_interrupts(struct athn_softc *sc) 2111 { 2112 2113 AR_WRITE(sc, AR_IER, 0); 2114 (void)AR_READ(sc, AR_IER); 2115 2116 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2117 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2118 2119 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2120 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2121 2122 AR_WRITE(sc, AR_IMR, 0); 2123 2124 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2125 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2126 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2127 2128 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2129 AR_WRITE_BARRIER(sc); 2130 } 2131 2132 Static void 2133 athn_init_qos(struct athn_softc *sc) 2134 { 2135 2136 /* Initialize QoS settings. */ 2137 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2138 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2139 AR_WRITE(sc, AR_QOS_NO_ACK, 2140 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2141 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2142 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2143 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2144 /* Initialize TXOP for all TIDs. */ 2145 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2146 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2147 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2148 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2149 AR_WRITE_BARRIER(sc); 2150 } 2151 2152 PUBLIC int 2153 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2154 struct ieee80211_channel *extchan, int init) 2155 { 2156 struct ieee80211com *ic = &sc->sc_ic; 2157 struct athn_ops *ops = &sc->sc_ops; 2158 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2159 int i, error; 2160 2161 /* XXX not if already awake */ 2162 if ((error = athn_set_power_awake(sc)) != 0) { 2163 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2164 return error; 2165 } 2166 2167 /* Preserve the antenna on a channel switch. */ 2168 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2169 def_ant = 1; 2170 /* Preserve other registers. */ 2171 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2172 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2173 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2174 AR_CFG_LED_BLINK_SLOW); 2175 2176 /* Mark PHY as inactive. */ 2177 ops->disable_phy(sc); 2178 2179 if (init && AR_SREV_9271(sc)) { 2180 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2181 AR9271_RADIO_RF_RST); 2182 DELAY(50); 2183 } 2184 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2185 /* Save TSF before it gets cleared. */ 2186 tsfhi = AR_READ(sc, AR_TSF_U32); 2187 tsflo = AR_READ(sc, AR_TSF_L32); 2188 2189 /* NB: RTC reset clears TSF. */ 2190 error = athn_reset_power_on(sc); 2191 } 2192 else { 2193 tsfhi = tsflo = 0; /* XXX: gcc */ 2194 error = athn_reset(sc, 0); 2195 } 2196 if (error != 0) { 2197 aprint_error_dev(sc->sc_dev, 2198 "could not reset chip (error=%d)\n", error); 2199 return error; 2200 } 2201 2202 /* XXX not if already awake */ 2203 if ((error = athn_set_power_awake(sc)) != 0) { 2204 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2205 return error; 2206 } 2207 2208 athn_init_pll(sc, curchan); 2209 ops->set_rf_mode(sc, curchan); 2210 2211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2212 /* Check that the radio is not disabled by hardware switch. */ 2213 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2214 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2215 reg = !reg; 2216 if (!reg) { 2217 aprint_error_dev(sc->sc_dev, 2218 "radio is disabled by hardware switch\n"); 2219 return EPERM; 2220 } 2221 } 2222 if (init && AR_SREV_9271(sc)) { 2223 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2224 AR9271_GATE_MAC_CTL); 2225 DELAY(50); 2226 } 2227 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2228 /* Restore TSF if it got cleared. */ 2229 AR_WRITE(sc, AR_TSF_L32, tsflo); 2230 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2231 } 2232 2233 if (AR_SREV_9280_10_OR_LATER(sc)) 2234 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2235 2236 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2237 ar9287_1_3_enable_async_fifo(sc); 2238 2239 /* Write init values to hardware. */ 2240 ops->hw_init(sc, curchan, extchan); 2241 2242 /* 2243 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2244 * management frames using CCMP. 2245 */ 2246 if (AR_SREV_9280_20_OR_LATER(sc)) { 2247 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2248 /* Do not mask the subtype field in management frames. */ 2249 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2250 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2251 ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2252 IEEE80211_FC1_MORE_DATA)); 2253 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2254 } 2255 else if (AR_SREV_9160_10_OR_LATER(sc)) { 2256 /* Disable hardware crypto for management frames. */ 2257 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2258 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2259 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2260 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2261 } 2262 2263 if (ic->ic_curmode != IEEE80211_MODE_11B) 2264 ops->set_delta_slope(sc, curchan, extchan); 2265 2266 ops->spur_mitigate(sc, curchan, extchan); 2267 ops->init_from_rom(sc, curchan, extchan); 2268 2269 /* XXX */ 2270 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2271 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2272 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2273 2274 athn_set_opmode(sc); 2275 2276 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2277 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2278 2279 /* Restore previous antenna. */ 2280 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2281 2282 AR_WRITE(sc, AR_BSS_ID0, 0); 2283 AR_WRITE(sc, AR_BSS_ID1, 0); 2284 2285 AR_WRITE(sc, AR_ISR, 0xffffffff); 2286 2287 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2288 2289 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2290 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2291 return error; 2292 } 2293 sc->sc_curchan = curchan; 2294 sc->sc_curchanext = extchan; 2295 2296 for (i = 0; i < AR_NUM_DCU; i++) 2297 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2298 2299 athn_init_tx_queues(sc); 2300 2301 /* Initialize interrupt mask. */ 2302 sc->sc_imask = 2303 AR_IMR_TXDESC | AR_IMR_TXEOL | 2304 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2305 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2306 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2307 if (AR_SREV_9380_10_OR_LATER(sc)) 2308 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2309 #ifndef IEEE80211_STA_ONLY 2310 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2311 sc->sc_imask |= AR_IMR_MIB; 2312 #endif 2313 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2314 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2315 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2316 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2317 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2318 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2319 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2320 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2321 if (AR_SREV_9380_10_OR_LATER(sc)) { 2322 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2323 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2324 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2325 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2326 } 2327 2328 athn_init_qos(sc); 2329 2330 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2331 2332 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2333 ar9287_1_3_setup_async_fifo(sc); 2334 2335 /* Disable sequence number generation in hardware. */ 2336 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2337 2338 athn_init_dma(sc); 2339 2340 /* Program observation bus to see MAC interrupts. */ 2341 AR_WRITE(sc, sc->sc_obs_off, 8); 2342 2343 /* Setup Rx interrupt mitigation. */ 2344 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2345 2346 ops->init_baseband(sc); 2347 2348 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2349 aprint_error_dev(sc->sc_dev, 2350 "could not initialize calibration\n"); 2351 return error; 2352 } 2353 2354 ops->set_rxchains(sc); 2355 2356 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2357 2358 if (sc->sc_flags & ATHN_FLAG_USB) { 2359 if (AR_SREV_9271(sc)) 2360 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2361 else 2362 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2363 } 2364 #if BYTE_ORDER == BIG_ENDIAN 2365 else { 2366 /* Default is LE, turn on swapping for BE. */ 2367 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2368 } 2369 #endif 2370 AR_WRITE_BARRIER(sc); 2371 2372 return 0; 2373 } 2374 2375 Static struct ieee80211_node * 2376 athn_node_alloc(struct ieee80211_node_table *ntp) 2377 { 2378 2379 return malloc(sizeof(struct athn_node), M_DEVBUF, 2380 M_NOWAIT | M_ZERO); 2381 } 2382 2383 Static void 2384 athn_newassoc(struct ieee80211_node *ni, int isnew) 2385 { 2386 struct ieee80211com *ic = ni->ni_ic; 2387 struct athn_softc *sc = ic->ic_ifp->if_softc; 2388 struct athn_node *an = (void *)ni; 2389 struct ieee80211_rateset *rs = &ni->ni_rates; 2390 uint8_t rate; 2391 int ridx, i, j; 2392 2393 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2394 /* Start at lowest available bit-rate, AMRR will raise. */ 2395 ni->ni_txrate = 0; 2396 2397 for (i = 0; i < rs->rs_nrates; i++) { 2398 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2399 2400 /* Map 802.11 rate to HW rate index. */ 2401 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2402 if (athn_rates[ridx].rate == rate) 2403 break; 2404 an->ridx[i] = ridx; 2405 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2406 2407 /* Compute fallback rate for retries. */ 2408 an->fallback[i] = i; 2409 for (j = i - 1; j >= 0; j--) { 2410 if (athn_rates[an->ridx[j]].phy == 2411 athn_rates[an->ridx[i]].phy) { 2412 an->fallback[i] = j; 2413 break; 2414 } 2415 } 2416 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2417 i, an->fallback[i]); 2418 } 2419 } 2420 2421 Static int 2422 athn_media_change(struct ifnet *ifp) 2423 { 2424 struct athn_softc *sc = ifp->if_softc; 2425 struct ieee80211com *ic = &sc->sc_ic; 2426 uint8_t rate, ridx; 2427 int error; 2428 2429 error = ieee80211_media_change(ifp); 2430 if (error != ENETRESET) 2431 return error; 2432 2433 if (ic->ic_fixed_rate != -1) { 2434 rate = ic->ic_sup_rates[ic->ic_curmode]. 2435 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2436 /* Map 802.11 rate to HW rate index. */ 2437 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2438 if (athn_rates[ridx].rate == rate) 2439 break; 2440 sc->sc_fixed_ridx = ridx; 2441 } 2442 if (IS_UP_AND_RUNNING(ifp)) { 2443 athn_stop(ifp, 0); 2444 error = athn_init(ifp); 2445 } 2446 return error; 2447 } 2448 2449 Static void 2450 athn_next_scan(void *arg) 2451 { 2452 struct athn_softc *sc = arg; 2453 struct ieee80211com *ic = &sc->sc_ic; 2454 int s; 2455 2456 s = splnet(); 2457 if (ic->ic_state == IEEE80211_S_SCAN) 2458 ieee80211_next_scan(ic); 2459 splx(s); 2460 } 2461 2462 Static int 2463 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2464 { 2465 struct ifnet *ifp = ic->ic_ifp; 2466 struct athn_softc *sc = ifp->if_softc; 2467 uint32_t reg; 2468 int error; 2469 2470 callout_stop(&sc->sc_calib_to); 2471 2472 switch (nstate) { 2473 case IEEE80211_S_INIT: 2474 athn_set_led(sc, 0); 2475 break; 2476 case IEEE80211_S_SCAN: 2477 /* Make the LED blink while scanning. */ 2478 athn_set_led(sc, !sc->sc_led_state); 2479 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2480 if (error != 0) 2481 return error; 2482 callout_schedule(&sc->sc_scan_to, hz / 5); 2483 break; 2484 case IEEE80211_S_AUTH: 2485 athn_set_led(sc, 0); 2486 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2487 if (error != 0) 2488 return error; 2489 break; 2490 case IEEE80211_S_ASSOC: 2491 break; 2492 case IEEE80211_S_RUN: 2493 athn_set_led(sc, 1); 2494 2495 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2496 break; 2497 2498 /* Fake a join to initialize the Tx rate. */ 2499 athn_newassoc(ic->ic_bss, 1); 2500 2501 athn_set_bss(sc, ic->ic_bss); 2502 athn_disable_interrupts(sc); 2503 #ifndef IEEE80211_STA_ONLY 2504 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2505 athn_set_hostap_timers(sc); 2506 /* Enable software beacon alert interrupts. */ 2507 sc->sc_imask |= AR_IMR_SWBA; 2508 } 2509 else 2510 #endif 2511 { 2512 athn_set_sta_timers(sc); 2513 /* Enable beacon miss interrupts. */ 2514 sc->sc_imask |= AR_IMR_BMISS; 2515 2516 /* Stop receiving beacons from other BSS. */ 2517 reg = AR_READ(sc, AR_RX_FILTER); 2518 reg = (reg & ~AR_RX_FILTER_BEACON) | 2519 AR_RX_FILTER_MYBEACON; 2520 AR_WRITE(sc, AR_RX_FILTER, reg); 2521 AR_WRITE_BARRIER(sc); 2522 } 2523 athn_enable_interrupts(sc); 2524 2525 if (sc->sc_sup_calib_mask != 0) { 2526 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2527 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2528 /* ops->do_calib(sc); */ 2529 } 2530 /* XXX Start ANI. */ 2531 2532 callout_schedule(&sc->sc_calib_to, hz / 2); 2533 break; 2534 } 2535 2536 return sc->sc_newstate(ic, nstate, arg); 2537 } 2538 2539 #ifdef notyet_edca 2540 PUBLIC void 2541 athn_updateedca(struct ieee80211com *ic) 2542 { 2543 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2544 struct athn_softc *sc = ic->ic_ifp->if_softc; 2545 const struct ieee80211_edca_ac_params *ac; 2546 int aci, qid; 2547 2548 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2549 ac = &ic->ic_edca_ac[aci]; 2550 qid = athn_ac2qid[aci]; 2551 2552 AR_WRITE(sc, AR_DLCL_IFS(qid), 2553 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2554 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2555 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2556 if (ac->ac_txoplimit != 0) { 2557 AR_WRITE(sc, AR_DCHNTIME(qid), 2558 SM(AR_D_CHNTIME_DUR, 2559 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2560 AR_D_CHNTIME_EN); 2561 } 2562 else 2563 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2564 } 2565 AR_WRITE_BARRIER(sc); 2566 #undef ATHN_EXP2 2567 } 2568 #endif /* notyet_edca */ 2569 2570 Static int 2571 athn_clock_rate(struct athn_softc *sc) 2572 { 2573 struct ieee80211com *ic = &sc->sc_ic; 2574 int clockrate; /* MHz. */ 2575 2576 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2577 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2578 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2579 else 2580 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2581 } 2582 else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2583 clockrate = AR_CLOCK_RATE_CCK; 2584 } 2585 else 2586 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2587 #ifndef IEEE80211_NO_HT 2588 if (sc->sc_curchanext != NULL) 2589 clockrate *= 2; 2590 #endif 2591 return clockrate; 2592 } 2593 2594 PUBLIC void 2595 athn_updateslot(struct ifnet *ifp) 2596 { 2597 struct athn_softc *sc = ifp->if_softc; 2598 struct ieee80211com *ic = &sc->sc_ic; 2599 int slot; 2600 2601 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2602 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2603 AR_WRITE_BARRIER(sc); 2604 } 2605 2606 Static void 2607 athn_start(struct ifnet *ifp) 2608 { 2609 struct athn_softc *sc = ifp->if_softc; 2610 struct ieee80211com *ic = &sc->sc_ic; 2611 struct ether_header *eh; 2612 struct ieee80211_node *ni; 2613 struct mbuf *m; 2614 2615 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2616 || !device_is_active(sc->sc_dev)) 2617 return; 2618 2619 for (;;) { 2620 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2621 ifp->if_flags |= IFF_OACTIVE; 2622 break; 2623 } 2624 /* Send pending management frames first. */ 2625 IF_DEQUEUE(&ic->ic_mgtq, m); 2626 if (m != NULL) { 2627 ni = (void *)m->m_pkthdr.rcvif; 2628 goto sendit; 2629 } 2630 if (ic->ic_state != IEEE80211_S_RUN) 2631 break; 2632 2633 /* Encapsulate and send data frames. */ 2634 IFQ_DEQUEUE(&ifp->if_snd, m); 2635 if (m == NULL) 2636 break; 2637 2638 if (m->m_len < (int)sizeof(*eh) && 2639 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2640 ifp->if_oerrors++; 2641 continue; 2642 } 2643 eh = mtod(m, struct ether_header *); 2644 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2645 if (ni == NULL) { 2646 m_freem(m); 2647 ifp->if_oerrors++; 2648 continue; 2649 } 2650 2651 bpf_mtap(ifp, m); 2652 2653 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2654 continue; 2655 sendit: 2656 bpf_mtap3(ic->ic_rawbpf, m); 2657 2658 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2659 ieee80211_free_node(ni); 2660 ifp->if_oerrors++; 2661 continue; 2662 } 2663 2664 sc->sc_tx_timer = 5; 2665 ifp->if_timer = 1; 2666 } 2667 } 2668 2669 Static void 2670 athn_watchdog(struct ifnet *ifp) 2671 { 2672 struct athn_softc *sc = ifp->if_softc; 2673 2674 ifp->if_timer = 0; 2675 2676 if (sc->sc_tx_timer > 0) { 2677 if (--sc->sc_tx_timer == 0) { 2678 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2679 /* see athn_init, no need to call athn_stop here */ 2680 /* athn_stop(ifp, 0); */ 2681 (void)athn_init(ifp); 2682 ifp->if_oerrors++; 2683 return; 2684 } 2685 ifp->if_timer = 1; 2686 } 2687 ieee80211_watchdog(&sc->sc_ic); 2688 } 2689 2690 #ifdef notyet 2691 Static void 2692 athn_set_multi(struct athn_softc *sc) 2693 { 2694 struct arpcom *ac = &sc->sc_ic.ic_ac; 2695 struct ifnet *ifp = &ac->ac_if; 2696 struct ether_multi *enm; 2697 struct ether_multistep step; 2698 const uint8_t *addr; 2699 uint32_t val, lo, hi; 2700 uint8_t bit; 2701 2702 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2703 lo = hi = 0xffffffff; 2704 goto done; 2705 } 2706 lo = hi = 0; 2707 ETHER_FIRST_MULTI(step, ac, enm); 2708 while (enm != NULL) { 2709 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2710 ifp->if_flags |= IFF_ALLMULTI; 2711 lo = hi = 0xffffffff; 2712 goto done; 2713 } 2714 addr = enm->enm_addrlo; 2715 /* Calculate the XOR value of all eight 6-bit words. */ 2716 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2717 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2718 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2719 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2720 bit &= 0x3f; 2721 if (bit < 32) 2722 lo |= 1 << bit; 2723 else 2724 hi |= 1 << (bit - 32); 2725 ETHER_NEXT_MULTI(step, enm); 2726 } 2727 done: 2728 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2729 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2730 AR_WRITE_BARRIER(sc); 2731 } 2732 #endif /* notyet */ 2733 2734 Static int 2735 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2736 { 2737 struct athn_softc *sc = ifp->if_softc; 2738 struct ieee80211com *ic = &sc->sc_ic; 2739 int s, error = 0; 2740 2741 s = splnet(); 2742 2743 switch (cmd) { 2744 case SIOCSIFFLAGS: 2745 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2746 break; 2747 2748 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2749 case IFF_UP | IFF_RUNNING: 2750 #ifdef notyet 2751 if (((ifp->if_flags ^ sc->sc_if_flags) & 2752 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2753 /* XXX: setup multi */ 2754 #endif 2755 break; 2756 case IFF_UP: 2757 athn_init(ifp); 2758 break; 2759 2760 case IFF_RUNNING: 2761 athn_stop(ifp, 1); 2762 break; 2763 case 0: 2764 default: 2765 break; 2766 } 2767 sc->sc_if_flags = ifp->if_flags; 2768 break; 2769 2770 case SIOCADDMULTI: 2771 case SIOCDELMULTI: 2772 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2773 /* setup multicast filter, etc */ 2774 #ifdef notyet 2775 athn_set_multi(sc); 2776 #endif 2777 error = 0; 2778 } 2779 break; 2780 2781 case SIOCS80211CHANNEL: 2782 error = ieee80211_ioctl(ic, cmd, data); 2783 if (error == ENETRESET && 2784 ic->ic_opmode == IEEE80211_M_MONITOR) { 2785 if (IS_UP_AND_RUNNING(ifp)) 2786 athn_switch_chan(sc, ic->ic_curchan, NULL); 2787 error = 0; 2788 } 2789 break; 2790 2791 default: 2792 error = ieee80211_ioctl(ic, cmd, data); 2793 } 2794 2795 if (error == ENETRESET) { 2796 error = 0; 2797 if (IS_UP_AND_RUNNING(ifp) && 2798 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2799 athn_stop(ifp, 0); 2800 error = athn_init(ifp); 2801 } 2802 } 2803 2804 splx(s); 2805 return error; 2806 } 2807 2808 Static int 2809 athn_init(struct ifnet *ifp) 2810 { 2811 struct athn_softc *sc = ifp->if_softc; 2812 struct athn_ops *ops = &sc->sc_ops; 2813 struct ieee80211com *ic = &sc->sc_ic; 2814 struct ieee80211_channel *curchan, *extchan; 2815 size_t i; 2816 int error; 2817 2818 KASSERT(!cpu_intr_p()); 2819 2820 if (device_is_active(sc->sc_dev)) { 2821 athn_stop(ifp, 0); /* see athn_watchdog() */ 2822 } else { 2823 short flags = ifp->if_flags; 2824 ifp->if_flags &= ~IFF_UP; 2825 /* avoid recursion in athn_resume */ 2826 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2827 !device_is_active(sc->sc_dev)) { 2828 aprint_error_dev(sc->sc_dev, 2829 "failed to power up device\n"); 2830 return 0; 2831 } 2832 ifp->if_flags = flags; 2833 } 2834 2835 curchan = ic->ic_curchan; 2836 extchan = NULL; 2837 2838 /* In case a new MAC address has been configured. */ 2839 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2840 2841 #ifdef openbsd_power_management 2842 /* For CardBus, power on the socket. */ 2843 if (sc->sc_enable != NULL) { 2844 if ((error = sc->sc_enable(sc)) != 0) { 2845 aprint_error_dev(sc->sc_dev, 2846 "could not enable device\n"); 2847 goto fail; 2848 } 2849 if ((error = athn_reset_power_on(sc)) != 0) { 2850 aprint_error_dev(sc->sc_dev, 2851 "could not power on device\n"); 2852 goto fail; 2853 } 2854 } 2855 #endif 2856 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2857 athn_config_nonpcie(sc); 2858 else 2859 athn_config_pcie(sc); 2860 2861 /* Reset HW key cache entries. */ 2862 for (i = 0; i < sc->sc_kc_entries; i++) 2863 athn_reset_key(sc, i); 2864 2865 ops->enable_antenna_diversity(sc); 2866 2867 #ifdef ATHN_BT_COEXISTENCE 2868 /* Configure bluetooth coexistence for combo chips. */ 2869 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2870 athn_btcoex_init(sc); 2871 #endif 2872 2873 /* Configure LED. */ 2874 athn_led_init(sc); 2875 2876 /* Configure hardware radio switch. */ 2877 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2878 ops->rfsilent_init(sc); 2879 2880 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2881 aprint_error_dev(sc->sc_dev, 2882 "unable to reset hardware; reset status %d\n", error); 2883 goto fail; 2884 } 2885 2886 /* Enable Rx. */ 2887 athn_rx_start(sc); 2888 2889 /* Enable interrupts. */ 2890 athn_enable_interrupts(sc); 2891 2892 #ifdef ATHN_BT_COEXISTENCE 2893 /* Enable bluetooth coexistence for combo chips. */ 2894 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2895 athn_btcoex_enable(sc); 2896 #endif 2897 2898 ifp->if_flags &= ~IFF_OACTIVE; 2899 ifp->if_flags |= IFF_RUNNING; 2900 2901 #ifdef notyet 2902 if (ic->ic_flags & IEEE80211_F_WEPON) { 2903 /* Configure WEP keys. */ 2904 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2905 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2906 } 2907 #endif 2908 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2909 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2910 else 2911 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2912 2913 return 0; 2914 fail: 2915 athn_stop(ifp, 1); 2916 return error; 2917 } 2918 2919 PUBLIC void 2920 athn_stop(struct ifnet *ifp, int disable) 2921 { 2922 struct athn_softc *sc = ifp->if_softc; 2923 struct ieee80211com *ic = &sc->sc_ic; 2924 int qid; 2925 2926 ifp->if_timer = sc->sc_tx_timer = 0; 2927 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2928 2929 callout_stop(&sc->sc_scan_to); 2930 /* In case we were scanning, release the scan "lock". */ 2931 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2932 2933 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2934 2935 #ifdef ATHN_BT_COEXISTENCE 2936 /* Disable bluetooth coexistence for combo chips. */ 2937 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2938 athn_btcoex_disable(sc); 2939 #endif 2940 2941 /* Disable interrupts. */ 2942 athn_disable_interrupts(sc); 2943 /* Acknowledge interrupts (avoids interrupt storms). */ 2944 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2945 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2946 2947 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2948 athn_stop_tx_dma(sc, qid); 2949 /* XXX call athn_hw_reset if Tx still pending? */ 2950 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2951 athn_tx_reclaim(sc, qid); 2952 2953 /* Stop Rx. */ 2954 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2955 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2956 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2957 AR_WRITE(sc, AR_FILT_OFDM, 0); 2958 AR_WRITE(sc, AR_FILT_CCK, 0); 2959 AR_WRITE_BARRIER(sc); 2960 athn_set_rxfilter(sc, 0); 2961 athn_stop_rx_dma(sc); 2962 2963 athn_reset(sc, 0); 2964 athn_init_pll(sc, NULL); 2965 athn_set_power_awake(sc); 2966 athn_reset(sc, 1); 2967 athn_init_pll(sc, NULL); 2968 2969 athn_set_power_sleep(sc); 2970 2971 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 2972 /* For CardBus, power down the socket. */ 2973 if (disable && sc->sc_disable != NULL) 2974 sc->sc_disable(sc); 2975 #endif 2976 if (disable) 2977 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2978 } 2979 2980 Static void 2981 athn_pmf_wlan_off(device_t self) 2982 { 2983 struct athn_softc *sc = device_private(self); 2984 struct ifnet *ifp = &sc->sc_if; 2985 2986 /* Turn the interface down. */ 2987 ifp->if_flags &= ~IFF_UP; 2988 athn_stop(ifp, 1); 2989 } 2990 2991 PUBLIC void 2992 athn_suspend(struct athn_softc *sc) 2993 { 2994 struct ifnet *ifp = &sc->sc_if; 2995 2996 if (ifp->if_flags & IFF_RUNNING) 2997 athn_stop(ifp, 1); 2998 } 2999 3000 PUBLIC bool 3001 athn_resume(struct athn_softc *sc) 3002 { 3003 struct ifnet *ifp = &sc->sc_if; 3004 3005 if (ifp->if_flags & IFF_UP) 3006 athn_init(ifp); 3007 3008 return true; 3009 } 3010