1 /* $NetBSD: ath.c,v 1.102 2008/07/09 19:47:24 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.102 2008/07/09 19:47:24 joerg Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/errno.h> 71 #include <sys/callout.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/if_ether.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_netbsd.h> 84 #include <net80211/ieee80211_var.h> 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #endif 93 94 #include <sys/device.h> 95 #include <dev/ic/ath_netbsd.h> 96 97 #define AR_DEBUG 98 #include <dev/ic/athvar.h> 99 #include <contrib/dev/ath/ah_desc.h> 100 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 101 #include "athhal_options.h" 102 103 #ifdef ATH_TX99_DIAG 104 #include <dev/ath/ath_tx99/ath_tx99.h> 105 #endif 106 107 /* unaligned little endian access */ 108 #define LE_READ_2(p) \ 109 ((u_int16_t) \ 110 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 111 #define LE_READ_4(p) \ 112 ((u_int32_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 114 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 115 116 enum { 117 ATH_LED_TX, 118 ATH_LED_RX, 119 ATH_LED_POLL, 120 }; 121 122 #ifdef AH_NEED_DESC_SWAP 123 #define HTOAH32(x) htole32(x) 124 #else 125 #define HTOAH32(x) (x) 126 #endif 127 128 static int ath_ifinit(struct ifnet *); 129 static int ath_init(struct ath_softc *); 130 static void ath_stop_locked(struct ifnet *, int); 131 static void ath_stop(struct ifnet *, int); 132 static void ath_start(struct ifnet *); 133 static int ath_media_change(struct ifnet *); 134 static void ath_watchdog(struct ifnet *); 135 static int ath_ioctl(struct ifnet *, u_long, void *); 136 static void ath_fatal_proc(void *, int); 137 static void ath_rxorn_proc(void *, int); 138 static void ath_bmiss_proc(void *, int); 139 static void ath_radar_proc(void *, int); 140 static int ath_key_alloc(struct ieee80211com *, 141 const struct ieee80211_key *, 142 ieee80211_keyix *, ieee80211_keyix *); 143 static int ath_key_delete(struct ieee80211com *, 144 const struct ieee80211_key *); 145 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 146 const u_int8_t mac[IEEE80211_ADDR_LEN]); 147 static void ath_key_update_begin(struct ieee80211com *); 148 static void ath_key_update_end(struct ieee80211com *); 149 static void ath_mode_init(struct ath_softc *); 150 static void ath_setslottime(struct ath_softc *); 151 static void ath_updateslot(struct ifnet *); 152 static int ath_beaconq_setup(struct ath_hal *); 153 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 154 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 155 static void ath_beacon_proc(void *, int); 156 static void ath_bstuck_proc(void *, int); 157 static void ath_beacon_free(struct ath_softc *); 158 static void ath_beacon_config(struct ath_softc *); 159 static void ath_descdma_cleanup(struct ath_softc *sc, 160 struct ath_descdma *, ath_bufhead *); 161 static int ath_desc_alloc(struct ath_softc *); 162 static void ath_desc_free(struct ath_softc *); 163 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 164 static void ath_node_free(struct ieee80211_node *); 165 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 166 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 167 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 168 struct ieee80211_node *ni, 169 int subtype, int rssi, u_int32_t rstamp); 170 static void ath_setdefantenna(struct ath_softc *, u_int); 171 static void ath_rx_proc(void *, int); 172 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 173 static int ath_tx_setup(struct ath_softc *, int, int); 174 static int ath_wme_update(struct ieee80211com *); 175 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 176 static void ath_tx_cleanup(struct ath_softc *); 177 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 178 struct ath_buf *, struct mbuf *); 179 static void ath_tx_proc_q0(void *, int); 180 static void ath_tx_proc_q0123(void *, int); 181 static void ath_tx_proc(void *, int); 182 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_draintxq(struct ath_softc *); 184 static void ath_stoprecv(struct ath_softc *); 185 static int ath_startrecv(struct ath_softc *); 186 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 187 static void ath_next_scan(void *); 188 static void ath_calibrate(void *); 189 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 190 static void ath_setup_stationkey(struct ieee80211_node *); 191 static void ath_newassoc(struct ieee80211_node *, int); 192 static int ath_getchannels(struct ath_softc *, u_int cc, 193 HAL_BOOL outdoor, HAL_BOOL xchanmode); 194 static void ath_led_event(struct ath_softc *, int); 195 static void ath_update_txpow(struct ath_softc *); 196 static void ath_freetx(struct mbuf *); 197 static void ath_restore_diversity(struct ath_softc *); 198 199 static int ath_rate_setup(struct ath_softc *, u_int mode); 200 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 201 202 #if NBPFILTER > 0 203 static void ath_bpfattach(struct ath_softc *); 204 #endif 205 static void ath_announce(struct ath_softc *); 206 207 int ath_dwelltime = 200; /* 5 channels/second */ 208 int ath_calinterval = 30; /* calibrate every 30 secs */ 209 int ath_outdoor = AH_TRUE; /* outdoor operation */ 210 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 211 int ath_countrycode = CTRY_DEFAULT; /* country code */ 212 int ath_regdomain = 0; /* regulatory domain */ 213 int ath_debug = 0; 214 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 215 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 216 217 #ifdef AR_DEBUG 218 enum { 219 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 220 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 221 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 222 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 223 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 224 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 225 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 226 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 227 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 228 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 229 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 230 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 231 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 232 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 233 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 234 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 235 ATH_DEBUG_NODE = 0x00080000, /* node management */ 236 ATH_DEBUG_LED = 0x00100000, /* led management */ 237 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 238 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 239 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 240 ATH_DEBUG_ANY = 0xffffffff 241 }; 242 #define IFF_DUMPPKTS(sc, m) \ 243 ((sc->sc_debug & (m)) || \ 244 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245 #define DPRINTF(sc, m, fmt, ...) do { \ 246 if (sc->sc_debug & (m)) \ 247 printf(fmt, __VA_ARGS__); \ 248 } while (0) 249 #define KEYPRINTF(sc, ix, hk, mac) do { \ 250 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 251 ath_keyprint(__func__, ix, hk, mac); \ 252 } while (0) 253 static void ath_printrxbuf(struct ath_buf *bf, int); 254 static void ath_printtxbuf(struct ath_buf *bf, int); 255 #else 256 #define IFF_DUMPPKTS(sc, m) \ 257 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 258 #define DPRINTF(m, fmt, ...) 259 #define KEYPRINTF(sc, k, ix, mac) 260 #endif 261 262 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 263 264 int 265 ath_attach(u_int16_t devid, struct ath_softc *sc) 266 { 267 struct ifnet *ifp = &sc->sc_if; 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ath_hal *ah = NULL; 270 HAL_STATUS status; 271 int error = 0, i; 272 273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 274 275 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 276 277 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 278 if (ah == NULL) { 279 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 280 status); 281 error = ENXIO; 282 goto bad; 283 } 284 if (ah->ah_abi != HAL_ABI_VERSION) { 285 if_printf(ifp, "HAL ABI mismatch detected " 286 "(HAL:0x%x != driver:0x%x)\n", 287 ah->ah_abi, HAL_ABI_VERSION); 288 error = ENXIO; 289 goto bad; 290 } 291 sc->sc_ah = ah; 292 293 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 294 "pmf-powerdown", false)) 295 goto bad; 296 297 /* 298 * Check if the MAC has multi-rate retry support. 299 * We do this by trying to setup a fake extended 300 * descriptor. MAC's that don't have support will 301 * return false w/o doing anything. MAC's that do 302 * support it will return true w/o doing anything. 303 */ 304 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 305 306 /* 307 * Check if the device has hardware counters for PHY 308 * errors. If so we need to enable the MIB interrupt 309 * so we can act on stat triggers. 310 */ 311 if (ath_hal_hwphycounters(ah)) 312 sc->sc_needmib = 1; 313 314 /* 315 * Get the hardware key cache size. 316 */ 317 sc->sc_keymax = ath_hal_keycachesize(ah); 318 if (sc->sc_keymax > ATH_KEYMAX) { 319 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 320 ATH_KEYMAX, sc->sc_keymax); 321 sc->sc_keymax = ATH_KEYMAX; 322 } 323 /* 324 * Reset the key cache since some parts do not 325 * reset the contents on initial power up. 326 */ 327 for (i = 0; i < sc->sc_keymax; i++) 328 ath_hal_keyreset(ah, i); 329 /* 330 * Mark key cache slots associated with global keys 331 * as in use. If we knew TKIP was not to be used we 332 * could leave the +32, +64, and +32+64 slots free. 333 * XXX only for splitmic. 334 */ 335 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 336 setbit(sc->sc_keymap, i); 337 setbit(sc->sc_keymap, i+32); 338 setbit(sc->sc_keymap, i+64); 339 setbit(sc->sc_keymap, i+32+64); 340 } 341 342 /* 343 * Collect the channel list using the default country 344 * code and including outdoor channels. The 802.11 layer 345 * is resposible for filtering this list based on settings 346 * like the phy mode. 347 */ 348 error = ath_getchannels(sc, ath_countrycode, 349 ath_outdoor, ath_xchanmode); 350 if (error != 0) 351 goto bad; 352 353 /* 354 * Setup rate tables for all potential media types. 355 */ 356 ath_rate_setup(sc, IEEE80211_MODE_11A); 357 ath_rate_setup(sc, IEEE80211_MODE_11B); 358 ath_rate_setup(sc, IEEE80211_MODE_11G); 359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 360 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 361 /* NB: setup here so ath_rate_update is happy */ 362 ath_setcurmode(sc, IEEE80211_MODE_11A); 363 364 /* 365 * Allocate tx+rx descriptors and populate the lists. 366 */ 367 error = ath_desc_alloc(sc); 368 if (error != 0) { 369 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 370 goto bad; 371 } 372 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 373 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 374 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 375 376 ATH_TXBUF_LOCK_INIT(sc); 377 378 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 379 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 380 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 381 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 382 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 383 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 384 385 /* 386 * Allocate hardware transmit queues: one queue for 387 * beacon frames and one data queue for each QoS 388 * priority. Note that the hal handles reseting 389 * these queues at the needed time. 390 * 391 * XXX PS-Poll 392 */ 393 sc->sc_bhalq = ath_beaconq_setup(ah); 394 if (sc->sc_bhalq == (u_int) -1) { 395 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 396 error = EIO; 397 goto bad2; 398 } 399 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 400 if (sc->sc_cabq == NULL) { 401 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 402 error = EIO; 403 goto bad2; 404 } 405 /* NB: insure BK queue is the lowest priority h/w queue */ 406 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 407 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 408 ieee80211_wme_acnames[WME_AC_BK]); 409 error = EIO; 410 goto bad2; 411 } 412 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 413 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 414 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 415 /* 416 * Not enough hardware tx queues to properly do WME; 417 * just punt and assign them all to the same h/w queue. 418 * We could do a better job of this if, for example, 419 * we allocate queues when we switch from station to 420 * AP mode. 421 */ 422 if (sc->sc_ac2q[WME_AC_VI] != NULL) 423 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 424 if (sc->sc_ac2q[WME_AC_BE] != NULL) 425 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 426 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 427 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 428 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 429 } 430 431 /* 432 * Special case certain configurations. Note the 433 * CAB queue is handled by these specially so don't 434 * include them when checking the txq setup mask. 435 */ 436 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 437 case 0x01: 438 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 439 break; 440 case 0x0f: 441 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 442 break; 443 default: 444 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 445 break; 446 } 447 448 /* 449 * Setup rate control. Some rate control modules 450 * call back to change the anntena state so expose 451 * the necessary entry points. 452 * XXX maybe belongs in struct ath_ratectrl? 453 */ 454 sc->sc_setdefantenna = ath_setdefantenna; 455 sc->sc_rc = ath_rate_attach(sc); 456 if (sc->sc_rc == NULL) { 457 error = EIO; 458 goto bad2; 459 } 460 461 sc->sc_blinking = 0; 462 sc->sc_ledstate = 1; 463 sc->sc_ledon = 0; /* low true */ 464 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 465 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 466 /* 467 * Auto-enable soft led processing for IBM cards and for 468 * 5211 minipci cards. Users can also manually enable/disable 469 * support with a sysctl. 470 */ 471 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 472 if (sc->sc_softled) { 473 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 474 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 475 } 476 477 ifp->if_softc = sc; 478 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 479 ifp->if_start = ath_start; 480 ifp->if_stop = ath_stop; 481 ifp->if_watchdog = ath_watchdog; 482 ifp->if_ioctl = ath_ioctl; 483 ifp->if_init = ath_ifinit; 484 IFQ_SET_READY(&ifp->if_snd); 485 486 ic->ic_ifp = ifp; 487 ic->ic_reset = ath_reset; 488 ic->ic_newassoc = ath_newassoc; 489 ic->ic_updateslot = ath_updateslot; 490 ic->ic_wme.wme_update = ath_wme_update; 491 /* XXX not right but it's not used anywhere important */ 492 ic->ic_phytype = IEEE80211_T_OFDM; 493 ic->ic_opmode = IEEE80211_M_STA; 494 ic->ic_caps = 495 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 496 | IEEE80211_C_HOSTAP /* hostap mode */ 497 | IEEE80211_C_MONITOR /* monitor mode */ 498 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 499 | IEEE80211_C_SHSLOT /* short slot time supported */ 500 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 501 | IEEE80211_C_TXFRAG /* handle tx frags */ 502 ; 503 /* 504 * Query the hal to figure out h/w crypto support. 505 */ 506 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 507 ic->ic_caps |= IEEE80211_C_WEP; 508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 509 ic->ic_caps |= IEEE80211_C_AES; 510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 511 ic->ic_caps |= IEEE80211_C_AES_CCM; 512 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 513 ic->ic_caps |= IEEE80211_C_CKIP; 514 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 515 ic->ic_caps |= IEEE80211_C_TKIP; 516 /* 517 * Check if h/w does the MIC and/or whether the 518 * separate key cache entries are required to 519 * handle both tx+rx MIC keys. 520 */ 521 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 522 ic->ic_caps |= IEEE80211_C_TKIPMIC; 523 if (ath_hal_tkipsplit(ah)) 524 sc->sc_splitmic = 1; 525 } 526 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 527 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 528 /* 529 * TPC support can be done either with a global cap or 530 * per-packet support. The latter is not available on 531 * all parts. We're a bit pedantic here as all parts 532 * support a global cap. 533 */ 534 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 535 ic->ic_caps |= IEEE80211_C_TXPMGT; 536 537 /* 538 * Mark WME capability only if we have sufficient 539 * hardware queues to do proper priority scheduling. 540 */ 541 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 542 ic->ic_caps |= IEEE80211_C_WME; 543 /* 544 * Check for misc other capabilities. 545 */ 546 if (ath_hal_hasbursting(ah)) 547 ic->ic_caps |= IEEE80211_C_BURST; 548 549 /* 550 * Indicate we need the 802.11 header padded to a 551 * 32-bit boundary for 4-address and QoS frames. 552 */ 553 ic->ic_flags |= IEEE80211_F_DATAPAD; 554 555 /* 556 * Query the hal about antenna support. 557 */ 558 sc->sc_defant = ath_hal_getdefantenna(ah); 559 560 /* 561 * Not all chips have the VEOL support we want to 562 * use with IBSS beacons; check here for it. 563 */ 564 sc->sc_hasveol = ath_hal_hasveol(ah); 565 566 /* get mac address from hardware */ 567 ath_hal_getmac(ah, ic->ic_myaddr); 568 569 if_attach(ifp); 570 /* call MI attach routine. */ 571 ieee80211_ifattach(ic); 572 /* override default methods */ 573 ic->ic_node_alloc = ath_node_alloc; 574 sc->sc_node_free = ic->ic_node_free; 575 ic->ic_node_free = ath_node_free; 576 ic->ic_node_getrssi = ath_node_getrssi; 577 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 578 ic->ic_recv_mgmt = ath_recv_mgmt; 579 sc->sc_newstate = ic->ic_newstate; 580 ic->ic_newstate = ath_newstate; 581 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 582 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 583 ic->ic_crypto.cs_key_delete = ath_key_delete; 584 ic->ic_crypto.cs_key_set = ath_key_set; 585 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 586 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 587 /* complete initialization */ 588 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 589 590 #if NBPFILTER > 0 591 ath_bpfattach(sc); 592 #endif 593 594 sc->sc_flags |= ATH_ATTACHED; 595 596 /* 597 * Setup dynamic sysctl's now that country code and 598 * regdomain are available from the hal. 599 */ 600 ath_sysctlattach(sc); 601 602 ieee80211_announce(ic); 603 ath_announce(sc); 604 return 0; 605 bad2: 606 ath_tx_cleanup(sc); 607 ath_desc_free(sc); 608 bad: 609 if (ah) 610 ath_hal_detach(ah); 611 /* XXX don't get under the abstraction like this */ 612 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 613 return error; 614 } 615 616 int 617 ath_detach(struct ath_softc *sc) 618 { 619 struct ifnet *ifp = &sc->sc_if; 620 int s; 621 622 if ((sc->sc_flags & ATH_ATTACHED) == 0) 623 return (0); 624 625 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 626 __func__, ifp->if_flags); 627 628 s = splnet(); 629 ath_stop(ifp, 1); 630 #if NBPFILTER > 0 631 bpfdetach(ifp); 632 #endif 633 /* 634 * NB: the order of these is important: 635 * o call the 802.11 layer before detaching the hal to 636 * insure callbacks into the driver to delete global 637 * key cache entries can be handled 638 * o reclaim the tx queue data structures after calling 639 * the 802.11 layer as we'll get called back to reclaim 640 * node state and potentially want to use them 641 * o to cleanup the tx queues the hal is called, so detach 642 * it last 643 * Other than that, it's straightforward... 644 */ 645 ieee80211_ifdetach(&sc->sc_ic); 646 #ifdef ATH_TX99_DIAG 647 if (sc->sc_tx99 != NULL) 648 sc->sc_tx99->detach(sc->sc_tx99); 649 #endif 650 ath_rate_detach(sc->sc_rc); 651 ath_desc_free(sc); 652 ath_tx_cleanup(sc); 653 sysctl_teardown(&sc->sc_sysctllog); 654 ath_hal_detach(sc->sc_ah); 655 if_detach(ifp); 656 splx(s); 657 658 return 0; 659 } 660 661 void 662 ath_suspend(struct ath_softc *sc) 663 { 664 /* 665 * Set the chip in full sleep mode. Note that we are 666 * careful to do this only when bringing the interface 667 * completely to a stop. When the chip is in this state 668 * it must be carefully woken up or references to 669 * registers in the PCI clock domain may freeze the bus 670 * (and system). This varies by chip and is mostly an 671 * issue with newer parts that go to sleep more quickly. 672 */ 673 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 674 } 675 676 bool 677 ath_resume(struct ath_softc *sc) 678 { 679 int i; 680 struct ath_hal *ah = sc->sc_ah; 681 682 ath_hal_setpower(ah, HAL_PM_AWAKE); 683 684 /* 685 * Reset the key cache since some parts do not 686 * reset the contents on initial power up. 687 */ 688 for (i = 0; i < sc->sc_keymax; i++) 689 ath_hal_keyreset(ah, i); 690 691 ath_hal_resettxqueue(ah, sc->sc_bhalq); 692 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 693 if (ATH_TXQ_SETUP(sc, i)) 694 ath_hal_resettxqueue(ah, i); 695 696 if (sc->sc_softled) { 697 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 698 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 699 } 700 return true; 701 } 702 703 /* 704 * Interrupt handler. Most of the actual processing is deferred. 705 */ 706 int 707 ath_intr(void *arg) 708 { 709 struct ath_softc *sc = arg; 710 struct ifnet *ifp = &sc->sc_if; 711 struct ath_hal *ah = sc->sc_ah; 712 HAL_INT status; 713 714 if (!device_is_active(sc->sc_dev)) { 715 /* 716 * The hardware is not ready/present, don't touch anything. 717 * Note this can happen early on if the IRQ is shared. 718 */ 719 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 720 return 0; 721 } 722 723 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 724 return 0; 725 726 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 727 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 728 __func__, ifp->if_flags); 729 ath_hal_getisr(ah, &status); /* clear ISR */ 730 ath_hal_intrset(ah, 0); /* disable further intr's */ 731 return 1; /* XXX */ 732 } 733 /* 734 * Figure out the reason(s) for the interrupt. Note 735 * that the hal returns a pseudo-ISR that may include 736 * bits we haven't explicitly enabled so we mask the 737 * value to insure we only process bits we requested. 738 */ 739 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 740 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 741 status &= sc->sc_imask; /* discard unasked for bits */ 742 if (status & HAL_INT_FATAL) { 743 /* 744 * Fatal errors are unrecoverable. Typically 745 * these are caused by DMA errors. Unfortunately 746 * the exact reason is not (presently) returned 747 * by the hal. 748 */ 749 sc->sc_stats.ast_hardware++; 750 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 751 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 752 } else if (status & HAL_INT_RXORN) { 753 sc->sc_stats.ast_rxorn++; 754 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 755 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 756 } else { 757 if (status & HAL_INT_SWBA) { 758 /* 759 * Software beacon alert--time to send a beacon. 760 * Handle beacon transmission directly; deferring 761 * this is too slow to meet timing constraints 762 * under load. 763 */ 764 ath_beacon_proc(sc, 0); 765 } 766 if (status & HAL_INT_RXEOL) { 767 /* 768 * NB: the hardware should re-read the link when 769 * RXE bit is written, but it doesn't work at 770 * least on older hardware revs. 771 */ 772 sc->sc_stats.ast_rxeol++; 773 sc->sc_rxlink = NULL; 774 } 775 if (status & HAL_INT_TXURN) { 776 sc->sc_stats.ast_txurn++; 777 /* bump tx trigger level */ 778 ath_hal_updatetxtriglevel(ah, AH_TRUE); 779 } 780 if (status & HAL_INT_RX) 781 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 782 if (status & HAL_INT_TX) 783 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 784 if (status & HAL_INT_BMISS) { 785 sc->sc_stats.ast_bmiss++; 786 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 787 } 788 if (status & HAL_INT_MIB) { 789 sc->sc_stats.ast_mib++; 790 /* 791 * Disable interrupts until we service the MIB 792 * interrupt; otherwise it will continue to fire. 793 */ 794 ath_hal_intrset(ah, 0); 795 /* 796 * Let the hal handle the event. We assume it will 797 * clear whatever condition caused the interrupt. 798 */ 799 ath_hal_mibevent(ah, &sc->sc_halstats); 800 ath_hal_intrset(ah, sc->sc_imask); 801 } 802 } 803 return 1; 804 } 805 806 /* Swap transmit descriptor. 807 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 808 * function. 809 */ 810 static inline void 811 ath_desc_swap(struct ath_desc *ds) 812 { 813 #ifdef AH_NEED_DESC_SWAP 814 ds->ds_link = htole32(ds->ds_link); 815 ds->ds_data = htole32(ds->ds_data); 816 ds->ds_ctl0 = htole32(ds->ds_ctl0); 817 ds->ds_ctl1 = htole32(ds->ds_ctl1); 818 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 819 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 820 #endif 821 } 822 823 static void 824 ath_fatal_proc(void *arg, int pending) 825 { 826 struct ath_softc *sc = arg; 827 struct ifnet *ifp = &sc->sc_if; 828 829 if_printf(ifp, "hardware error; resetting\n"); 830 ath_reset(ifp); 831 } 832 833 static void 834 ath_rxorn_proc(void *arg, int pending) 835 { 836 struct ath_softc *sc = arg; 837 struct ifnet *ifp = &sc->sc_if; 838 839 if_printf(ifp, "rx FIFO overrun; resetting\n"); 840 ath_reset(ifp); 841 } 842 843 static void 844 ath_bmiss_proc(void *arg, int pending) 845 { 846 struct ath_softc *sc = arg; 847 struct ieee80211com *ic = &sc->sc_ic; 848 849 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 850 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 851 ("unexpect operating mode %u", ic->ic_opmode)); 852 if (ic->ic_state == IEEE80211_S_RUN) { 853 u_int64_t lastrx = sc->sc_lastrx; 854 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 855 856 DPRINTF(sc, ATH_DEBUG_BEACON, 857 "%s: tsf %" PRIu64 " lastrx %" PRId64 858 " (%" PRIu64 ") bmiss %u\n", 859 __func__, tsf, tsf - lastrx, lastrx, 860 ic->ic_bmisstimeout*1024); 861 /* 862 * Workaround phantom bmiss interrupts by sanity-checking 863 * the time of our last rx'd frame. If it is within the 864 * beacon miss interval then ignore the interrupt. If it's 865 * truly a bmiss we'll get another interrupt soon and that'll 866 * be dispatched up for processing. 867 */ 868 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 869 NET_LOCK_GIANT(); 870 ieee80211_beacon_miss(ic); 871 NET_UNLOCK_GIANT(); 872 } else 873 sc->sc_stats.ast_bmiss_phantom++; 874 } 875 } 876 877 static void 878 ath_radar_proc(void *arg, int pending) 879 { 880 struct ath_softc *sc = arg; 881 struct ifnet *ifp = &sc->sc_if; 882 struct ath_hal *ah = sc->sc_ah; 883 HAL_CHANNEL hchan; 884 885 if (ath_hal_procdfs(ah, &hchan)) { 886 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 887 hchan.channel, hchan.channelFlags, hchan.privFlags); 888 /* 889 * Initiate channel change. 890 */ 891 /* XXX not yet */ 892 } 893 } 894 895 static u_int 896 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 897 { 898 #define N(a) (sizeof(a) / sizeof(a[0])) 899 static const u_int modeflags[] = { 900 0, /* IEEE80211_MODE_AUTO */ 901 CHANNEL_A, /* IEEE80211_MODE_11A */ 902 CHANNEL_B, /* IEEE80211_MODE_11B */ 903 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 904 0, /* IEEE80211_MODE_FH */ 905 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 906 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 907 }; 908 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 909 910 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 911 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 912 return modeflags[mode]; 913 #undef N 914 } 915 916 static int 917 ath_ifinit(struct ifnet *ifp) 918 { 919 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 920 921 return ath_init(sc); 922 } 923 924 static int 925 ath_init(struct ath_softc *sc) 926 { 927 struct ifnet *ifp = &sc->sc_if; 928 struct ieee80211com *ic = &sc->sc_ic; 929 struct ath_hal *ah = sc->sc_ah; 930 HAL_STATUS status; 931 int error = 0; 932 933 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 934 __func__, ifp->if_flags); 935 936 if (device_is_active(sc->sc_dev)) { 937 ATH_LOCK(sc); 938 } else if (!pmf_device_resume_self(sc->sc_dev)) 939 return ENXIO; 940 else 941 ATH_LOCK(sc); 942 943 /* 944 * Stop anything previously setup. This is safe 945 * whether this is the first time through or not. 946 */ 947 ath_stop_locked(ifp, 0); 948 949 /* 950 * The basic interface to setting the hardware in a good 951 * state is ``reset''. On return the hardware is known to 952 * be powered up and with interrupts disabled. This must 953 * be followed by initialization of the appropriate bits 954 * and then setup of the interrupt mask. 955 */ 956 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 957 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 958 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 959 if_printf(ifp, "unable to reset hardware; hal status %u\n", 960 status); 961 error = EIO; 962 goto done; 963 } 964 965 /* 966 * This is needed only to setup initial state 967 * but it's best done after a reset. 968 */ 969 ath_update_txpow(sc); 970 /* 971 * Likewise this is set during reset so update 972 * state cached in the driver. 973 */ 974 ath_restore_diversity(sc); 975 sc->sc_calinterval = 1; 976 sc->sc_caltries = 0; 977 978 /* 979 * Setup the hardware after reset: the key cache 980 * is filled as needed and the receive engine is 981 * set going. Frame transmit is handled entirely 982 * in the frame output path; there's nothing to do 983 * here except setup the interrupt mask. 984 */ 985 if ((error = ath_startrecv(sc)) != 0) { 986 if_printf(ifp, "unable to start recv logic\n"); 987 goto done; 988 } 989 990 /* 991 * Enable interrupts. 992 */ 993 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 994 | HAL_INT_RXEOL | HAL_INT_RXORN 995 | HAL_INT_FATAL | HAL_INT_GLOBAL; 996 /* 997 * Enable MIB interrupts when there are hardware phy counters. 998 * Note we only do this (at the moment) for station mode. 999 */ 1000 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1001 sc->sc_imask |= HAL_INT_MIB; 1002 ath_hal_intrset(ah, sc->sc_imask); 1003 1004 ifp->if_flags |= IFF_RUNNING; 1005 ic->ic_state = IEEE80211_S_INIT; 1006 1007 /* 1008 * The hardware should be ready to go now so it's safe 1009 * to kick the 802.11 state machine as it's likely to 1010 * immediately call back to us to send mgmt frames. 1011 */ 1012 ath_chan_change(sc, ic->ic_curchan); 1013 #ifdef ATH_TX99_DIAG 1014 if (sc->sc_tx99 != NULL) 1015 sc->sc_tx99->start(sc->sc_tx99); 1016 else 1017 #endif 1018 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1019 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1020 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1021 } else 1022 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1023 done: 1024 ATH_UNLOCK(sc); 1025 return error; 1026 } 1027 1028 static void 1029 ath_stop_locked(struct ifnet *ifp, int disable) 1030 { 1031 struct ath_softc *sc = ifp->if_softc; 1032 struct ieee80211com *ic = &sc->sc_ic; 1033 struct ath_hal *ah = sc->sc_ah; 1034 1035 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1036 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1037 1038 ATH_LOCK_ASSERT(sc); 1039 if (ifp->if_flags & IFF_RUNNING) { 1040 /* 1041 * Shutdown the hardware and driver: 1042 * reset 802.11 state machine 1043 * turn off timers 1044 * disable interrupts 1045 * turn off the radio 1046 * clear transmit machinery 1047 * clear receive machinery 1048 * drain and release tx queues 1049 * reclaim beacon resources 1050 * power down hardware 1051 * 1052 * Note that some of this work is not possible if the 1053 * hardware is gone (invalid). 1054 */ 1055 #ifdef ATH_TX99_DIAG 1056 if (sc->sc_tx99 != NULL) 1057 sc->sc_tx99->stop(sc->sc_tx99); 1058 #endif 1059 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1060 ifp->if_flags &= ~IFF_RUNNING; 1061 ifp->if_timer = 0; 1062 if (device_is_enabled(sc->sc_dev)) { 1063 if (sc->sc_softled) { 1064 callout_stop(&sc->sc_ledtimer); 1065 ath_hal_gpioset(ah, sc->sc_ledpin, 1066 !sc->sc_ledon); 1067 sc->sc_blinking = 0; 1068 } 1069 ath_hal_intrset(ah, 0); 1070 } 1071 ath_draintxq(sc); 1072 if (device_is_enabled(sc->sc_dev)) { 1073 ath_stoprecv(sc); 1074 ath_hal_phydisable(ah); 1075 } else 1076 sc->sc_rxlink = NULL; 1077 IF_PURGE(&ifp->if_snd); 1078 ath_beacon_free(sc); 1079 if (disable) 1080 pmf_device_suspend_self(sc->sc_dev); 1081 } 1082 } 1083 1084 static void 1085 ath_stop(struct ifnet *ifp, int disable) 1086 { 1087 struct ath_softc *sc = ifp->if_softc; 1088 1089 ATH_LOCK(sc); 1090 ath_stop_locked(ifp, disable); 1091 ATH_UNLOCK(sc); 1092 } 1093 1094 static void 1095 ath_restore_diversity(struct ath_softc *sc) 1096 { 1097 struct ifnet *ifp = &sc->sc_if; 1098 struct ath_hal *ah = sc->sc_ah; 1099 1100 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1101 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1102 if_printf(ifp, "could not restore diversity setting %d\n", 1103 sc->sc_diversity); 1104 sc->sc_diversity = ath_hal_getdiversity(ah); 1105 } 1106 } 1107 1108 /* 1109 * Reset the hardware w/o losing operational state. This is 1110 * basically a more efficient way of doing ath_stop, ath_init, 1111 * followed by state transitions to the current 802.11 1112 * operational state. Used to recover from various errors and 1113 * to reset or reload hardware state. 1114 */ 1115 int 1116 ath_reset(struct ifnet *ifp) 1117 { 1118 struct ath_softc *sc = ifp->if_softc; 1119 struct ieee80211com *ic = &sc->sc_ic; 1120 struct ath_hal *ah = sc->sc_ah; 1121 struct ieee80211_channel *c; 1122 HAL_STATUS status; 1123 1124 /* 1125 * Convert to a HAL channel description with the flags 1126 * constrained to reflect the current operating mode. 1127 */ 1128 c = ic->ic_curchan; 1129 sc->sc_curchan.channel = c->ic_freq; 1130 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1131 1132 ath_hal_intrset(ah, 0); /* disable interrupts */ 1133 ath_draintxq(sc); /* stop xmit side */ 1134 ath_stoprecv(sc); /* stop recv side */ 1135 /* NB: indicate channel change so we do a full reset */ 1136 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1137 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1138 __func__, status); 1139 ath_update_txpow(sc); /* update tx power state */ 1140 ath_restore_diversity(sc); 1141 sc->sc_calinterval = 1; 1142 sc->sc_caltries = 0; 1143 if (ath_startrecv(sc) != 0) /* restart recv */ 1144 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1145 /* 1146 * We may be doing a reset in response to an ioctl 1147 * that changes the channel so update any state that 1148 * might change as a result. 1149 */ 1150 ath_chan_change(sc, c); 1151 if (ic->ic_state == IEEE80211_S_RUN) 1152 ath_beacon_config(sc); /* restart beacons */ 1153 ath_hal_intrset(ah, sc->sc_imask); 1154 1155 ath_start(ifp); /* restart xmit */ 1156 return 0; 1157 } 1158 1159 /* 1160 * Cleanup driver resources when we run out of buffers 1161 * while processing fragments; return the tx buffers 1162 * allocated and drop node references. 1163 */ 1164 static void 1165 ath_txfrag_cleanup(struct ath_softc *sc, 1166 ath_bufhead *frags, struct ieee80211_node *ni) 1167 { 1168 struct ath_buf *bf; 1169 1170 ATH_TXBUF_LOCK_ASSERT(sc); 1171 1172 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1173 STAILQ_REMOVE_HEAD(frags, bf_list); 1174 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1175 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1176 ieee80211_node_decref(ni); 1177 } 1178 } 1179 1180 /* 1181 * Setup xmit of a fragmented frame. Allocate a buffer 1182 * for each frag and bump the node reference count to 1183 * reflect the held reference to be setup by ath_tx_start. 1184 */ 1185 static int 1186 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1187 struct mbuf *m0, struct ieee80211_node *ni) 1188 { 1189 struct mbuf *m; 1190 struct ath_buf *bf; 1191 1192 ATH_TXBUF_LOCK(sc); 1193 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1194 bf = STAILQ_FIRST(&sc->sc_txbuf); 1195 if (bf == NULL) { /* out of buffers, cleanup */ 1196 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1197 __func__); 1198 sc->sc_if.if_flags |= IFF_OACTIVE; 1199 ath_txfrag_cleanup(sc, frags, ni); 1200 break; 1201 } 1202 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1203 ieee80211_node_incref(ni); 1204 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1205 } 1206 ATH_TXBUF_UNLOCK(sc); 1207 1208 return !STAILQ_EMPTY(frags); 1209 } 1210 1211 static void 1212 ath_start(struct ifnet *ifp) 1213 { 1214 struct ath_softc *sc = ifp->if_softc; 1215 struct ath_hal *ah = sc->sc_ah; 1216 struct ieee80211com *ic = &sc->sc_ic; 1217 struct ieee80211_node *ni; 1218 struct ath_buf *bf; 1219 struct mbuf *m, *next; 1220 struct ieee80211_frame *wh; 1221 struct ether_header *eh; 1222 ath_bufhead frags; 1223 1224 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1225 !device_is_active(sc->sc_dev)) 1226 return; 1227 for (;;) { 1228 /* 1229 * Grab a TX buffer and associated resources. 1230 */ 1231 ATH_TXBUF_LOCK(sc); 1232 bf = STAILQ_FIRST(&sc->sc_txbuf); 1233 if (bf != NULL) 1234 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1235 ATH_TXBUF_UNLOCK(sc); 1236 if (bf == NULL) { 1237 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1238 __func__); 1239 sc->sc_stats.ast_tx_qstop++; 1240 ifp->if_flags |= IFF_OACTIVE; 1241 break; 1242 } 1243 /* 1244 * Poll the management queue for frames; they 1245 * have priority over normal data frames. 1246 */ 1247 IF_DEQUEUE(&ic->ic_mgtq, m); 1248 if (m == NULL) { 1249 /* 1250 * No data frames go out unless we're associated. 1251 */ 1252 if (ic->ic_state != IEEE80211_S_RUN) { 1253 DPRINTF(sc, ATH_DEBUG_XMIT, 1254 "%s: discard data packet, state %s\n", 1255 __func__, 1256 ieee80211_state_name[ic->ic_state]); 1257 sc->sc_stats.ast_tx_discard++; 1258 ATH_TXBUF_LOCK(sc); 1259 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1260 ATH_TXBUF_UNLOCK(sc); 1261 break; 1262 } 1263 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1264 if (m == NULL) { 1265 ATH_TXBUF_LOCK(sc); 1266 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1267 ATH_TXBUF_UNLOCK(sc); 1268 break; 1269 } 1270 STAILQ_INIT(&frags); 1271 /* 1272 * Find the node for the destination so we can do 1273 * things like power save and fast frames aggregation. 1274 */ 1275 if (m->m_len < sizeof(struct ether_header) && 1276 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1277 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1278 ni = NULL; 1279 goto bad; 1280 } 1281 eh = mtod(m, struct ether_header *); 1282 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1283 if (ni == NULL) { 1284 /* NB: ieee80211_find_txnode does stat+msg */ 1285 m_freem(m); 1286 goto bad; 1287 } 1288 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1289 (m->m_flags & M_PWR_SAV) == 0) { 1290 /* 1291 * Station in power save mode; pass the frame 1292 * to the 802.11 layer and continue. We'll get 1293 * the frame back when the time is right. 1294 */ 1295 ieee80211_pwrsave(ic, ni, m); 1296 goto reclaim; 1297 } 1298 /* calculate priority so we can find the tx queue */ 1299 if (ieee80211_classify(ic, m, ni)) { 1300 DPRINTF(sc, ATH_DEBUG_XMIT, 1301 "%s: discard, classification failure\n", 1302 __func__); 1303 m_freem(m); 1304 goto bad; 1305 } 1306 ifp->if_opackets++; 1307 1308 #if NBPFILTER > 0 1309 if (ifp->if_bpf) 1310 bpf_mtap(ifp->if_bpf, m); 1311 #endif 1312 /* 1313 * Encapsulate the packet in prep for transmission. 1314 */ 1315 m = ieee80211_encap(ic, m, ni); 1316 if (m == NULL) { 1317 DPRINTF(sc, ATH_DEBUG_XMIT, 1318 "%s: encapsulation failure\n", 1319 __func__); 1320 sc->sc_stats.ast_tx_encap++; 1321 goto bad; 1322 } 1323 /* 1324 * Check for fragmentation. If this has frame 1325 * has been broken up verify we have enough 1326 * buffers to send all the fragments so all 1327 * go out or none... 1328 */ 1329 if ((m->m_flags & M_FRAG) && 1330 !ath_txfrag_setup(sc, &frags, m, ni)) { 1331 DPRINTF(sc, ATH_DEBUG_ANY, 1332 "%s: out of txfrag buffers\n", __func__); 1333 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1334 ath_freetx(m); 1335 goto bad; 1336 } 1337 } else { 1338 /* 1339 * Hack! The referenced node pointer is in the 1340 * rcvif field of the packet header. This is 1341 * placed there by ieee80211_mgmt_output because 1342 * we need to hold the reference with the frame 1343 * and there's no other way (other than packet 1344 * tags which we consider too expensive to use) 1345 * to pass it along. 1346 */ 1347 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1348 m->m_pkthdr.rcvif = NULL; 1349 1350 wh = mtod(m, struct ieee80211_frame *); 1351 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1352 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1353 /* fill time stamp */ 1354 u_int64_t tsf; 1355 u_int32_t *tstamp; 1356 1357 tsf = ath_hal_gettsf64(ah); 1358 /* XXX: adjust 100us delay to xmit */ 1359 tsf += 100; 1360 tstamp = (u_int32_t *)&wh[1]; 1361 tstamp[0] = htole32(tsf & 0xffffffff); 1362 tstamp[1] = htole32(tsf >> 32); 1363 } 1364 sc->sc_stats.ast_tx_mgmt++; 1365 } 1366 1367 nextfrag: 1368 next = m->m_nextpkt; 1369 if (ath_tx_start(sc, ni, bf, m)) { 1370 bad: 1371 ifp->if_oerrors++; 1372 reclaim: 1373 ATH_TXBUF_LOCK(sc); 1374 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1375 ath_txfrag_cleanup(sc, &frags, ni); 1376 ATH_TXBUF_UNLOCK(sc); 1377 if (ni != NULL) 1378 ieee80211_free_node(ni); 1379 continue; 1380 } 1381 if (next != NULL) { 1382 m = next; 1383 bf = STAILQ_FIRST(&frags); 1384 KASSERT(bf != NULL, ("no buf for txfrag")); 1385 STAILQ_REMOVE_HEAD(&frags, bf_list); 1386 goto nextfrag; 1387 } 1388 1389 ifp->if_timer = 1; 1390 } 1391 } 1392 1393 static int 1394 ath_media_change(struct ifnet *ifp) 1395 { 1396 #define IS_UP(ifp) \ 1397 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1398 int error; 1399 1400 error = ieee80211_media_change(ifp); 1401 if (error == ENETRESET) { 1402 if (IS_UP(ifp)) 1403 ath_init(ifp->if_softc); /* XXX lose error */ 1404 error = 0; 1405 } 1406 return error; 1407 #undef IS_UP 1408 } 1409 1410 #ifdef AR_DEBUG 1411 static void 1412 ath_keyprint(const char *tag, u_int ix, 1413 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1414 { 1415 static const char *ciphers[] = { 1416 "WEP", 1417 "AES-OCB", 1418 "AES-CCM", 1419 "CKIP", 1420 "TKIP", 1421 "CLR", 1422 }; 1423 int i, n; 1424 1425 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1426 for (i = 0, n = hk->kv_len; i < n; i++) 1427 printf("%02x", hk->kv_val[i]); 1428 printf(" mac %s", ether_sprintf(mac)); 1429 if (hk->kv_type == HAL_CIPHER_TKIP) { 1430 printf(" mic "); 1431 for (i = 0; i < sizeof(hk->kv_mic); i++) 1432 printf("%02x", hk->kv_mic[i]); 1433 } 1434 printf("\n"); 1435 } 1436 #endif 1437 1438 /* 1439 * Set a TKIP key into the hardware. This handles the 1440 * potential distribution of key state to multiple key 1441 * cache slots for TKIP. 1442 */ 1443 static int 1444 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1445 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1446 { 1447 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1448 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1449 struct ath_hal *ah = sc->sc_ah; 1450 1451 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1452 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1453 KASSERT(sc->sc_splitmic, ("key cache !split")); 1454 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1455 /* 1456 * TX key goes at first index, RX key at the rx index. 1457 * The hal handles the MIC keys at index+64. 1458 */ 1459 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1460 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1461 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1462 return 0; 1463 1464 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1465 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1466 /* XXX delete tx key on failure? */ 1467 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1468 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1469 /* 1470 * TX/RX key goes at first index. 1471 * The hal handles the MIC keys are index+64. 1472 */ 1473 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1474 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1475 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1476 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1477 } 1478 return 0; 1479 #undef IEEE80211_KEY_XR 1480 } 1481 1482 /* 1483 * Set a net80211 key into the hardware. This handles the 1484 * potential distribution of key state to multiple key 1485 * cache slots for TKIP with hardware MIC support. 1486 */ 1487 static int 1488 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1489 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1490 struct ieee80211_node *bss) 1491 { 1492 #define N(a) (sizeof(a)/sizeof(a[0])) 1493 static const u_int8_t ciphermap[] = { 1494 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1495 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1496 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1497 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1498 (u_int8_t) -1, /* 4 is not allocated */ 1499 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1500 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1501 }; 1502 struct ath_hal *ah = sc->sc_ah; 1503 const struct ieee80211_cipher *cip = k->wk_cipher; 1504 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1505 const u_int8_t *mac; 1506 HAL_KEYVAL hk; 1507 1508 memset(&hk, 0, sizeof(hk)); 1509 /* 1510 * Software crypto uses a "clear key" so non-crypto 1511 * state kept in the key cache are maintained and 1512 * so that rx frames have an entry to match. 1513 */ 1514 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1515 KASSERT(cip->ic_cipher < N(ciphermap), 1516 ("invalid cipher type %u", cip->ic_cipher)); 1517 hk.kv_type = ciphermap[cip->ic_cipher]; 1518 hk.kv_len = k->wk_keylen; 1519 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1520 } else 1521 hk.kv_type = HAL_CIPHER_CLR; 1522 1523 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1524 /* 1525 * Group keys on hardware that supports multicast frame 1526 * key search use a mac that is the sender's address with 1527 * the high bit set instead of the app-specified address. 1528 */ 1529 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1530 gmac[0] |= 0x80; 1531 mac = gmac; 1532 } else 1533 mac = mac0; 1534 1535 if (hk.kv_type == HAL_CIPHER_TKIP && 1536 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1537 sc->sc_splitmic) { 1538 return ath_keyset_tkip(sc, k, &hk, mac); 1539 } else { 1540 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1541 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1542 } 1543 #undef N 1544 } 1545 1546 /* 1547 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1548 * each key, one for decrypt/encrypt and the other for the MIC. 1549 */ 1550 static u_int16_t 1551 key_alloc_2pair(struct ath_softc *sc, 1552 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1553 { 1554 #define N(a) (sizeof(a)/sizeof(a[0])) 1555 u_int i, keyix; 1556 1557 KASSERT(sc->sc_splitmic, ("key cache !split")); 1558 /* XXX could optimize */ 1559 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1560 u_int8_t b = sc->sc_keymap[i]; 1561 if (b != 0xff) { 1562 /* 1563 * One or more slots in this byte are free. 1564 */ 1565 keyix = i*NBBY; 1566 while (b & 1) { 1567 again: 1568 keyix++; 1569 b >>= 1; 1570 } 1571 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1572 if (isset(sc->sc_keymap, keyix+32) || 1573 isset(sc->sc_keymap, keyix+64) || 1574 isset(sc->sc_keymap, keyix+32+64)) { 1575 /* full pair unavailable */ 1576 /* XXX statistic */ 1577 if (keyix == (i+1)*NBBY) { 1578 /* no slots were appropriate, advance */ 1579 continue; 1580 } 1581 goto again; 1582 } 1583 setbit(sc->sc_keymap, keyix); 1584 setbit(sc->sc_keymap, keyix+64); 1585 setbit(sc->sc_keymap, keyix+32); 1586 setbit(sc->sc_keymap, keyix+32+64); 1587 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1588 "%s: key pair %u,%u %u,%u\n", 1589 __func__, keyix, keyix+64, 1590 keyix+32, keyix+32+64); 1591 *txkeyix = keyix; 1592 *rxkeyix = keyix+32; 1593 return 1; 1594 } 1595 } 1596 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1597 return 0; 1598 #undef N 1599 } 1600 1601 /* 1602 * Allocate a single key cache slot. 1603 */ 1604 static int 1605 key_alloc_single(struct ath_softc *sc, 1606 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1607 { 1608 #define N(a) (sizeof(a)/sizeof(a[0])) 1609 u_int i, keyix; 1610 1611 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1612 for (i = 0; i < N(sc->sc_keymap); i++) { 1613 u_int8_t b = sc->sc_keymap[i]; 1614 if (b != 0xff) { 1615 /* 1616 * One or more slots are free. 1617 */ 1618 keyix = i*NBBY; 1619 while (b & 1) 1620 keyix++, b >>= 1; 1621 setbit(sc->sc_keymap, keyix); 1622 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1623 __func__, keyix); 1624 *txkeyix = *rxkeyix = keyix; 1625 return 1; 1626 } 1627 } 1628 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1629 return 0; 1630 #undef N 1631 } 1632 1633 /* 1634 * Allocate one or more key cache slots for a uniacst key. The 1635 * key itself is needed only to identify the cipher. For hardware 1636 * TKIP with split cipher+MIC keys we allocate two key cache slot 1637 * pairs so that we can setup separate TX and RX MIC keys. Note 1638 * that the MIC key for a TKIP key at slot i is assumed by the 1639 * hardware to be at slot i+64. This limits TKIP keys to the first 1640 * 64 entries. 1641 */ 1642 static int 1643 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1644 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1645 { 1646 struct ath_softc *sc = ic->ic_ifp->if_softc; 1647 1648 /* 1649 * Group key allocation must be handled specially for 1650 * parts that do not support multicast key cache search 1651 * functionality. For those parts the key id must match 1652 * the h/w key index so lookups find the right key. On 1653 * parts w/ the key search facility we install the sender's 1654 * mac address (with the high bit set) and let the hardware 1655 * find the key w/o using the key id. This is preferred as 1656 * it permits us to support multiple users for adhoc and/or 1657 * multi-station operation. 1658 */ 1659 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1660 if (!(&ic->ic_nw_keys[0] <= k && 1661 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1662 /* should not happen */ 1663 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1664 "%s: bogus group key\n", __func__); 1665 return 0; 1666 } 1667 /* 1668 * XXX we pre-allocate the global keys so 1669 * have no way to check if they've already been allocated. 1670 */ 1671 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1672 return 1; 1673 } 1674 1675 /* 1676 * We allocate two pair for TKIP when using the h/w to do 1677 * the MIC. For everything else, including software crypto, 1678 * we allocate a single entry. Note that s/w crypto requires 1679 * a pass-through slot on the 5211 and 5212. The 5210 does 1680 * not support pass-through cache entries and we map all 1681 * those requests to slot 0. 1682 */ 1683 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1684 return key_alloc_single(sc, keyix, rxkeyix); 1685 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1686 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1687 return key_alloc_2pair(sc, keyix, rxkeyix); 1688 } else { 1689 return key_alloc_single(sc, keyix, rxkeyix); 1690 } 1691 } 1692 1693 /* 1694 * Delete an entry in the key cache allocated by ath_key_alloc. 1695 */ 1696 static int 1697 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1698 { 1699 struct ath_softc *sc = ic->ic_ifp->if_softc; 1700 struct ath_hal *ah = sc->sc_ah; 1701 const struct ieee80211_cipher *cip = k->wk_cipher; 1702 u_int keyix = k->wk_keyix; 1703 1704 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1705 1706 if (!device_has_power(sc->sc_dev)) { 1707 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1708 k->wk_keyix); 1709 } 1710 1711 ath_hal_keyreset(ah, keyix); 1712 /* 1713 * Handle split tx/rx keying required for TKIP with h/w MIC. 1714 */ 1715 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1716 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1717 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1718 if (keyix >= IEEE80211_WEP_NKID) { 1719 /* 1720 * Don't touch keymap entries for global keys so 1721 * they are never considered for dynamic allocation. 1722 */ 1723 clrbit(sc->sc_keymap, keyix); 1724 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1725 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1726 sc->sc_splitmic) { 1727 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1728 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1729 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1730 } 1731 } 1732 return 1; 1733 } 1734 1735 /* 1736 * Set the key cache contents for the specified key. Key cache 1737 * slot(s) must already have been allocated by ath_key_alloc. 1738 */ 1739 static int 1740 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1741 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1742 { 1743 struct ath_softc *sc = ic->ic_ifp->if_softc; 1744 1745 if (!device_has_power(sc->sc_dev)) { 1746 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1747 k->wk_keyix); 1748 } 1749 return ath_keyset(sc, k, mac, ic->ic_bss); 1750 } 1751 1752 /* 1753 * Block/unblock tx+rx processing while a key change is done. 1754 * We assume the caller serializes key management operations 1755 * so we only need to worry about synchronization with other 1756 * uses that originate in the driver. 1757 */ 1758 static void 1759 ath_key_update_begin(struct ieee80211com *ic) 1760 { 1761 struct ifnet *ifp = ic->ic_ifp; 1762 struct ath_softc *sc = ifp->if_softc; 1763 1764 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1765 #if 0 1766 tasklet_disable(&sc->sc_rxtq); 1767 #endif 1768 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1769 } 1770 1771 static void 1772 ath_key_update_end(struct ieee80211com *ic) 1773 { 1774 struct ifnet *ifp = ic->ic_ifp; 1775 struct ath_softc *sc = ifp->if_softc; 1776 1777 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1778 IF_UNLOCK(&ifp->if_snd); 1779 #if 0 1780 tasklet_enable(&sc->sc_rxtq); 1781 #endif 1782 } 1783 1784 /* 1785 * Calculate the receive filter according to the 1786 * operating mode and state: 1787 * 1788 * o always accept unicast, broadcast, and multicast traffic 1789 * o maintain current state of phy error reception (the hal 1790 * may enable phy error frames for noise immunity work) 1791 * o probe request frames are accepted only when operating in 1792 * hostap, adhoc, or monitor modes 1793 * o enable promiscuous mode according to the interface state 1794 * o accept beacons: 1795 * - when operating in adhoc mode so the 802.11 layer creates 1796 * node table entries for peers, 1797 * - when operating in station mode for collecting rssi data when 1798 * the station is otherwise quiet, or 1799 * - when scanning 1800 */ 1801 static u_int32_t 1802 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1803 { 1804 struct ieee80211com *ic = &sc->sc_ic; 1805 struct ath_hal *ah = sc->sc_ah; 1806 struct ifnet *ifp = &sc->sc_if; 1807 u_int32_t rfilt; 1808 1809 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1810 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1811 if (ic->ic_opmode != IEEE80211_M_STA) 1812 rfilt |= HAL_RX_FILTER_PROBEREQ; 1813 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1814 (ifp->if_flags & IFF_PROMISC)) 1815 rfilt |= HAL_RX_FILTER_PROM; 1816 if (ic->ic_opmode == IEEE80211_M_STA || 1817 ic->ic_opmode == IEEE80211_M_IBSS || 1818 state == IEEE80211_S_SCAN) 1819 rfilt |= HAL_RX_FILTER_BEACON; 1820 return rfilt; 1821 } 1822 1823 static void 1824 ath_mode_init(struct ath_softc *sc) 1825 { 1826 struct ifnet *ifp = &sc->sc_if; 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ath_hal *ah = sc->sc_ah; 1829 struct ether_multi *enm; 1830 struct ether_multistep estep; 1831 u_int32_t rfilt, mfilt[2], val; 1832 int i; 1833 uint8_t pos; 1834 1835 /* configure rx filter */ 1836 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1837 ath_hal_setrxfilter(ah, rfilt); 1838 1839 /* configure operational mode */ 1840 ath_hal_setopmode(ah); 1841 1842 /* Write keys to hardware; it may have been powered down. */ 1843 ath_key_update_begin(ic); 1844 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1845 ath_key_set(ic, 1846 &ic->ic_crypto.cs_nw_keys[i], 1847 ic->ic_myaddr); 1848 } 1849 ath_key_update_end(ic); 1850 1851 /* 1852 * Handle any link-level address change. Note that we only 1853 * need to force ic_myaddr; any other addresses are handled 1854 * as a byproduct of the ifnet code marking the interface 1855 * down then up. 1856 * 1857 * XXX should get from lladdr instead of arpcom but that's more work 1858 */ 1859 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1860 ath_hal_setmac(ah, ic->ic_myaddr); 1861 1862 /* calculate and install multicast filter */ 1863 ifp->if_flags &= ~IFF_ALLMULTI; 1864 mfilt[0] = mfilt[1] = 0; 1865 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1866 while (enm != NULL) { 1867 void *dl; 1868 /* XXX Punt on ranges. */ 1869 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1870 mfilt[0] = mfilt[1] = 0xffffffff; 1871 ifp->if_flags |= IFF_ALLMULTI; 1872 break; 1873 } 1874 dl = enm->enm_addrlo; 1875 val = LE_READ_4((char *)dl + 0); 1876 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1877 val = LE_READ_4((char *)dl + 3); 1878 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1879 pos &= 0x3f; 1880 mfilt[pos / 32] |= (1 << (pos % 32)); 1881 1882 ETHER_NEXT_MULTI(estep, enm); 1883 } 1884 1885 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1886 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1887 __func__, rfilt, mfilt[0], mfilt[1]); 1888 } 1889 1890 /* 1891 * Set the slot time based on the current setting. 1892 */ 1893 static void 1894 ath_setslottime(struct ath_softc *sc) 1895 { 1896 struct ieee80211com *ic = &sc->sc_ic; 1897 struct ath_hal *ah = sc->sc_ah; 1898 1899 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1900 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1901 else 1902 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1903 sc->sc_updateslot = OK; 1904 } 1905 1906 /* 1907 * Callback from the 802.11 layer to update the 1908 * slot time based on the current setting. 1909 */ 1910 static void 1911 ath_updateslot(struct ifnet *ifp) 1912 { 1913 struct ath_softc *sc = ifp->if_softc; 1914 struct ieee80211com *ic = &sc->sc_ic; 1915 1916 /* 1917 * When not coordinating the BSS, change the hardware 1918 * immediately. For other operation we defer the change 1919 * until beacon updates have propagated to the stations. 1920 */ 1921 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1922 sc->sc_updateslot = UPDATE; 1923 else 1924 ath_setslottime(sc); 1925 } 1926 1927 /* 1928 * Setup a h/w transmit queue for beacons. 1929 */ 1930 static int 1931 ath_beaconq_setup(struct ath_hal *ah) 1932 { 1933 HAL_TXQ_INFO qi; 1934 1935 memset(&qi, 0, sizeof(qi)); 1936 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1937 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1938 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1939 /* NB: for dynamic turbo, don't enable any other interrupts */ 1940 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1941 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1942 } 1943 1944 /* 1945 * Setup the transmit queue parameters for the beacon queue. 1946 */ 1947 static int 1948 ath_beaconq_config(struct ath_softc *sc) 1949 { 1950 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct ath_hal *ah = sc->sc_ah; 1953 HAL_TXQ_INFO qi; 1954 1955 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1956 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1957 /* 1958 * Always burst out beacon and CAB traffic. 1959 */ 1960 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1961 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1962 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1963 } else { 1964 struct wmeParams *wmep = 1965 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1966 /* 1967 * Adhoc mode; important thing is to use 2x cwmin. 1968 */ 1969 qi.tqi_aifs = wmep->wmep_aifsn; 1970 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1971 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1972 } 1973 1974 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1975 device_printf(sc->sc_dev, "unable to update parameters for " 1976 "beacon hardware queue!\n"); 1977 return 0; 1978 } else { 1979 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1980 return 1; 1981 } 1982 #undef ATH_EXPONENT_TO_VALUE 1983 } 1984 1985 /* 1986 * Allocate and setup an initial beacon frame. 1987 */ 1988 static int 1989 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1990 { 1991 struct ieee80211com *ic = ni->ni_ic; 1992 struct ath_buf *bf; 1993 struct mbuf *m; 1994 int error; 1995 1996 bf = STAILQ_FIRST(&sc->sc_bbuf); 1997 if (bf == NULL) { 1998 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1999 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2000 return ENOMEM; /* XXX */ 2001 } 2002 /* 2003 * NB: the beacon data buffer must be 32-bit aligned; 2004 * we assume the mbuf routines will return us something 2005 * with this alignment (perhaps should assert). 2006 */ 2007 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2008 if (m == NULL) { 2009 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2010 __func__); 2011 sc->sc_stats.ast_be_nombuf++; 2012 return ENOMEM; 2013 } 2014 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2015 BUS_DMA_NOWAIT); 2016 if (error == 0) { 2017 bf->bf_m = m; 2018 bf->bf_node = ieee80211_ref_node(ni); 2019 } else { 2020 m_freem(m); 2021 } 2022 return error; 2023 } 2024 2025 /* 2026 * Setup the beacon frame for transmit. 2027 */ 2028 static void 2029 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2030 { 2031 #define USE_SHPREAMBLE(_ic) \ 2032 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2033 == IEEE80211_F_SHPREAMBLE) 2034 struct ieee80211_node *ni = bf->bf_node; 2035 struct ieee80211com *ic = ni->ni_ic; 2036 struct mbuf *m = bf->bf_m; 2037 struct ath_hal *ah = sc->sc_ah; 2038 struct ath_desc *ds; 2039 int flags, antenna; 2040 const HAL_RATE_TABLE *rt; 2041 u_int8_t rix, rate; 2042 2043 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2044 __func__, m, m->m_len); 2045 2046 /* setup descriptors */ 2047 ds = bf->bf_desc; 2048 2049 flags = HAL_TXDESC_NOACK; 2050 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2051 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2052 flags |= HAL_TXDESC_VEOL; 2053 /* 2054 * Let hardware handle antenna switching unless 2055 * the user has selected a transmit antenna 2056 * (sc_txantenna is not 0). 2057 */ 2058 antenna = sc->sc_txantenna; 2059 } else { 2060 ds->ds_link = 0; 2061 /* 2062 * Switch antenna every 4 beacons, unless the user 2063 * has selected a transmit antenna (sc_txantenna 2064 * is not 0). 2065 * 2066 * XXX assumes two antenna 2067 */ 2068 if (sc->sc_txantenna == 0) 2069 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2070 else 2071 antenna = sc->sc_txantenna; 2072 } 2073 2074 KASSERT(bf->bf_nseg == 1, 2075 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2076 ds->ds_data = bf->bf_segs[0].ds_addr; 2077 /* 2078 * Calculate rate code. 2079 * XXX everything at min xmit rate 2080 */ 2081 rix = sc->sc_minrateix; 2082 rt = sc->sc_currates; 2083 rate = rt->info[rix].rateCode; 2084 if (USE_SHPREAMBLE(ic)) 2085 rate |= rt->info[rix].shortPreamble; 2086 ath_hal_setuptxdesc(ah, ds 2087 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2088 , sizeof(struct ieee80211_frame)/* header length */ 2089 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2090 , ni->ni_txpower /* txpower XXX */ 2091 , rate, 1 /* series 0 rate/tries */ 2092 , HAL_TXKEYIX_INVALID /* no encryption */ 2093 , antenna /* antenna mode */ 2094 , flags /* no ack, veol for beacons */ 2095 , 0 /* rts/cts rate */ 2096 , 0 /* rts/cts duration */ 2097 ); 2098 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2099 ath_hal_filltxdesc(ah, ds 2100 , roundup(m->m_len, 4) /* buffer length */ 2101 , AH_TRUE /* first segment */ 2102 , AH_TRUE /* last segment */ 2103 , ds /* first descriptor */ 2104 ); 2105 2106 /* NB: The desc swap function becomes void, 2107 * if descriptor swapping is not enabled 2108 */ 2109 ath_desc_swap(ds); 2110 2111 #undef USE_SHPREAMBLE 2112 } 2113 2114 /* 2115 * Transmit a beacon frame at SWBA. Dynamic updates to the 2116 * frame contents are done as needed and the slot time is 2117 * also adjusted based on current state. 2118 */ 2119 static void 2120 ath_beacon_proc(void *arg, int pending) 2121 { 2122 struct ath_softc *sc = arg; 2123 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2124 struct ieee80211_node *ni = bf->bf_node; 2125 struct ieee80211com *ic = ni->ni_ic; 2126 struct ath_hal *ah = sc->sc_ah; 2127 struct mbuf *m; 2128 int ncabq, error, otherant; 2129 2130 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2131 __func__, pending); 2132 2133 if (ic->ic_opmode == IEEE80211_M_STA || 2134 ic->ic_opmode == IEEE80211_M_MONITOR || 2135 bf == NULL || bf->bf_m == NULL) { 2136 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2137 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2138 return; 2139 } 2140 /* 2141 * Check if the previous beacon has gone out. If 2142 * not don't try to post another, skip this period 2143 * and wait for the next. Missed beacons indicate 2144 * a problem and should not occur. If we miss too 2145 * many consecutive beacons reset the device. 2146 */ 2147 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2148 sc->sc_bmisscount++; 2149 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2150 "%s: missed %u consecutive beacons\n", 2151 __func__, sc->sc_bmisscount); 2152 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2153 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2154 return; 2155 } 2156 if (sc->sc_bmisscount != 0) { 2157 DPRINTF(sc, ATH_DEBUG_BEACON, 2158 "%s: resume beacon xmit after %u misses\n", 2159 __func__, sc->sc_bmisscount); 2160 sc->sc_bmisscount = 0; 2161 } 2162 2163 /* 2164 * Update dynamic beacon contents. If this returns 2165 * non-zero then we need to remap the memory because 2166 * the beacon frame changed size (probably because 2167 * of the TIM bitmap). 2168 */ 2169 m = bf->bf_m; 2170 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2171 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2172 /* XXX too conservative? */ 2173 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2174 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2175 BUS_DMA_NOWAIT); 2176 if (error != 0) { 2177 if_printf(&sc->sc_if, 2178 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2179 __func__, error); 2180 return; 2181 } 2182 } 2183 2184 /* 2185 * Handle slot time change when a non-ERP station joins/leaves 2186 * an 11g network. The 802.11 layer notifies us via callback, 2187 * we mark updateslot, then wait one beacon before effecting 2188 * the change. This gives associated stations at least one 2189 * beacon interval to note the state change. 2190 */ 2191 /* XXX locking */ 2192 if (sc->sc_updateslot == UPDATE) 2193 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2194 else if (sc->sc_updateslot == COMMIT) 2195 ath_setslottime(sc); /* commit change to h/w */ 2196 2197 /* 2198 * Check recent per-antenna transmit statistics and flip 2199 * the default antenna if noticeably more frames went out 2200 * on the non-default antenna. 2201 * XXX assumes 2 anntenae 2202 */ 2203 otherant = sc->sc_defant & 1 ? 2 : 1; 2204 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2205 ath_setdefantenna(sc, otherant); 2206 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2207 2208 /* 2209 * Construct tx descriptor. 2210 */ 2211 ath_beacon_setup(sc, bf); 2212 2213 /* 2214 * Stop any current dma and put the new frame on the queue. 2215 * This should never fail since we check above that no frames 2216 * are still pending on the queue. 2217 */ 2218 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2219 DPRINTF(sc, ATH_DEBUG_ANY, 2220 "%s: beacon queue %u did not stop?\n", 2221 __func__, sc->sc_bhalq); 2222 } 2223 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2224 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2225 2226 /* 2227 * Enable the CAB queue before the beacon queue to 2228 * insure cab frames are triggered by this beacon. 2229 */ 2230 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2231 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2232 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2233 ath_hal_txstart(ah, sc->sc_bhalq); 2234 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2235 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2236 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2237 2238 sc->sc_stats.ast_be_xmit++; 2239 } 2240 2241 /* 2242 * Reset the hardware after detecting beacons have stopped. 2243 */ 2244 static void 2245 ath_bstuck_proc(void *arg, int pending) 2246 { 2247 struct ath_softc *sc = arg; 2248 struct ifnet *ifp = &sc->sc_if; 2249 2250 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2251 sc->sc_bmisscount); 2252 ath_reset(ifp); 2253 } 2254 2255 /* 2256 * Reclaim beacon resources. 2257 */ 2258 static void 2259 ath_beacon_free(struct ath_softc *sc) 2260 { 2261 struct ath_buf *bf; 2262 2263 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2264 if (bf->bf_m != NULL) { 2265 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2266 m_freem(bf->bf_m); 2267 bf->bf_m = NULL; 2268 } 2269 if (bf->bf_node != NULL) { 2270 ieee80211_free_node(bf->bf_node); 2271 bf->bf_node = NULL; 2272 } 2273 } 2274 } 2275 2276 /* 2277 * Configure the beacon and sleep timers. 2278 * 2279 * When operating as an AP this resets the TSF and sets 2280 * up the hardware to notify us when we need to issue beacons. 2281 * 2282 * When operating in station mode this sets up the beacon 2283 * timers according to the timestamp of the last received 2284 * beacon and the current TSF, configures PCF and DTIM 2285 * handling, programs the sleep registers so the hardware 2286 * will wakeup in time to receive beacons, and configures 2287 * the beacon miss handling so we'll receive a BMISS 2288 * interrupt when we stop seeing beacons from the AP 2289 * we've associated with. 2290 */ 2291 static void 2292 ath_beacon_config(struct ath_softc *sc) 2293 { 2294 #define TSF_TO_TU(_h,_l) \ 2295 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2296 #define FUDGE 2 2297 struct ath_hal *ah = sc->sc_ah; 2298 struct ieee80211com *ic = &sc->sc_ic; 2299 struct ieee80211_node *ni = ic->ic_bss; 2300 u_int32_t nexttbtt, intval, tsftu; 2301 u_int64_t tsf; 2302 2303 /* extract tstamp from last beacon and convert to TU */ 2304 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2305 LE_READ_4(ni->ni_tstamp.data)); 2306 /* NB: the beacon interval is kept internally in TU's */ 2307 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2308 if (nexttbtt == 0) /* e.g. for ap mode */ 2309 nexttbtt = intval; 2310 else if (intval) /* NB: can be 0 for monitor mode */ 2311 nexttbtt = roundup(nexttbtt, intval); 2312 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2313 __func__, nexttbtt, intval, ni->ni_intval); 2314 if (ic->ic_opmode == IEEE80211_M_STA) { 2315 HAL_BEACON_STATE bs; 2316 int dtimperiod, dtimcount; 2317 int cfpperiod, cfpcount; 2318 2319 /* 2320 * Setup dtim and cfp parameters according to 2321 * last beacon we received (which may be none). 2322 */ 2323 dtimperiod = ni->ni_dtim_period; 2324 if (dtimperiod <= 0) /* NB: 0 if not known */ 2325 dtimperiod = 1; 2326 dtimcount = ni->ni_dtim_count; 2327 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2328 dtimcount = 0; /* XXX? */ 2329 cfpperiod = 1; /* NB: no PCF support yet */ 2330 cfpcount = 0; 2331 /* 2332 * Pull nexttbtt forward to reflect the current 2333 * TSF and calculate dtim+cfp state for the result. 2334 */ 2335 tsf = ath_hal_gettsf64(ah); 2336 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2337 do { 2338 nexttbtt += intval; 2339 if (--dtimcount < 0) { 2340 dtimcount = dtimperiod - 1; 2341 if (--cfpcount < 0) 2342 cfpcount = cfpperiod - 1; 2343 } 2344 } while (nexttbtt < tsftu); 2345 memset(&bs, 0, sizeof(bs)); 2346 bs.bs_intval = intval; 2347 bs.bs_nexttbtt = nexttbtt; 2348 bs.bs_dtimperiod = dtimperiod*intval; 2349 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2350 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2351 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2352 bs.bs_cfpmaxduration = 0; 2353 #if 0 2354 /* 2355 * The 802.11 layer records the offset to the DTIM 2356 * bitmap while receiving beacons; use it here to 2357 * enable h/w detection of our AID being marked in 2358 * the bitmap vector (to indicate frames for us are 2359 * pending at the AP). 2360 * XXX do DTIM handling in s/w to WAR old h/w bugs 2361 * XXX enable based on h/w rev for newer chips 2362 */ 2363 bs.bs_timoffset = ni->ni_timoff; 2364 #endif 2365 /* 2366 * Calculate the number of consecutive beacons to miss 2367 * before taking a BMISS interrupt. The configuration 2368 * is specified in ms, so we need to convert that to 2369 * TU's and then calculate based on the beacon interval. 2370 * Note that we clamp the result to at most 10 beacons. 2371 */ 2372 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2373 if (bs.bs_bmissthreshold > 10) 2374 bs.bs_bmissthreshold = 10; 2375 else if (bs.bs_bmissthreshold <= 0) 2376 bs.bs_bmissthreshold = 1; 2377 2378 /* 2379 * Calculate sleep duration. The configuration is 2380 * given in ms. We insure a multiple of the beacon 2381 * period is used. Also, if the sleep duration is 2382 * greater than the DTIM period then it makes senses 2383 * to make it a multiple of that. 2384 * 2385 * XXX fixed at 100ms 2386 */ 2387 bs.bs_sleepduration = 2388 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2389 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2390 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2391 2392 DPRINTF(sc, ATH_DEBUG_BEACON, 2393 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2394 , __func__ 2395 , tsf, tsftu 2396 , bs.bs_intval 2397 , bs.bs_nexttbtt 2398 , bs.bs_dtimperiod 2399 , bs.bs_nextdtim 2400 , bs.bs_bmissthreshold 2401 , bs.bs_sleepduration 2402 , bs.bs_cfpperiod 2403 , bs.bs_cfpmaxduration 2404 , bs.bs_cfpnext 2405 , bs.bs_timoffset 2406 ); 2407 ath_hal_intrset(ah, 0); 2408 ath_hal_beacontimers(ah, &bs); 2409 sc->sc_imask |= HAL_INT_BMISS; 2410 ath_hal_intrset(ah, sc->sc_imask); 2411 } else { 2412 ath_hal_intrset(ah, 0); 2413 if (nexttbtt == intval) 2414 intval |= HAL_BEACON_RESET_TSF; 2415 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2416 /* 2417 * In IBSS mode enable the beacon timers but only 2418 * enable SWBA interrupts if we need to manually 2419 * prepare beacon frames. Otherwise we use a 2420 * self-linked tx descriptor and let the hardware 2421 * deal with things. 2422 */ 2423 intval |= HAL_BEACON_ENA; 2424 if (!sc->sc_hasveol) 2425 sc->sc_imask |= HAL_INT_SWBA; 2426 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2427 /* 2428 * Pull nexttbtt forward to reflect 2429 * the current TSF. 2430 */ 2431 tsf = ath_hal_gettsf64(ah); 2432 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2433 do { 2434 nexttbtt += intval; 2435 } while (nexttbtt < tsftu); 2436 } 2437 ath_beaconq_config(sc); 2438 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2439 /* 2440 * In AP mode we enable the beacon timers and 2441 * SWBA interrupts to prepare beacon frames. 2442 */ 2443 intval |= HAL_BEACON_ENA; 2444 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2445 ath_beaconq_config(sc); 2446 } 2447 ath_hal_beaconinit(ah, nexttbtt, intval); 2448 sc->sc_bmisscount = 0; 2449 ath_hal_intrset(ah, sc->sc_imask); 2450 /* 2451 * When using a self-linked beacon descriptor in 2452 * ibss mode load it once here. 2453 */ 2454 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2455 ath_beacon_proc(sc, 0); 2456 } 2457 sc->sc_syncbeacon = 0; 2458 #undef UNDEF 2459 #undef TSF_TO_TU 2460 } 2461 2462 static int 2463 ath_descdma_setup(struct ath_softc *sc, 2464 struct ath_descdma *dd, ath_bufhead *head, 2465 const char *name, int nbuf, int ndesc) 2466 { 2467 #define DS2PHYS(_dd, _ds) \ 2468 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2469 struct ifnet *ifp = &sc->sc_if; 2470 struct ath_desc *ds; 2471 struct ath_buf *bf; 2472 int i, bsize, error; 2473 2474 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2475 __func__, name, nbuf, ndesc); 2476 2477 dd->dd_name = name; 2478 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2479 2480 /* 2481 * Setup DMA descriptor area. 2482 */ 2483 dd->dd_dmat = sc->sc_dmat; 2484 2485 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2486 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2487 2488 if (error != 0) { 2489 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2490 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2491 goto fail0; 2492 } 2493 2494 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2495 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2496 if (error != 0) { 2497 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2498 nbuf * ndesc, dd->dd_name, error); 2499 goto fail1; 2500 } 2501 2502 /* allocate descriptors */ 2503 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2504 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2505 if (error != 0) { 2506 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2507 "error %u\n", dd->dd_name, error); 2508 goto fail2; 2509 } 2510 2511 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2512 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2513 if (error != 0) { 2514 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2515 dd->dd_name, error); 2516 goto fail3; 2517 } 2518 2519 ds = dd->dd_desc; 2520 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2521 DPRINTF(sc, ATH_DEBUG_RESET, 2522 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2523 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2524 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2525 2526 /* allocate rx buffers */ 2527 bsize = sizeof(struct ath_buf) * nbuf; 2528 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2529 if (bf == NULL) { 2530 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2531 dd->dd_name, bsize); 2532 goto fail4; 2533 } 2534 dd->dd_bufptr = bf; 2535 2536 STAILQ_INIT(head); 2537 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2538 bf->bf_desc = ds; 2539 bf->bf_daddr = DS2PHYS(dd, ds); 2540 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2541 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2542 if (error != 0) { 2543 if_printf(ifp, "unable to create dmamap for %s " 2544 "buffer %u, error %u\n", dd->dd_name, i, error); 2545 ath_descdma_cleanup(sc, dd, head); 2546 return error; 2547 } 2548 STAILQ_INSERT_TAIL(head, bf, bf_list); 2549 } 2550 return 0; 2551 fail4: 2552 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2553 fail3: 2554 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2555 fail2: 2556 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2557 fail1: 2558 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2559 fail0: 2560 memset(dd, 0, sizeof(*dd)); 2561 return error; 2562 #undef DS2PHYS 2563 } 2564 2565 static void 2566 ath_descdma_cleanup(struct ath_softc *sc, 2567 struct ath_descdma *dd, ath_bufhead *head) 2568 { 2569 struct ath_buf *bf; 2570 struct ieee80211_node *ni; 2571 2572 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2573 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2574 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2575 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2576 2577 STAILQ_FOREACH(bf, head, bf_list) { 2578 if (bf->bf_m) { 2579 m_freem(bf->bf_m); 2580 bf->bf_m = NULL; 2581 } 2582 if (bf->bf_dmamap != NULL) { 2583 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2584 bf->bf_dmamap = NULL; 2585 } 2586 ni = bf->bf_node; 2587 bf->bf_node = NULL; 2588 if (ni != NULL) { 2589 /* 2590 * Reclaim node reference. 2591 */ 2592 ieee80211_free_node(ni); 2593 } 2594 } 2595 2596 STAILQ_INIT(head); 2597 free(dd->dd_bufptr, M_ATHDEV); 2598 memset(dd, 0, sizeof(*dd)); 2599 } 2600 2601 static int 2602 ath_desc_alloc(struct ath_softc *sc) 2603 { 2604 int error; 2605 2606 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2607 "rx", ath_rxbuf, 1); 2608 if (error != 0) 2609 return error; 2610 2611 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2612 "tx", ath_txbuf, ATH_TXDESC); 2613 if (error != 0) { 2614 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2615 return error; 2616 } 2617 2618 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2619 "beacon", 1, 1); 2620 if (error != 0) { 2621 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2622 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2623 return error; 2624 } 2625 return 0; 2626 } 2627 2628 static void 2629 ath_desc_free(struct ath_softc *sc) 2630 { 2631 2632 if (sc->sc_bdma.dd_desc_len != 0) 2633 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2634 if (sc->sc_txdma.dd_desc_len != 0) 2635 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2636 if (sc->sc_rxdma.dd_desc_len != 0) 2637 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2638 } 2639 2640 static struct ieee80211_node * 2641 ath_node_alloc(struct ieee80211_node_table *nt) 2642 { 2643 struct ieee80211com *ic = nt->nt_ic; 2644 struct ath_softc *sc = ic->ic_ifp->if_softc; 2645 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2646 struct ath_node *an; 2647 2648 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2649 if (an == NULL) { 2650 /* XXX stat+msg */ 2651 return NULL; 2652 } 2653 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2654 ath_rate_node_init(sc, an); 2655 2656 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2657 return &an->an_node; 2658 } 2659 2660 static void 2661 ath_node_free(struct ieee80211_node *ni) 2662 { 2663 struct ieee80211com *ic = ni->ni_ic; 2664 struct ath_softc *sc = ic->ic_ifp->if_softc; 2665 2666 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2667 2668 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2669 sc->sc_node_free(ni); 2670 } 2671 2672 static u_int8_t 2673 ath_node_getrssi(const struct ieee80211_node *ni) 2674 { 2675 #define HAL_EP_RND(x, mul) \ 2676 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2677 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2678 int32_t rssi; 2679 2680 /* 2681 * When only one frame is received there will be no state in 2682 * avgrssi so fallback on the value recorded by the 802.11 layer. 2683 */ 2684 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2685 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2686 else 2687 rssi = ni->ni_rssi; 2688 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2689 #undef HAL_EP_RND 2690 } 2691 2692 static int 2693 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2694 { 2695 struct ath_hal *ah = sc->sc_ah; 2696 int error; 2697 struct mbuf *m; 2698 struct ath_desc *ds; 2699 2700 m = bf->bf_m; 2701 if (m == NULL) { 2702 /* 2703 * NB: by assigning a page to the rx dma buffer we 2704 * implicitly satisfy the Atheros requirement that 2705 * this buffer be cache-line-aligned and sized to be 2706 * multiple of the cache line size. Not doing this 2707 * causes weird stuff to happen (for the 5210 at least). 2708 */ 2709 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2710 if (m == NULL) { 2711 DPRINTF(sc, ATH_DEBUG_ANY, 2712 "%s: no mbuf/cluster\n", __func__); 2713 sc->sc_stats.ast_rx_nombuf++; 2714 return ENOMEM; 2715 } 2716 bf->bf_m = m; 2717 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2718 2719 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2720 bf->bf_dmamap, m, 2721 BUS_DMA_NOWAIT); 2722 if (error != 0) { 2723 DPRINTF(sc, ATH_DEBUG_ANY, 2724 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2725 __func__, error); 2726 sc->sc_stats.ast_rx_busdma++; 2727 return error; 2728 } 2729 KASSERT(bf->bf_nseg == 1, 2730 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2731 } 2732 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2733 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2734 2735 /* 2736 * Setup descriptors. For receive we always terminate 2737 * the descriptor list with a self-linked entry so we'll 2738 * not get overrun under high load (as can happen with a 2739 * 5212 when ANI processing enables PHY error frames). 2740 * 2741 * To insure the last descriptor is self-linked we create 2742 * each descriptor as self-linked and add it to the end. As 2743 * each additional descriptor is added the previous self-linked 2744 * entry is ``fixed'' naturally. This should be safe even 2745 * if DMA is happening. When processing RX interrupts we 2746 * never remove/process the last, self-linked, entry on the 2747 * descriptor list. This insures the hardware always has 2748 * someplace to write a new frame. 2749 */ 2750 ds = bf->bf_desc; 2751 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2752 ds->ds_data = bf->bf_segs[0].ds_addr; 2753 ds->ds_vdata = mtod(m, void *); /* for radar */ 2754 ath_hal_setuprxdesc(ah, ds 2755 , m->m_len /* buffer size */ 2756 , 0 2757 ); 2758 2759 if (sc->sc_rxlink != NULL) 2760 *sc->sc_rxlink = bf->bf_daddr; 2761 sc->sc_rxlink = &ds->ds_link; 2762 return 0; 2763 } 2764 2765 /* 2766 * Extend 15-bit time stamp from rx descriptor to 2767 * a full 64-bit TSF using the specified TSF. 2768 */ 2769 static inline u_int64_t 2770 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2771 { 2772 if ((tsf & 0x7fff) < rstamp) 2773 tsf -= 0x8000; 2774 return ((tsf &~ 0x7fff) | rstamp); 2775 } 2776 2777 /* 2778 * Intercept management frames to collect beacon rssi data 2779 * and to do ibss merges. 2780 */ 2781 static void 2782 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2783 struct ieee80211_node *ni, 2784 int subtype, int rssi, u_int32_t rstamp) 2785 { 2786 struct ath_softc *sc = ic->ic_ifp->if_softc; 2787 2788 /* 2789 * Call up first so subsequent work can use information 2790 * potentially stored in the node (e.g. for ibss merge). 2791 */ 2792 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2793 switch (subtype) { 2794 case IEEE80211_FC0_SUBTYPE_BEACON: 2795 /* update rssi statistics for use by the hal */ 2796 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2797 if (sc->sc_syncbeacon && 2798 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2799 /* 2800 * Resync beacon timers using the tsf of the beacon 2801 * frame we just received. 2802 */ 2803 ath_beacon_config(sc); 2804 } 2805 /* fall thru... */ 2806 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2807 if (ic->ic_opmode == IEEE80211_M_IBSS && 2808 ic->ic_state == IEEE80211_S_RUN) { 2809 u_int64_t tsf = ath_extend_tsf(rstamp, 2810 ath_hal_gettsf64(sc->sc_ah)); 2811 2812 /* 2813 * Handle ibss merge as needed; check the tsf on the 2814 * frame before attempting the merge. The 802.11 spec 2815 * says the station should change it's bssid to match 2816 * the oldest station with the same ssid, where oldest 2817 * is determined by the tsf. Note that hardware 2818 * reconfiguration happens through callback to 2819 * ath_newstate as the state machine will go from 2820 * RUN -> RUN when this happens. 2821 */ 2822 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2823 DPRINTF(sc, ATH_DEBUG_STATE, 2824 "ibss merge, rstamp %u tsf %ju " 2825 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2826 (uintmax_t)ni->ni_tstamp.tsf); 2827 (void) ieee80211_ibss_merge(ni); 2828 } 2829 } 2830 break; 2831 } 2832 } 2833 2834 /* 2835 * Set the default antenna. 2836 */ 2837 static void 2838 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2839 { 2840 struct ath_hal *ah = sc->sc_ah; 2841 2842 /* XXX block beacon interrupts */ 2843 ath_hal_setdefantenna(ah, antenna); 2844 if (sc->sc_defant != antenna) 2845 sc->sc_stats.ast_ant_defswitch++; 2846 sc->sc_defant = antenna; 2847 sc->sc_rxotherant = 0; 2848 } 2849 2850 static void 2851 ath_rx_proc(void *arg, int npending) 2852 { 2853 #define PA2DESC(_sc, _pa) \ 2854 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2855 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2856 struct ath_softc *sc = arg; 2857 struct ath_buf *bf; 2858 struct ieee80211com *ic = &sc->sc_ic; 2859 struct ifnet *ifp = &sc->sc_if; 2860 struct ath_hal *ah = sc->sc_ah; 2861 struct ath_desc *ds; 2862 struct mbuf *m; 2863 struct ieee80211_node *ni; 2864 struct ath_node *an; 2865 int len, type, ngood; 2866 u_int phyerr; 2867 HAL_STATUS status; 2868 int16_t nf; 2869 u_int64_t tsf; 2870 2871 NET_LOCK_GIANT(); /* XXX */ 2872 2873 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2874 ngood = 0; 2875 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2876 tsf = ath_hal_gettsf64(ah); 2877 do { 2878 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2879 if (bf == NULL) { /* NB: shouldn't happen */ 2880 if_printf(ifp, "%s: no buffer!\n", __func__); 2881 break; 2882 } 2883 ds = bf->bf_desc; 2884 if (ds->ds_link == bf->bf_daddr) { 2885 /* NB: never process the self-linked entry at the end */ 2886 break; 2887 } 2888 m = bf->bf_m; 2889 if (m == NULL) { /* NB: shouldn't happen */ 2890 if_printf(ifp, "%s: no mbuf!\n", __func__); 2891 break; 2892 } 2893 /* XXX sync descriptor memory */ 2894 /* 2895 * Must provide the virtual address of the current 2896 * descriptor, the physical address, and the virtual 2897 * address of the next descriptor in the h/w chain. 2898 * This allows the HAL to look ahead to see if the 2899 * hardware is done with a descriptor by checking the 2900 * done bit in the following descriptor and the address 2901 * of the current descriptor the DMA engine is working 2902 * on. All this is necessary because of our use of 2903 * a self-linked list to avoid rx overruns. 2904 */ 2905 status = ath_hal_rxprocdesc(ah, ds, 2906 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2907 #ifdef AR_DEBUG 2908 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2909 ath_printrxbuf(bf, status == HAL_OK); 2910 #endif 2911 if (status == HAL_EINPROGRESS) 2912 break; 2913 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2914 if (ds->ds_rxstat.rs_more) { 2915 /* 2916 * Frame spans multiple descriptors; this 2917 * cannot happen yet as we don't support 2918 * jumbograms. If not in monitor mode, 2919 * discard the frame. 2920 */ 2921 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2922 sc->sc_stats.ast_rx_toobig++; 2923 goto rx_next; 2924 } 2925 /* fall thru for monitor mode handling... */ 2926 } else if (ds->ds_rxstat.rs_status != 0) { 2927 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2928 sc->sc_stats.ast_rx_crcerr++; 2929 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2930 sc->sc_stats.ast_rx_fifoerr++; 2931 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2932 sc->sc_stats.ast_rx_phyerr++; 2933 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2934 sc->sc_stats.ast_rx_phy[phyerr]++; 2935 goto rx_next; 2936 } 2937 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2938 /* 2939 * Decrypt error. If the error occurred 2940 * because there was no hardware key, then 2941 * let the frame through so the upper layers 2942 * can process it. This is necessary for 5210 2943 * parts which have no way to setup a ``clear'' 2944 * key cache entry. 2945 * 2946 * XXX do key cache faulting 2947 */ 2948 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2949 goto rx_accept; 2950 sc->sc_stats.ast_rx_badcrypt++; 2951 } 2952 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2953 sc->sc_stats.ast_rx_badmic++; 2954 /* 2955 * Do minimal work required to hand off 2956 * the 802.11 header for notifcation. 2957 */ 2958 /* XXX frag's and qos frames */ 2959 len = ds->ds_rxstat.rs_datalen; 2960 if (len >= sizeof (struct ieee80211_frame)) { 2961 bus_dmamap_sync(sc->sc_dmat, 2962 bf->bf_dmamap, 2963 0, bf->bf_dmamap->dm_mapsize, 2964 BUS_DMASYNC_POSTREAD); 2965 ieee80211_notify_michael_failure(ic, 2966 mtod(m, struct ieee80211_frame *), 2967 sc->sc_splitmic ? 2968 ds->ds_rxstat.rs_keyix-32 : 2969 ds->ds_rxstat.rs_keyix 2970 ); 2971 } 2972 } 2973 ifp->if_ierrors++; 2974 /* 2975 * Reject error frames, we normally don't want 2976 * to see them in monitor mode (in monitor mode 2977 * allow through packets that have crypto problems). 2978 */ 2979 if ((ds->ds_rxstat.rs_status &~ 2980 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2981 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2982 goto rx_next; 2983 } 2984 rx_accept: 2985 /* 2986 * Sync and unmap the frame. At this point we're 2987 * committed to passing the mbuf somewhere so clear 2988 * bf_m; this means a new sk_buff must be allocated 2989 * when the rx descriptor is setup again to receive 2990 * another frame. 2991 */ 2992 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2993 0, bf->bf_dmamap->dm_mapsize, 2994 BUS_DMASYNC_POSTREAD); 2995 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2996 bf->bf_m = NULL; 2997 2998 m->m_pkthdr.rcvif = ifp; 2999 len = ds->ds_rxstat.rs_datalen; 3000 m->m_pkthdr.len = m->m_len = len; 3001 3002 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3003 3004 #if NBPFILTER > 0 3005 if (sc->sc_drvbpf) { 3006 u_int8_t rix; 3007 3008 /* 3009 * Discard anything shorter than an ack or cts. 3010 */ 3011 if (len < IEEE80211_ACK_LEN) { 3012 DPRINTF(sc, ATH_DEBUG_RECV, 3013 "%s: runt packet %d\n", 3014 __func__, len); 3015 sc->sc_stats.ast_rx_tooshort++; 3016 m_freem(m); 3017 goto rx_next; 3018 } 3019 rix = ds->ds_rxstat.rs_rate; 3020 sc->sc_rx_th.wr_tsf = htole64( 3021 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3022 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3023 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3024 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3025 sc->sc_rx_th.wr_antnoise = nf; 3026 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3027 3028 bpf_mtap2(sc->sc_drvbpf, 3029 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3030 } 3031 #endif 3032 3033 /* 3034 * From this point on we assume the frame is at least 3035 * as large as ieee80211_frame_min; verify that. 3036 */ 3037 if (len < IEEE80211_MIN_LEN) { 3038 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3039 __func__, len); 3040 sc->sc_stats.ast_rx_tooshort++; 3041 m_freem(m); 3042 goto rx_next; 3043 } 3044 3045 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3046 ieee80211_dump_pkt(mtod(m, void *), len, 3047 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3048 ds->ds_rxstat.rs_rssi); 3049 } 3050 3051 m_adj(m, -IEEE80211_CRC_LEN); 3052 3053 /* 3054 * Locate the node for sender, track state, and then 3055 * pass the (referenced) node up to the 802.11 layer 3056 * for its use. 3057 */ 3058 ni = ieee80211_find_rxnode_withkey(ic, 3059 mtod(m, const struct ieee80211_frame_min *), 3060 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3061 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3062 /* 3063 * Track rx rssi and do any rx antenna management. 3064 */ 3065 an = ATH_NODE(ni); 3066 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3067 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3068 /* 3069 * Send frame up for processing. 3070 */ 3071 type = ieee80211_input(ic, m, ni, 3072 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3073 ieee80211_free_node(ni); 3074 if (sc->sc_diversity) { 3075 /* 3076 * When using fast diversity, change the default rx 3077 * antenna if diversity chooses the other antenna 3 3078 * times in a row. 3079 */ 3080 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3081 if (++sc->sc_rxotherant >= 3) 3082 ath_setdefantenna(sc, 3083 ds->ds_rxstat.rs_antenna); 3084 } else 3085 sc->sc_rxotherant = 0; 3086 } 3087 if (sc->sc_softled) { 3088 /* 3089 * Blink for any data frame. Otherwise do a 3090 * heartbeat-style blink when idle. The latter 3091 * is mainly for station mode where we depend on 3092 * periodic beacon frames to trigger the poll event. 3093 */ 3094 if (type == IEEE80211_FC0_TYPE_DATA) { 3095 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3096 ath_led_event(sc, ATH_LED_RX); 3097 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3098 ath_led_event(sc, ATH_LED_POLL); 3099 } 3100 /* 3101 * Arrange to update the last rx timestamp only for 3102 * frames from our ap when operating in station mode. 3103 * This assumes the rx key is always setup when associated. 3104 */ 3105 if (ic->ic_opmode == IEEE80211_M_STA && 3106 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3107 ngood++; 3108 rx_next: 3109 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3110 } while (ath_rxbuf_init(sc, bf) == 0); 3111 3112 /* rx signal state monitoring */ 3113 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3114 if (ath_hal_radar_event(ah)) 3115 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3116 if (ngood) 3117 sc->sc_lastrx = tsf; 3118 3119 #ifdef __NetBSD__ 3120 /* XXX Why isn't this necessary in FreeBSD? */ 3121 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3122 ath_start(ifp); 3123 #endif /* __NetBSD__ */ 3124 3125 NET_UNLOCK_GIANT(); /* XXX */ 3126 #undef PA2DESC 3127 } 3128 3129 /* 3130 * Setup a h/w transmit queue. 3131 */ 3132 static struct ath_txq * 3133 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3134 { 3135 #define N(a) (sizeof(a)/sizeof(a[0])) 3136 struct ath_hal *ah = sc->sc_ah; 3137 HAL_TXQ_INFO qi; 3138 int qnum; 3139 3140 memset(&qi, 0, sizeof(qi)); 3141 qi.tqi_subtype = subtype; 3142 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3143 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3144 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3145 /* 3146 * Enable interrupts only for EOL and DESC conditions. 3147 * We mark tx descriptors to receive a DESC interrupt 3148 * when a tx queue gets deep; otherwise waiting for the 3149 * EOL to reap descriptors. Note that this is done to 3150 * reduce interrupt load and this only defers reaping 3151 * descriptors, never transmitting frames. Aside from 3152 * reducing interrupts this also permits more concurrency. 3153 * The only potential downside is if the tx queue backs 3154 * up in which case the top half of the kernel may backup 3155 * due to a lack of tx descriptors. 3156 */ 3157 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3158 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3159 if (qnum == -1) { 3160 /* 3161 * NB: don't print a message, this happens 3162 * normally on parts with too few tx queues 3163 */ 3164 return NULL; 3165 } 3166 if (qnum >= N(sc->sc_txq)) { 3167 device_printf(sc->sc_dev, 3168 "hal qnum %u out of range, max %zu!\n", 3169 qnum, N(sc->sc_txq)); 3170 ath_hal_releasetxqueue(ah, qnum); 3171 return NULL; 3172 } 3173 if (!ATH_TXQ_SETUP(sc, qnum)) { 3174 struct ath_txq *txq = &sc->sc_txq[qnum]; 3175 3176 txq->axq_qnum = qnum; 3177 txq->axq_depth = 0; 3178 txq->axq_intrcnt = 0; 3179 txq->axq_link = NULL; 3180 STAILQ_INIT(&txq->axq_q); 3181 ATH_TXQ_LOCK_INIT(sc, txq); 3182 sc->sc_txqsetup |= 1<<qnum; 3183 } 3184 return &sc->sc_txq[qnum]; 3185 #undef N 3186 } 3187 3188 /* 3189 * Setup a hardware data transmit queue for the specified 3190 * access control. The hal may not support all requested 3191 * queues in which case it will return a reference to a 3192 * previously setup queue. We record the mapping from ac's 3193 * to h/w queues for use by ath_tx_start and also track 3194 * the set of h/w queues being used to optimize work in the 3195 * transmit interrupt handler and related routines. 3196 */ 3197 static int 3198 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3199 { 3200 #define N(a) (sizeof(a)/sizeof(a[0])) 3201 struct ath_txq *txq; 3202 3203 if (ac >= N(sc->sc_ac2q)) { 3204 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3205 ac, N(sc->sc_ac2q)); 3206 return 0; 3207 } 3208 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3209 if (txq != NULL) { 3210 sc->sc_ac2q[ac] = txq; 3211 return 1; 3212 } else 3213 return 0; 3214 #undef N 3215 } 3216 3217 /* 3218 * Update WME parameters for a transmit queue. 3219 */ 3220 static int 3221 ath_txq_update(struct ath_softc *sc, int ac) 3222 { 3223 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3224 #define ATH_TXOP_TO_US(v) (v<<5) 3225 struct ieee80211com *ic = &sc->sc_ic; 3226 struct ath_txq *txq = sc->sc_ac2q[ac]; 3227 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3228 struct ath_hal *ah = sc->sc_ah; 3229 HAL_TXQ_INFO qi; 3230 3231 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3232 qi.tqi_aifs = wmep->wmep_aifsn; 3233 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3234 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3235 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3236 3237 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3238 device_printf(sc->sc_dev, "unable to update hardware queue " 3239 "parameters for %s traffic!\n", 3240 ieee80211_wme_acnames[ac]); 3241 return 0; 3242 } else { 3243 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3244 return 1; 3245 } 3246 #undef ATH_TXOP_TO_US 3247 #undef ATH_EXPONENT_TO_VALUE 3248 } 3249 3250 /* 3251 * Callback from the 802.11 layer to update WME parameters. 3252 */ 3253 static int 3254 ath_wme_update(struct ieee80211com *ic) 3255 { 3256 struct ath_softc *sc = ic->ic_ifp->if_softc; 3257 3258 return !ath_txq_update(sc, WME_AC_BE) || 3259 !ath_txq_update(sc, WME_AC_BK) || 3260 !ath_txq_update(sc, WME_AC_VI) || 3261 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3262 } 3263 3264 /* 3265 * Reclaim resources for a setup queue. 3266 */ 3267 static void 3268 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3269 { 3270 3271 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3272 ATH_TXQ_LOCK_DESTROY(txq); 3273 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3274 } 3275 3276 /* 3277 * Reclaim all tx queue resources. 3278 */ 3279 static void 3280 ath_tx_cleanup(struct ath_softc *sc) 3281 { 3282 int i; 3283 3284 ATH_TXBUF_LOCK_DESTROY(sc); 3285 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3286 if (ATH_TXQ_SETUP(sc, i)) 3287 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3288 } 3289 3290 /* 3291 * Defragment an mbuf chain, returning at most maxfrags separate 3292 * mbufs+clusters. If this is not possible NULL is returned and 3293 * the original mbuf chain is left in it's present (potentially 3294 * modified) state. We use two techniques: collapsing consecutive 3295 * mbufs and replacing consecutive mbufs by a cluster. 3296 */ 3297 static struct mbuf * 3298 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3299 { 3300 struct mbuf *m, *n, *n2, **prev; 3301 u_int curfrags; 3302 3303 /* 3304 * Calculate the current number of frags. 3305 */ 3306 curfrags = 0; 3307 for (m = m0; m != NULL; m = m->m_next) 3308 curfrags++; 3309 /* 3310 * First, try to collapse mbufs. Note that we always collapse 3311 * towards the front so we don't need to deal with moving the 3312 * pkthdr. This may be suboptimal if the first mbuf has much 3313 * less data than the following. 3314 */ 3315 m = m0; 3316 again: 3317 for (;;) { 3318 n = m->m_next; 3319 if (n == NULL) 3320 break; 3321 if (n->m_len < M_TRAILINGSPACE(m)) { 3322 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3323 n->m_len); 3324 m->m_len += n->m_len; 3325 m->m_next = n->m_next; 3326 m_free(n); 3327 if (--curfrags <= maxfrags) 3328 return m0; 3329 } else 3330 m = n; 3331 } 3332 KASSERT(maxfrags > 1, 3333 ("maxfrags %u, but normal collapse failed", maxfrags)); 3334 /* 3335 * Collapse consecutive mbufs to a cluster. 3336 */ 3337 prev = &m0->m_next; /* NB: not the first mbuf */ 3338 while ((n = *prev) != NULL) { 3339 if ((n2 = n->m_next) != NULL && 3340 n->m_len + n2->m_len < MCLBYTES) { 3341 m = m_getcl(how, MT_DATA, 0); 3342 if (m == NULL) 3343 goto bad; 3344 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3345 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3346 n2->m_len); 3347 m->m_len = n->m_len + n2->m_len; 3348 m->m_next = n2->m_next; 3349 *prev = m; 3350 m_free(n); 3351 m_free(n2); 3352 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3353 return m0; 3354 /* 3355 * Still not there, try the normal collapse 3356 * again before we allocate another cluster. 3357 */ 3358 goto again; 3359 } 3360 prev = &n->m_next; 3361 } 3362 /* 3363 * No place where we can collapse to a cluster; punt. 3364 * This can occur if, for example, you request 2 frags 3365 * but the packet requires that both be clusters (we 3366 * never reallocate the first mbuf to avoid moving the 3367 * packet header). 3368 */ 3369 bad: 3370 return NULL; 3371 } 3372 3373 /* 3374 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3375 */ 3376 static int 3377 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3378 { 3379 int i; 3380 3381 for (i = 0; i < rt->rateCount; i++) 3382 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3383 return i; 3384 return 0; /* NB: lowest rate */ 3385 } 3386 3387 static void 3388 ath_freetx(struct mbuf *m) 3389 { 3390 struct mbuf *next; 3391 3392 do { 3393 next = m->m_nextpkt; 3394 m->m_nextpkt = NULL; 3395 m_freem(m); 3396 } while ((m = next) != NULL); 3397 } 3398 3399 static int 3400 deduct_pad_bytes(int len, int hdrlen) 3401 { 3402 /* XXX I am suspicious that this code, which I extracted 3403 * XXX from ath_tx_start() for reuse, does the right thing. 3404 */ 3405 return len - (hdrlen & 3); 3406 } 3407 3408 static int 3409 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3410 struct mbuf *m0) 3411 { 3412 struct ieee80211com *ic = &sc->sc_ic; 3413 struct ath_hal *ah = sc->sc_ah; 3414 struct ifnet *ifp = &sc->sc_if; 3415 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3416 int i, error, iswep, ismcast, isfrag, ismrr; 3417 int keyix, hdrlen, pktlen, try0; 3418 u_int8_t rix, txrate, ctsrate; 3419 u_int8_t cix = 0xff; /* NB: silence compiler */ 3420 struct ath_desc *ds, *ds0; 3421 struct ath_txq *txq; 3422 struct ieee80211_frame *wh; 3423 u_int subtype, flags, ctsduration; 3424 HAL_PKT_TYPE atype; 3425 const HAL_RATE_TABLE *rt; 3426 HAL_BOOL shortPreamble; 3427 struct ath_node *an; 3428 struct mbuf *m; 3429 u_int pri; 3430 3431 wh = mtod(m0, struct ieee80211_frame *); 3432 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3433 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3434 isfrag = m0->m_flags & M_FRAG; 3435 hdrlen = ieee80211_anyhdrsize(wh); 3436 /* 3437 * Packet length must not include any 3438 * pad bytes; deduct them here. 3439 */ 3440 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3441 3442 if (iswep) { 3443 const struct ieee80211_cipher *cip; 3444 struct ieee80211_key *k; 3445 3446 /* 3447 * Construct the 802.11 header+trailer for an encrypted 3448 * frame. The only reason this can fail is because of an 3449 * unknown or unsupported cipher/key type. 3450 */ 3451 k = ieee80211_crypto_encap(ic, ni, m0); 3452 if (k == NULL) { 3453 /* 3454 * This can happen when the key is yanked after the 3455 * frame was queued. Just discard the frame; the 3456 * 802.11 layer counts failures and provides 3457 * debugging/diagnostics. 3458 */ 3459 ath_freetx(m0); 3460 return EIO; 3461 } 3462 /* 3463 * Adjust the packet + header lengths for the crypto 3464 * additions and calculate the h/w key index. When 3465 * a s/w mic is done the frame will have had any mic 3466 * added to it prior to entry so m0->m_pkthdr.len above will 3467 * account for it. Otherwise we need to add it to the 3468 * packet length. 3469 */ 3470 cip = k->wk_cipher; 3471 hdrlen += cip->ic_header; 3472 pktlen += cip->ic_header + cip->ic_trailer; 3473 /* NB: frags always have any TKIP MIC done in s/w */ 3474 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3475 pktlen += cip->ic_miclen; 3476 keyix = k->wk_keyix; 3477 3478 /* packet header may have moved, reset our local pointer */ 3479 wh = mtod(m0, struct ieee80211_frame *); 3480 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3481 /* 3482 * Use station key cache slot, if assigned. 3483 */ 3484 keyix = ni->ni_ucastkey.wk_keyix; 3485 if (keyix == IEEE80211_KEYIX_NONE) 3486 keyix = HAL_TXKEYIX_INVALID; 3487 } else 3488 keyix = HAL_TXKEYIX_INVALID; 3489 3490 pktlen += IEEE80211_CRC_LEN; 3491 3492 /* 3493 * Load the DMA map so any coalescing is done. This 3494 * also calculates the number of descriptors we need. 3495 */ 3496 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3497 BUS_DMA_NOWAIT); 3498 if (error == EFBIG) { 3499 /* XXX packet requires too many descriptors */ 3500 bf->bf_nseg = ATH_TXDESC+1; 3501 } else if (error != 0) { 3502 sc->sc_stats.ast_tx_busdma++; 3503 ath_freetx(m0); 3504 return error; 3505 } 3506 /* 3507 * Discard null packets and check for packets that 3508 * require too many TX descriptors. We try to convert 3509 * the latter to a cluster. 3510 */ 3511 if (error == EFBIG) { /* too many desc's, linearize */ 3512 sc->sc_stats.ast_tx_linear++; 3513 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3514 if (m == NULL) { 3515 ath_freetx(m0); 3516 sc->sc_stats.ast_tx_nombuf++; 3517 return ENOMEM; 3518 } 3519 m0 = m; 3520 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3521 BUS_DMA_NOWAIT); 3522 if (error != 0) { 3523 sc->sc_stats.ast_tx_busdma++; 3524 ath_freetx(m0); 3525 return error; 3526 } 3527 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3528 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3529 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3530 sc->sc_stats.ast_tx_nodata++; 3531 ath_freetx(m0); 3532 return EIO; 3533 } 3534 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3535 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3536 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3537 bf->bf_m = m0; 3538 bf->bf_node = ni; /* NB: held reference */ 3539 3540 /* setup descriptors */ 3541 ds = bf->bf_desc; 3542 rt = sc->sc_currates; 3543 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3544 3545 /* 3546 * NB: the 802.11 layer marks whether or not we should 3547 * use short preamble based on the current mode and 3548 * negotiated parameters. 3549 */ 3550 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3551 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3552 shortPreamble = AH_TRUE; 3553 sc->sc_stats.ast_tx_shortpre++; 3554 } else { 3555 shortPreamble = AH_FALSE; 3556 } 3557 3558 an = ATH_NODE(ni); 3559 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3560 ismrr = 0; /* default no multi-rate retry*/ 3561 /* 3562 * Calculate Atheros packet type from IEEE80211 packet header, 3563 * setup for rate calculations, and select h/w transmit queue. 3564 */ 3565 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3566 case IEEE80211_FC0_TYPE_MGT: 3567 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3568 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3569 atype = HAL_PKT_TYPE_BEACON; 3570 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3571 atype = HAL_PKT_TYPE_PROBE_RESP; 3572 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3573 atype = HAL_PKT_TYPE_ATIM; 3574 else 3575 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3576 rix = sc->sc_minrateix; 3577 txrate = rt->info[rix].rateCode; 3578 if (shortPreamble) 3579 txrate |= rt->info[rix].shortPreamble; 3580 try0 = ATH_TXMGTTRY; 3581 /* NB: force all management frames to highest queue */ 3582 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3583 /* NB: force all management frames to highest queue */ 3584 pri = WME_AC_VO; 3585 } else 3586 pri = WME_AC_BE; 3587 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3588 break; 3589 case IEEE80211_FC0_TYPE_CTL: 3590 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3591 rix = sc->sc_minrateix; 3592 txrate = rt->info[rix].rateCode; 3593 if (shortPreamble) 3594 txrate |= rt->info[rix].shortPreamble; 3595 try0 = ATH_TXMGTTRY; 3596 /* NB: force all ctl frames to highest queue */ 3597 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3598 /* NB: force all ctl frames to highest queue */ 3599 pri = WME_AC_VO; 3600 } else 3601 pri = WME_AC_BE; 3602 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3603 break; 3604 case IEEE80211_FC0_TYPE_DATA: 3605 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3606 /* 3607 * Data frames: multicast frames go out at a fixed rate, 3608 * otherwise consult the rate control module for the 3609 * rate to use. 3610 */ 3611 if (ismcast) { 3612 /* 3613 * Check mcast rate setting in case it's changed. 3614 * XXX move out of fastpath 3615 */ 3616 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3617 sc->sc_mcastrix = 3618 ath_tx_findrix(rt, ic->ic_mcast_rate); 3619 sc->sc_mcastrate = ic->ic_mcast_rate; 3620 } 3621 rix = sc->sc_mcastrix; 3622 txrate = rt->info[rix].rateCode; 3623 try0 = 1; 3624 } else { 3625 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3626 &rix, &try0, &txrate); 3627 sc->sc_txrate = txrate; /* for LED blinking */ 3628 if (try0 != ATH_TXMAXTRY) 3629 ismrr = 1; 3630 } 3631 pri = M_WME_GETAC(m0); 3632 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3633 flags |= HAL_TXDESC_NOACK; 3634 break; 3635 default: 3636 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3637 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3638 /* XXX statistic */ 3639 ath_freetx(m0); 3640 return EIO; 3641 } 3642 txq = sc->sc_ac2q[pri]; 3643 3644 /* 3645 * When servicing one or more stations in power-save mode 3646 * multicast frames must be buffered until after the beacon. 3647 * We use the CAB queue for that. 3648 */ 3649 if (ismcast && ic->ic_ps_sta) { 3650 txq = sc->sc_cabq; 3651 /* XXX? more bit in 802.11 frame header */ 3652 } 3653 3654 /* 3655 * Calculate miscellaneous flags. 3656 */ 3657 if (ismcast) { 3658 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3659 } else if (pktlen > ic->ic_rtsthreshold) { 3660 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3661 cix = rt->info[rix].controlRate; 3662 sc->sc_stats.ast_tx_rts++; 3663 } 3664 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3665 sc->sc_stats.ast_tx_noack++; 3666 3667 /* 3668 * If 802.11g protection is enabled, determine whether 3669 * to use RTS/CTS or just CTS. Note that this is only 3670 * done for OFDM unicast frames. 3671 */ 3672 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3673 rt->info[rix].phy == IEEE80211_T_OFDM && 3674 (flags & HAL_TXDESC_NOACK) == 0) { 3675 /* XXX fragments must use CCK rates w/ protection */ 3676 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3677 flags |= HAL_TXDESC_RTSENA; 3678 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3679 flags |= HAL_TXDESC_CTSENA; 3680 if (isfrag) { 3681 /* 3682 * For frags it would be desirable to use the 3683 * highest CCK rate for RTS/CTS. But stations 3684 * farther away may detect it at a lower CCK rate 3685 * so use the configured protection rate instead 3686 * (for now). 3687 */ 3688 cix = rt->info[sc->sc_protrix].controlRate; 3689 } else 3690 cix = rt->info[sc->sc_protrix].controlRate; 3691 sc->sc_stats.ast_tx_protect++; 3692 } 3693 3694 /* 3695 * Calculate duration. This logically belongs in the 802.11 3696 * layer but it lacks sufficient information to calculate it. 3697 */ 3698 if ((flags & HAL_TXDESC_NOACK) == 0 && 3699 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3700 u_int16_t dur; 3701 /* 3702 * XXX not right with fragmentation. 3703 */ 3704 if (shortPreamble) 3705 dur = rt->info[rix].spAckDuration; 3706 else 3707 dur = rt->info[rix].lpAckDuration; 3708 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3709 dur += dur; /* additional SIFS+ACK */ 3710 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3711 /* 3712 * Include the size of next fragment so NAV is 3713 * updated properly. The last fragment uses only 3714 * the ACK duration 3715 */ 3716 dur += ath_hal_computetxtime(ah, rt, 3717 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3718 hdrlen) - 3719 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3720 rix, shortPreamble); 3721 } 3722 if (isfrag) { 3723 /* 3724 * Force hardware to use computed duration for next 3725 * fragment by disabling multi-rate retry which updates 3726 * duration based on the multi-rate duration table. 3727 */ 3728 try0 = ATH_TXMAXTRY; 3729 } 3730 *(u_int16_t *)wh->i_dur = htole16(dur); 3731 } 3732 3733 /* 3734 * Calculate RTS/CTS rate and duration if needed. 3735 */ 3736 ctsduration = 0; 3737 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3738 /* 3739 * CTS transmit rate is derived from the transmit rate 3740 * by looking in the h/w rate table. We must also factor 3741 * in whether or not a short preamble is to be used. 3742 */ 3743 /* NB: cix is set above where RTS/CTS is enabled */ 3744 KASSERT(cix != 0xff, ("cix not setup")); 3745 ctsrate = rt->info[cix].rateCode; 3746 /* 3747 * Compute the transmit duration based on the frame 3748 * size and the size of an ACK frame. We call into the 3749 * HAL to do the computation since it depends on the 3750 * characteristics of the actual PHY being used. 3751 * 3752 * NB: CTS is assumed the same size as an ACK so we can 3753 * use the precalculated ACK durations. 3754 */ 3755 if (shortPreamble) { 3756 ctsrate |= rt->info[cix].shortPreamble; 3757 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3758 ctsduration += rt->info[cix].spAckDuration; 3759 ctsduration += ath_hal_computetxtime(ah, 3760 rt, pktlen, rix, AH_TRUE); 3761 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3762 ctsduration += rt->info[rix].spAckDuration; 3763 } else { 3764 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3765 ctsduration += rt->info[cix].lpAckDuration; 3766 ctsduration += ath_hal_computetxtime(ah, 3767 rt, pktlen, rix, AH_FALSE); 3768 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3769 ctsduration += rt->info[rix].lpAckDuration; 3770 } 3771 /* 3772 * Must disable multi-rate retry when using RTS/CTS. 3773 */ 3774 ismrr = 0; 3775 try0 = ATH_TXMGTTRY; /* XXX */ 3776 } else 3777 ctsrate = 0; 3778 3779 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3780 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3781 sc->sc_hwmap[txrate].ieeerate, -1); 3782 #if NBPFILTER > 0 3783 if (ic->ic_rawbpf) 3784 bpf_mtap(ic->ic_rawbpf, m0); 3785 if (sc->sc_drvbpf) { 3786 u_int64_t tsf = ath_hal_gettsf64(ah); 3787 3788 sc->sc_tx_th.wt_tsf = htole64(tsf); 3789 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3790 if (iswep) 3791 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3792 if (isfrag) 3793 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3794 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3795 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3796 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3797 3798 bpf_mtap2(sc->sc_drvbpf, 3799 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3800 } 3801 #endif 3802 3803 /* 3804 * Determine if a tx interrupt should be generated for 3805 * this descriptor. We take a tx interrupt to reap 3806 * descriptors when the h/w hits an EOL condition or 3807 * when the descriptor is specifically marked to generate 3808 * an interrupt. We periodically mark descriptors in this 3809 * way to insure timely replenishing of the supply needed 3810 * for sending frames. Defering interrupts reduces system 3811 * load and potentially allows more concurrent work to be 3812 * done but if done to aggressively can cause senders to 3813 * backup. 3814 * 3815 * NB: use >= to deal with sc_txintrperiod changing 3816 * dynamically through sysctl. 3817 */ 3818 if (flags & HAL_TXDESC_INTREQ) { 3819 txq->axq_intrcnt = 0; 3820 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3821 flags |= HAL_TXDESC_INTREQ; 3822 txq->axq_intrcnt = 0; 3823 } 3824 3825 /* 3826 * Formulate first tx descriptor with tx controls. 3827 */ 3828 /* XXX check return value? */ 3829 ath_hal_setuptxdesc(ah, ds 3830 , pktlen /* packet length */ 3831 , hdrlen /* header length */ 3832 , atype /* Atheros packet type */ 3833 , ni->ni_txpower /* txpower */ 3834 , txrate, try0 /* series 0 rate/tries */ 3835 , keyix /* key cache index */ 3836 , sc->sc_txantenna /* antenna mode */ 3837 , flags /* flags */ 3838 , ctsrate /* rts/cts rate */ 3839 , ctsduration /* rts/cts duration */ 3840 ); 3841 bf->bf_flags = flags; 3842 /* 3843 * Setup the multi-rate retry state only when we're 3844 * going to use it. This assumes ath_hal_setuptxdesc 3845 * initializes the descriptors (so we don't have to) 3846 * when the hardware supports multi-rate retry and 3847 * we don't use it. 3848 */ 3849 if (ismrr) 3850 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3851 3852 /* 3853 * Fillin the remainder of the descriptor info. 3854 */ 3855 ds0 = ds; 3856 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3857 ds->ds_data = bf->bf_segs[i].ds_addr; 3858 if (i == bf->bf_nseg - 1) 3859 ds->ds_link = 0; 3860 else 3861 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3862 ath_hal_filltxdesc(ah, ds 3863 , bf->bf_segs[i].ds_len /* segment length */ 3864 , i == 0 /* first segment */ 3865 , i == bf->bf_nseg - 1 /* last segment */ 3866 , ds0 /* first descriptor */ 3867 ); 3868 3869 /* NB: The desc swap function becomes void, 3870 * if descriptor swapping is not enabled 3871 */ 3872 ath_desc_swap(ds); 3873 3874 DPRINTF(sc, ATH_DEBUG_XMIT, 3875 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3876 __func__, i, ds->ds_link, ds->ds_data, 3877 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3878 } 3879 /* 3880 * Insert the frame on the outbound list and 3881 * pass it on to the hardware. 3882 */ 3883 ATH_TXQ_LOCK(txq); 3884 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3885 if (txq->axq_link == NULL) { 3886 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3887 DPRINTF(sc, ATH_DEBUG_XMIT, 3888 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3889 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3890 txq->axq_depth); 3891 } else { 3892 *txq->axq_link = HTOAH32(bf->bf_daddr); 3893 DPRINTF(sc, ATH_DEBUG_XMIT, 3894 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3895 __func__, txq->axq_qnum, txq->axq_link, 3896 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3897 } 3898 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3899 /* 3900 * The CAB queue is started from the SWBA handler since 3901 * frames only go out on DTIM and to avoid possible races. 3902 */ 3903 if (txq != sc->sc_cabq) 3904 ath_hal_txstart(ah, txq->axq_qnum); 3905 ATH_TXQ_UNLOCK(txq); 3906 3907 return 0; 3908 } 3909 3910 /* 3911 * Process completed xmit descriptors from the specified queue. 3912 */ 3913 static int 3914 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3915 { 3916 struct ath_hal *ah = sc->sc_ah; 3917 struct ieee80211com *ic = &sc->sc_ic; 3918 struct ath_buf *bf; 3919 struct ath_desc *ds, *ds0; 3920 struct ieee80211_node *ni; 3921 struct ath_node *an; 3922 int sr, lr, pri, nacked; 3923 HAL_STATUS status; 3924 3925 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3926 __func__, txq->axq_qnum, 3927 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3928 txq->axq_link); 3929 nacked = 0; 3930 for (;;) { 3931 ATH_TXQ_LOCK(txq); 3932 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3933 bf = STAILQ_FIRST(&txq->axq_q); 3934 if (bf == NULL) { 3935 txq->axq_link = NULL; 3936 ATH_TXQ_UNLOCK(txq); 3937 break; 3938 } 3939 ds0 = &bf->bf_desc[0]; 3940 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3941 status = ath_hal_txprocdesc(ah, ds); 3942 #ifdef AR_DEBUG 3943 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3944 ath_printtxbuf(bf, status == HAL_OK); 3945 #endif 3946 if (status == HAL_EINPROGRESS) { 3947 ATH_TXQ_UNLOCK(txq); 3948 break; 3949 } 3950 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3951 ATH_TXQ_UNLOCK(txq); 3952 3953 ni = bf->bf_node; 3954 if (ni != NULL) { 3955 an = ATH_NODE(ni); 3956 if (ds->ds_txstat.ts_status == 0) { 3957 u_int8_t txant = ds->ds_txstat.ts_antenna; 3958 sc->sc_stats.ast_ant_tx[txant]++; 3959 sc->sc_ant_tx[txant]++; 3960 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3961 sc->sc_stats.ast_tx_altrate++; 3962 sc->sc_stats.ast_tx_rssi = 3963 ds->ds_txstat.ts_rssi; 3964 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3965 ds->ds_txstat.ts_rssi); 3966 pri = M_WME_GETAC(bf->bf_m); 3967 if (pri >= WME_AC_VO) 3968 ic->ic_wme.wme_hipri_traffic++; 3969 ni->ni_inact = ni->ni_inact_reload; 3970 } else { 3971 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3972 sc->sc_stats.ast_tx_xretries++; 3973 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3974 sc->sc_stats.ast_tx_fifoerr++; 3975 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3976 sc->sc_stats.ast_tx_filtered++; 3977 } 3978 sr = ds->ds_txstat.ts_shortretry; 3979 lr = ds->ds_txstat.ts_longretry; 3980 sc->sc_stats.ast_tx_shortretry += sr; 3981 sc->sc_stats.ast_tx_longretry += lr; 3982 /* 3983 * Hand the descriptor to the rate control algorithm. 3984 */ 3985 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3986 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 3987 /* 3988 * If frame was ack'd update the last rx time 3989 * used to workaround phantom bmiss interrupts. 3990 */ 3991 if (ds->ds_txstat.ts_status == 0) 3992 nacked++; 3993 ath_rate_tx_complete(sc, an, ds, ds0); 3994 } 3995 /* 3996 * Reclaim reference to node. 3997 * 3998 * NB: the node may be reclaimed here if, for example 3999 * this is a DEAUTH message that was sent and the 4000 * node was timed out due to inactivity. 4001 */ 4002 ieee80211_free_node(ni); 4003 } 4004 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4005 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4006 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4007 m_freem(bf->bf_m); 4008 bf->bf_m = NULL; 4009 bf->bf_node = NULL; 4010 4011 ATH_TXBUF_LOCK(sc); 4012 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4013 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4014 ATH_TXBUF_UNLOCK(sc); 4015 } 4016 return nacked; 4017 } 4018 4019 static inline int 4020 txqactive(struct ath_hal *ah, int qnum) 4021 { 4022 u_int32_t txqs = 1<<qnum; 4023 ath_hal_gettxintrtxqs(ah, &txqs); 4024 return (txqs & (1<<qnum)); 4025 } 4026 4027 /* 4028 * Deferred processing of transmit interrupt; special-cased 4029 * for a single hardware transmit queue (e.g. 5210 and 5211). 4030 */ 4031 static void 4032 ath_tx_proc_q0(void *arg, int npending) 4033 { 4034 struct ath_softc *sc = arg; 4035 struct ifnet *ifp = &sc->sc_if; 4036 4037 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4038 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4039 } 4040 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4041 ath_tx_processq(sc, sc->sc_cabq); 4042 4043 if (sc->sc_softled) 4044 ath_led_event(sc, ATH_LED_TX); 4045 4046 ath_start(ifp); 4047 } 4048 4049 /* 4050 * Deferred processing of transmit interrupt; special-cased 4051 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4052 */ 4053 static void 4054 ath_tx_proc_q0123(void *arg, int npending) 4055 { 4056 struct ath_softc *sc = arg; 4057 struct ifnet *ifp = &sc->sc_if; 4058 int nacked; 4059 4060 /* 4061 * Process each active queue. 4062 */ 4063 nacked = 0; 4064 if (txqactive(sc->sc_ah, 0)) 4065 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4066 if (txqactive(sc->sc_ah, 1)) 4067 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4068 if (txqactive(sc->sc_ah, 2)) 4069 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4070 if (txqactive(sc->sc_ah, 3)) 4071 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4072 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4073 ath_tx_processq(sc, sc->sc_cabq); 4074 if (nacked) { 4075 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4076 } 4077 4078 if (sc->sc_softled) 4079 ath_led_event(sc, ATH_LED_TX); 4080 4081 ath_start(ifp); 4082 } 4083 4084 /* 4085 * Deferred processing of transmit interrupt. 4086 */ 4087 static void 4088 ath_tx_proc(void *arg, int npending) 4089 { 4090 struct ath_softc *sc = arg; 4091 struct ifnet *ifp = &sc->sc_if; 4092 int i, nacked; 4093 4094 /* 4095 * Process each active queue. 4096 */ 4097 nacked = 0; 4098 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4099 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4100 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4101 if (nacked) { 4102 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4103 } 4104 4105 if (sc->sc_softled) 4106 ath_led_event(sc, ATH_LED_TX); 4107 4108 ath_start(ifp); 4109 } 4110 4111 static void 4112 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4113 { 4114 struct ath_hal *ah = sc->sc_ah; 4115 struct ieee80211_node *ni; 4116 struct ath_buf *bf; 4117 4118 /* 4119 * NB: this assumes output has been stopped and 4120 * we do not need to block ath_tx_tasklet 4121 */ 4122 for (;;) { 4123 ATH_TXQ_LOCK(txq); 4124 bf = STAILQ_FIRST(&txq->axq_q); 4125 if (bf == NULL) { 4126 txq->axq_link = NULL; 4127 ATH_TXQ_UNLOCK(txq); 4128 break; 4129 } 4130 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4131 ATH_TXQ_UNLOCK(txq); 4132 #ifdef AR_DEBUG 4133 if (sc->sc_debug & ATH_DEBUG_RESET) 4134 ath_printtxbuf(bf, 4135 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4136 #endif /* AR_DEBUG */ 4137 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4138 m_freem(bf->bf_m); 4139 bf->bf_m = NULL; 4140 ni = bf->bf_node; 4141 bf->bf_node = NULL; 4142 if (ni != NULL) { 4143 /* 4144 * Reclaim node reference. 4145 */ 4146 ieee80211_free_node(ni); 4147 } 4148 ATH_TXBUF_LOCK(sc); 4149 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4150 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4151 ATH_TXBUF_UNLOCK(sc); 4152 } 4153 } 4154 4155 static void 4156 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4157 { 4158 struct ath_hal *ah = sc->sc_ah; 4159 4160 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4161 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4162 __func__, txq->axq_qnum, 4163 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4164 txq->axq_link); 4165 } 4166 4167 /* 4168 * Drain the transmit queues and reclaim resources. 4169 */ 4170 static void 4171 ath_draintxq(struct ath_softc *sc) 4172 { 4173 struct ath_hal *ah = sc->sc_ah; 4174 int i; 4175 4176 /* XXX return value */ 4177 if (device_is_active(sc->sc_dev)) { 4178 /* don't touch the hardware if marked invalid */ 4179 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4180 DPRINTF(sc, ATH_DEBUG_RESET, 4181 "%s: beacon queue %p\n", __func__, 4182 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4183 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4184 if (ATH_TXQ_SETUP(sc, i)) 4185 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4186 } 4187 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4188 if (ATH_TXQ_SETUP(sc, i)) 4189 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4190 } 4191 4192 /* 4193 * Disable the receive h/w in preparation for a reset. 4194 */ 4195 static void 4196 ath_stoprecv(struct ath_softc *sc) 4197 { 4198 #define PA2DESC(_sc, _pa) \ 4199 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4200 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4201 struct ath_hal *ah = sc->sc_ah; 4202 4203 ath_hal_stoppcurecv(ah); /* disable PCU */ 4204 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4205 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4206 DELAY(3000); /* 3ms is long enough for 1 frame */ 4207 #ifdef AR_DEBUG 4208 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4209 struct ath_buf *bf; 4210 4211 printf("%s: rx queue %p, link %p\n", __func__, 4212 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4213 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4214 struct ath_desc *ds = bf->bf_desc; 4215 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4216 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4217 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4218 ath_printrxbuf(bf, status == HAL_OK); 4219 } 4220 } 4221 #endif 4222 sc->sc_rxlink = NULL; /* just in case */ 4223 #undef PA2DESC 4224 } 4225 4226 /* 4227 * Enable the receive h/w following a reset. 4228 */ 4229 static int 4230 ath_startrecv(struct ath_softc *sc) 4231 { 4232 struct ath_hal *ah = sc->sc_ah; 4233 struct ath_buf *bf; 4234 4235 sc->sc_rxlink = NULL; 4236 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4237 int error = ath_rxbuf_init(sc, bf); 4238 if (error != 0) { 4239 DPRINTF(sc, ATH_DEBUG_RECV, 4240 "%s: ath_rxbuf_init failed %d\n", 4241 __func__, error); 4242 return error; 4243 } 4244 } 4245 4246 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4247 ath_hal_putrxbuf(ah, bf->bf_daddr); 4248 ath_hal_rxena(ah); /* enable recv descriptors */ 4249 ath_mode_init(sc); /* set filters, etc. */ 4250 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4251 return 0; 4252 } 4253 4254 /* 4255 * Update internal state after a channel change. 4256 */ 4257 static void 4258 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4259 { 4260 struct ieee80211com *ic = &sc->sc_ic; 4261 enum ieee80211_phymode mode; 4262 u_int16_t flags; 4263 4264 /* 4265 * Change channels and update the h/w rate map 4266 * if we're switching; e.g. 11a to 11b/g. 4267 */ 4268 mode = ieee80211_chan2mode(ic, chan); 4269 if (mode != sc->sc_curmode) 4270 ath_setcurmode(sc, mode); 4271 /* 4272 * Update BPF state. NB: ethereal et. al. don't handle 4273 * merged flags well so pick a unique mode for their use. 4274 */ 4275 if (IEEE80211_IS_CHAN_A(chan)) 4276 flags = IEEE80211_CHAN_A; 4277 /* XXX 11g schizophrenia */ 4278 else if (IEEE80211_IS_CHAN_G(chan) || 4279 IEEE80211_IS_CHAN_PUREG(chan)) 4280 flags = IEEE80211_CHAN_G; 4281 else 4282 flags = IEEE80211_CHAN_B; 4283 if (IEEE80211_IS_CHAN_T(chan)) 4284 flags |= IEEE80211_CHAN_TURBO; 4285 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4286 htole16(chan->ic_freq); 4287 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4288 htole16(flags); 4289 } 4290 4291 /* 4292 * Poll for a channel clear indication; this is required 4293 * for channels requiring DFS and not previously visited 4294 * and/or with a recent radar detection. 4295 */ 4296 static void 4297 ath_dfswait(void *arg) 4298 { 4299 struct ath_softc *sc = arg; 4300 struct ath_hal *ah = sc->sc_ah; 4301 HAL_CHANNEL hchan; 4302 4303 ath_hal_radar_wait(ah, &hchan); 4304 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4305 if_printf(&sc->sc_if, 4306 "channel %u/0x%x/0x%x has interference\n", 4307 hchan.channel, hchan.channelFlags, hchan.privFlags); 4308 return; 4309 } 4310 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4311 /* XXX should not happen */ 4312 return; 4313 } 4314 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4315 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4316 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4317 if_printf(&sc->sc_if, 4318 "channel %u/0x%x/0x%x marked clear\n", 4319 hchan.channel, hchan.channelFlags, hchan.privFlags); 4320 } else 4321 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4322 } 4323 4324 /* 4325 * Set/change channels. If the channel is really being changed, 4326 * it's done by reseting the chip. To accomplish this we must 4327 * first cleanup any pending DMA, then restart stuff after a la 4328 * ath_init. 4329 */ 4330 static int 4331 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4332 { 4333 struct ath_hal *ah = sc->sc_ah; 4334 struct ieee80211com *ic = &sc->sc_ic; 4335 HAL_CHANNEL hchan; 4336 4337 /* 4338 * Convert to a HAL channel description with 4339 * the flags constrained to reflect the current 4340 * operating mode. 4341 */ 4342 hchan.channel = chan->ic_freq; 4343 hchan.channelFlags = ath_chan2flags(ic, chan); 4344 4345 DPRINTF(sc, ATH_DEBUG_RESET, 4346 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4347 __func__, 4348 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4349 sc->sc_curchan.channelFlags), 4350 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4351 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4352 hchan.channel, hchan.channelFlags); 4353 if (hchan.channel != sc->sc_curchan.channel || 4354 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4355 HAL_STATUS status; 4356 4357 /* 4358 * To switch channels clear any pending DMA operations; 4359 * wait long enough for the RX fifo to drain, reset the 4360 * hardware at the new frequency, and then re-enable 4361 * the relevant bits of the h/w. 4362 */ 4363 ath_hal_intrset(ah, 0); /* disable interrupts */ 4364 ath_draintxq(sc); /* clear pending tx frames */ 4365 ath_stoprecv(sc); /* turn off frame recv */ 4366 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4367 if_printf(ic->ic_ifp, "%s: unable to reset " 4368 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4369 __func__, ieee80211_chan2ieee(ic, chan), 4370 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4371 return EIO; 4372 } 4373 sc->sc_curchan = hchan; 4374 ath_update_txpow(sc); /* update tx power state */ 4375 ath_restore_diversity(sc); 4376 sc->sc_calinterval = 1; 4377 sc->sc_caltries = 0; 4378 4379 /* 4380 * Re-enable rx framework. 4381 */ 4382 if (ath_startrecv(sc) != 0) { 4383 if_printf(&sc->sc_if, 4384 "%s: unable to restart recv logic\n", __func__); 4385 return EIO; 4386 } 4387 4388 /* 4389 * Change channels and update the h/w rate map 4390 * if we're switching; e.g. 11a to 11b/g. 4391 */ 4392 ic->ic_ibss_chan = chan; 4393 ath_chan_change(sc, chan); 4394 4395 /* 4396 * Handle DFS required waiting period to determine 4397 * if channel is clear of radar traffic. 4398 */ 4399 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4400 #define DFS_AND_NOT_CLEAR(_c) \ 4401 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4402 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4403 if_printf(&sc->sc_if, 4404 "wait for DFS clear channel signal\n"); 4405 /* XXX stop sndq */ 4406 sc->sc_if.if_flags |= IFF_OACTIVE; 4407 callout_reset(&sc->sc_dfs_ch, 4408 2 * hz, ath_dfswait, sc); 4409 } else 4410 callout_stop(&sc->sc_dfs_ch); 4411 #undef DFS_NOT_CLEAR 4412 } 4413 4414 /* 4415 * Re-enable interrupts. 4416 */ 4417 ath_hal_intrset(ah, sc->sc_imask); 4418 } 4419 return 0; 4420 } 4421 4422 static void 4423 ath_next_scan(void *arg) 4424 { 4425 struct ath_softc *sc = arg; 4426 struct ieee80211com *ic = &sc->sc_ic; 4427 int s; 4428 4429 /* don't call ath_start w/o network interrupts blocked */ 4430 s = splnet(); 4431 4432 if (ic->ic_state == IEEE80211_S_SCAN) 4433 ieee80211_next_scan(ic); 4434 splx(s); 4435 } 4436 4437 /* 4438 * Periodically recalibrate the PHY to account 4439 * for temperature/environment changes. 4440 */ 4441 static void 4442 ath_calibrate(void *arg) 4443 { 4444 struct ath_softc *sc = arg; 4445 struct ath_hal *ah = sc->sc_ah; 4446 HAL_BOOL iqCalDone; 4447 4448 sc->sc_stats.ast_per_cal++; 4449 4450 ATH_LOCK(sc); 4451 4452 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4453 /* 4454 * Rfgain is out of bounds, reset the chip 4455 * to load new gain values. 4456 */ 4457 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4458 "%s: rfgain change\n", __func__); 4459 sc->sc_stats.ast_per_rfgain++; 4460 ath_reset(&sc->sc_if); 4461 } 4462 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4463 DPRINTF(sc, ATH_DEBUG_ANY, 4464 "%s: calibration of channel %u failed\n", 4465 __func__, sc->sc_curchan.channel); 4466 sc->sc_stats.ast_per_calfail++; 4467 } 4468 /* 4469 * Calibrate noise floor data again in case of change. 4470 */ 4471 ath_hal_process_noisefloor(ah); 4472 /* 4473 * Poll more frequently when the IQ calibration is in 4474 * progress to speedup loading the final settings. 4475 * We temper this aggressive polling with an exponential 4476 * back off after 4 tries up to ath_calinterval. 4477 */ 4478 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4479 sc->sc_caltries = 0; 4480 sc->sc_calinterval = ath_calinterval; 4481 } else if (sc->sc_caltries > 4) { 4482 sc->sc_caltries = 0; 4483 sc->sc_calinterval <<= 1; 4484 if (sc->sc_calinterval > ath_calinterval) 4485 sc->sc_calinterval = ath_calinterval; 4486 } 4487 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4488 ("bad calibration interval %u", sc->sc_calinterval)); 4489 4490 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4491 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4492 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4493 sc->sc_caltries++; 4494 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4495 ath_calibrate, sc); 4496 ATH_UNLOCK(sc); 4497 } 4498 4499 static int 4500 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4501 { 4502 struct ifnet *ifp = ic->ic_ifp; 4503 struct ath_softc *sc = ifp->if_softc; 4504 struct ath_hal *ah = sc->sc_ah; 4505 struct ieee80211_node *ni; 4506 int i, error; 4507 const u_int8_t *bssid; 4508 u_int32_t rfilt; 4509 static const HAL_LED_STATE leds[] = { 4510 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4511 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4512 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4513 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4514 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4515 }; 4516 4517 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4518 ieee80211_state_name[ic->ic_state], 4519 ieee80211_state_name[nstate]); 4520 4521 callout_stop(&sc->sc_scan_ch); 4522 callout_stop(&sc->sc_cal_ch); 4523 callout_stop(&sc->sc_dfs_ch); 4524 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4525 4526 if (nstate == IEEE80211_S_INIT) { 4527 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4528 /* 4529 * NB: disable interrupts so we don't rx frames. 4530 */ 4531 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4532 /* 4533 * Notify the rate control algorithm. 4534 */ 4535 ath_rate_newstate(sc, nstate); 4536 goto done; 4537 } 4538 ni = ic->ic_bss; 4539 error = ath_chan_set(sc, ic->ic_curchan); 4540 if (error != 0) 4541 goto bad; 4542 rfilt = ath_calcrxfilter(sc, nstate); 4543 if (nstate == IEEE80211_S_SCAN) 4544 bssid = ifp->if_broadcastaddr; 4545 else 4546 bssid = ni->ni_bssid; 4547 ath_hal_setrxfilter(ah, rfilt); 4548 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4549 __func__, rfilt, ether_sprintf(bssid)); 4550 4551 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4552 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4553 else 4554 ath_hal_setassocid(ah, bssid, 0); 4555 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4556 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4557 if (ath_hal_keyisvalid(ah, i)) 4558 ath_hal_keysetmac(ah, i, bssid); 4559 } 4560 4561 /* 4562 * Notify the rate control algorithm so rates 4563 * are setup should ath_beacon_alloc be called. 4564 */ 4565 ath_rate_newstate(sc, nstate); 4566 4567 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4568 /* nothing to do */; 4569 } else if (nstate == IEEE80211_S_RUN) { 4570 DPRINTF(sc, ATH_DEBUG_STATE, 4571 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4572 "capinfo=0x%04x chan=%d\n" 4573 , __func__ 4574 , ic->ic_flags 4575 , ni->ni_intval 4576 , ether_sprintf(ni->ni_bssid) 4577 , ni->ni_capinfo 4578 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4579 4580 switch (ic->ic_opmode) { 4581 case IEEE80211_M_HOSTAP: 4582 case IEEE80211_M_IBSS: 4583 /* 4584 * Allocate and setup the beacon frame. 4585 * 4586 * Stop any previous beacon DMA. This may be 4587 * necessary, for example, when an ibss merge 4588 * causes reconfiguration; there will be a state 4589 * transition from RUN->RUN that means we may 4590 * be called with beacon transmission active. 4591 */ 4592 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4593 ath_beacon_free(sc); 4594 error = ath_beacon_alloc(sc, ni); 4595 if (error != 0) 4596 goto bad; 4597 /* 4598 * If joining an adhoc network defer beacon timer 4599 * configuration to the next beacon frame so we 4600 * have a current TSF to use. Otherwise we're 4601 * starting an ibss/bss so there's no need to delay. 4602 */ 4603 if (ic->ic_opmode == IEEE80211_M_IBSS && 4604 ic->ic_bss->ni_tstamp.tsf != 0) 4605 sc->sc_syncbeacon = 1; 4606 else 4607 ath_beacon_config(sc); 4608 break; 4609 case IEEE80211_M_STA: 4610 /* 4611 * Allocate a key cache slot to the station. 4612 */ 4613 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4614 sc->sc_hasclrkey && 4615 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4616 ath_setup_stationkey(ni); 4617 /* 4618 * Defer beacon timer configuration to the next 4619 * beacon frame so we have a current TSF to use 4620 * (any TSF collected when scanning is likely old). 4621 */ 4622 sc->sc_syncbeacon = 1; 4623 break; 4624 default: 4625 break; 4626 } 4627 /* 4628 * Let the hal process statistics collected during a 4629 * scan so it can provide calibrated noise floor data. 4630 */ 4631 ath_hal_process_noisefloor(ah); 4632 /* 4633 * Reset rssi stats; maybe not the best place... 4634 */ 4635 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4636 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4637 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4638 } else { 4639 ath_hal_intrset(ah, 4640 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4641 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4642 } 4643 done: 4644 /* 4645 * Invoke the parent method to complete the work. 4646 */ 4647 error = sc->sc_newstate(ic, nstate, arg); 4648 /* 4649 * Finally, start any timers. 4650 */ 4651 if (nstate == IEEE80211_S_RUN) { 4652 /* start periodic recalibration timer */ 4653 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4654 ath_calibrate, sc); 4655 } else if (nstate == IEEE80211_S_SCAN) { 4656 /* start ap/neighbor scan timer */ 4657 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4658 ath_next_scan, sc); 4659 } 4660 bad: 4661 return error; 4662 } 4663 4664 /* 4665 * Allocate a key cache slot to the station so we can 4666 * setup a mapping from key index to node. The key cache 4667 * slot is needed for managing antenna state and for 4668 * compression when stations do not use crypto. We do 4669 * it uniliaterally here; if crypto is employed this slot 4670 * will be reassigned. 4671 */ 4672 static void 4673 ath_setup_stationkey(struct ieee80211_node *ni) 4674 { 4675 struct ieee80211com *ic = ni->ni_ic; 4676 struct ath_softc *sc = ic->ic_ifp->if_softc; 4677 ieee80211_keyix keyix, rxkeyix; 4678 4679 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4680 /* 4681 * Key cache is full; we'll fall back to doing 4682 * the more expensive lookup in software. Note 4683 * this also means no h/w compression. 4684 */ 4685 /* XXX msg+statistic */ 4686 } else { 4687 /* XXX locking? */ 4688 ni->ni_ucastkey.wk_keyix = keyix; 4689 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4690 /* NB: this will create a pass-thru key entry */ 4691 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4692 } 4693 } 4694 4695 /* 4696 * Setup driver-specific state for a newly associated node. 4697 * Note that we're called also on a re-associate, the isnew 4698 * param tells us if this is the first time or not. 4699 */ 4700 static void 4701 ath_newassoc(struct ieee80211_node *ni, int isnew) 4702 { 4703 struct ieee80211com *ic = ni->ni_ic; 4704 struct ath_softc *sc = ic->ic_ifp->if_softc; 4705 4706 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4707 if (isnew && 4708 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4709 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4710 ("new assoc with a unicast key already setup (keyix %u)", 4711 ni->ni_ucastkey.wk_keyix)); 4712 ath_setup_stationkey(ni); 4713 } 4714 } 4715 4716 static int 4717 ath_getchannels(struct ath_softc *sc, u_int cc, 4718 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4719 { 4720 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4721 struct ieee80211com *ic = &sc->sc_ic; 4722 struct ifnet *ifp = &sc->sc_if; 4723 struct ath_hal *ah = sc->sc_ah; 4724 HAL_CHANNEL *chans; 4725 int i, ix, nchan; 4726 4727 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4728 M_TEMP, M_NOWAIT); 4729 if (chans == NULL) { 4730 if_printf(ifp, "unable to allocate channel table\n"); 4731 return ENOMEM; 4732 } 4733 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4734 NULL, 0, NULL, 4735 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4736 u_int32_t rd; 4737 4738 (void)ath_hal_getregdomain(ah, &rd); 4739 if_printf(ifp, "unable to collect channel list from hal; " 4740 "regdomain likely %u country code %u\n", rd, cc); 4741 free(chans, M_TEMP); 4742 return EINVAL; 4743 } 4744 4745 /* 4746 * Convert HAL channels to ieee80211 ones and insert 4747 * them in the table according to their channel number. 4748 */ 4749 for (i = 0; i < nchan; i++) { 4750 HAL_CHANNEL *c = &chans[i]; 4751 u_int16_t flags; 4752 4753 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4754 if (ix > IEEE80211_CHAN_MAX) { 4755 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4756 ix, c->channel, c->channelFlags); 4757 continue; 4758 } 4759 if (ix < 0) { 4760 /* XXX can't handle stuff <2400 right now */ 4761 if (bootverbose) 4762 if_printf(ifp, "hal channel %d (%u/%x) " 4763 "cannot be handled; ignored\n", 4764 ix, c->channel, c->channelFlags); 4765 continue; 4766 } 4767 /* 4768 * Calculate net80211 flags; most are compatible 4769 * but some need massaging. Note the static turbo 4770 * conversion can be removed once net80211 is updated 4771 * to understand static vs. dynamic turbo. 4772 */ 4773 flags = c->channelFlags & COMPAT; 4774 if (c->channelFlags & CHANNEL_STURBO) 4775 flags |= IEEE80211_CHAN_TURBO; 4776 if (ic->ic_channels[ix].ic_freq == 0) { 4777 ic->ic_channels[ix].ic_freq = c->channel; 4778 ic->ic_channels[ix].ic_flags = flags; 4779 } else { 4780 /* channels overlap; e.g. 11g and 11b */ 4781 ic->ic_channels[ix].ic_flags |= flags; 4782 } 4783 } 4784 free(chans, M_TEMP); 4785 return 0; 4786 #undef COMPAT 4787 } 4788 4789 static void 4790 ath_led_done(void *arg) 4791 { 4792 struct ath_softc *sc = arg; 4793 4794 sc->sc_blinking = 0; 4795 } 4796 4797 /* 4798 * Turn the LED off: flip the pin and then set a timer so no 4799 * update will happen for the specified duration. 4800 */ 4801 static void 4802 ath_led_off(void *arg) 4803 { 4804 struct ath_softc *sc = arg; 4805 4806 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4807 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4808 } 4809 4810 /* 4811 * Blink the LED according to the specified on/off times. 4812 */ 4813 static void 4814 ath_led_blink(struct ath_softc *sc, int on, int off) 4815 { 4816 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4817 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4818 sc->sc_blinking = 1; 4819 sc->sc_ledoff = off; 4820 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4821 } 4822 4823 static void 4824 ath_led_event(struct ath_softc *sc, int event) 4825 { 4826 4827 sc->sc_ledevent = ticks; /* time of last event */ 4828 if (sc->sc_blinking) /* don't interrupt active blink */ 4829 return; 4830 switch (event) { 4831 case ATH_LED_POLL: 4832 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4833 sc->sc_hwmap[0].ledoff); 4834 break; 4835 case ATH_LED_TX: 4836 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4837 sc->sc_hwmap[sc->sc_txrate].ledoff); 4838 break; 4839 case ATH_LED_RX: 4840 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4841 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4842 break; 4843 } 4844 } 4845 4846 static void 4847 ath_update_txpow(struct ath_softc *sc) 4848 { 4849 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4850 struct ieee80211com *ic = &sc->sc_ic; 4851 struct ath_hal *ah = sc->sc_ah; 4852 u_int32_t txpow; 4853 4854 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4855 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4856 /* read back in case value is clamped */ 4857 (void)ath_hal_gettxpowlimit(ah, &txpow); 4858 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4859 } 4860 /* 4861 * Fetch max tx power level for status requests. 4862 */ 4863 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4864 ic->ic_bss->ni_txpower = txpow; 4865 } 4866 4867 static void 4868 rate_setup(struct ath_softc *sc, 4869 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4870 { 4871 int i, maxrates; 4872 4873 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4874 DPRINTF(sc, ATH_DEBUG_ANY, 4875 "%s: rate table too small (%u > %u)\n", 4876 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4877 maxrates = IEEE80211_RATE_MAXSIZE; 4878 } else 4879 maxrates = rt->rateCount; 4880 for (i = 0; i < maxrates; i++) 4881 rs->rs_rates[i] = rt->info[i].dot11Rate; 4882 rs->rs_nrates = maxrates; 4883 } 4884 4885 static int 4886 ath_rate_setup(struct ath_softc *sc, u_int mode) 4887 { 4888 struct ath_hal *ah = sc->sc_ah; 4889 struct ieee80211com *ic = &sc->sc_ic; 4890 const HAL_RATE_TABLE *rt; 4891 4892 switch (mode) { 4893 case IEEE80211_MODE_11A: 4894 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4895 break; 4896 case IEEE80211_MODE_11B: 4897 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4898 break; 4899 case IEEE80211_MODE_11G: 4900 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4901 break; 4902 case IEEE80211_MODE_TURBO_A: 4903 /* XXX until static/dynamic turbo is fixed */ 4904 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4905 break; 4906 case IEEE80211_MODE_TURBO_G: 4907 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4908 break; 4909 default: 4910 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4911 __func__, mode); 4912 return 0; 4913 } 4914 sc->sc_rates[mode] = rt; 4915 if (rt != NULL) { 4916 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 4917 return 1; 4918 } else 4919 return 0; 4920 } 4921 4922 static void 4923 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4924 { 4925 #define N(a) (sizeof(a)/sizeof(a[0])) 4926 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4927 static const struct { 4928 u_int rate; /* tx/rx 802.11 rate */ 4929 u_int16_t timeOn; /* LED on time (ms) */ 4930 u_int16_t timeOff; /* LED off time (ms) */ 4931 } blinkrates[] = { 4932 { 108, 40, 10 }, 4933 { 96, 44, 11 }, 4934 { 72, 50, 13 }, 4935 { 48, 57, 14 }, 4936 { 36, 67, 16 }, 4937 { 24, 80, 20 }, 4938 { 22, 100, 25 }, 4939 { 18, 133, 34 }, 4940 { 12, 160, 40 }, 4941 { 10, 200, 50 }, 4942 { 6, 240, 58 }, 4943 { 4, 267, 66 }, 4944 { 2, 400, 100 }, 4945 { 0, 500, 130 }, 4946 }; 4947 const HAL_RATE_TABLE *rt; 4948 int i, j; 4949 4950 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4951 rt = sc->sc_rates[mode]; 4952 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4953 for (i = 0; i < rt->rateCount; i++) 4954 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4955 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4956 for (i = 0; i < 32; i++) { 4957 u_int8_t ix = rt->rateCodeToIndex[i]; 4958 if (ix == 0xff) { 4959 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4960 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4961 continue; 4962 } 4963 sc->sc_hwmap[i].ieeerate = 4964 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4965 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4966 if (rt->info[ix].shortPreamble || 4967 rt->info[ix].phy == IEEE80211_T_OFDM) 4968 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4969 /* NB: receive frames include FCS */ 4970 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4971 IEEE80211_RADIOTAP_F_FCS; 4972 /* setup blink rate table to avoid per-packet lookup */ 4973 for (j = 0; j < N(blinkrates)-1; j++) 4974 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4975 break; 4976 /* NB: this uses the last entry if the rate isn't found */ 4977 /* XXX beware of overlow */ 4978 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4979 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4980 } 4981 sc->sc_currates = rt; 4982 sc->sc_curmode = mode; 4983 /* 4984 * All protection frames are transmited at 2Mb/s for 4985 * 11g, otherwise at 1Mb/s. 4986 */ 4987 if (mode == IEEE80211_MODE_11G) 4988 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 4989 else 4990 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 4991 /* rate index used to send management frames */ 4992 sc->sc_minrateix = 0; 4993 /* 4994 * Setup multicast rate state. 4995 */ 4996 /* XXX layering violation */ 4997 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 4998 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 4999 /* NB: caller is responsible for reseting rate control state */ 5000 #undef N 5001 } 5002 5003 #ifdef AR_DEBUG 5004 static void 5005 ath_printrxbuf(struct ath_buf *bf, int done) 5006 { 5007 struct ath_desc *ds; 5008 int i; 5009 5010 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5011 printf("R%d (%p %" PRIx64 5012 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5013 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5014 ds->ds_link, ds->ds_data, 5015 ds->ds_ctl0, ds->ds_ctl1, 5016 ds->ds_hw[0], ds->ds_hw[1], 5017 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5018 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5019 } 5020 } 5021 5022 static void 5023 ath_printtxbuf(struct ath_buf *bf, int done) 5024 { 5025 struct ath_desc *ds; 5026 int i; 5027 5028 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5029 printf("T%d (%p %" PRIx64 5030 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5031 i, ds, 5032 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5033 ds->ds_link, ds->ds_data, 5034 ds->ds_ctl0, ds->ds_ctl1, 5035 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5036 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5037 } 5038 } 5039 #endif /* AR_DEBUG */ 5040 5041 static void 5042 ath_watchdog(struct ifnet *ifp) 5043 { 5044 struct ath_softc *sc = ifp->if_softc; 5045 struct ieee80211com *ic = &sc->sc_ic; 5046 struct ath_txq *axq; 5047 int i; 5048 5049 ifp->if_timer = 0; 5050 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5051 !device_is_active(sc->sc_dev)) 5052 return; 5053 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5054 if (!ATH_TXQ_SETUP(sc, i)) 5055 continue; 5056 axq = &sc->sc_txq[i]; 5057 ATH_TXQ_LOCK(axq); 5058 if (axq->axq_timer == 0) 5059 ; 5060 else if (--axq->axq_timer == 0) { 5061 ATH_TXQ_UNLOCK(axq); 5062 if_printf(ifp, "device timeout (txq %d, " 5063 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5064 if (sc->sc_txintrperiod > 1) 5065 sc->sc_txintrperiod--; 5066 ath_reset(ifp); 5067 ifp->if_oerrors++; 5068 sc->sc_stats.ast_watchdog++; 5069 break; 5070 } else 5071 ifp->if_timer = 1; 5072 ATH_TXQ_UNLOCK(axq); 5073 } 5074 ieee80211_watchdog(ic); 5075 } 5076 5077 /* 5078 * Diagnostic interface to the HAL. This is used by various 5079 * tools to do things like retrieve register contents for 5080 * debugging. The mechanism is intentionally opaque so that 5081 * it can change frequently w/o concern for compatiblity. 5082 */ 5083 static int 5084 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5085 { 5086 struct ath_hal *ah = sc->sc_ah; 5087 u_int id = ad->ad_id & ATH_DIAG_ID; 5088 void *indata = NULL; 5089 void *outdata = NULL; 5090 u_int32_t insize = ad->ad_in_size; 5091 u_int32_t outsize = ad->ad_out_size; 5092 int error = 0; 5093 5094 if (ad->ad_id & ATH_DIAG_IN) { 5095 /* 5096 * Copy in data. 5097 */ 5098 indata = malloc(insize, M_TEMP, M_NOWAIT); 5099 if (indata == NULL) { 5100 error = ENOMEM; 5101 goto bad; 5102 } 5103 error = copyin(ad->ad_in_data, indata, insize); 5104 if (error) 5105 goto bad; 5106 } 5107 if (ad->ad_id & ATH_DIAG_DYN) { 5108 /* 5109 * Allocate a buffer for the results (otherwise the HAL 5110 * returns a pointer to a buffer where we can read the 5111 * results). Note that we depend on the HAL leaving this 5112 * pointer for us to use below in reclaiming the buffer; 5113 * may want to be more defensive. 5114 */ 5115 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5116 if (outdata == NULL) { 5117 error = ENOMEM; 5118 goto bad; 5119 } 5120 } 5121 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5122 if (outsize < ad->ad_out_size) 5123 ad->ad_out_size = outsize; 5124 if (outdata != NULL) 5125 error = copyout(outdata, ad->ad_out_data, 5126 ad->ad_out_size); 5127 } else { 5128 error = EINVAL; 5129 } 5130 bad: 5131 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5132 free(indata, M_TEMP); 5133 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5134 free(outdata, M_TEMP); 5135 return error; 5136 } 5137 5138 static int 5139 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5140 { 5141 #define IS_RUNNING(ifp) \ 5142 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5143 struct ath_softc *sc = ifp->if_softc; 5144 struct ieee80211com *ic = &sc->sc_ic; 5145 struct ifreq *ifr = (struct ifreq *)data; 5146 int error = 0; 5147 5148 ATH_LOCK(sc); 5149 switch (cmd) { 5150 case SIOCSIFFLAGS: 5151 if (IS_RUNNING(ifp)) { 5152 /* 5153 * To avoid rescanning another access point, 5154 * do not call ath_init() here. Instead, 5155 * only reflect promisc mode settings. 5156 */ 5157 ath_mode_init(sc); 5158 } else if (ifp->if_flags & IFF_UP) { 5159 /* 5160 * Beware of being called during attach/detach 5161 * to reset promiscuous mode. In that case we 5162 * will still be marked UP but not RUNNING. 5163 * However trying to re-init the interface 5164 * is the wrong thing to do as we've already 5165 * torn down much of our state. There's 5166 * probably a better way to deal with this. 5167 */ 5168 error = ath_init(sc); 5169 } else if (device_is_active(sc->sc_dev)) 5170 ath_stop_locked(ifp, 1); 5171 break; 5172 case SIOCADDMULTI: 5173 case SIOCDELMULTI: 5174 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5175 if (ifp->if_flags & IFF_RUNNING) 5176 ath_mode_init(sc); 5177 error = 0; 5178 } 5179 break; 5180 case SIOCGATHSTATS: 5181 /* NB: embed these numbers to get a consistent view */ 5182 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5183 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5184 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5185 ATH_UNLOCK(sc); 5186 /* 5187 * NB: Drop the softc lock in case of a page fault; 5188 * we'll accept any potential inconsisentcy in the 5189 * statistics. The alternative is to copy the data 5190 * to a local structure. 5191 */ 5192 return copyout(&sc->sc_stats, 5193 ifr->ifr_data, sizeof (sc->sc_stats)); 5194 case SIOCGATHDIAG: 5195 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5196 break; 5197 default: 5198 error = ieee80211_ioctl(ic, cmd, data); 5199 if (error != ENETRESET) 5200 ; 5201 else if (IS_RUNNING(ifp) && 5202 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5203 error = ath_init(sc); 5204 else 5205 error = 0; 5206 break; 5207 } 5208 ATH_UNLOCK(sc); 5209 return error; 5210 #undef IS_RUNNING 5211 } 5212 5213 #if NBPFILTER > 0 5214 static void 5215 ath_bpfattach(struct ath_softc *sc) 5216 { 5217 struct ifnet *ifp = &sc->sc_if; 5218 5219 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5220 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5221 &sc->sc_drvbpf); 5222 /* 5223 * Initialize constant fields. 5224 * XXX make header lengths a multiple of 32-bits so subsequent 5225 * headers are properly aligned; this is a kludge to keep 5226 * certain applications happy. 5227 * 5228 * NB: the channel is setup each time we transition to the 5229 * RUN state to avoid filling it in for each frame. 5230 */ 5231 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5232 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5233 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5234 5235 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5236 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5237 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5238 } 5239 #endif 5240 5241 /* 5242 * Announce various information on device/driver attach. 5243 */ 5244 static void 5245 ath_announce(struct ath_softc *sc) 5246 { 5247 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5248 struct ifnet *ifp = &sc->sc_if; 5249 struct ath_hal *ah = sc->sc_ah; 5250 u_int modes, cc; 5251 5252 if_printf(ifp, "mac %d.%d phy %d.%d", 5253 ah->ah_macVersion, ah->ah_macRev, 5254 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5255 /* 5256 * Print radio revision(s). We check the wireless modes 5257 * to avoid falsely printing revs for inoperable parts. 5258 * Dual-band radio revs are returned in the 5 GHz rev number. 5259 */ 5260 ath_hal_getcountrycode(ah, &cc); 5261 modes = ath_hal_getwirelessmodes(ah, cc); 5262 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5263 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5264 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5265 ah->ah_analog5GhzRev >> 4, 5266 ah->ah_analog5GhzRev & 0xf, 5267 ah->ah_analog2GhzRev >> 4, 5268 ah->ah_analog2GhzRev & 0xf); 5269 else 5270 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5271 ah->ah_analog5GhzRev & 0xf); 5272 } else 5273 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5274 ah->ah_analog5GhzRev & 0xf); 5275 printf("\n"); 5276 if (bootverbose) { 5277 int i; 5278 for (i = 0; i <= WME_AC_VO; i++) { 5279 struct ath_txq *txq = sc->sc_ac2q[i]; 5280 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5281 txq->axq_qnum, ieee80211_wme_acnames[i]); 5282 } 5283 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5284 sc->sc_cabq->axq_qnum); 5285 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5286 } 5287 if (ath_rxbuf != ATH_RXBUF) 5288 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5289 if (ath_txbuf != ATH_TXBUF) 5290 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5291 #undef HAL_MODE_DUALBAND 5292 } 5293