1 /* $NetBSD: ath.c,v 1.96 2007/12/14 02:46:49 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.96 2007/12/14 02:46:49 dyoung Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <sys/bus.h> 74 #include <sys/endian.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/if_ether.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_netbsd.h> 85 #include <net80211/ieee80211_var.h> 86 87 #if NBPFILTER > 0 88 #include <net/bpf.h> 89 #endif 90 91 #ifdef INET 92 #include <netinet/in.h> 93 #endif 94 95 #include <sys/device.h> 96 #include <dev/ic/ath_netbsd.h> 97 98 #define AR_DEBUG 99 #include <dev/ic/athvar.h> 100 #include <contrib/dev/ath/ah_desc.h> 101 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 102 #include "athhal_options.h" 103 104 #ifdef ATH_TX99_DIAG 105 #include <dev/ath/ath_tx99/ath_tx99.h> 106 #endif 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 enum { 118 ATH_LED_TX, 119 ATH_LED_RX, 120 ATH_LED_POLL, 121 }; 122 123 #ifdef AH_NEED_DESC_SWAP 124 #define HTOAH32(x) htole32(x) 125 #else 126 #define HTOAH32(x) (x) 127 #endif 128 129 static int ath_ifinit(struct ifnet *); 130 static int ath_init(struct ath_softc *); 131 static void ath_stop_locked(struct ifnet *, int); 132 static void ath_stop(struct ifnet *, int); 133 static void ath_start(struct ifnet *); 134 static int ath_media_change(struct ifnet *); 135 static void ath_watchdog(struct ifnet *); 136 static int ath_ioctl(struct ifnet *, u_long, void *); 137 static void ath_fatal_proc(void *, int); 138 static void ath_rxorn_proc(void *, int); 139 static void ath_bmiss_proc(void *, int); 140 static void ath_radar_proc(void *, int); 141 static int ath_key_alloc(struct ieee80211com *, 142 const struct ieee80211_key *, 143 ieee80211_keyix *, ieee80211_keyix *); 144 static int ath_key_delete(struct ieee80211com *, 145 const struct ieee80211_key *); 146 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 147 const u_int8_t mac[IEEE80211_ADDR_LEN]); 148 static void ath_key_update_begin(struct ieee80211com *); 149 static void ath_key_update_end(struct ieee80211com *); 150 static void ath_mode_init(struct ath_softc *); 151 static void ath_setslottime(struct ath_softc *); 152 static void ath_updateslot(struct ifnet *); 153 static int ath_beaconq_setup(struct ath_hal *); 154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 155 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 156 static void ath_beacon_proc(void *, int); 157 static void ath_bstuck_proc(void *, int); 158 static void ath_beacon_free(struct ath_softc *); 159 static void ath_beacon_config(struct ath_softc *); 160 static void ath_descdma_cleanup(struct ath_softc *sc, 161 struct ath_descdma *, ath_bufhead *); 162 static int ath_desc_alloc(struct ath_softc *); 163 static void ath_desc_free(struct ath_softc *); 164 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 165 static void ath_node_free(struct ieee80211_node *); 166 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 167 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 168 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 169 struct ieee80211_node *ni, 170 int subtype, int rssi, u_int32_t rstamp); 171 static void ath_setdefantenna(struct ath_softc *, u_int); 172 static void ath_rx_proc(void *, int); 173 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 174 static int ath_tx_setup(struct ath_softc *, int, int); 175 static int ath_wme_update(struct ieee80211com *); 176 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 177 static void ath_tx_cleanup(struct ath_softc *); 178 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 179 struct ath_buf *, struct mbuf *); 180 static void ath_tx_proc_q0(void *, int); 181 static void ath_tx_proc_q0123(void *, int); 182 static void ath_tx_proc(void *, int); 183 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 184 static void ath_draintxq(struct ath_softc *); 185 static void ath_stoprecv(struct ath_softc *); 186 static int ath_startrecv(struct ath_softc *); 187 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 188 static void ath_next_scan(void *); 189 static void ath_calibrate(void *); 190 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 191 static void ath_setup_stationkey(struct ieee80211_node *); 192 static void ath_newassoc(struct ieee80211_node *, int); 193 static int ath_getchannels(struct ath_softc *, u_int cc, 194 HAL_BOOL outdoor, HAL_BOOL xchanmode); 195 static void ath_led_event(struct ath_softc *, int); 196 static void ath_update_txpow(struct ath_softc *); 197 static void ath_freetx(struct mbuf *); 198 static void ath_restore_diversity(struct ath_softc *); 199 200 static int ath_rate_setup(struct ath_softc *, u_int mode); 201 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 202 203 #ifdef __NetBSD__ 204 int ath_enable(struct ath_softc *); 205 void ath_disable(struct ath_softc *); 206 #endif 207 208 #if NBPFILTER > 0 209 static void ath_bpfattach(struct ath_softc *); 210 #endif 211 static void ath_announce(struct ath_softc *); 212 213 int ath_dwelltime = 200; /* 5 channels/second */ 214 int ath_calinterval = 30; /* calibrate every 30 secs */ 215 int ath_outdoor = AH_TRUE; /* outdoor operation */ 216 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 217 int ath_countrycode = CTRY_DEFAULT; /* country code */ 218 int ath_regdomain = 0; /* regulatory domain */ 219 int ath_debug = 0; 220 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 221 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 222 223 #ifdef AR_DEBUG 224 enum { 225 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 226 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 227 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 228 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 229 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 230 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 231 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 232 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 233 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 234 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 235 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 236 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 237 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 238 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 239 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 240 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 241 ATH_DEBUG_NODE = 0x00080000, /* node management */ 242 ATH_DEBUG_LED = 0x00100000, /* led management */ 243 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 244 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 245 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 246 ATH_DEBUG_ANY = 0xffffffff 247 }; 248 #define IFF_DUMPPKTS(sc, m) \ 249 ((sc->sc_debug & (m)) || \ 250 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 251 #define DPRINTF(sc, m, fmt, ...) do { \ 252 if (sc->sc_debug & (m)) \ 253 printf(fmt, __VA_ARGS__); \ 254 } while (0) 255 #define KEYPRINTF(sc, ix, hk, mac) do { \ 256 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 257 ath_keyprint(__func__, ix, hk, mac); \ 258 } while (0) 259 static void ath_printrxbuf(struct ath_buf *bf, int); 260 static void ath_printtxbuf(struct ath_buf *bf, int); 261 #else 262 #define IFF_DUMPPKTS(sc, m) \ 263 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 264 #define DPRINTF(m, fmt, ...) 265 #define KEYPRINTF(sc, k, ix, mac) 266 #endif 267 268 #ifdef __NetBSD__ 269 int 270 ath_activate(struct device *self, enum devact act) 271 { 272 struct ath_softc *sc = (struct ath_softc *)self; 273 int rv = 0, s; 274 275 s = splnet(); 276 switch (act) { 277 case DVACT_ACTIVATE: 278 rv = EOPNOTSUPP; 279 break; 280 case DVACT_DEACTIVATE: 281 if_deactivate(&sc->sc_if); 282 break; 283 } 284 splx(s); 285 return rv; 286 } 287 288 int 289 ath_enable(struct ath_softc *sc) 290 { 291 if (ATH_IS_ENABLED(sc) == 0) { 292 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 293 printf("%s: device enable failed\n", 294 device_xname(&sc->sc_dev)); 295 return (EIO); 296 } 297 sc->sc_flags |= ATH_ENABLED; 298 } 299 return (0); 300 } 301 302 void 303 ath_disable(struct ath_softc *sc) 304 { 305 if (!ATH_IS_ENABLED(sc)) 306 return; 307 if (sc->sc_disable != NULL) 308 (*sc->sc_disable)(sc); 309 sc->sc_flags &= ~ATH_ENABLED; 310 } 311 #endif /* __NetBSD__ */ 312 313 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 314 315 int 316 ath_attach(u_int16_t devid, struct ath_softc *sc) 317 { 318 struct ifnet *ifp = &sc->sc_if; 319 struct ieee80211com *ic = &sc->sc_ic; 320 struct ath_hal *ah = NULL; 321 HAL_STATUS status; 322 int error = 0, i; 323 324 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 325 326 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 327 328 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 329 if (ah == NULL) { 330 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 331 status); 332 error = ENXIO; 333 goto bad; 334 } 335 if (ah->ah_abi != HAL_ABI_VERSION) { 336 if_printf(ifp, "HAL ABI mismatch detected " 337 "(HAL:0x%x != driver:0x%x)\n", 338 ah->ah_abi, HAL_ABI_VERSION); 339 error = ENXIO; 340 goto bad; 341 } 342 sc->sc_ah = ah; 343 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 344 345 /* 346 * Check if the MAC has multi-rate retry support. 347 * We do this by trying to setup a fake extended 348 * descriptor. MAC's that don't have support will 349 * return false w/o doing anything. MAC's that do 350 * support it will return true w/o doing anything. 351 */ 352 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 353 354 /* 355 * Check if the device has hardware counters for PHY 356 * errors. If so we need to enable the MIB interrupt 357 * so we can act on stat triggers. 358 */ 359 if (ath_hal_hwphycounters(ah)) 360 sc->sc_needmib = 1; 361 362 /* 363 * Get the hardware key cache size. 364 */ 365 sc->sc_keymax = ath_hal_keycachesize(ah); 366 if (sc->sc_keymax > ATH_KEYMAX) { 367 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 368 ATH_KEYMAX, sc->sc_keymax); 369 sc->sc_keymax = ATH_KEYMAX; 370 } 371 /* 372 * Reset the key cache since some parts do not 373 * reset the contents on initial power up. 374 */ 375 for (i = 0; i < sc->sc_keymax; i++) 376 ath_hal_keyreset(ah, i); 377 /* 378 * Mark key cache slots associated with global keys 379 * as in use. If we knew TKIP was not to be used we 380 * could leave the +32, +64, and +32+64 slots free. 381 * XXX only for splitmic. 382 */ 383 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 384 setbit(sc->sc_keymap, i); 385 setbit(sc->sc_keymap, i+32); 386 setbit(sc->sc_keymap, i+64); 387 setbit(sc->sc_keymap, i+32+64); 388 } 389 390 /* 391 * Collect the channel list using the default country 392 * code and including outdoor channels. The 802.11 layer 393 * is resposible for filtering this list based on settings 394 * like the phy mode. 395 */ 396 error = ath_getchannels(sc, ath_countrycode, 397 ath_outdoor, ath_xchanmode); 398 if (error != 0) 399 goto bad; 400 401 /* 402 * Setup rate tables for all potential media types. 403 */ 404 ath_rate_setup(sc, IEEE80211_MODE_11A); 405 ath_rate_setup(sc, IEEE80211_MODE_11B); 406 ath_rate_setup(sc, IEEE80211_MODE_11G); 407 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 408 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 409 /* NB: setup here so ath_rate_update is happy */ 410 ath_setcurmode(sc, IEEE80211_MODE_11A); 411 412 /* 413 * Allocate tx+rx descriptors and populate the lists. 414 */ 415 error = ath_desc_alloc(sc); 416 if (error != 0) { 417 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 418 goto bad; 419 } 420 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 421 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 422 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 423 424 ATH_TXBUF_LOCK_INIT(sc); 425 426 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 427 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 428 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 429 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 430 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 431 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 432 433 /* 434 * Allocate hardware transmit queues: one queue for 435 * beacon frames and one data queue for each QoS 436 * priority. Note that the hal handles reseting 437 * these queues at the needed time. 438 * 439 * XXX PS-Poll 440 */ 441 sc->sc_bhalq = ath_beaconq_setup(ah); 442 if (sc->sc_bhalq == (u_int) -1) { 443 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 444 error = EIO; 445 goto bad2; 446 } 447 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 448 if (sc->sc_cabq == NULL) { 449 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 450 error = EIO; 451 goto bad2; 452 } 453 /* NB: insure BK queue is the lowest priority h/w queue */ 454 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 455 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 456 ieee80211_wme_acnames[WME_AC_BK]); 457 error = EIO; 458 goto bad2; 459 } 460 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 461 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 462 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 463 /* 464 * Not enough hardware tx queues to properly do WME; 465 * just punt and assign them all to the same h/w queue. 466 * We could do a better job of this if, for example, 467 * we allocate queues when we switch from station to 468 * AP mode. 469 */ 470 if (sc->sc_ac2q[WME_AC_VI] != NULL) 471 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 472 if (sc->sc_ac2q[WME_AC_BE] != NULL) 473 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 474 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 475 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 476 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 477 } 478 479 /* 480 * Special case certain configurations. Note the 481 * CAB queue is handled by these specially so don't 482 * include them when checking the txq setup mask. 483 */ 484 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 485 case 0x01: 486 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 487 break; 488 case 0x0f: 489 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 490 break; 491 default: 492 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 493 break; 494 } 495 496 /* 497 * Setup rate control. Some rate control modules 498 * call back to change the anntena state so expose 499 * the necessary entry points. 500 * XXX maybe belongs in struct ath_ratectrl? 501 */ 502 sc->sc_setdefantenna = ath_setdefantenna; 503 sc->sc_rc = ath_rate_attach(sc); 504 if (sc->sc_rc == NULL) { 505 error = EIO; 506 goto bad2; 507 } 508 509 sc->sc_blinking = 0; 510 sc->sc_ledstate = 1; 511 sc->sc_ledon = 0; /* low true */ 512 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 513 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 514 /* 515 * Auto-enable soft led processing for IBM cards and for 516 * 5211 minipci cards. Users can also manually enable/disable 517 * support with a sysctl. 518 */ 519 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 520 if (sc->sc_softled) { 521 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 522 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 523 } 524 525 ifp->if_softc = sc; 526 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 527 ifp->if_start = ath_start; 528 ifp->if_stop = ath_stop; 529 ifp->if_watchdog = ath_watchdog; 530 ifp->if_ioctl = ath_ioctl; 531 ifp->if_init = ath_ifinit; 532 IFQ_SET_READY(&ifp->if_snd); 533 534 ic->ic_ifp = ifp; 535 ic->ic_reset = ath_reset; 536 ic->ic_newassoc = ath_newassoc; 537 ic->ic_updateslot = ath_updateslot; 538 ic->ic_wme.wme_update = ath_wme_update; 539 /* XXX not right but it's not used anywhere important */ 540 ic->ic_phytype = IEEE80211_T_OFDM; 541 ic->ic_opmode = IEEE80211_M_STA; 542 ic->ic_caps = 543 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 544 | IEEE80211_C_HOSTAP /* hostap mode */ 545 | IEEE80211_C_MONITOR /* monitor mode */ 546 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 547 | IEEE80211_C_SHSLOT /* short slot time supported */ 548 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 549 | IEEE80211_C_TXFRAG /* handle tx frags */ 550 ; 551 /* 552 * Query the hal to figure out h/w crypto support. 553 */ 554 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 555 ic->ic_caps |= IEEE80211_C_WEP; 556 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 557 ic->ic_caps |= IEEE80211_C_AES; 558 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 559 ic->ic_caps |= IEEE80211_C_AES_CCM; 560 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 561 ic->ic_caps |= IEEE80211_C_CKIP; 562 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 563 ic->ic_caps |= IEEE80211_C_TKIP; 564 /* 565 * Check if h/w does the MIC and/or whether the 566 * separate key cache entries are required to 567 * handle both tx+rx MIC keys. 568 */ 569 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 570 ic->ic_caps |= IEEE80211_C_TKIPMIC; 571 if (ath_hal_tkipsplit(ah)) 572 sc->sc_splitmic = 1; 573 } 574 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 575 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 576 /* 577 * TPC support can be done either with a global cap or 578 * per-packet support. The latter is not available on 579 * all parts. We're a bit pedantic here as all parts 580 * support a global cap. 581 */ 582 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 583 ic->ic_caps |= IEEE80211_C_TXPMGT; 584 585 /* 586 * Mark WME capability only if we have sufficient 587 * hardware queues to do proper priority scheduling. 588 */ 589 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 590 ic->ic_caps |= IEEE80211_C_WME; 591 /* 592 * Check for misc other capabilities. 593 */ 594 if (ath_hal_hasbursting(ah)) 595 ic->ic_caps |= IEEE80211_C_BURST; 596 597 /* 598 * Indicate we need the 802.11 header padded to a 599 * 32-bit boundary for 4-address and QoS frames. 600 */ 601 ic->ic_flags |= IEEE80211_F_DATAPAD; 602 603 /* 604 * Query the hal about antenna support. 605 */ 606 sc->sc_defant = ath_hal_getdefantenna(ah); 607 608 /* 609 * Not all chips have the VEOL support we want to 610 * use with IBSS beacons; check here for it. 611 */ 612 sc->sc_hasveol = ath_hal_hasveol(ah); 613 614 /* get mac address from hardware */ 615 ath_hal_getmac(ah, ic->ic_myaddr); 616 617 if_attach(ifp); 618 /* call MI attach routine. */ 619 ieee80211_ifattach(ic); 620 /* override default methods */ 621 ic->ic_node_alloc = ath_node_alloc; 622 sc->sc_node_free = ic->ic_node_free; 623 ic->ic_node_free = ath_node_free; 624 ic->ic_node_getrssi = ath_node_getrssi; 625 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 626 ic->ic_recv_mgmt = ath_recv_mgmt; 627 sc->sc_newstate = ic->ic_newstate; 628 ic->ic_newstate = ath_newstate; 629 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 630 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 631 ic->ic_crypto.cs_key_delete = ath_key_delete; 632 ic->ic_crypto.cs_key_set = ath_key_set; 633 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 634 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 635 /* complete initialization */ 636 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 637 638 #if NBPFILTER > 0 639 ath_bpfattach(sc); 640 #endif 641 642 sc->sc_flags |= ATH_ATTACHED; 643 644 /* 645 * Setup dynamic sysctl's now that country code and 646 * regdomain are available from the hal. 647 */ 648 ath_sysctlattach(sc); 649 650 ieee80211_announce(ic); 651 ath_announce(sc); 652 return 0; 653 bad2: 654 ath_tx_cleanup(sc); 655 ath_desc_free(sc); 656 bad: 657 if (ah) 658 ath_hal_detach(ah); 659 sc->sc_invalid = 1; 660 return error; 661 } 662 663 int 664 ath_detach(struct ath_softc *sc) 665 { 666 struct ifnet *ifp = &sc->sc_if; 667 int s; 668 669 if ((sc->sc_flags & ATH_ATTACHED) == 0) 670 return (0); 671 672 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 673 __func__, ifp->if_flags); 674 675 s = splnet(); 676 ath_stop(ifp, 1); 677 #if NBPFILTER > 0 678 bpfdetach(ifp); 679 #endif 680 /* 681 * NB: the order of these is important: 682 * o call the 802.11 layer before detaching the hal to 683 * insure callbacks into the driver to delete global 684 * key cache entries can be handled 685 * o reclaim the tx queue data structures after calling 686 * the 802.11 layer as we'll get called back to reclaim 687 * node state and potentially want to use them 688 * o to cleanup the tx queues the hal is called, so detach 689 * it last 690 * Other than that, it's straightforward... 691 */ 692 ieee80211_ifdetach(&sc->sc_ic); 693 #ifdef ATH_TX99_DIAG 694 if (sc->sc_tx99 != NULL) 695 sc->sc_tx99->detach(sc->sc_tx99); 696 #endif 697 ath_rate_detach(sc->sc_rc); 698 ath_desc_free(sc); 699 ath_tx_cleanup(sc); 700 sysctl_teardown(&sc->sc_sysctllog); 701 ath_hal_detach(sc->sc_ah); 702 if_detach(ifp); 703 splx(s); 704 powerhook_disestablish(sc->sc_powerhook); 705 706 return 0; 707 } 708 709 void 710 ath_resume(struct ath_softc *sc) 711 { 712 if (sc->sc_softled) { 713 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 714 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 715 } 716 } 717 718 /* 719 * Interrupt handler. Most of the actual processing is deferred. 720 */ 721 int 722 ath_intr(void *arg) 723 { 724 struct ath_softc *sc = arg; 725 struct ifnet *ifp = &sc->sc_if; 726 struct ath_hal *ah = sc->sc_ah; 727 HAL_INT status; 728 729 if (sc->sc_invalid) { 730 /* 731 * The hardware is not ready/present, don't touch anything. 732 * Note this can happen early on if the IRQ is shared. 733 */ 734 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 735 return 0; 736 } 737 738 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 739 return 0; 740 741 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 742 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 743 __func__, ifp->if_flags); 744 ath_hal_getisr(ah, &status); /* clear ISR */ 745 ath_hal_intrset(ah, 0); /* disable further intr's */ 746 return 1; /* XXX */ 747 } 748 /* 749 * Figure out the reason(s) for the interrupt. Note 750 * that the hal returns a pseudo-ISR that may include 751 * bits we haven't explicitly enabled so we mask the 752 * value to insure we only process bits we requested. 753 */ 754 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 755 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 756 status &= sc->sc_imask; /* discard unasked for bits */ 757 if (status & HAL_INT_FATAL) { 758 /* 759 * Fatal errors are unrecoverable. Typically 760 * these are caused by DMA errors. Unfortunately 761 * the exact reason is not (presently) returned 762 * by the hal. 763 */ 764 sc->sc_stats.ast_hardware++; 765 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 766 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 767 } else if (status & HAL_INT_RXORN) { 768 sc->sc_stats.ast_rxorn++; 769 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 770 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 771 } else { 772 if (status & HAL_INT_SWBA) { 773 /* 774 * Software beacon alert--time to send a beacon. 775 * Handle beacon transmission directly; deferring 776 * this is too slow to meet timing constraints 777 * under load. 778 */ 779 ath_beacon_proc(sc, 0); 780 } 781 if (status & HAL_INT_RXEOL) { 782 /* 783 * NB: the hardware should re-read the link when 784 * RXE bit is written, but it doesn't work at 785 * least on older hardware revs. 786 */ 787 sc->sc_stats.ast_rxeol++; 788 sc->sc_rxlink = NULL; 789 } 790 if (status & HAL_INT_TXURN) { 791 sc->sc_stats.ast_txurn++; 792 /* bump tx trigger level */ 793 ath_hal_updatetxtriglevel(ah, AH_TRUE); 794 } 795 if (status & HAL_INT_RX) 796 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 797 if (status & HAL_INT_TX) 798 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 799 if (status & HAL_INT_BMISS) { 800 sc->sc_stats.ast_bmiss++; 801 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 802 } 803 if (status & HAL_INT_MIB) { 804 sc->sc_stats.ast_mib++; 805 /* 806 * Disable interrupts until we service the MIB 807 * interrupt; otherwise it will continue to fire. 808 */ 809 ath_hal_intrset(ah, 0); 810 /* 811 * Let the hal handle the event. We assume it will 812 * clear whatever condition caused the interrupt. 813 */ 814 ath_hal_mibevent(ah, &sc->sc_halstats); 815 ath_hal_intrset(ah, sc->sc_imask); 816 } 817 } 818 return 1; 819 } 820 821 /* Swap transmit descriptor. 822 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 823 * function. 824 */ 825 static inline void 826 ath_desc_swap(struct ath_desc *ds) 827 { 828 #ifdef AH_NEED_DESC_SWAP 829 ds->ds_link = htole32(ds->ds_link); 830 ds->ds_data = htole32(ds->ds_data); 831 ds->ds_ctl0 = htole32(ds->ds_ctl0); 832 ds->ds_ctl1 = htole32(ds->ds_ctl1); 833 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 834 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 835 #endif 836 } 837 838 static void 839 ath_fatal_proc(void *arg, int pending) 840 { 841 struct ath_softc *sc = arg; 842 struct ifnet *ifp = &sc->sc_if; 843 844 if_printf(ifp, "hardware error; resetting\n"); 845 ath_reset(ifp); 846 } 847 848 static void 849 ath_rxorn_proc(void *arg, int pending) 850 { 851 struct ath_softc *sc = arg; 852 struct ifnet *ifp = &sc->sc_if; 853 854 if_printf(ifp, "rx FIFO overrun; resetting\n"); 855 ath_reset(ifp); 856 } 857 858 static void 859 ath_bmiss_proc(void *arg, int pending) 860 { 861 struct ath_softc *sc = arg; 862 struct ieee80211com *ic = &sc->sc_ic; 863 864 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 865 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 866 ("unexpect operating mode %u", ic->ic_opmode)); 867 if (ic->ic_state == IEEE80211_S_RUN) { 868 u_int64_t lastrx = sc->sc_lastrx; 869 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 870 871 DPRINTF(sc, ATH_DEBUG_BEACON, 872 "%s: tsf %" PRIu64 " lastrx %" PRId64 873 " (%" PRIu64 ") bmiss %u\n", 874 __func__, tsf, tsf - lastrx, lastrx, 875 ic->ic_bmisstimeout*1024); 876 /* 877 * Workaround phantom bmiss interrupts by sanity-checking 878 * the time of our last rx'd frame. If it is within the 879 * beacon miss interval then ignore the interrupt. If it's 880 * truly a bmiss we'll get another interrupt soon and that'll 881 * be dispatched up for processing. 882 */ 883 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 884 NET_LOCK_GIANT(); 885 ieee80211_beacon_miss(ic); 886 NET_UNLOCK_GIANT(); 887 } else 888 sc->sc_stats.ast_bmiss_phantom++; 889 } 890 } 891 892 static void 893 ath_radar_proc(void *arg, int pending) 894 { 895 struct ath_softc *sc = arg; 896 struct ifnet *ifp = &sc->sc_if; 897 struct ath_hal *ah = sc->sc_ah; 898 HAL_CHANNEL hchan; 899 900 if (ath_hal_procdfs(ah, &hchan)) { 901 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 902 hchan.channel, hchan.channelFlags, hchan.privFlags); 903 /* 904 * Initiate channel change. 905 */ 906 /* XXX not yet */ 907 } 908 } 909 910 static u_int 911 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 912 { 913 #define N(a) (sizeof(a) / sizeof(a[0])) 914 static const u_int modeflags[] = { 915 0, /* IEEE80211_MODE_AUTO */ 916 CHANNEL_A, /* IEEE80211_MODE_11A */ 917 CHANNEL_B, /* IEEE80211_MODE_11B */ 918 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 919 0, /* IEEE80211_MODE_FH */ 920 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 921 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 922 }; 923 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 924 925 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 926 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 927 return modeflags[mode]; 928 #undef N 929 } 930 931 static int 932 ath_ifinit(struct ifnet *ifp) 933 { 934 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 935 936 return ath_init(sc); 937 } 938 939 static int 940 ath_init(struct ath_softc *sc) 941 { 942 struct ifnet *ifp = &sc->sc_if; 943 struct ieee80211com *ic = &sc->sc_ic; 944 struct ath_hal *ah = sc->sc_ah; 945 HAL_STATUS status; 946 int error = 0; 947 948 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 949 __func__, ifp->if_flags); 950 951 if (!device_has_power(&sc->sc_dev)) 952 return EBUSY; 953 954 ATH_LOCK(sc); 955 956 if ((error = ath_enable(sc)) != 0) { 957 ATH_UNLOCK(sc); 958 return error; 959 } 960 961 /* 962 * Stop anything previously setup. This is safe 963 * whether this is the first time through or not. 964 */ 965 ath_stop_locked(ifp, 0); 966 967 /* 968 * The basic interface to setting the hardware in a good 969 * state is ``reset''. On return the hardware is known to 970 * be powered up and with interrupts disabled. This must 971 * be followed by initialization of the appropriate bits 972 * and then setup of the interrupt mask. 973 */ 974 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 975 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 976 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 977 if_printf(ifp, "unable to reset hardware; hal status %u\n", 978 status); 979 error = EIO; 980 goto done; 981 } 982 983 /* 984 * This is needed only to setup initial state 985 * but it's best done after a reset. 986 */ 987 ath_update_txpow(sc); 988 /* 989 * Likewise this is set during reset so update 990 * state cached in the driver. 991 */ 992 ath_restore_diversity(sc); 993 sc->sc_calinterval = 1; 994 sc->sc_caltries = 0; 995 996 /* 997 * Setup the hardware after reset: the key cache 998 * is filled as needed and the receive engine is 999 * set going. Frame transmit is handled entirely 1000 * in the frame output path; there's nothing to do 1001 * here except setup the interrupt mask. 1002 */ 1003 if ((error = ath_startrecv(sc)) != 0) { 1004 if_printf(ifp, "unable to start recv logic\n"); 1005 goto done; 1006 } 1007 1008 /* 1009 * Enable interrupts. 1010 */ 1011 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1012 | HAL_INT_RXEOL | HAL_INT_RXORN 1013 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1014 /* 1015 * Enable MIB interrupts when there are hardware phy counters. 1016 * Note we only do this (at the moment) for station mode. 1017 */ 1018 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1019 sc->sc_imask |= HAL_INT_MIB; 1020 ath_hal_intrset(ah, sc->sc_imask); 1021 1022 ifp->if_flags |= IFF_RUNNING; 1023 ic->ic_state = IEEE80211_S_INIT; 1024 1025 /* 1026 * The hardware should be ready to go now so it's safe 1027 * to kick the 802.11 state machine as it's likely to 1028 * immediately call back to us to send mgmt frames. 1029 */ 1030 ath_chan_change(sc, ic->ic_curchan); 1031 #ifdef ATH_TX99_DIAG 1032 if (sc->sc_tx99 != NULL) 1033 sc->sc_tx99->start(sc->sc_tx99); 1034 else 1035 #endif 1036 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1037 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1038 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1039 } else 1040 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1041 done: 1042 ATH_UNLOCK(sc); 1043 return error; 1044 } 1045 1046 static void 1047 ath_stop_locked(struct ifnet *ifp, int disable) 1048 { 1049 struct ath_softc *sc = ifp->if_softc; 1050 struct ieee80211com *ic = &sc->sc_ic; 1051 struct ath_hal *ah = sc->sc_ah; 1052 1053 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1054 __func__, sc->sc_invalid, ifp->if_flags); 1055 1056 ATH_LOCK_ASSERT(sc); 1057 if (ifp->if_flags & IFF_RUNNING) { 1058 /* 1059 * Shutdown the hardware and driver: 1060 * reset 802.11 state machine 1061 * turn off timers 1062 * disable interrupts 1063 * turn off the radio 1064 * clear transmit machinery 1065 * clear receive machinery 1066 * drain and release tx queues 1067 * reclaim beacon resources 1068 * power down hardware 1069 * 1070 * Note that some of this work is not possible if the 1071 * hardware is gone (invalid). 1072 */ 1073 #ifdef ATH_TX99_DIAG 1074 if (sc->sc_tx99 != NULL) 1075 sc->sc_tx99->stop(sc->sc_tx99); 1076 #endif 1077 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1078 ifp->if_flags &= ~IFF_RUNNING; 1079 ifp->if_timer = 0; 1080 if (!sc->sc_invalid) { 1081 if (sc->sc_softled) { 1082 callout_stop(&sc->sc_ledtimer); 1083 ath_hal_gpioset(ah, sc->sc_ledpin, 1084 !sc->sc_ledon); 1085 sc->sc_blinking = 0; 1086 } 1087 ath_hal_intrset(ah, 0); 1088 } 1089 ath_draintxq(sc); 1090 if (!sc->sc_invalid) { 1091 ath_stoprecv(sc); 1092 ath_hal_phydisable(ah); 1093 } else 1094 sc->sc_rxlink = NULL; 1095 IF_PURGE(&ifp->if_snd); 1096 ath_beacon_free(sc); 1097 if (disable) 1098 ath_disable(sc); 1099 } 1100 } 1101 1102 static void 1103 ath_stop(struct ifnet *ifp, int disable) 1104 { 1105 struct ath_softc *sc = ifp->if_softc; 1106 1107 ATH_LOCK(sc); 1108 ath_stop_locked(ifp, disable); 1109 if (!sc->sc_invalid) { 1110 /* 1111 * Set the chip in full sleep mode. Note that we are 1112 * careful to do this only when bringing the interface 1113 * completely to a stop. When the chip is in this state 1114 * it must be carefully woken up or references to 1115 * registers in the PCI clock domain may freeze the bus 1116 * (and system). This varies by chip and is mostly an 1117 * issue with newer parts that go to sleep more quickly. 1118 */ 1119 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1120 } 1121 ATH_UNLOCK(sc); 1122 } 1123 1124 static void 1125 ath_restore_diversity(struct ath_softc *sc) 1126 { 1127 struct ifnet *ifp = &sc->sc_if; 1128 struct ath_hal *ah = sc->sc_ah; 1129 1130 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1131 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1132 if_printf(ifp, "could not restore diversity setting %d\n", 1133 sc->sc_diversity); 1134 sc->sc_diversity = ath_hal_getdiversity(ah); 1135 } 1136 } 1137 1138 /* 1139 * Reset the hardware w/o losing operational state. This is 1140 * basically a more efficient way of doing ath_stop, ath_init, 1141 * followed by state transitions to the current 802.11 1142 * operational state. Used to recover from various errors and 1143 * to reset or reload hardware state. 1144 */ 1145 int 1146 ath_reset(struct ifnet *ifp) 1147 { 1148 struct ath_softc *sc = ifp->if_softc; 1149 struct ieee80211com *ic = &sc->sc_ic; 1150 struct ath_hal *ah = sc->sc_ah; 1151 struct ieee80211_channel *c; 1152 HAL_STATUS status; 1153 1154 /* 1155 * Convert to a HAL channel description with the flags 1156 * constrained to reflect the current operating mode. 1157 */ 1158 c = ic->ic_curchan; 1159 sc->sc_curchan.channel = c->ic_freq; 1160 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1161 1162 ath_hal_intrset(ah, 0); /* disable interrupts */ 1163 ath_draintxq(sc); /* stop xmit side */ 1164 ath_stoprecv(sc); /* stop recv side */ 1165 /* NB: indicate channel change so we do a full reset */ 1166 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1167 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1168 __func__, status); 1169 ath_update_txpow(sc); /* update tx power state */ 1170 ath_restore_diversity(sc); 1171 sc->sc_calinterval = 1; 1172 sc->sc_caltries = 0; 1173 if (ath_startrecv(sc) != 0) /* restart recv */ 1174 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1175 /* 1176 * We may be doing a reset in response to an ioctl 1177 * that changes the channel so update any state that 1178 * might change as a result. 1179 */ 1180 ath_chan_change(sc, c); 1181 if (ic->ic_state == IEEE80211_S_RUN) 1182 ath_beacon_config(sc); /* restart beacons */ 1183 ath_hal_intrset(ah, sc->sc_imask); 1184 1185 ath_start(ifp); /* restart xmit */ 1186 return 0; 1187 } 1188 1189 /* 1190 * Cleanup driver resources when we run out of buffers 1191 * while processing fragments; return the tx buffers 1192 * allocated and drop node references. 1193 */ 1194 static void 1195 ath_txfrag_cleanup(struct ath_softc *sc, 1196 ath_bufhead *frags, struct ieee80211_node *ni) 1197 { 1198 struct ath_buf *bf; 1199 1200 ATH_TXBUF_LOCK_ASSERT(sc); 1201 1202 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1203 STAILQ_REMOVE_HEAD(frags, bf_list); 1204 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1205 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1206 ieee80211_node_decref(ni); 1207 } 1208 } 1209 1210 /* 1211 * Setup xmit of a fragmented frame. Allocate a buffer 1212 * for each frag and bump the node reference count to 1213 * reflect the held reference to be setup by ath_tx_start. 1214 */ 1215 static int 1216 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1217 struct mbuf *m0, struct ieee80211_node *ni) 1218 { 1219 struct mbuf *m; 1220 struct ath_buf *bf; 1221 1222 ATH_TXBUF_LOCK(sc); 1223 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1224 bf = STAILQ_FIRST(&sc->sc_txbuf); 1225 if (bf == NULL) { /* out of buffers, cleanup */ 1226 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1227 __func__); 1228 sc->sc_if.if_flags |= IFF_OACTIVE; 1229 ath_txfrag_cleanup(sc, frags, ni); 1230 break; 1231 } 1232 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1233 ieee80211_node_incref(ni); 1234 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1235 } 1236 ATH_TXBUF_UNLOCK(sc); 1237 1238 return !STAILQ_EMPTY(frags); 1239 } 1240 1241 static void 1242 ath_start(struct ifnet *ifp) 1243 { 1244 struct ath_softc *sc = ifp->if_softc; 1245 struct ath_hal *ah = sc->sc_ah; 1246 struct ieee80211com *ic = &sc->sc_ic; 1247 struct ieee80211_node *ni; 1248 struct ath_buf *bf; 1249 struct mbuf *m, *next; 1250 struct ieee80211_frame *wh; 1251 struct ether_header *eh; 1252 ath_bufhead frags; 1253 1254 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1255 return; 1256 for (;;) { 1257 /* 1258 * Grab a TX buffer and associated resources. 1259 */ 1260 ATH_TXBUF_LOCK(sc); 1261 bf = STAILQ_FIRST(&sc->sc_txbuf); 1262 if (bf != NULL) 1263 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1264 ATH_TXBUF_UNLOCK(sc); 1265 if (bf == NULL) { 1266 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1267 __func__); 1268 sc->sc_stats.ast_tx_qstop++; 1269 ifp->if_flags |= IFF_OACTIVE; 1270 break; 1271 } 1272 /* 1273 * Poll the management queue for frames; they 1274 * have priority over normal data frames. 1275 */ 1276 IF_DEQUEUE(&ic->ic_mgtq, m); 1277 if (m == NULL) { 1278 /* 1279 * No data frames go out unless we're associated. 1280 */ 1281 if (ic->ic_state != IEEE80211_S_RUN) { 1282 DPRINTF(sc, ATH_DEBUG_XMIT, 1283 "%s: discard data packet, state %s\n", 1284 __func__, 1285 ieee80211_state_name[ic->ic_state]); 1286 sc->sc_stats.ast_tx_discard++; 1287 ATH_TXBUF_LOCK(sc); 1288 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1289 ATH_TXBUF_UNLOCK(sc); 1290 break; 1291 } 1292 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1293 if (m == NULL) { 1294 ATH_TXBUF_LOCK(sc); 1295 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1296 ATH_TXBUF_UNLOCK(sc); 1297 break; 1298 } 1299 STAILQ_INIT(&frags); 1300 /* 1301 * Find the node for the destination so we can do 1302 * things like power save and fast frames aggregation. 1303 */ 1304 if (m->m_len < sizeof(struct ether_header) && 1305 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1306 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1307 ni = NULL; 1308 goto bad; 1309 } 1310 eh = mtod(m, struct ether_header *); 1311 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1312 if (ni == NULL) { 1313 /* NB: ieee80211_find_txnode does stat+msg */ 1314 m_freem(m); 1315 goto bad; 1316 } 1317 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1318 (m->m_flags & M_PWR_SAV) == 0) { 1319 /* 1320 * Station in power save mode; pass the frame 1321 * to the 802.11 layer and continue. We'll get 1322 * the frame back when the time is right. 1323 */ 1324 ieee80211_pwrsave(ic, ni, m); 1325 goto reclaim; 1326 } 1327 /* calculate priority so we can find the tx queue */ 1328 if (ieee80211_classify(ic, m, ni)) { 1329 DPRINTF(sc, ATH_DEBUG_XMIT, 1330 "%s: discard, classification failure\n", 1331 __func__); 1332 m_freem(m); 1333 goto bad; 1334 } 1335 ifp->if_opackets++; 1336 1337 #if NBPFILTER > 0 1338 if (ifp->if_bpf) 1339 bpf_mtap(ifp->if_bpf, m); 1340 #endif 1341 /* 1342 * Encapsulate the packet in prep for transmission. 1343 */ 1344 m = ieee80211_encap(ic, m, ni); 1345 if (m == NULL) { 1346 DPRINTF(sc, ATH_DEBUG_XMIT, 1347 "%s: encapsulation failure\n", 1348 __func__); 1349 sc->sc_stats.ast_tx_encap++; 1350 goto bad; 1351 } 1352 /* 1353 * Check for fragmentation. If this has frame 1354 * has been broken up verify we have enough 1355 * buffers to send all the fragments so all 1356 * go out or none... 1357 */ 1358 if ((m->m_flags & M_FRAG) && 1359 !ath_txfrag_setup(sc, &frags, m, ni)) { 1360 DPRINTF(sc, ATH_DEBUG_ANY, 1361 "%s: out of txfrag buffers\n", __func__); 1362 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1363 ath_freetx(m); 1364 goto bad; 1365 } 1366 } else { 1367 /* 1368 * Hack! The referenced node pointer is in the 1369 * rcvif field of the packet header. This is 1370 * placed there by ieee80211_mgmt_output because 1371 * we need to hold the reference with the frame 1372 * and there's no other way (other than packet 1373 * tags which we consider too expensive to use) 1374 * to pass it along. 1375 */ 1376 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1377 m->m_pkthdr.rcvif = NULL; 1378 1379 wh = mtod(m, struct ieee80211_frame *); 1380 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1381 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1382 /* fill time stamp */ 1383 u_int64_t tsf; 1384 u_int32_t *tstamp; 1385 1386 tsf = ath_hal_gettsf64(ah); 1387 /* XXX: adjust 100us delay to xmit */ 1388 tsf += 100; 1389 tstamp = (u_int32_t *)&wh[1]; 1390 tstamp[0] = htole32(tsf & 0xffffffff); 1391 tstamp[1] = htole32(tsf >> 32); 1392 } 1393 sc->sc_stats.ast_tx_mgmt++; 1394 } 1395 1396 nextfrag: 1397 next = m->m_nextpkt; 1398 if (ath_tx_start(sc, ni, bf, m)) { 1399 bad: 1400 ifp->if_oerrors++; 1401 reclaim: 1402 ATH_TXBUF_LOCK(sc); 1403 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1404 ath_txfrag_cleanup(sc, &frags, ni); 1405 ATH_TXBUF_UNLOCK(sc); 1406 if (ni != NULL) 1407 ieee80211_free_node(ni); 1408 continue; 1409 } 1410 if (next != NULL) { 1411 m = next; 1412 bf = STAILQ_FIRST(&frags); 1413 KASSERT(bf != NULL, ("no buf for txfrag")); 1414 STAILQ_REMOVE_HEAD(&frags, bf_list); 1415 goto nextfrag; 1416 } 1417 1418 ifp->if_timer = 1; 1419 } 1420 } 1421 1422 static int 1423 ath_media_change(struct ifnet *ifp) 1424 { 1425 #define IS_UP(ifp) \ 1426 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1427 int error; 1428 1429 error = ieee80211_media_change(ifp); 1430 if (error == ENETRESET) { 1431 if (IS_UP(ifp)) 1432 ath_init(ifp->if_softc); /* XXX lose error */ 1433 error = 0; 1434 } 1435 return error; 1436 #undef IS_UP 1437 } 1438 1439 #ifdef AR_DEBUG 1440 static void 1441 ath_keyprint(const char *tag, u_int ix, 1442 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1443 { 1444 static const char *ciphers[] = { 1445 "WEP", 1446 "AES-OCB", 1447 "AES-CCM", 1448 "CKIP", 1449 "TKIP", 1450 "CLR", 1451 }; 1452 int i, n; 1453 1454 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1455 for (i = 0, n = hk->kv_len; i < n; i++) 1456 printf("%02x", hk->kv_val[i]); 1457 printf(" mac %s", ether_sprintf(mac)); 1458 if (hk->kv_type == HAL_CIPHER_TKIP) { 1459 printf(" mic "); 1460 for (i = 0; i < sizeof(hk->kv_mic); i++) 1461 printf("%02x", hk->kv_mic[i]); 1462 } 1463 printf("\n"); 1464 } 1465 #endif 1466 1467 /* 1468 * Set a TKIP key into the hardware. This handles the 1469 * potential distribution of key state to multiple key 1470 * cache slots for TKIP. 1471 */ 1472 static int 1473 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1474 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1475 { 1476 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1477 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1478 struct ath_hal *ah = sc->sc_ah; 1479 1480 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1481 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1482 KASSERT(sc->sc_splitmic, ("key cache !split")); 1483 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1484 /* 1485 * TX key goes at first index, RX key at the rx index. 1486 * The hal handles the MIC keys at index+64. 1487 */ 1488 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1489 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1490 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1491 return 0; 1492 1493 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1494 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1495 /* XXX delete tx key on failure? */ 1496 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1497 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1498 /* 1499 * TX/RX key goes at first index. 1500 * The hal handles the MIC keys are index+64. 1501 */ 1502 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1503 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1504 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1505 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1506 } 1507 return 0; 1508 #undef IEEE80211_KEY_XR 1509 } 1510 1511 /* 1512 * Set a net80211 key into the hardware. This handles the 1513 * potential distribution of key state to multiple key 1514 * cache slots for TKIP with hardware MIC support. 1515 */ 1516 static int 1517 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1518 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1519 struct ieee80211_node *bss) 1520 { 1521 #define N(a) (sizeof(a)/sizeof(a[0])) 1522 static const u_int8_t ciphermap[] = { 1523 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1524 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1525 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1526 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1527 (u_int8_t) -1, /* 4 is not allocated */ 1528 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1529 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1530 }; 1531 struct ath_hal *ah = sc->sc_ah; 1532 const struct ieee80211_cipher *cip = k->wk_cipher; 1533 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1534 const u_int8_t *mac; 1535 HAL_KEYVAL hk; 1536 1537 memset(&hk, 0, sizeof(hk)); 1538 /* 1539 * Software crypto uses a "clear key" so non-crypto 1540 * state kept in the key cache are maintained and 1541 * so that rx frames have an entry to match. 1542 */ 1543 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1544 KASSERT(cip->ic_cipher < N(ciphermap), 1545 ("invalid cipher type %u", cip->ic_cipher)); 1546 hk.kv_type = ciphermap[cip->ic_cipher]; 1547 hk.kv_len = k->wk_keylen; 1548 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1549 } else 1550 hk.kv_type = HAL_CIPHER_CLR; 1551 1552 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1553 /* 1554 * Group keys on hardware that supports multicast frame 1555 * key search use a mac that is the sender's address with 1556 * the high bit set instead of the app-specified address. 1557 */ 1558 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1559 gmac[0] |= 0x80; 1560 mac = gmac; 1561 } else 1562 mac = mac0; 1563 1564 if (hk.kv_type == HAL_CIPHER_TKIP && 1565 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1566 sc->sc_splitmic) { 1567 return ath_keyset_tkip(sc, k, &hk, mac); 1568 } else { 1569 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1570 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1571 } 1572 #undef N 1573 } 1574 1575 /* 1576 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1577 * each key, one for decrypt/encrypt and the other for the MIC. 1578 */ 1579 static u_int16_t 1580 key_alloc_2pair(struct ath_softc *sc, 1581 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1582 { 1583 #define N(a) (sizeof(a)/sizeof(a[0])) 1584 u_int i, keyix; 1585 1586 KASSERT(sc->sc_splitmic, ("key cache !split")); 1587 /* XXX could optimize */ 1588 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1589 u_int8_t b = sc->sc_keymap[i]; 1590 if (b != 0xff) { 1591 /* 1592 * One or more slots in this byte are free. 1593 */ 1594 keyix = i*NBBY; 1595 while (b & 1) { 1596 again: 1597 keyix++; 1598 b >>= 1; 1599 } 1600 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1601 if (isset(sc->sc_keymap, keyix+32) || 1602 isset(sc->sc_keymap, keyix+64) || 1603 isset(sc->sc_keymap, keyix+32+64)) { 1604 /* full pair unavailable */ 1605 /* XXX statistic */ 1606 if (keyix == (i+1)*NBBY) { 1607 /* no slots were appropriate, advance */ 1608 continue; 1609 } 1610 goto again; 1611 } 1612 setbit(sc->sc_keymap, keyix); 1613 setbit(sc->sc_keymap, keyix+64); 1614 setbit(sc->sc_keymap, keyix+32); 1615 setbit(sc->sc_keymap, keyix+32+64); 1616 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1617 "%s: key pair %u,%u %u,%u\n", 1618 __func__, keyix, keyix+64, 1619 keyix+32, keyix+32+64); 1620 *txkeyix = keyix; 1621 *rxkeyix = keyix+32; 1622 return 1; 1623 } 1624 } 1625 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1626 return 0; 1627 #undef N 1628 } 1629 1630 /* 1631 * Allocate a single key cache slot. 1632 */ 1633 static int 1634 key_alloc_single(struct ath_softc *sc, 1635 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1636 { 1637 #define N(a) (sizeof(a)/sizeof(a[0])) 1638 u_int i, keyix; 1639 1640 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1641 for (i = 0; i < N(sc->sc_keymap); i++) { 1642 u_int8_t b = sc->sc_keymap[i]; 1643 if (b != 0xff) { 1644 /* 1645 * One or more slots are free. 1646 */ 1647 keyix = i*NBBY; 1648 while (b & 1) 1649 keyix++, b >>= 1; 1650 setbit(sc->sc_keymap, keyix); 1651 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1652 __func__, keyix); 1653 *txkeyix = *rxkeyix = keyix; 1654 return 1; 1655 } 1656 } 1657 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1658 return 0; 1659 #undef N 1660 } 1661 1662 /* 1663 * Allocate one or more key cache slots for a uniacst key. The 1664 * key itself is needed only to identify the cipher. For hardware 1665 * TKIP with split cipher+MIC keys we allocate two key cache slot 1666 * pairs so that we can setup separate TX and RX MIC keys. Note 1667 * that the MIC key for a TKIP key at slot i is assumed by the 1668 * hardware to be at slot i+64. This limits TKIP keys to the first 1669 * 64 entries. 1670 */ 1671 static int 1672 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1673 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1674 { 1675 struct ath_softc *sc = ic->ic_ifp->if_softc; 1676 1677 /* 1678 * Group key allocation must be handled specially for 1679 * parts that do not support multicast key cache search 1680 * functionality. For those parts the key id must match 1681 * the h/w key index so lookups find the right key. On 1682 * parts w/ the key search facility we install the sender's 1683 * mac address (with the high bit set) and let the hardware 1684 * find the key w/o using the key id. This is preferred as 1685 * it permits us to support multiple users for adhoc and/or 1686 * multi-station operation. 1687 */ 1688 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1689 if (!(&ic->ic_nw_keys[0] <= k && 1690 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1691 /* should not happen */ 1692 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1693 "%s: bogus group key\n", __func__); 1694 return 0; 1695 } 1696 /* 1697 * XXX we pre-allocate the global keys so 1698 * have no way to check if they've already been allocated. 1699 */ 1700 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1701 return 1; 1702 } 1703 1704 /* 1705 * We allocate two pair for TKIP when using the h/w to do 1706 * the MIC. For everything else, including software crypto, 1707 * we allocate a single entry. Note that s/w crypto requires 1708 * a pass-through slot on the 5211 and 5212. The 5210 does 1709 * not support pass-through cache entries and we map all 1710 * those requests to slot 0. 1711 */ 1712 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1713 return key_alloc_single(sc, keyix, rxkeyix); 1714 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1715 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1716 return key_alloc_2pair(sc, keyix, rxkeyix); 1717 } else { 1718 return key_alloc_single(sc, keyix, rxkeyix); 1719 } 1720 } 1721 1722 /* 1723 * Delete an entry in the key cache allocated by ath_key_alloc. 1724 */ 1725 static int 1726 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1727 { 1728 struct ath_softc *sc = ic->ic_ifp->if_softc; 1729 struct ath_hal *ah = sc->sc_ah; 1730 const struct ieee80211_cipher *cip = k->wk_cipher; 1731 u_int keyix = k->wk_keyix; 1732 1733 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1734 1735 ath_hal_keyreset(ah, keyix); 1736 /* 1737 * Handle split tx/rx keying required for TKIP with h/w MIC. 1738 */ 1739 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1740 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1741 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1742 if (keyix >= IEEE80211_WEP_NKID) { 1743 /* 1744 * Don't touch keymap entries for global keys so 1745 * they are never considered for dynamic allocation. 1746 */ 1747 clrbit(sc->sc_keymap, keyix); 1748 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1749 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1750 sc->sc_splitmic) { 1751 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1752 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1753 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1754 } 1755 } 1756 return 1; 1757 } 1758 1759 /* 1760 * Set the key cache contents for the specified key. Key cache 1761 * slot(s) must already have been allocated by ath_key_alloc. 1762 */ 1763 static int 1764 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1765 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1766 { 1767 struct ath_softc *sc = ic->ic_ifp->if_softc; 1768 1769 return ath_keyset(sc, k, mac, ic->ic_bss); 1770 } 1771 1772 /* 1773 * Block/unblock tx+rx processing while a key change is done. 1774 * We assume the caller serializes key management operations 1775 * so we only need to worry about synchronization with other 1776 * uses that originate in the driver. 1777 */ 1778 static void 1779 ath_key_update_begin(struct ieee80211com *ic) 1780 { 1781 struct ifnet *ifp = ic->ic_ifp; 1782 struct ath_softc *sc = ifp->if_softc; 1783 1784 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1785 #if 0 1786 tasklet_disable(&sc->sc_rxtq); 1787 #endif 1788 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1789 } 1790 1791 static void 1792 ath_key_update_end(struct ieee80211com *ic) 1793 { 1794 struct ifnet *ifp = ic->ic_ifp; 1795 struct ath_softc *sc = ifp->if_softc; 1796 1797 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1798 IF_UNLOCK(&ifp->if_snd); 1799 #if 0 1800 tasklet_enable(&sc->sc_rxtq); 1801 #endif 1802 } 1803 1804 /* 1805 * Calculate the receive filter according to the 1806 * operating mode and state: 1807 * 1808 * o always accept unicast, broadcast, and multicast traffic 1809 * o maintain current state of phy error reception (the hal 1810 * may enable phy error frames for noise immunity work) 1811 * o probe request frames are accepted only when operating in 1812 * hostap, adhoc, or monitor modes 1813 * o enable promiscuous mode according to the interface state 1814 * o accept beacons: 1815 * - when operating in adhoc mode so the 802.11 layer creates 1816 * node table entries for peers, 1817 * - when operating in station mode for collecting rssi data when 1818 * the station is otherwise quiet, or 1819 * - when scanning 1820 */ 1821 static u_int32_t 1822 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1823 { 1824 struct ieee80211com *ic = &sc->sc_ic; 1825 struct ath_hal *ah = sc->sc_ah; 1826 struct ifnet *ifp = &sc->sc_if; 1827 u_int32_t rfilt; 1828 1829 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1830 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1831 if (ic->ic_opmode != IEEE80211_M_STA) 1832 rfilt |= HAL_RX_FILTER_PROBEREQ; 1833 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1834 (ifp->if_flags & IFF_PROMISC)) 1835 rfilt |= HAL_RX_FILTER_PROM; 1836 if (ic->ic_opmode == IEEE80211_M_STA || 1837 ic->ic_opmode == IEEE80211_M_IBSS || 1838 state == IEEE80211_S_SCAN) 1839 rfilt |= HAL_RX_FILTER_BEACON; 1840 return rfilt; 1841 } 1842 1843 static void 1844 ath_mcastfilter_accum(void *dl, u_int32_t *mfilt) 1845 { 1846 u_int32_t val; 1847 u_int8_t pos; 1848 1849 /* calculate XOR of eight 6bit values */ 1850 val = LE_READ_4((char *)dl + 0); 1851 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1852 val = LE_READ_4((char *)dl + 3); 1853 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1854 pos &= 0x3f; 1855 mfilt[pos / 32] |= (1 << (pos % 32)); 1856 } 1857 1858 static void 1859 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1860 { 1861 struct ifnet *ifp = &sc->sc_if; 1862 struct ether_multi *enm; 1863 struct ether_multistep estep; 1864 1865 mfilt[0] = mfilt[1] = 0; 1866 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1867 while (enm != NULL) { 1868 /* XXX Punt on ranges. */ 1869 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1870 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1871 ifp->if_flags |= IFF_ALLMULTI; 1872 return; 1873 } 1874 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1875 ETHER_NEXT_MULTI(estep, enm); 1876 } 1877 ifp->if_flags &= ~IFF_ALLMULTI; 1878 } 1879 1880 static void 1881 ath_mode_init(struct ath_softc *sc) 1882 { 1883 struct ieee80211com *ic = &sc->sc_ic; 1884 struct ath_hal *ah = sc->sc_ah; 1885 u_int32_t rfilt, mfilt[2]; 1886 int i; 1887 1888 /* configure rx filter */ 1889 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1890 ath_hal_setrxfilter(ah, rfilt); 1891 1892 /* configure operational mode */ 1893 ath_hal_setopmode(ah); 1894 1895 /* Write keys to hardware; it may have been powered down. */ 1896 ath_key_update_begin(ic); 1897 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1898 ath_key_set(ic, 1899 &ic->ic_crypto.cs_nw_keys[i], 1900 ic->ic_myaddr); 1901 } 1902 ath_key_update_end(ic); 1903 1904 /* 1905 * Handle any link-level address change. Note that we only 1906 * need to force ic_myaddr; any other addresses are handled 1907 * as a byproduct of the ifnet code marking the interface 1908 * down then up. 1909 * 1910 * XXX should get from lladdr instead of arpcom but that's more work 1911 */ 1912 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1913 ath_hal_setmac(ah, ic->ic_myaddr); 1914 1915 /* calculate and install multicast filter */ 1916 #ifdef __FreeBSD__ 1917 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1918 mfilt[0] = mfilt[1] = 0; 1919 IF_ADDR_LOCK(ifp); 1920 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1921 void *dl; 1922 1923 /* calculate XOR of eight 6bit values */ 1924 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1925 val = LE_READ_4((char *)dl + 0); 1926 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1927 val = LE_READ_4((char *)dl + 3); 1928 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1929 pos &= 0x3f; 1930 mfilt[pos / 32] |= (1 << (pos % 32)); 1931 } 1932 IF_ADDR_UNLOCK(ifp); 1933 } else { 1934 mfilt[0] = mfilt[1] = ~0; 1935 } 1936 #endif 1937 #ifdef __NetBSD__ 1938 ath_mcastfilter_compute(sc, mfilt); 1939 #endif 1940 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1941 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1942 __func__, rfilt, mfilt[0], mfilt[1]); 1943 } 1944 1945 /* 1946 * Set the slot time based on the current setting. 1947 */ 1948 static void 1949 ath_setslottime(struct ath_softc *sc) 1950 { 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct ath_hal *ah = sc->sc_ah; 1953 1954 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1955 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1956 else 1957 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1958 sc->sc_updateslot = OK; 1959 } 1960 1961 /* 1962 * Callback from the 802.11 layer to update the 1963 * slot time based on the current setting. 1964 */ 1965 static void 1966 ath_updateslot(struct ifnet *ifp) 1967 { 1968 struct ath_softc *sc = ifp->if_softc; 1969 struct ieee80211com *ic = &sc->sc_ic; 1970 1971 /* 1972 * When not coordinating the BSS, change the hardware 1973 * immediately. For other operation we defer the change 1974 * until beacon updates have propagated to the stations. 1975 */ 1976 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1977 sc->sc_updateslot = UPDATE; 1978 else 1979 ath_setslottime(sc); 1980 } 1981 1982 /* 1983 * Setup a h/w transmit queue for beacons. 1984 */ 1985 static int 1986 ath_beaconq_setup(struct ath_hal *ah) 1987 { 1988 HAL_TXQ_INFO qi; 1989 1990 memset(&qi, 0, sizeof(qi)); 1991 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1992 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1993 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1994 /* NB: for dynamic turbo, don't enable any other interrupts */ 1995 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1996 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1997 } 1998 1999 /* 2000 * Setup the transmit queue parameters for the beacon queue. 2001 */ 2002 static int 2003 ath_beaconq_config(struct ath_softc *sc) 2004 { 2005 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 struct ath_hal *ah = sc->sc_ah; 2008 HAL_TXQ_INFO qi; 2009 2010 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2011 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2012 /* 2013 * Always burst out beacon and CAB traffic. 2014 */ 2015 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2016 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2017 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2018 } else { 2019 struct wmeParams *wmep = 2020 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2021 /* 2022 * Adhoc mode; important thing is to use 2x cwmin. 2023 */ 2024 qi.tqi_aifs = wmep->wmep_aifsn; 2025 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2026 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2027 } 2028 2029 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2030 device_printf(&sc->sc_dev, "unable to update parameters for " 2031 "beacon hardware queue!\n"); 2032 return 0; 2033 } else { 2034 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2035 return 1; 2036 } 2037 #undef ATH_EXPONENT_TO_VALUE 2038 } 2039 2040 /* 2041 * Allocate and setup an initial beacon frame. 2042 */ 2043 static int 2044 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2045 { 2046 struct ieee80211com *ic = ni->ni_ic; 2047 struct ath_buf *bf; 2048 struct mbuf *m; 2049 int error; 2050 2051 bf = STAILQ_FIRST(&sc->sc_bbuf); 2052 if (bf == NULL) { 2053 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2054 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2055 return ENOMEM; /* XXX */ 2056 } 2057 /* 2058 * NB: the beacon data buffer must be 32-bit aligned; 2059 * we assume the mbuf routines will return us something 2060 * with this alignment (perhaps should assert). 2061 */ 2062 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2063 if (m == NULL) { 2064 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2065 __func__); 2066 sc->sc_stats.ast_be_nombuf++; 2067 return ENOMEM; 2068 } 2069 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2070 BUS_DMA_NOWAIT); 2071 if (error == 0) { 2072 bf->bf_m = m; 2073 bf->bf_node = ieee80211_ref_node(ni); 2074 } else { 2075 m_freem(m); 2076 } 2077 return error; 2078 } 2079 2080 /* 2081 * Setup the beacon frame for transmit. 2082 */ 2083 static void 2084 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2085 { 2086 #define USE_SHPREAMBLE(_ic) \ 2087 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2088 == IEEE80211_F_SHPREAMBLE) 2089 struct ieee80211_node *ni = bf->bf_node; 2090 struct ieee80211com *ic = ni->ni_ic; 2091 struct mbuf *m = bf->bf_m; 2092 struct ath_hal *ah = sc->sc_ah; 2093 struct ath_desc *ds; 2094 int flags, antenna; 2095 const HAL_RATE_TABLE *rt; 2096 u_int8_t rix, rate; 2097 2098 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2099 __func__, m, m->m_len); 2100 2101 /* setup descriptors */ 2102 ds = bf->bf_desc; 2103 2104 flags = HAL_TXDESC_NOACK; 2105 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2106 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2107 flags |= HAL_TXDESC_VEOL; 2108 /* 2109 * Let hardware handle antenna switching unless 2110 * the user has selected a transmit antenna 2111 * (sc_txantenna is not 0). 2112 */ 2113 antenna = sc->sc_txantenna; 2114 } else { 2115 ds->ds_link = 0; 2116 /* 2117 * Switch antenna every 4 beacons, unless the user 2118 * has selected a transmit antenna (sc_txantenna 2119 * is not 0). 2120 * 2121 * XXX assumes two antenna 2122 */ 2123 if (sc->sc_txantenna == 0) 2124 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2125 else 2126 antenna = sc->sc_txantenna; 2127 } 2128 2129 KASSERT(bf->bf_nseg == 1, 2130 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2131 ds->ds_data = bf->bf_segs[0].ds_addr; 2132 /* 2133 * Calculate rate code. 2134 * XXX everything at min xmit rate 2135 */ 2136 rix = sc->sc_minrateix; 2137 rt = sc->sc_currates; 2138 rate = rt->info[rix].rateCode; 2139 if (USE_SHPREAMBLE(ic)) 2140 rate |= rt->info[rix].shortPreamble; 2141 ath_hal_setuptxdesc(ah, ds 2142 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2143 , sizeof(struct ieee80211_frame)/* header length */ 2144 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2145 , ni->ni_txpower /* txpower XXX */ 2146 , rate, 1 /* series 0 rate/tries */ 2147 , HAL_TXKEYIX_INVALID /* no encryption */ 2148 , antenna /* antenna mode */ 2149 , flags /* no ack, veol for beacons */ 2150 , 0 /* rts/cts rate */ 2151 , 0 /* rts/cts duration */ 2152 ); 2153 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2154 ath_hal_filltxdesc(ah, ds 2155 , roundup(m->m_len, 4) /* buffer length */ 2156 , AH_TRUE /* first segment */ 2157 , AH_TRUE /* last segment */ 2158 , ds /* first descriptor */ 2159 ); 2160 2161 /* NB: The desc swap function becomes void, 2162 * if descriptor swapping is not enabled 2163 */ 2164 ath_desc_swap(ds); 2165 2166 #undef USE_SHPREAMBLE 2167 } 2168 2169 /* 2170 * Transmit a beacon frame at SWBA. Dynamic updates to the 2171 * frame contents are done as needed and the slot time is 2172 * also adjusted based on current state. 2173 */ 2174 static void 2175 ath_beacon_proc(void *arg, int pending) 2176 { 2177 struct ath_softc *sc = arg; 2178 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2179 struct ieee80211_node *ni = bf->bf_node; 2180 struct ieee80211com *ic = ni->ni_ic; 2181 struct ath_hal *ah = sc->sc_ah; 2182 struct mbuf *m; 2183 int ncabq, error, otherant; 2184 2185 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2186 __func__, pending); 2187 2188 if (ic->ic_opmode == IEEE80211_M_STA || 2189 ic->ic_opmode == IEEE80211_M_MONITOR || 2190 bf == NULL || bf->bf_m == NULL) { 2191 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2192 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2193 return; 2194 } 2195 /* 2196 * Check if the previous beacon has gone out. If 2197 * not don't try to post another, skip this period 2198 * and wait for the next. Missed beacons indicate 2199 * a problem and should not occur. If we miss too 2200 * many consecutive beacons reset the device. 2201 */ 2202 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2203 sc->sc_bmisscount++; 2204 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2205 "%s: missed %u consecutive beacons\n", 2206 __func__, sc->sc_bmisscount); 2207 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2208 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2209 return; 2210 } 2211 if (sc->sc_bmisscount != 0) { 2212 DPRINTF(sc, ATH_DEBUG_BEACON, 2213 "%s: resume beacon xmit after %u misses\n", 2214 __func__, sc->sc_bmisscount); 2215 sc->sc_bmisscount = 0; 2216 } 2217 2218 /* 2219 * Update dynamic beacon contents. If this returns 2220 * non-zero then we need to remap the memory because 2221 * the beacon frame changed size (probably because 2222 * of the TIM bitmap). 2223 */ 2224 m = bf->bf_m; 2225 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2226 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2227 /* XXX too conservative? */ 2228 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2229 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2230 BUS_DMA_NOWAIT); 2231 if (error != 0) { 2232 if_printf(&sc->sc_if, 2233 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2234 __func__, error); 2235 return; 2236 } 2237 } 2238 2239 /* 2240 * Handle slot time change when a non-ERP station joins/leaves 2241 * an 11g network. The 802.11 layer notifies us via callback, 2242 * we mark updateslot, then wait one beacon before effecting 2243 * the change. This gives associated stations at least one 2244 * beacon interval to note the state change. 2245 */ 2246 /* XXX locking */ 2247 if (sc->sc_updateslot == UPDATE) 2248 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2249 else if (sc->sc_updateslot == COMMIT) 2250 ath_setslottime(sc); /* commit change to h/w */ 2251 2252 /* 2253 * Check recent per-antenna transmit statistics and flip 2254 * the default antenna if noticeably more frames went out 2255 * on the non-default antenna. 2256 * XXX assumes 2 anntenae 2257 */ 2258 otherant = sc->sc_defant & 1 ? 2 : 1; 2259 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2260 ath_setdefantenna(sc, otherant); 2261 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2262 2263 /* 2264 * Construct tx descriptor. 2265 */ 2266 ath_beacon_setup(sc, bf); 2267 2268 /* 2269 * Stop any current dma and put the new frame on the queue. 2270 * This should never fail since we check above that no frames 2271 * are still pending on the queue. 2272 */ 2273 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2274 DPRINTF(sc, ATH_DEBUG_ANY, 2275 "%s: beacon queue %u did not stop?\n", 2276 __func__, sc->sc_bhalq); 2277 } 2278 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2279 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2280 2281 /* 2282 * Enable the CAB queue before the beacon queue to 2283 * insure cab frames are triggered by this beacon. 2284 */ 2285 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2286 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2287 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2288 ath_hal_txstart(ah, sc->sc_bhalq); 2289 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2290 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2291 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2292 2293 sc->sc_stats.ast_be_xmit++; 2294 } 2295 2296 /* 2297 * Reset the hardware after detecting beacons have stopped. 2298 */ 2299 static void 2300 ath_bstuck_proc(void *arg, int pending) 2301 { 2302 struct ath_softc *sc = arg; 2303 struct ifnet *ifp = &sc->sc_if; 2304 2305 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2306 sc->sc_bmisscount); 2307 ath_reset(ifp); 2308 } 2309 2310 /* 2311 * Reclaim beacon resources. 2312 */ 2313 static void 2314 ath_beacon_free(struct ath_softc *sc) 2315 { 2316 struct ath_buf *bf; 2317 2318 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2319 if (bf->bf_m != NULL) { 2320 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2321 m_freem(bf->bf_m); 2322 bf->bf_m = NULL; 2323 } 2324 if (bf->bf_node != NULL) { 2325 ieee80211_free_node(bf->bf_node); 2326 bf->bf_node = NULL; 2327 } 2328 } 2329 } 2330 2331 /* 2332 * Configure the beacon and sleep timers. 2333 * 2334 * When operating as an AP this resets the TSF and sets 2335 * up the hardware to notify us when we need to issue beacons. 2336 * 2337 * When operating in station mode this sets up the beacon 2338 * timers according to the timestamp of the last received 2339 * beacon and the current TSF, configures PCF and DTIM 2340 * handling, programs the sleep registers so the hardware 2341 * will wakeup in time to receive beacons, and configures 2342 * the beacon miss handling so we'll receive a BMISS 2343 * interrupt when we stop seeing beacons from the AP 2344 * we've associated with. 2345 */ 2346 static void 2347 ath_beacon_config(struct ath_softc *sc) 2348 { 2349 #define TSF_TO_TU(_h,_l) \ 2350 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2351 #define FUDGE 2 2352 struct ath_hal *ah = sc->sc_ah; 2353 struct ieee80211com *ic = &sc->sc_ic; 2354 struct ieee80211_node *ni = ic->ic_bss; 2355 u_int32_t nexttbtt, intval, tsftu; 2356 u_int64_t tsf; 2357 2358 /* extract tstamp from last beacon and convert to TU */ 2359 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2360 LE_READ_4(ni->ni_tstamp.data)); 2361 /* NB: the beacon interval is kept internally in TU's */ 2362 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2363 if (nexttbtt == 0) /* e.g. for ap mode */ 2364 nexttbtt = intval; 2365 else if (intval) /* NB: can be 0 for monitor mode */ 2366 nexttbtt = roundup(nexttbtt, intval); 2367 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2368 __func__, nexttbtt, intval, ni->ni_intval); 2369 if (ic->ic_opmode == IEEE80211_M_STA) { 2370 HAL_BEACON_STATE bs; 2371 int dtimperiod, dtimcount; 2372 int cfpperiod, cfpcount; 2373 2374 /* 2375 * Setup dtim and cfp parameters according to 2376 * last beacon we received (which may be none). 2377 */ 2378 dtimperiod = ni->ni_dtim_period; 2379 if (dtimperiod <= 0) /* NB: 0 if not known */ 2380 dtimperiod = 1; 2381 dtimcount = ni->ni_dtim_count; 2382 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2383 dtimcount = 0; /* XXX? */ 2384 cfpperiod = 1; /* NB: no PCF support yet */ 2385 cfpcount = 0; 2386 /* 2387 * Pull nexttbtt forward to reflect the current 2388 * TSF and calculate dtim+cfp state for the result. 2389 */ 2390 tsf = ath_hal_gettsf64(ah); 2391 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2392 do { 2393 nexttbtt += intval; 2394 if (--dtimcount < 0) { 2395 dtimcount = dtimperiod - 1; 2396 if (--cfpcount < 0) 2397 cfpcount = cfpperiod - 1; 2398 } 2399 } while (nexttbtt < tsftu); 2400 memset(&bs, 0, sizeof(bs)); 2401 bs.bs_intval = intval; 2402 bs.bs_nexttbtt = nexttbtt; 2403 bs.bs_dtimperiod = dtimperiod*intval; 2404 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2405 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2406 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2407 bs.bs_cfpmaxduration = 0; 2408 #if 0 2409 /* 2410 * The 802.11 layer records the offset to the DTIM 2411 * bitmap while receiving beacons; use it here to 2412 * enable h/w detection of our AID being marked in 2413 * the bitmap vector (to indicate frames for us are 2414 * pending at the AP). 2415 * XXX do DTIM handling in s/w to WAR old h/w bugs 2416 * XXX enable based on h/w rev for newer chips 2417 */ 2418 bs.bs_timoffset = ni->ni_timoff; 2419 #endif 2420 /* 2421 * Calculate the number of consecutive beacons to miss 2422 * before taking a BMISS interrupt. The configuration 2423 * is specified in ms, so we need to convert that to 2424 * TU's and then calculate based on the beacon interval. 2425 * Note that we clamp the result to at most 10 beacons. 2426 */ 2427 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2428 if (bs.bs_bmissthreshold > 10) 2429 bs.bs_bmissthreshold = 10; 2430 else if (bs.bs_bmissthreshold <= 0) 2431 bs.bs_bmissthreshold = 1; 2432 2433 /* 2434 * Calculate sleep duration. The configuration is 2435 * given in ms. We insure a multiple of the beacon 2436 * period is used. Also, if the sleep duration is 2437 * greater than the DTIM period then it makes senses 2438 * to make it a multiple of that. 2439 * 2440 * XXX fixed at 100ms 2441 */ 2442 bs.bs_sleepduration = 2443 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2444 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2445 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2446 2447 DPRINTF(sc, ATH_DEBUG_BEACON, 2448 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2449 , __func__ 2450 , tsf, tsftu 2451 , bs.bs_intval 2452 , bs.bs_nexttbtt 2453 , bs.bs_dtimperiod 2454 , bs.bs_nextdtim 2455 , bs.bs_bmissthreshold 2456 , bs.bs_sleepduration 2457 , bs.bs_cfpperiod 2458 , bs.bs_cfpmaxduration 2459 , bs.bs_cfpnext 2460 , bs.bs_timoffset 2461 ); 2462 ath_hal_intrset(ah, 0); 2463 ath_hal_beacontimers(ah, &bs); 2464 sc->sc_imask |= HAL_INT_BMISS; 2465 ath_hal_intrset(ah, sc->sc_imask); 2466 } else { 2467 ath_hal_intrset(ah, 0); 2468 if (nexttbtt == intval) 2469 intval |= HAL_BEACON_RESET_TSF; 2470 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2471 /* 2472 * In IBSS mode enable the beacon timers but only 2473 * enable SWBA interrupts if we need to manually 2474 * prepare beacon frames. Otherwise we use a 2475 * self-linked tx descriptor and let the hardware 2476 * deal with things. 2477 */ 2478 intval |= HAL_BEACON_ENA; 2479 if (!sc->sc_hasveol) 2480 sc->sc_imask |= HAL_INT_SWBA; 2481 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2482 /* 2483 * Pull nexttbtt forward to reflect 2484 * the current TSF. 2485 */ 2486 tsf = ath_hal_gettsf64(ah); 2487 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2488 do { 2489 nexttbtt += intval; 2490 } while (nexttbtt < tsftu); 2491 } 2492 ath_beaconq_config(sc); 2493 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2494 /* 2495 * In AP mode we enable the beacon timers and 2496 * SWBA interrupts to prepare beacon frames. 2497 */ 2498 intval |= HAL_BEACON_ENA; 2499 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2500 ath_beaconq_config(sc); 2501 } 2502 ath_hal_beaconinit(ah, nexttbtt, intval); 2503 sc->sc_bmisscount = 0; 2504 ath_hal_intrset(ah, sc->sc_imask); 2505 /* 2506 * When using a self-linked beacon descriptor in 2507 * ibss mode load it once here. 2508 */ 2509 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2510 ath_beacon_proc(sc, 0); 2511 } 2512 sc->sc_syncbeacon = 0; 2513 #undef UNDEF 2514 #undef TSF_TO_TU 2515 } 2516 2517 static int 2518 ath_descdma_setup(struct ath_softc *sc, 2519 struct ath_descdma *dd, ath_bufhead *head, 2520 const char *name, int nbuf, int ndesc) 2521 { 2522 #define DS2PHYS(_dd, _ds) \ 2523 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2524 struct ifnet *ifp = &sc->sc_if; 2525 struct ath_desc *ds; 2526 struct ath_buf *bf; 2527 int i, bsize, error; 2528 2529 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2530 __func__, name, nbuf, ndesc); 2531 2532 dd->dd_name = name; 2533 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2534 2535 /* 2536 * Setup DMA descriptor area. 2537 */ 2538 dd->dd_dmat = sc->sc_dmat; 2539 2540 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2541 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2542 2543 if (error != 0) { 2544 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2545 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2546 goto fail0; 2547 } 2548 2549 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2550 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2551 if (error != 0) { 2552 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2553 nbuf * ndesc, dd->dd_name, error); 2554 goto fail1; 2555 } 2556 2557 /* allocate descriptors */ 2558 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2559 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2560 if (error != 0) { 2561 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2562 "error %u\n", dd->dd_name, error); 2563 goto fail2; 2564 } 2565 2566 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2567 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2568 if (error != 0) { 2569 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2570 dd->dd_name, error); 2571 goto fail3; 2572 } 2573 2574 ds = dd->dd_desc; 2575 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2576 DPRINTF(sc, ATH_DEBUG_RESET, 2577 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2578 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2579 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2580 2581 /* allocate rx buffers */ 2582 bsize = sizeof(struct ath_buf) * nbuf; 2583 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2584 if (bf == NULL) { 2585 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2586 dd->dd_name, bsize); 2587 goto fail4; 2588 } 2589 dd->dd_bufptr = bf; 2590 2591 STAILQ_INIT(head); 2592 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2593 bf->bf_desc = ds; 2594 bf->bf_daddr = DS2PHYS(dd, ds); 2595 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2596 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2597 if (error != 0) { 2598 if_printf(ifp, "unable to create dmamap for %s " 2599 "buffer %u, error %u\n", dd->dd_name, i, error); 2600 ath_descdma_cleanup(sc, dd, head); 2601 return error; 2602 } 2603 STAILQ_INSERT_TAIL(head, bf, bf_list); 2604 } 2605 return 0; 2606 fail4: 2607 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2608 fail3: 2609 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2610 fail2: 2611 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2612 fail1: 2613 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2614 fail0: 2615 memset(dd, 0, sizeof(*dd)); 2616 return error; 2617 #undef DS2PHYS 2618 } 2619 2620 static void 2621 ath_descdma_cleanup(struct ath_softc *sc, 2622 struct ath_descdma *dd, ath_bufhead *head) 2623 { 2624 struct ath_buf *bf; 2625 struct ieee80211_node *ni; 2626 2627 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2628 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2629 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2630 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2631 2632 STAILQ_FOREACH(bf, head, bf_list) { 2633 if (bf->bf_m) { 2634 m_freem(bf->bf_m); 2635 bf->bf_m = NULL; 2636 } 2637 if (bf->bf_dmamap != NULL) { 2638 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2639 bf->bf_dmamap = NULL; 2640 } 2641 ni = bf->bf_node; 2642 bf->bf_node = NULL; 2643 if (ni != NULL) { 2644 /* 2645 * Reclaim node reference. 2646 */ 2647 ieee80211_free_node(ni); 2648 } 2649 } 2650 2651 STAILQ_INIT(head); 2652 free(dd->dd_bufptr, M_ATHDEV); 2653 memset(dd, 0, sizeof(*dd)); 2654 } 2655 2656 static int 2657 ath_desc_alloc(struct ath_softc *sc) 2658 { 2659 int error; 2660 2661 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2662 "rx", ath_rxbuf, 1); 2663 if (error != 0) 2664 return error; 2665 2666 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2667 "tx", ath_txbuf, ATH_TXDESC); 2668 if (error != 0) { 2669 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2670 return error; 2671 } 2672 2673 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2674 "beacon", 1, 1); 2675 if (error != 0) { 2676 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2677 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2678 return error; 2679 } 2680 return 0; 2681 } 2682 2683 static void 2684 ath_desc_free(struct ath_softc *sc) 2685 { 2686 2687 if (sc->sc_bdma.dd_desc_len != 0) 2688 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2689 if (sc->sc_txdma.dd_desc_len != 0) 2690 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2691 if (sc->sc_rxdma.dd_desc_len != 0) 2692 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2693 } 2694 2695 static struct ieee80211_node * 2696 ath_node_alloc(struct ieee80211_node_table *nt) 2697 { 2698 struct ieee80211com *ic = nt->nt_ic; 2699 struct ath_softc *sc = ic->ic_ifp->if_softc; 2700 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2701 struct ath_node *an; 2702 2703 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2704 if (an == NULL) { 2705 /* XXX stat+msg */ 2706 return NULL; 2707 } 2708 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2709 ath_rate_node_init(sc, an); 2710 2711 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2712 return &an->an_node; 2713 } 2714 2715 static void 2716 ath_node_free(struct ieee80211_node *ni) 2717 { 2718 struct ieee80211com *ic = ni->ni_ic; 2719 struct ath_softc *sc = ic->ic_ifp->if_softc; 2720 2721 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2722 2723 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2724 sc->sc_node_free(ni); 2725 } 2726 2727 static u_int8_t 2728 ath_node_getrssi(const struct ieee80211_node *ni) 2729 { 2730 #define HAL_EP_RND(x, mul) \ 2731 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2732 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2733 int32_t rssi; 2734 2735 /* 2736 * When only one frame is received there will be no state in 2737 * avgrssi so fallback on the value recorded by the 802.11 layer. 2738 */ 2739 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2740 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2741 else 2742 rssi = ni->ni_rssi; 2743 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2744 #undef HAL_EP_RND 2745 } 2746 2747 static int 2748 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2749 { 2750 struct ath_hal *ah = sc->sc_ah; 2751 int error; 2752 struct mbuf *m; 2753 struct ath_desc *ds; 2754 2755 m = bf->bf_m; 2756 if (m == NULL) { 2757 /* 2758 * NB: by assigning a page to the rx dma buffer we 2759 * implicitly satisfy the Atheros requirement that 2760 * this buffer be cache-line-aligned and sized to be 2761 * multiple of the cache line size. Not doing this 2762 * causes weird stuff to happen (for the 5210 at least). 2763 */ 2764 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2765 if (m == NULL) { 2766 DPRINTF(sc, ATH_DEBUG_ANY, 2767 "%s: no mbuf/cluster\n", __func__); 2768 sc->sc_stats.ast_rx_nombuf++; 2769 return ENOMEM; 2770 } 2771 bf->bf_m = m; 2772 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2773 2774 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2775 bf->bf_dmamap, m, 2776 BUS_DMA_NOWAIT); 2777 if (error != 0) { 2778 DPRINTF(sc, ATH_DEBUG_ANY, 2779 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2780 __func__, error); 2781 sc->sc_stats.ast_rx_busdma++; 2782 return error; 2783 } 2784 KASSERT(bf->bf_nseg == 1, 2785 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2786 } 2787 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2788 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2789 2790 /* 2791 * Setup descriptors. For receive we always terminate 2792 * the descriptor list with a self-linked entry so we'll 2793 * not get overrun under high load (as can happen with a 2794 * 5212 when ANI processing enables PHY error frames). 2795 * 2796 * To insure the last descriptor is self-linked we create 2797 * each descriptor as self-linked and add it to the end. As 2798 * each additional descriptor is added the previous self-linked 2799 * entry is ``fixed'' naturally. This should be safe even 2800 * if DMA is happening. When processing RX interrupts we 2801 * never remove/process the last, self-linked, entry on the 2802 * descriptor list. This insures the hardware always has 2803 * someplace to write a new frame. 2804 */ 2805 ds = bf->bf_desc; 2806 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2807 ds->ds_data = bf->bf_segs[0].ds_addr; 2808 ds->ds_vdata = mtod(m, void *); /* for radar */ 2809 ath_hal_setuprxdesc(ah, ds 2810 , m->m_len /* buffer size */ 2811 , 0 2812 ); 2813 2814 if (sc->sc_rxlink != NULL) 2815 *sc->sc_rxlink = bf->bf_daddr; 2816 sc->sc_rxlink = &ds->ds_link; 2817 return 0; 2818 } 2819 2820 /* 2821 * Extend 15-bit time stamp from rx descriptor to 2822 * a full 64-bit TSF using the specified TSF. 2823 */ 2824 static inline u_int64_t 2825 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2826 { 2827 if ((tsf & 0x7fff) < rstamp) 2828 tsf -= 0x8000; 2829 return ((tsf &~ 0x7fff) | rstamp); 2830 } 2831 2832 /* 2833 * Intercept management frames to collect beacon rssi data 2834 * and to do ibss merges. 2835 */ 2836 static void 2837 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2838 struct ieee80211_node *ni, 2839 int subtype, int rssi, u_int32_t rstamp) 2840 { 2841 struct ath_softc *sc = ic->ic_ifp->if_softc; 2842 2843 /* 2844 * Call up first so subsequent work can use information 2845 * potentially stored in the node (e.g. for ibss merge). 2846 */ 2847 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2848 switch (subtype) { 2849 case IEEE80211_FC0_SUBTYPE_BEACON: 2850 /* update rssi statistics for use by the hal */ 2851 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2852 if (sc->sc_syncbeacon && 2853 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2854 /* 2855 * Resync beacon timers using the tsf of the beacon 2856 * frame we just received. 2857 */ 2858 ath_beacon_config(sc); 2859 } 2860 /* fall thru... */ 2861 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2862 if (ic->ic_opmode == IEEE80211_M_IBSS && 2863 ic->ic_state == IEEE80211_S_RUN) { 2864 u_int64_t tsf = ath_extend_tsf(rstamp, 2865 ath_hal_gettsf64(sc->sc_ah)); 2866 2867 /* 2868 * Handle ibss merge as needed; check the tsf on the 2869 * frame before attempting the merge. The 802.11 spec 2870 * says the station should change it's bssid to match 2871 * the oldest station with the same ssid, where oldest 2872 * is determined by the tsf. Note that hardware 2873 * reconfiguration happens through callback to 2874 * ath_newstate as the state machine will go from 2875 * RUN -> RUN when this happens. 2876 */ 2877 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2878 DPRINTF(sc, ATH_DEBUG_STATE, 2879 "ibss merge, rstamp %u tsf %ju " 2880 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2881 (uintmax_t)ni->ni_tstamp.tsf); 2882 (void) ieee80211_ibss_merge(ni); 2883 } 2884 } 2885 break; 2886 } 2887 } 2888 2889 /* 2890 * Set the default antenna. 2891 */ 2892 static void 2893 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2894 { 2895 struct ath_hal *ah = sc->sc_ah; 2896 2897 /* XXX block beacon interrupts */ 2898 ath_hal_setdefantenna(ah, antenna); 2899 if (sc->sc_defant != antenna) 2900 sc->sc_stats.ast_ant_defswitch++; 2901 sc->sc_defant = antenna; 2902 sc->sc_rxotherant = 0; 2903 } 2904 2905 static void 2906 ath_rx_proc(void *arg, int npending) 2907 { 2908 #define PA2DESC(_sc, _pa) \ 2909 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2910 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2911 struct ath_softc *sc = arg; 2912 struct ath_buf *bf; 2913 struct ieee80211com *ic = &sc->sc_ic; 2914 struct ifnet *ifp = &sc->sc_if; 2915 struct ath_hal *ah = sc->sc_ah; 2916 struct ath_desc *ds; 2917 struct mbuf *m; 2918 struct ieee80211_node *ni; 2919 struct ath_node *an; 2920 int len, type, ngood; 2921 u_int phyerr; 2922 HAL_STATUS status; 2923 int16_t nf; 2924 u_int64_t tsf; 2925 2926 NET_LOCK_GIANT(); /* XXX */ 2927 2928 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2929 ngood = 0; 2930 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2931 tsf = ath_hal_gettsf64(ah); 2932 do { 2933 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2934 if (bf == NULL) { /* NB: shouldn't happen */ 2935 if_printf(ifp, "%s: no buffer!\n", __func__); 2936 break; 2937 } 2938 ds = bf->bf_desc; 2939 if (ds->ds_link == bf->bf_daddr) { 2940 /* NB: never process the self-linked entry at the end */ 2941 break; 2942 } 2943 m = bf->bf_m; 2944 if (m == NULL) { /* NB: shouldn't happen */ 2945 if_printf(ifp, "%s: no mbuf!\n", __func__); 2946 break; 2947 } 2948 /* XXX sync descriptor memory */ 2949 /* 2950 * Must provide the virtual address of the current 2951 * descriptor, the physical address, and the virtual 2952 * address of the next descriptor in the h/w chain. 2953 * This allows the HAL to look ahead to see if the 2954 * hardware is done with a descriptor by checking the 2955 * done bit in the following descriptor and the address 2956 * of the current descriptor the DMA engine is working 2957 * on. All this is necessary because of our use of 2958 * a self-linked list to avoid rx overruns. 2959 */ 2960 status = ath_hal_rxprocdesc(ah, ds, 2961 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2962 #ifdef AR_DEBUG 2963 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2964 ath_printrxbuf(bf, status == HAL_OK); 2965 #endif 2966 if (status == HAL_EINPROGRESS) 2967 break; 2968 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2969 if (ds->ds_rxstat.rs_more) { 2970 /* 2971 * Frame spans multiple descriptors; this 2972 * cannot happen yet as we don't support 2973 * jumbograms. If not in monitor mode, 2974 * discard the frame. 2975 */ 2976 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2977 sc->sc_stats.ast_rx_toobig++; 2978 goto rx_next; 2979 } 2980 /* fall thru for monitor mode handling... */ 2981 } else if (ds->ds_rxstat.rs_status != 0) { 2982 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2983 sc->sc_stats.ast_rx_crcerr++; 2984 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2985 sc->sc_stats.ast_rx_fifoerr++; 2986 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2987 sc->sc_stats.ast_rx_phyerr++; 2988 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2989 sc->sc_stats.ast_rx_phy[phyerr]++; 2990 goto rx_next; 2991 } 2992 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2993 /* 2994 * Decrypt error. If the error occurred 2995 * because there was no hardware key, then 2996 * let the frame through so the upper layers 2997 * can process it. This is necessary for 5210 2998 * parts which have no way to setup a ``clear'' 2999 * key cache entry. 3000 * 3001 * XXX do key cache faulting 3002 */ 3003 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3004 goto rx_accept; 3005 sc->sc_stats.ast_rx_badcrypt++; 3006 } 3007 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3008 sc->sc_stats.ast_rx_badmic++; 3009 /* 3010 * Do minimal work required to hand off 3011 * the 802.11 header for notifcation. 3012 */ 3013 /* XXX frag's and qos frames */ 3014 len = ds->ds_rxstat.rs_datalen; 3015 if (len >= sizeof (struct ieee80211_frame)) { 3016 bus_dmamap_sync(sc->sc_dmat, 3017 bf->bf_dmamap, 3018 0, bf->bf_dmamap->dm_mapsize, 3019 BUS_DMASYNC_POSTREAD); 3020 ieee80211_notify_michael_failure(ic, 3021 mtod(m, struct ieee80211_frame *), 3022 sc->sc_splitmic ? 3023 ds->ds_rxstat.rs_keyix-32 : 3024 ds->ds_rxstat.rs_keyix 3025 ); 3026 } 3027 } 3028 ifp->if_ierrors++; 3029 /* 3030 * Reject error frames, we normally don't want 3031 * to see them in monitor mode (in monitor mode 3032 * allow through packets that have crypto problems). 3033 */ 3034 if ((ds->ds_rxstat.rs_status &~ 3035 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 3036 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 3037 goto rx_next; 3038 } 3039 rx_accept: 3040 /* 3041 * Sync and unmap the frame. At this point we're 3042 * committed to passing the mbuf somewhere so clear 3043 * bf_m; this means a new sk_buff must be allocated 3044 * when the rx descriptor is setup again to receive 3045 * another frame. 3046 */ 3047 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3048 0, bf->bf_dmamap->dm_mapsize, 3049 BUS_DMASYNC_POSTREAD); 3050 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3051 bf->bf_m = NULL; 3052 3053 m->m_pkthdr.rcvif = ifp; 3054 len = ds->ds_rxstat.rs_datalen; 3055 m->m_pkthdr.len = m->m_len = len; 3056 3057 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3058 3059 #if NBPFILTER > 0 3060 if (sc->sc_drvbpf) { 3061 u_int8_t rix; 3062 3063 /* 3064 * Discard anything shorter than an ack or cts. 3065 */ 3066 if (len < IEEE80211_ACK_LEN) { 3067 DPRINTF(sc, ATH_DEBUG_RECV, 3068 "%s: runt packet %d\n", 3069 __func__, len); 3070 sc->sc_stats.ast_rx_tooshort++; 3071 m_freem(m); 3072 goto rx_next; 3073 } 3074 rix = ds->ds_rxstat.rs_rate; 3075 sc->sc_rx_th.wr_tsf = htole64( 3076 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3077 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3078 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3079 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3080 sc->sc_rx_th.wr_antnoise = nf; 3081 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3082 3083 bpf_mtap2(sc->sc_drvbpf, 3084 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3085 } 3086 #endif 3087 3088 /* 3089 * From this point on we assume the frame is at least 3090 * as large as ieee80211_frame_min; verify that. 3091 */ 3092 if (len < IEEE80211_MIN_LEN) { 3093 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3094 __func__, len); 3095 sc->sc_stats.ast_rx_tooshort++; 3096 m_freem(m); 3097 goto rx_next; 3098 } 3099 3100 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3101 ieee80211_dump_pkt(mtod(m, void *), len, 3102 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3103 ds->ds_rxstat.rs_rssi); 3104 } 3105 3106 m_adj(m, -IEEE80211_CRC_LEN); 3107 3108 /* 3109 * Locate the node for sender, track state, and then 3110 * pass the (referenced) node up to the 802.11 layer 3111 * for its use. 3112 */ 3113 ni = ieee80211_find_rxnode_withkey(ic, 3114 mtod(m, const struct ieee80211_frame_min *), 3115 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3116 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3117 /* 3118 * Track rx rssi and do any rx antenna management. 3119 */ 3120 an = ATH_NODE(ni); 3121 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3122 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3123 /* 3124 * Send frame up for processing. 3125 */ 3126 type = ieee80211_input(ic, m, ni, 3127 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3128 ieee80211_free_node(ni); 3129 if (sc->sc_diversity) { 3130 /* 3131 * When using fast diversity, change the default rx 3132 * antenna if diversity chooses the other antenna 3 3133 * times in a row. 3134 */ 3135 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3136 if (++sc->sc_rxotherant >= 3) 3137 ath_setdefantenna(sc, 3138 ds->ds_rxstat.rs_antenna); 3139 } else 3140 sc->sc_rxotherant = 0; 3141 } 3142 if (sc->sc_softled) { 3143 /* 3144 * Blink for any data frame. Otherwise do a 3145 * heartbeat-style blink when idle. The latter 3146 * is mainly for station mode where we depend on 3147 * periodic beacon frames to trigger the poll event. 3148 */ 3149 if (type == IEEE80211_FC0_TYPE_DATA) { 3150 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3151 ath_led_event(sc, ATH_LED_RX); 3152 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3153 ath_led_event(sc, ATH_LED_POLL); 3154 } 3155 /* 3156 * Arrange to update the last rx timestamp only for 3157 * frames from our ap when operating in station mode. 3158 * This assumes the rx key is always setup when associated. 3159 */ 3160 if (ic->ic_opmode == IEEE80211_M_STA && 3161 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3162 ngood++; 3163 rx_next: 3164 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3165 } while (ath_rxbuf_init(sc, bf) == 0); 3166 3167 /* rx signal state monitoring */ 3168 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3169 if (ath_hal_radar_event(ah)) 3170 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3171 if (ngood) 3172 sc->sc_lastrx = tsf; 3173 3174 #ifdef __NetBSD__ 3175 /* XXX Why isn't this necessary in FreeBSD? */ 3176 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3177 ath_start(ifp); 3178 #endif /* __NetBSD__ */ 3179 3180 NET_UNLOCK_GIANT(); /* XXX */ 3181 #undef PA2DESC 3182 } 3183 3184 /* 3185 * Setup a h/w transmit queue. 3186 */ 3187 static struct ath_txq * 3188 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3189 { 3190 #define N(a) (sizeof(a)/sizeof(a[0])) 3191 struct ath_hal *ah = sc->sc_ah; 3192 HAL_TXQ_INFO qi; 3193 int qnum; 3194 3195 memset(&qi, 0, sizeof(qi)); 3196 qi.tqi_subtype = subtype; 3197 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3198 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3199 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3200 /* 3201 * Enable interrupts only for EOL and DESC conditions. 3202 * We mark tx descriptors to receive a DESC interrupt 3203 * when a tx queue gets deep; otherwise waiting for the 3204 * EOL to reap descriptors. Note that this is done to 3205 * reduce interrupt load and this only defers reaping 3206 * descriptors, never transmitting frames. Aside from 3207 * reducing interrupts this also permits more concurrency. 3208 * The only potential downside is if the tx queue backs 3209 * up in which case the top half of the kernel may backup 3210 * due to a lack of tx descriptors. 3211 */ 3212 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3213 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3214 if (qnum == -1) { 3215 /* 3216 * NB: don't print a message, this happens 3217 * normally on parts with too few tx queues 3218 */ 3219 return NULL; 3220 } 3221 if (qnum >= N(sc->sc_txq)) { 3222 device_printf(&sc->sc_dev, 3223 "hal qnum %u out of range, max %zu!\n", 3224 qnum, N(sc->sc_txq)); 3225 ath_hal_releasetxqueue(ah, qnum); 3226 return NULL; 3227 } 3228 if (!ATH_TXQ_SETUP(sc, qnum)) { 3229 struct ath_txq *txq = &sc->sc_txq[qnum]; 3230 3231 txq->axq_qnum = qnum; 3232 txq->axq_depth = 0; 3233 txq->axq_intrcnt = 0; 3234 txq->axq_link = NULL; 3235 STAILQ_INIT(&txq->axq_q); 3236 ATH_TXQ_LOCK_INIT(sc, txq); 3237 sc->sc_txqsetup |= 1<<qnum; 3238 } 3239 return &sc->sc_txq[qnum]; 3240 #undef N 3241 } 3242 3243 /* 3244 * Setup a hardware data transmit queue for the specified 3245 * access control. The hal may not support all requested 3246 * queues in which case it will return a reference to a 3247 * previously setup queue. We record the mapping from ac's 3248 * to h/w queues for use by ath_tx_start and also track 3249 * the set of h/w queues being used to optimize work in the 3250 * transmit interrupt handler and related routines. 3251 */ 3252 static int 3253 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3254 { 3255 #define N(a) (sizeof(a)/sizeof(a[0])) 3256 struct ath_txq *txq; 3257 3258 if (ac >= N(sc->sc_ac2q)) { 3259 device_printf(&sc->sc_dev, "AC %u out of range, max %zu!\n", 3260 ac, N(sc->sc_ac2q)); 3261 return 0; 3262 } 3263 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3264 if (txq != NULL) { 3265 sc->sc_ac2q[ac] = txq; 3266 return 1; 3267 } else 3268 return 0; 3269 #undef N 3270 } 3271 3272 /* 3273 * Update WME parameters for a transmit queue. 3274 */ 3275 static int 3276 ath_txq_update(struct ath_softc *sc, int ac) 3277 { 3278 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3279 #define ATH_TXOP_TO_US(v) (v<<5) 3280 struct ieee80211com *ic = &sc->sc_ic; 3281 struct ath_txq *txq = sc->sc_ac2q[ac]; 3282 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3283 struct ath_hal *ah = sc->sc_ah; 3284 HAL_TXQ_INFO qi; 3285 3286 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3287 qi.tqi_aifs = wmep->wmep_aifsn; 3288 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3289 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3290 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3291 3292 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3293 device_printf(&sc->sc_dev, "unable to update hardware queue " 3294 "parameters for %s traffic!\n", 3295 ieee80211_wme_acnames[ac]); 3296 return 0; 3297 } else { 3298 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3299 return 1; 3300 } 3301 #undef ATH_TXOP_TO_US 3302 #undef ATH_EXPONENT_TO_VALUE 3303 } 3304 3305 /* 3306 * Callback from the 802.11 layer to update WME parameters. 3307 */ 3308 static int 3309 ath_wme_update(struct ieee80211com *ic) 3310 { 3311 struct ath_softc *sc = ic->ic_ifp->if_softc; 3312 3313 return !ath_txq_update(sc, WME_AC_BE) || 3314 !ath_txq_update(sc, WME_AC_BK) || 3315 !ath_txq_update(sc, WME_AC_VI) || 3316 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3317 } 3318 3319 /* 3320 * Reclaim resources for a setup queue. 3321 */ 3322 static void 3323 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3324 { 3325 3326 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3327 ATH_TXQ_LOCK_DESTROY(txq); 3328 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3329 } 3330 3331 /* 3332 * Reclaim all tx queue resources. 3333 */ 3334 static void 3335 ath_tx_cleanup(struct ath_softc *sc) 3336 { 3337 int i; 3338 3339 ATH_TXBUF_LOCK_DESTROY(sc); 3340 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3341 if (ATH_TXQ_SETUP(sc, i)) 3342 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3343 } 3344 3345 /* 3346 * Defragment an mbuf chain, returning at most maxfrags separate 3347 * mbufs+clusters. If this is not possible NULL is returned and 3348 * the original mbuf chain is left in it's present (potentially 3349 * modified) state. We use two techniques: collapsing consecutive 3350 * mbufs and replacing consecutive mbufs by a cluster. 3351 */ 3352 static struct mbuf * 3353 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3354 { 3355 struct mbuf *m, *n, *n2, **prev; 3356 u_int curfrags; 3357 3358 /* 3359 * Calculate the current number of frags. 3360 */ 3361 curfrags = 0; 3362 for (m = m0; m != NULL; m = m->m_next) 3363 curfrags++; 3364 /* 3365 * First, try to collapse mbufs. Note that we always collapse 3366 * towards the front so we don't need to deal with moving the 3367 * pkthdr. This may be suboptimal if the first mbuf has much 3368 * less data than the following. 3369 */ 3370 m = m0; 3371 again: 3372 for (;;) { 3373 n = m->m_next; 3374 if (n == NULL) 3375 break; 3376 if (n->m_len < M_TRAILINGSPACE(m)) { 3377 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3378 n->m_len); 3379 m->m_len += n->m_len; 3380 m->m_next = n->m_next; 3381 m_free(n); 3382 if (--curfrags <= maxfrags) 3383 return m0; 3384 } else 3385 m = n; 3386 } 3387 KASSERT(maxfrags > 1, 3388 ("maxfrags %u, but normal collapse failed", maxfrags)); 3389 /* 3390 * Collapse consecutive mbufs to a cluster. 3391 */ 3392 prev = &m0->m_next; /* NB: not the first mbuf */ 3393 while ((n = *prev) != NULL) { 3394 if ((n2 = n->m_next) != NULL && 3395 n->m_len + n2->m_len < MCLBYTES) { 3396 m = m_getcl(how, MT_DATA, 0); 3397 if (m == NULL) 3398 goto bad; 3399 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3400 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3401 n2->m_len); 3402 m->m_len = n->m_len + n2->m_len; 3403 m->m_next = n2->m_next; 3404 *prev = m; 3405 m_free(n); 3406 m_free(n2); 3407 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3408 return m0; 3409 /* 3410 * Still not there, try the normal collapse 3411 * again before we allocate another cluster. 3412 */ 3413 goto again; 3414 } 3415 prev = &n->m_next; 3416 } 3417 /* 3418 * No place where we can collapse to a cluster; punt. 3419 * This can occur if, for example, you request 2 frags 3420 * but the packet requires that both be clusters (we 3421 * never reallocate the first mbuf to avoid moving the 3422 * packet header). 3423 */ 3424 bad: 3425 return NULL; 3426 } 3427 3428 /* 3429 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3430 */ 3431 static int 3432 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3433 { 3434 int i; 3435 3436 for (i = 0; i < rt->rateCount; i++) 3437 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3438 return i; 3439 return 0; /* NB: lowest rate */ 3440 } 3441 3442 static void 3443 ath_freetx(struct mbuf *m) 3444 { 3445 struct mbuf *next; 3446 3447 do { 3448 next = m->m_nextpkt; 3449 m->m_nextpkt = NULL; 3450 m_freem(m); 3451 } while ((m = next) != NULL); 3452 } 3453 3454 static int 3455 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3456 struct mbuf *m0) 3457 { 3458 struct ieee80211com *ic = &sc->sc_ic; 3459 struct ath_hal *ah = sc->sc_ah; 3460 struct ifnet *ifp = &sc->sc_if; 3461 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3462 int i, error, iswep, ismcast, isfrag, ismrr; 3463 int keyix, hdrlen, pktlen, try0; 3464 u_int8_t rix, txrate, ctsrate; 3465 u_int8_t cix = 0xff; /* NB: silence compiler */ 3466 struct ath_desc *ds, *ds0; 3467 struct ath_txq *txq; 3468 struct ieee80211_frame *wh; 3469 u_int subtype, flags, ctsduration; 3470 HAL_PKT_TYPE atype; 3471 const HAL_RATE_TABLE *rt; 3472 HAL_BOOL shortPreamble; 3473 struct ath_node *an; 3474 struct mbuf *m; 3475 u_int pri; 3476 3477 wh = mtod(m0, struct ieee80211_frame *); 3478 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3479 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3480 isfrag = m0->m_flags & M_FRAG; 3481 hdrlen = ieee80211_anyhdrsize(wh); 3482 /* 3483 * Packet length must not include any 3484 * pad bytes; deduct them here. 3485 */ 3486 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3487 3488 if (iswep) { 3489 const struct ieee80211_cipher *cip; 3490 struct ieee80211_key *k; 3491 3492 /* 3493 * Construct the 802.11 header+trailer for an encrypted 3494 * frame. The only reason this can fail is because of an 3495 * unknown or unsupported cipher/key type. 3496 */ 3497 k = ieee80211_crypto_encap(ic, ni, m0); 3498 if (k == NULL) { 3499 /* 3500 * This can happen when the key is yanked after the 3501 * frame was queued. Just discard the frame; the 3502 * 802.11 layer counts failures and provides 3503 * debugging/diagnostics. 3504 */ 3505 ath_freetx(m0); 3506 return EIO; 3507 } 3508 /* 3509 * Adjust the packet + header lengths for the crypto 3510 * additions and calculate the h/w key index. When 3511 * a s/w mic is done the frame will have had any mic 3512 * added to it prior to entry so m0->m_pkthdr.len above will 3513 * account for it. Otherwise we need to add it to the 3514 * packet length. 3515 */ 3516 cip = k->wk_cipher; 3517 hdrlen += cip->ic_header; 3518 pktlen += cip->ic_header + cip->ic_trailer; 3519 /* NB: frags always have any TKIP MIC done in s/w */ 3520 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3521 pktlen += cip->ic_miclen; 3522 keyix = k->wk_keyix; 3523 3524 /* packet header may have moved, reset our local pointer */ 3525 wh = mtod(m0, struct ieee80211_frame *); 3526 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3527 /* 3528 * Use station key cache slot, if assigned. 3529 */ 3530 keyix = ni->ni_ucastkey.wk_keyix; 3531 if (keyix == IEEE80211_KEYIX_NONE) 3532 keyix = HAL_TXKEYIX_INVALID; 3533 } else 3534 keyix = HAL_TXKEYIX_INVALID; 3535 3536 pktlen += IEEE80211_CRC_LEN; 3537 3538 /* 3539 * Load the DMA map so any coalescing is done. This 3540 * also calculates the number of descriptors we need. 3541 */ 3542 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3543 BUS_DMA_NOWAIT); 3544 if (error == EFBIG) { 3545 /* XXX packet requires too many descriptors */ 3546 bf->bf_nseg = ATH_TXDESC+1; 3547 } else if (error != 0) { 3548 sc->sc_stats.ast_tx_busdma++; 3549 ath_freetx(m0); 3550 return error; 3551 } 3552 /* 3553 * Discard null packets and check for packets that 3554 * require too many TX descriptors. We try to convert 3555 * the latter to a cluster. 3556 */ 3557 if (error == EFBIG) { /* too many desc's, linearize */ 3558 sc->sc_stats.ast_tx_linear++; 3559 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3560 if (m == NULL) { 3561 ath_freetx(m0); 3562 sc->sc_stats.ast_tx_nombuf++; 3563 return ENOMEM; 3564 } 3565 m0 = m; 3566 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3567 BUS_DMA_NOWAIT); 3568 if (error != 0) { 3569 sc->sc_stats.ast_tx_busdma++; 3570 ath_freetx(m0); 3571 return error; 3572 } 3573 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3574 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3575 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3576 sc->sc_stats.ast_tx_nodata++; 3577 ath_freetx(m0); 3578 return EIO; 3579 } 3580 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3581 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3582 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3583 bf->bf_m = m0; 3584 bf->bf_node = ni; /* NB: held reference */ 3585 3586 /* setup descriptors */ 3587 ds = bf->bf_desc; 3588 rt = sc->sc_currates; 3589 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3590 3591 /* 3592 * NB: the 802.11 layer marks whether or not we should 3593 * use short preamble based on the current mode and 3594 * negotiated parameters. 3595 */ 3596 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3597 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3598 shortPreamble = AH_TRUE; 3599 sc->sc_stats.ast_tx_shortpre++; 3600 } else { 3601 shortPreamble = AH_FALSE; 3602 } 3603 3604 an = ATH_NODE(ni); 3605 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3606 ismrr = 0; /* default no multi-rate retry*/ 3607 /* 3608 * Calculate Atheros packet type from IEEE80211 packet header, 3609 * setup for rate calculations, and select h/w transmit queue. 3610 */ 3611 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3612 case IEEE80211_FC0_TYPE_MGT: 3613 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3614 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3615 atype = HAL_PKT_TYPE_BEACON; 3616 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3617 atype = HAL_PKT_TYPE_PROBE_RESP; 3618 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3619 atype = HAL_PKT_TYPE_ATIM; 3620 else 3621 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3622 rix = sc->sc_minrateix; 3623 txrate = rt->info[rix].rateCode; 3624 if (shortPreamble) 3625 txrate |= rt->info[rix].shortPreamble; 3626 try0 = ATH_TXMGTTRY; 3627 /* NB: force all management frames to highest queue */ 3628 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3629 /* NB: force all management frames to highest queue */ 3630 pri = WME_AC_VO; 3631 } else 3632 pri = WME_AC_BE; 3633 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3634 break; 3635 case IEEE80211_FC0_TYPE_CTL: 3636 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3637 rix = sc->sc_minrateix; 3638 txrate = rt->info[rix].rateCode; 3639 if (shortPreamble) 3640 txrate |= rt->info[rix].shortPreamble; 3641 try0 = ATH_TXMGTTRY; 3642 /* NB: force all ctl frames to highest queue */ 3643 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3644 /* NB: force all ctl frames to highest queue */ 3645 pri = WME_AC_VO; 3646 } else 3647 pri = WME_AC_BE; 3648 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3649 break; 3650 case IEEE80211_FC0_TYPE_DATA: 3651 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3652 /* 3653 * Data frames: multicast frames go out at a fixed rate, 3654 * otherwise consult the rate control module for the 3655 * rate to use. 3656 */ 3657 if (ismcast) { 3658 /* 3659 * Check mcast rate setting in case it's changed. 3660 * XXX move out of fastpath 3661 */ 3662 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3663 sc->sc_mcastrix = 3664 ath_tx_findrix(rt, ic->ic_mcast_rate); 3665 sc->sc_mcastrate = ic->ic_mcast_rate; 3666 } 3667 rix = sc->sc_mcastrix; 3668 txrate = rt->info[rix].rateCode; 3669 try0 = 1; 3670 } else { 3671 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3672 &rix, &try0, &txrate); 3673 sc->sc_txrate = txrate; /* for LED blinking */ 3674 if (try0 != ATH_TXMAXTRY) 3675 ismrr = 1; 3676 } 3677 pri = M_WME_GETAC(m0); 3678 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3679 flags |= HAL_TXDESC_NOACK; 3680 break; 3681 default: 3682 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3683 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3684 /* XXX statistic */ 3685 ath_freetx(m0); 3686 return EIO; 3687 } 3688 txq = sc->sc_ac2q[pri]; 3689 3690 /* 3691 * When servicing one or more stations in power-save mode 3692 * multicast frames must be buffered until after the beacon. 3693 * We use the CAB queue for that. 3694 */ 3695 if (ismcast && ic->ic_ps_sta) { 3696 txq = sc->sc_cabq; 3697 /* XXX? more bit in 802.11 frame header */ 3698 } 3699 3700 /* 3701 * Calculate miscellaneous flags. 3702 */ 3703 if (ismcast) { 3704 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3705 } else if (pktlen > ic->ic_rtsthreshold) { 3706 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3707 cix = rt->info[rix].controlRate; 3708 sc->sc_stats.ast_tx_rts++; 3709 } 3710 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3711 sc->sc_stats.ast_tx_noack++; 3712 3713 /* 3714 * If 802.11g protection is enabled, determine whether 3715 * to use RTS/CTS or just CTS. Note that this is only 3716 * done for OFDM unicast frames. 3717 */ 3718 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3719 rt->info[rix].phy == IEEE80211_T_OFDM && 3720 (flags & HAL_TXDESC_NOACK) == 0) { 3721 /* XXX fragments must use CCK rates w/ protection */ 3722 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3723 flags |= HAL_TXDESC_RTSENA; 3724 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3725 flags |= HAL_TXDESC_CTSENA; 3726 if (isfrag) { 3727 /* 3728 * For frags it would be desirable to use the 3729 * highest CCK rate for RTS/CTS. But stations 3730 * farther away may detect it at a lower CCK rate 3731 * so use the configured protection rate instead 3732 * (for now). 3733 */ 3734 cix = rt->info[sc->sc_protrix].controlRate; 3735 } else 3736 cix = rt->info[sc->sc_protrix].controlRate; 3737 sc->sc_stats.ast_tx_protect++; 3738 } 3739 3740 /* 3741 * Calculate duration. This logically belongs in the 802.11 3742 * layer but it lacks sufficient information to calculate it. 3743 */ 3744 if ((flags & HAL_TXDESC_NOACK) == 0 && 3745 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3746 u_int16_t dur; 3747 /* 3748 * XXX not right with fragmentation. 3749 */ 3750 if (shortPreamble) 3751 dur = rt->info[rix].spAckDuration; 3752 else 3753 dur = rt->info[rix].lpAckDuration; 3754 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3755 dur += dur; /* additional SIFS+ACK */ 3756 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3757 /* 3758 * Include the size of next fragment so NAV is 3759 * updated properly. The last fragment uses only 3760 * the ACK duration 3761 */ 3762 dur += ath_hal_computetxtime(ah, rt, 3763 m0->m_nextpkt->m_pkthdr.len, 3764 rix, shortPreamble); 3765 } 3766 if (isfrag) { 3767 /* 3768 * Force hardware to use computed duration for next 3769 * fragment by disabling multi-rate retry which updates 3770 * duration based on the multi-rate duration table. 3771 */ 3772 try0 = ATH_TXMAXTRY; 3773 } 3774 *(u_int16_t *)wh->i_dur = htole16(dur); 3775 } 3776 3777 /* 3778 * Calculate RTS/CTS rate and duration if needed. 3779 */ 3780 ctsduration = 0; 3781 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3782 /* 3783 * CTS transmit rate is derived from the transmit rate 3784 * by looking in the h/w rate table. We must also factor 3785 * in whether or not a short preamble is to be used. 3786 */ 3787 /* NB: cix is set above where RTS/CTS is enabled */ 3788 KASSERT(cix != 0xff, ("cix not setup")); 3789 ctsrate = rt->info[cix].rateCode; 3790 /* 3791 * Compute the transmit duration based on the frame 3792 * size and the size of an ACK frame. We call into the 3793 * HAL to do the computation since it depends on the 3794 * characteristics of the actual PHY being used. 3795 * 3796 * NB: CTS is assumed the same size as an ACK so we can 3797 * use the precalculated ACK durations. 3798 */ 3799 if (shortPreamble) { 3800 ctsrate |= rt->info[cix].shortPreamble; 3801 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3802 ctsduration += rt->info[cix].spAckDuration; 3803 ctsduration += ath_hal_computetxtime(ah, 3804 rt, pktlen, rix, AH_TRUE); 3805 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3806 ctsduration += rt->info[rix].spAckDuration; 3807 } else { 3808 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3809 ctsduration += rt->info[cix].lpAckDuration; 3810 ctsduration += ath_hal_computetxtime(ah, 3811 rt, pktlen, rix, AH_FALSE); 3812 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3813 ctsduration += rt->info[rix].lpAckDuration; 3814 } 3815 /* 3816 * Must disable multi-rate retry when using RTS/CTS. 3817 */ 3818 ismrr = 0; 3819 try0 = ATH_TXMGTTRY; /* XXX */ 3820 } else 3821 ctsrate = 0; 3822 3823 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3824 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3825 sc->sc_hwmap[txrate].ieeerate, -1); 3826 #if NBPFILTER > 0 3827 if (ic->ic_rawbpf) 3828 bpf_mtap(ic->ic_rawbpf, m0); 3829 if (sc->sc_drvbpf) { 3830 u_int64_t tsf = ath_hal_gettsf64(ah); 3831 3832 sc->sc_tx_th.wt_tsf = htole64(tsf); 3833 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3834 if (iswep) 3835 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3836 if (isfrag) 3837 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3838 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3839 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3840 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3841 3842 bpf_mtap2(sc->sc_drvbpf, 3843 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3844 } 3845 #endif 3846 3847 /* 3848 * Determine if a tx interrupt should be generated for 3849 * this descriptor. We take a tx interrupt to reap 3850 * descriptors when the h/w hits an EOL condition or 3851 * when the descriptor is specifically marked to generate 3852 * an interrupt. We periodically mark descriptors in this 3853 * way to insure timely replenishing of the supply needed 3854 * for sending frames. Defering interrupts reduces system 3855 * load and potentially allows more concurrent work to be 3856 * done but if done to aggressively can cause senders to 3857 * backup. 3858 * 3859 * NB: use >= to deal with sc_txintrperiod changing 3860 * dynamically through sysctl. 3861 */ 3862 if (flags & HAL_TXDESC_INTREQ) { 3863 txq->axq_intrcnt = 0; 3864 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3865 flags |= HAL_TXDESC_INTREQ; 3866 txq->axq_intrcnt = 0; 3867 } 3868 3869 /* 3870 * Formulate first tx descriptor with tx controls. 3871 */ 3872 /* XXX check return value? */ 3873 ath_hal_setuptxdesc(ah, ds 3874 , pktlen /* packet length */ 3875 , hdrlen /* header length */ 3876 , atype /* Atheros packet type */ 3877 , ni->ni_txpower /* txpower */ 3878 , txrate, try0 /* series 0 rate/tries */ 3879 , keyix /* key cache index */ 3880 , sc->sc_txantenna /* antenna mode */ 3881 , flags /* flags */ 3882 , ctsrate /* rts/cts rate */ 3883 , ctsduration /* rts/cts duration */ 3884 ); 3885 bf->bf_flags = flags; 3886 /* 3887 * Setup the multi-rate retry state only when we're 3888 * going to use it. This assumes ath_hal_setuptxdesc 3889 * initializes the descriptors (so we don't have to) 3890 * when the hardware supports multi-rate retry and 3891 * we don't use it. 3892 */ 3893 if (ismrr) 3894 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3895 3896 /* 3897 * Fillin the remainder of the descriptor info. 3898 */ 3899 ds0 = ds; 3900 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3901 ds->ds_data = bf->bf_segs[i].ds_addr; 3902 if (i == bf->bf_nseg - 1) 3903 ds->ds_link = 0; 3904 else 3905 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3906 ath_hal_filltxdesc(ah, ds 3907 , bf->bf_segs[i].ds_len /* segment length */ 3908 , i == 0 /* first segment */ 3909 , i == bf->bf_nseg - 1 /* last segment */ 3910 , ds0 /* first descriptor */ 3911 ); 3912 3913 /* NB: The desc swap function becomes void, 3914 * if descriptor swapping is not enabled 3915 */ 3916 ath_desc_swap(ds); 3917 3918 DPRINTF(sc, ATH_DEBUG_XMIT, 3919 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3920 __func__, i, ds->ds_link, ds->ds_data, 3921 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3922 } 3923 /* 3924 * Insert the frame on the outbound list and 3925 * pass it on to the hardware. 3926 */ 3927 ATH_TXQ_LOCK(txq); 3928 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3929 if (txq->axq_link == NULL) { 3930 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3931 DPRINTF(sc, ATH_DEBUG_XMIT, 3932 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3933 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3934 txq->axq_depth); 3935 } else { 3936 *txq->axq_link = HTOAH32(bf->bf_daddr); 3937 DPRINTF(sc, ATH_DEBUG_XMIT, 3938 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3939 __func__, txq->axq_qnum, txq->axq_link, 3940 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3941 } 3942 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3943 /* 3944 * The CAB queue is started from the SWBA handler since 3945 * frames only go out on DTIM and to avoid possible races. 3946 */ 3947 if (txq != sc->sc_cabq) 3948 ath_hal_txstart(ah, txq->axq_qnum); 3949 ATH_TXQ_UNLOCK(txq); 3950 3951 return 0; 3952 } 3953 3954 /* 3955 * Process completed xmit descriptors from the specified queue. 3956 */ 3957 static int 3958 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3959 { 3960 struct ath_hal *ah = sc->sc_ah; 3961 struct ieee80211com *ic = &sc->sc_ic; 3962 struct ath_buf *bf; 3963 struct ath_desc *ds, *ds0; 3964 struct ieee80211_node *ni; 3965 struct ath_node *an; 3966 int sr, lr, pri, nacked; 3967 HAL_STATUS status; 3968 3969 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3970 __func__, txq->axq_qnum, 3971 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3972 txq->axq_link); 3973 nacked = 0; 3974 for (;;) { 3975 ATH_TXQ_LOCK(txq); 3976 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3977 bf = STAILQ_FIRST(&txq->axq_q); 3978 if (bf == NULL) { 3979 txq->axq_link = NULL; 3980 ATH_TXQ_UNLOCK(txq); 3981 break; 3982 } 3983 ds0 = &bf->bf_desc[0]; 3984 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3985 status = ath_hal_txprocdesc(ah, ds); 3986 #ifdef AR_DEBUG 3987 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3988 ath_printtxbuf(bf, status == HAL_OK); 3989 #endif 3990 if (status == HAL_EINPROGRESS) { 3991 ATH_TXQ_UNLOCK(txq); 3992 break; 3993 } 3994 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3995 ATH_TXQ_UNLOCK(txq); 3996 3997 ni = bf->bf_node; 3998 if (ni != NULL) { 3999 an = ATH_NODE(ni); 4000 if (ds->ds_txstat.ts_status == 0) { 4001 u_int8_t txant = ds->ds_txstat.ts_antenna; 4002 sc->sc_stats.ast_ant_tx[txant]++; 4003 sc->sc_ant_tx[txant]++; 4004 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4005 sc->sc_stats.ast_tx_altrate++; 4006 sc->sc_stats.ast_tx_rssi = 4007 ds->ds_txstat.ts_rssi; 4008 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4009 ds->ds_txstat.ts_rssi); 4010 pri = M_WME_GETAC(bf->bf_m); 4011 if (pri >= WME_AC_VO) 4012 ic->ic_wme.wme_hipri_traffic++; 4013 ni->ni_inact = ni->ni_inact_reload; 4014 } else { 4015 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4016 sc->sc_stats.ast_tx_xretries++; 4017 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4018 sc->sc_stats.ast_tx_fifoerr++; 4019 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4020 sc->sc_stats.ast_tx_filtered++; 4021 } 4022 sr = ds->ds_txstat.ts_shortretry; 4023 lr = ds->ds_txstat.ts_longretry; 4024 sc->sc_stats.ast_tx_shortretry += sr; 4025 sc->sc_stats.ast_tx_longretry += lr; 4026 /* 4027 * Hand the descriptor to the rate control algorithm. 4028 */ 4029 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4030 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4031 /* 4032 * If frame was ack'd update the last rx time 4033 * used to workaround phantom bmiss interrupts. 4034 */ 4035 if (ds->ds_txstat.ts_status == 0) 4036 nacked++; 4037 ath_rate_tx_complete(sc, an, ds, ds0); 4038 } 4039 /* 4040 * Reclaim reference to node. 4041 * 4042 * NB: the node may be reclaimed here if, for example 4043 * this is a DEAUTH message that was sent and the 4044 * node was timed out due to inactivity. 4045 */ 4046 ieee80211_free_node(ni); 4047 } 4048 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4049 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4050 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4051 m_freem(bf->bf_m); 4052 bf->bf_m = NULL; 4053 bf->bf_node = NULL; 4054 4055 ATH_TXBUF_LOCK(sc); 4056 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4057 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4058 ATH_TXBUF_UNLOCK(sc); 4059 } 4060 return nacked; 4061 } 4062 4063 static inline int 4064 txqactive(struct ath_hal *ah, int qnum) 4065 { 4066 u_int32_t txqs = 1<<qnum; 4067 ath_hal_gettxintrtxqs(ah, &txqs); 4068 return (txqs & (1<<qnum)); 4069 } 4070 4071 /* 4072 * Deferred processing of transmit interrupt; special-cased 4073 * for a single hardware transmit queue (e.g. 5210 and 5211). 4074 */ 4075 static void 4076 ath_tx_proc_q0(void *arg, int npending) 4077 { 4078 struct ath_softc *sc = arg; 4079 struct ifnet *ifp = &sc->sc_if; 4080 4081 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4082 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4083 } 4084 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4085 ath_tx_processq(sc, sc->sc_cabq); 4086 4087 if (sc->sc_softled) 4088 ath_led_event(sc, ATH_LED_TX); 4089 4090 ath_start(ifp); 4091 } 4092 4093 /* 4094 * Deferred processing of transmit interrupt; special-cased 4095 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4096 */ 4097 static void 4098 ath_tx_proc_q0123(void *arg, int npending) 4099 { 4100 struct ath_softc *sc = arg; 4101 struct ifnet *ifp = &sc->sc_if; 4102 int nacked; 4103 4104 /* 4105 * Process each active queue. 4106 */ 4107 nacked = 0; 4108 if (txqactive(sc->sc_ah, 0)) 4109 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4110 if (txqactive(sc->sc_ah, 1)) 4111 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4112 if (txqactive(sc->sc_ah, 2)) 4113 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4114 if (txqactive(sc->sc_ah, 3)) 4115 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4116 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4117 ath_tx_processq(sc, sc->sc_cabq); 4118 if (nacked) { 4119 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4120 } 4121 4122 if (sc->sc_softled) 4123 ath_led_event(sc, ATH_LED_TX); 4124 4125 ath_start(ifp); 4126 } 4127 4128 /* 4129 * Deferred processing of transmit interrupt. 4130 */ 4131 static void 4132 ath_tx_proc(void *arg, int npending) 4133 { 4134 struct ath_softc *sc = arg; 4135 struct ifnet *ifp = &sc->sc_if; 4136 int i, nacked; 4137 4138 /* 4139 * Process each active queue. 4140 */ 4141 nacked = 0; 4142 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4143 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4144 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4145 if (nacked) { 4146 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4147 } 4148 4149 if (sc->sc_softled) 4150 ath_led_event(sc, ATH_LED_TX); 4151 4152 ath_start(ifp); 4153 } 4154 4155 static void 4156 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4157 { 4158 struct ath_hal *ah = sc->sc_ah; 4159 struct ieee80211_node *ni; 4160 struct ath_buf *bf; 4161 4162 /* 4163 * NB: this assumes output has been stopped and 4164 * we do not need to block ath_tx_tasklet 4165 */ 4166 for (;;) { 4167 ATH_TXQ_LOCK(txq); 4168 bf = STAILQ_FIRST(&txq->axq_q); 4169 if (bf == NULL) { 4170 txq->axq_link = NULL; 4171 ATH_TXQ_UNLOCK(txq); 4172 break; 4173 } 4174 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4175 ATH_TXQ_UNLOCK(txq); 4176 #ifdef AR_DEBUG 4177 if (sc->sc_debug & ATH_DEBUG_RESET) 4178 ath_printtxbuf(bf, 4179 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4180 #endif /* AR_DEBUG */ 4181 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4182 m_freem(bf->bf_m); 4183 bf->bf_m = NULL; 4184 ni = bf->bf_node; 4185 bf->bf_node = NULL; 4186 if (ni != NULL) { 4187 /* 4188 * Reclaim node reference. 4189 */ 4190 ieee80211_free_node(ni); 4191 } 4192 ATH_TXBUF_LOCK(sc); 4193 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4194 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4195 ATH_TXBUF_UNLOCK(sc); 4196 } 4197 } 4198 4199 static void 4200 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4201 { 4202 struct ath_hal *ah = sc->sc_ah; 4203 4204 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4205 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4206 __func__, txq->axq_qnum, 4207 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4208 txq->axq_link); 4209 } 4210 4211 /* 4212 * Drain the transmit queues and reclaim resources. 4213 */ 4214 static void 4215 ath_draintxq(struct ath_softc *sc) 4216 { 4217 struct ath_hal *ah = sc->sc_ah; 4218 int i; 4219 4220 /* XXX return value */ 4221 if (!sc->sc_invalid) { 4222 /* don't touch the hardware if marked invalid */ 4223 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4224 DPRINTF(sc, ATH_DEBUG_RESET, 4225 "%s: beacon queue %p\n", __func__, 4226 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4227 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4228 if (ATH_TXQ_SETUP(sc, i)) 4229 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4230 } 4231 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4232 if (ATH_TXQ_SETUP(sc, i)) 4233 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4234 } 4235 4236 /* 4237 * Disable the receive h/w in preparation for a reset. 4238 */ 4239 static void 4240 ath_stoprecv(struct ath_softc *sc) 4241 { 4242 #define PA2DESC(_sc, _pa) \ 4243 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4244 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4245 struct ath_hal *ah = sc->sc_ah; 4246 4247 ath_hal_stoppcurecv(ah); /* disable PCU */ 4248 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4249 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4250 DELAY(3000); /* 3ms is long enough for 1 frame */ 4251 #ifdef AR_DEBUG 4252 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4253 struct ath_buf *bf; 4254 4255 printf("%s: rx queue %p, link %p\n", __func__, 4256 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4257 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4258 struct ath_desc *ds = bf->bf_desc; 4259 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4260 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4261 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4262 ath_printrxbuf(bf, status == HAL_OK); 4263 } 4264 } 4265 #endif 4266 sc->sc_rxlink = NULL; /* just in case */ 4267 #undef PA2DESC 4268 } 4269 4270 /* 4271 * Enable the receive h/w following a reset. 4272 */ 4273 static int 4274 ath_startrecv(struct ath_softc *sc) 4275 { 4276 struct ath_hal *ah = sc->sc_ah; 4277 struct ath_buf *bf; 4278 4279 sc->sc_rxlink = NULL; 4280 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4281 int error = ath_rxbuf_init(sc, bf); 4282 if (error != 0) { 4283 DPRINTF(sc, ATH_DEBUG_RECV, 4284 "%s: ath_rxbuf_init failed %d\n", 4285 __func__, error); 4286 return error; 4287 } 4288 } 4289 4290 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4291 ath_hal_putrxbuf(ah, bf->bf_daddr); 4292 ath_hal_rxena(ah); /* enable recv descriptors */ 4293 ath_mode_init(sc); /* set filters, etc. */ 4294 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4295 return 0; 4296 } 4297 4298 /* 4299 * Update internal state after a channel change. 4300 */ 4301 static void 4302 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4303 { 4304 struct ieee80211com *ic = &sc->sc_ic; 4305 enum ieee80211_phymode mode; 4306 u_int16_t flags; 4307 4308 /* 4309 * Change channels and update the h/w rate map 4310 * if we're switching; e.g. 11a to 11b/g. 4311 */ 4312 mode = ieee80211_chan2mode(ic, chan); 4313 if (mode != sc->sc_curmode) 4314 ath_setcurmode(sc, mode); 4315 /* 4316 * Update BPF state. NB: ethereal et. al. don't handle 4317 * merged flags well so pick a unique mode for their use. 4318 */ 4319 if (IEEE80211_IS_CHAN_A(chan)) 4320 flags = IEEE80211_CHAN_A; 4321 /* XXX 11g schizophrenia */ 4322 else if (IEEE80211_IS_CHAN_G(chan) || 4323 IEEE80211_IS_CHAN_PUREG(chan)) 4324 flags = IEEE80211_CHAN_G; 4325 else 4326 flags = IEEE80211_CHAN_B; 4327 if (IEEE80211_IS_CHAN_T(chan)) 4328 flags |= IEEE80211_CHAN_TURBO; 4329 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4330 htole16(chan->ic_freq); 4331 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4332 htole16(flags); 4333 } 4334 4335 /* 4336 * Poll for a channel clear indication; this is required 4337 * for channels requiring DFS and not previously visited 4338 * and/or with a recent radar detection. 4339 */ 4340 static void 4341 ath_dfswait(void *arg) 4342 { 4343 struct ath_softc *sc = arg; 4344 struct ath_hal *ah = sc->sc_ah; 4345 HAL_CHANNEL hchan; 4346 4347 ath_hal_radar_wait(ah, &hchan); 4348 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4349 if_printf(&sc->sc_if, 4350 "channel %u/0x%x/0x%x has interference\n", 4351 hchan.channel, hchan.channelFlags, hchan.privFlags); 4352 return; 4353 } 4354 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4355 /* XXX should not happen */ 4356 return; 4357 } 4358 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4359 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4360 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4361 if_printf(&sc->sc_if, 4362 "channel %u/0x%x/0x%x marked clear\n", 4363 hchan.channel, hchan.channelFlags, hchan.privFlags); 4364 } else 4365 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4366 } 4367 4368 /* 4369 * Set/change channels. If the channel is really being changed, 4370 * it's done by reseting the chip. To accomplish this we must 4371 * first cleanup any pending DMA, then restart stuff after a la 4372 * ath_init. 4373 */ 4374 static int 4375 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4376 { 4377 struct ath_hal *ah = sc->sc_ah; 4378 struct ieee80211com *ic = &sc->sc_ic; 4379 HAL_CHANNEL hchan; 4380 4381 /* 4382 * Convert to a HAL channel description with 4383 * the flags constrained to reflect the current 4384 * operating mode. 4385 */ 4386 hchan.channel = chan->ic_freq; 4387 hchan.channelFlags = ath_chan2flags(ic, chan); 4388 4389 DPRINTF(sc, ATH_DEBUG_RESET, 4390 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4391 __func__, 4392 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4393 sc->sc_curchan.channelFlags), 4394 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4395 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4396 hchan.channel, hchan.channelFlags); 4397 if (hchan.channel != sc->sc_curchan.channel || 4398 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4399 HAL_STATUS status; 4400 4401 /* 4402 * To switch channels clear any pending DMA operations; 4403 * wait long enough for the RX fifo to drain, reset the 4404 * hardware at the new frequency, and then re-enable 4405 * the relevant bits of the h/w. 4406 */ 4407 ath_hal_intrset(ah, 0); /* disable interrupts */ 4408 ath_draintxq(sc); /* clear pending tx frames */ 4409 ath_stoprecv(sc); /* turn off frame recv */ 4410 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4411 if_printf(ic->ic_ifp, "%s: unable to reset " 4412 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4413 __func__, ieee80211_chan2ieee(ic, chan), 4414 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4415 return EIO; 4416 } 4417 sc->sc_curchan = hchan; 4418 ath_update_txpow(sc); /* update tx power state */ 4419 ath_restore_diversity(sc); 4420 sc->sc_calinterval = 1; 4421 sc->sc_caltries = 0; 4422 4423 /* 4424 * Re-enable rx framework. 4425 */ 4426 if (ath_startrecv(sc) != 0) { 4427 if_printf(&sc->sc_if, 4428 "%s: unable to restart recv logic\n", __func__); 4429 return EIO; 4430 } 4431 4432 /* 4433 * Change channels and update the h/w rate map 4434 * if we're switching; e.g. 11a to 11b/g. 4435 */ 4436 ic->ic_ibss_chan = chan; 4437 ath_chan_change(sc, chan); 4438 4439 /* 4440 * Handle DFS required waiting period to determine 4441 * if channel is clear of radar traffic. 4442 */ 4443 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4444 #define DFS_AND_NOT_CLEAR(_c) \ 4445 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4446 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4447 if_printf(&sc->sc_if, 4448 "wait for DFS clear channel signal\n"); 4449 /* XXX stop sndq */ 4450 sc->sc_if.if_flags |= IFF_OACTIVE; 4451 callout_reset(&sc->sc_dfs_ch, 4452 2 * hz, ath_dfswait, sc); 4453 } else 4454 callout_stop(&sc->sc_dfs_ch); 4455 #undef DFS_NOT_CLEAR 4456 } 4457 4458 /* 4459 * Re-enable interrupts. 4460 */ 4461 ath_hal_intrset(ah, sc->sc_imask); 4462 } 4463 return 0; 4464 } 4465 4466 static void 4467 ath_next_scan(void *arg) 4468 { 4469 struct ath_softc *sc = arg; 4470 struct ieee80211com *ic = &sc->sc_ic; 4471 int s; 4472 4473 /* don't call ath_start w/o network interrupts blocked */ 4474 s = splnet(); 4475 4476 if (ic->ic_state == IEEE80211_S_SCAN) 4477 ieee80211_next_scan(ic); 4478 splx(s); 4479 } 4480 4481 /* 4482 * Periodically recalibrate the PHY to account 4483 * for temperature/environment changes. 4484 */ 4485 static void 4486 ath_calibrate(void *arg) 4487 { 4488 struct ath_softc *sc = arg; 4489 struct ath_hal *ah = sc->sc_ah; 4490 HAL_BOOL iqCalDone; 4491 4492 sc->sc_stats.ast_per_cal++; 4493 4494 ATH_LOCK(sc); 4495 4496 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4497 /* 4498 * Rfgain is out of bounds, reset the chip 4499 * to load new gain values. 4500 */ 4501 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4502 "%s: rfgain change\n", __func__); 4503 sc->sc_stats.ast_per_rfgain++; 4504 ath_reset(&sc->sc_if); 4505 } 4506 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4507 DPRINTF(sc, ATH_DEBUG_ANY, 4508 "%s: calibration of channel %u failed\n", 4509 __func__, sc->sc_curchan.channel); 4510 sc->sc_stats.ast_per_calfail++; 4511 } 4512 /* 4513 * Calibrate noise floor data again in case of change. 4514 */ 4515 ath_hal_process_noisefloor(ah); 4516 /* 4517 * Poll more frequently when the IQ calibration is in 4518 * progress to speedup loading the final settings. 4519 * We temper this aggressive polling with an exponential 4520 * back off after 4 tries up to ath_calinterval. 4521 */ 4522 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4523 sc->sc_caltries = 0; 4524 sc->sc_calinterval = ath_calinterval; 4525 } else if (sc->sc_caltries > 4) { 4526 sc->sc_caltries = 0; 4527 sc->sc_calinterval <<= 1; 4528 if (sc->sc_calinterval > ath_calinterval) 4529 sc->sc_calinterval = ath_calinterval; 4530 } 4531 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4532 ("bad calibration interval %u", sc->sc_calinterval)); 4533 4534 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4535 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4536 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4537 sc->sc_caltries++; 4538 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4539 ath_calibrate, sc); 4540 ATH_UNLOCK(sc); 4541 } 4542 4543 static int 4544 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4545 { 4546 struct ifnet *ifp = ic->ic_ifp; 4547 struct ath_softc *sc = ifp->if_softc; 4548 struct ath_hal *ah = sc->sc_ah; 4549 struct ieee80211_node *ni; 4550 int i, error; 4551 const u_int8_t *bssid; 4552 u_int32_t rfilt; 4553 static const HAL_LED_STATE leds[] = { 4554 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4555 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4556 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4557 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4558 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4559 }; 4560 4561 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4562 ieee80211_state_name[ic->ic_state], 4563 ieee80211_state_name[nstate]); 4564 4565 callout_stop(&sc->sc_scan_ch); 4566 callout_stop(&sc->sc_cal_ch); 4567 callout_stop(&sc->sc_dfs_ch); 4568 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4569 4570 if (nstate == IEEE80211_S_INIT) { 4571 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4572 /* 4573 * NB: disable interrupts so we don't rx frames. 4574 */ 4575 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4576 /* 4577 * Notify the rate control algorithm. 4578 */ 4579 ath_rate_newstate(sc, nstate); 4580 goto done; 4581 } 4582 ni = ic->ic_bss; 4583 error = ath_chan_set(sc, ic->ic_curchan); 4584 if (error != 0) 4585 goto bad; 4586 rfilt = ath_calcrxfilter(sc, nstate); 4587 if (nstate == IEEE80211_S_SCAN) 4588 bssid = ifp->if_broadcastaddr; 4589 else 4590 bssid = ni->ni_bssid; 4591 ath_hal_setrxfilter(ah, rfilt); 4592 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4593 __func__, rfilt, ether_sprintf(bssid)); 4594 4595 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4596 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4597 else 4598 ath_hal_setassocid(ah, bssid, 0); 4599 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4600 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4601 if (ath_hal_keyisvalid(ah, i)) 4602 ath_hal_keysetmac(ah, i, bssid); 4603 } 4604 4605 /* 4606 * Notify the rate control algorithm so rates 4607 * are setup should ath_beacon_alloc be called. 4608 */ 4609 ath_rate_newstate(sc, nstate); 4610 4611 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4612 /* nothing to do */; 4613 } else if (nstate == IEEE80211_S_RUN) { 4614 DPRINTF(sc, ATH_DEBUG_STATE, 4615 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4616 "capinfo=0x%04x chan=%d\n" 4617 , __func__ 4618 , ic->ic_flags 4619 , ni->ni_intval 4620 , ether_sprintf(ni->ni_bssid) 4621 , ni->ni_capinfo 4622 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4623 4624 switch (ic->ic_opmode) { 4625 case IEEE80211_M_HOSTAP: 4626 case IEEE80211_M_IBSS: 4627 /* 4628 * Allocate and setup the beacon frame. 4629 * 4630 * Stop any previous beacon DMA. This may be 4631 * necessary, for example, when an ibss merge 4632 * causes reconfiguration; there will be a state 4633 * transition from RUN->RUN that means we may 4634 * be called with beacon transmission active. 4635 */ 4636 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4637 ath_beacon_free(sc); 4638 error = ath_beacon_alloc(sc, ni); 4639 if (error != 0) 4640 goto bad; 4641 /* 4642 * If joining an adhoc network defer beacon timer 4643 * configuration to the next beacon frame so we 4644 * have a current TSF to use. Otherwise we're 4645 * starting an ibss/bss so there's no need to delay. 4646 */ 4647 if (ic->ic_opmode == IEEE80211_M_IBSS && 4648 ic->ic_bss->ni_tstamp.tsf != 0) 4649 sc->sc_syncbeacon = 1; 4650 else 4651 ath_beacon_config(sc); 4652 break; 4653 case IEEE80211_M_STA: 4654 /* 4655 * Allocate a key cache slot to the station. 4656 */ 4657 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4658 sc->sc_hasclrkey && 4659 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4660 ath_setup_stationkey(ni); 4661 /* 4662 * Defer beacon timer configuration to the next 4663 * beacon frame so we have a current TSF to use 4664 * (any TSF collected when scanning is likely old). 4665 */ 4666 sc->sc_syncbeacon = 1; 4667 break; 4668 default: 4669 break; 4670 } 4671 /* 4672 * Let the hal process statistics collected during a 4673 * scan so it can provide calibrated noise floor data. 4674 */ 4675 ath_hal_process_noisefloor(ah); 4676 /* 4677 * Reset rssi stats; maybe not the best place... 4678 */ 4679 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4680 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4681 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4682 } else { 4683 ath_hal_intrset(ah, 4684 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4685 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4686 } 4687 done: 4688 /* 4689 * Invoke the parent method to complete the work. 4690 */ 4691 error = sc->sc_newstate(ic, nstate, arg); 4692 /* 4693 * Finally, start any timers. 4694 */ 4695 if (nstate == IEEE80211_S_RUN) { 4696 /* start periodic recalibration timer */ 4697 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4698 ath_calibrate, sc); 4699 } else if (nstate == IEEE80211_S_SCAN) { 4700 /* start ap/neighbor scan timer */ 4701 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4702 ath_next_scan, sc); 4703 } 4704 bad: 4705 return error; 4706 } 4707 4708 /* 4709 * Allocate a key cache slot to the station so we can 4710 * setup a mapping from key index to node. The key cache 4711 * slot is needed for managing antenna state and for 4712 * compression when stations do not use crypto. We do 4713 * it uniliaterally here; if crypto is employed this slot 4714 * will be reassigned. 4715 */ 4716 static void 4717 ath_setup_stationkey(struct ieee80211_node *ni) 4718 { 4719 struct ieee80211com *ic = ni->ni_ic; 4720 struct ath_softc *sc = ic->ic_ifp->if_softc; 4721 ieee80211_keyix keyix, rxkeyix; 4722 4723 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4724 /* 4725 * Key cache is full; we'll fall back to doing 4726 * the more expensive lookup in software. Note 4727 * this also means no h/w compression. 4728 */ 4729 /* XXX msg+statistic */ 4730 } else { 4731 /* XXX locking? */ 4732 ni->ni_ucastkey.wk_keyix = keyix; 4733 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4734 /* NB: this will create a pass-thru key entry */ 4735 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4736 } 4737 } 4738 4739 /* 4740 * Setup driver-specific state for a newly associated node. 4741 * Note that we're called also on a re-associate, the isnew 4742 * param tells us if this is the first time or not. 4743 */ 4744 static void 4745 ath_newassoc(struct ieee80211_node *ni, int isnew) 4746 { 4747 struct ieee80211com *ic = ni->ni_ic; 4748 struct ath_softc *sc = ic->ic_ifp->if_softc; 4749 4750 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4751 if (isnew && 4752 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4753 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4754 ("new assoc with a unicast key already setup (keyix %u)", 4755 ni->ni_ucastkey.wk_keyix)); 4756 ath_setup_stationkey(ni); 4757 } 4758 } 4759 4760 static int 4761 ath_getchannels(struct ath_softc *sc, u_int cc, 4762 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4763 { 4764 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4765 struct ieee80211com *ic = &sc->sc_ic; 4766 struct ifnet *ifp = &sc->sc_if; 4767 struct ath_hal *ah = sc->sc_ah; 4768 HAL_CHANNEL *chans; 4769 int i, ix, nchan; 4770 4771 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4772 M_TEMP, M_NOWAIT); 4773 if (chans == NULL) { 4774 if_printf(ifp, "unable to allocate channel table\n"); 4775 return ENOMEM; 4776 } 4777 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4778 NULL, 0, NULL, 4779 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4780 u_int32_t rd; 4781 4782 (void)ath_hal_getregdomain(ah, &rd); 4783 if_printf(ifp, "unable to collect channel list from hal; " 4784 "regdomain likely %u country code %u\n", rd, cc); 4785 free(chans, M_TEMP); 4786 return EINVAL; 4787 } 4788 4789 /* 4790 * Convert HAL channels to ieee80211 ones and insert 4791 * them in the table according to their channel number. 4792 */ 4793 for (i = 0; i < nchan; i++) { 4794 HAL_CHANNEL *c = &chans[i]; 4795 u_int16_t flags; 4796 4797 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4798 if (ix > IEEE80211_CHAN_MAX) { 4799 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4800 ix, c->channel, c->channelFlags); 4801 continue; 4802 } 4803 if (ix < 0) { 4804 /* XXX can't handle stuff <2400 right now */ 4805 if (bootverbose) 4806 if_printf(ifp, "hal channel %d (%u/%x) " 4807 "cannot be handled; ignored\n", 4808 ix, c->channel, c->channelFlags); 4809 continue; 4810 } 4811 /* 4812 * Calculate net80211 flags; most are compatible 4813 * but some need massaging. Note the static turbo 4814 * conversion can be removed once net80211 is updated 4815 * to understand static vs. dynamic turbo. 4816 */ 4817 flags = c->channelFlags & COMPAT; 4818 if (c->channelFlags & CHANNEL_STURBO) 4819 flags |= IEEE80211_CHAN_TURBO; 4820 if (ic->ic_channels[ix].ic_freq == 0) { 4821 ic->ic_channels[ix].ic_freq = c->channel; 4822 ic->ic_channels[ix].ic_flags = flags; 4823 } else { 4824 /* channels overlap; e.g. 11g and 11b */ 4825 ic->ic_channels[ix].ic_flags |= flags; 4826 } 4827 } 4828 free(chans, M_TEMP); 4829 return 0; 4830 #undef COMPAT 4831 } 4832 4833 static void 4834 ath_led_done(void *arg) 4835 { 4836 struct ath_softc *sc = arg; 4837 4838 sc->sc_blinking = 0; 4839 } 4840 4841 /* 4842 * Turn the LED off: flip the pin and then set a timer so no 4843 * update will happen for the specified duration. 4844 */ 4845 static void 4846 ath_led_off(void *arg) 4847 { 4848 struct ath_softc *sc = arg; 4849 4850 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4851 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4852 } 4853 4854 /* 4855 * Blink the LED according to the specified on/off times. 4856 */ 4857 static void 4858 ath_led_blink(struct ath_softc *sc, int on, int off) 4859 { 4860 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4861 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4862 sc->sc_blinking = 1; 4863 sc->sc_ledoff = off; 4864 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4865 } 4866 4867 static void 4868 ath_led_event(struct ath_softc *sc, int event) 4869 { 4870 4871 sc->sc_ledevent = ticks; /* time of last event */ 4872 if (sc->sc_blinking) /* don't interrupt active blink */ 4873 return; 4874 switch (event) { 4875 case ATH_LED_POLL: 4876 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4877 sc->sc_hwmap[0].ledoff); 4878 break; 4879 case ATH_LED_TX: 4880 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4881 sc->sc_hwmap[sc->sc_txrate].ledoff); 4882 break; 4883 case ATH_LED_RX: 4884 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4885 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4886 break; 4887 } 4888 } 4889 4890 static void 4891 ath_update_txpow(struct ath_softc *sc) 4892 { 4893 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4894 struct ieee80211com *ic = &sc->sc_ic; 4895 struct ath_hal *ah = sc->sc_ah; 4896 u_int32_t txpow; 4897 4898 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4899 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4900 /* read back in case value is clamped */ 4901 (void)ath_hal_gettxpowlimit(ah, &txpow); 4902 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4903 } 4904 /* 4905 * Fetch max tx power level for status requests. 4906 */ 4907 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4908 ic->ic_bss->ni_txpower = txpow; 4909 } 4910 4911 static void 4912 rate_setup(struct ath_softc *sc, 4913 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4914 { 4915 int i, maxrates; 4916 4917 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4918 DPRINTF(sc, ATH_DEBUG_ANY, 4919 "%s: rate table too small (%u > %u)\n", 4920 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4921 maxrates = IEEE80211_RATE_MAXSIZE; 4922 } else 4923 maxrates = rt->rateCount; 4924 for (i = 0; i < maxrates; i++) 4925 rs->rs_rates[i] = rt->info[i].dot11Rate; 4926 rs->rs_nrates = maxrates; 4927 } 4928 4929 static int 4930 ath_rate_setup(struct ath_softc *sc, u_int mode) 4931 { 4932 struct ath_hal *ah = sc->sc_ah; 4933 struct ieee80211com *ic = &sc->sc_ic; 4934 const HAL_RATE_TABLE *rt; 4935 4936 switch (mode) { 4937 case IEEE80211_MODE_11A: 4938 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4939 break; 4940 case IEEE80211_MODE_11B: 4941 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4942 break; 4943 case IEEE80211_MODE_11G: 4944 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4945 break; 4946 case IEEE80211_MODE_TURBO_A: 4947 /* XXX until static/dynamic turbo is fixed */ 4948 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4949 break; 4950 case IEEE80211_MODE_TURBO_G: 4951 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4952 break; 4953 default: 4954 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4955 __func__, mode); 4956 return 0; 4957 } 4958 sc->sc_rates[mode] = rt; 4959 if (rt != NULL) { 4960 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 4961 return 1; 4962 } else 4963 return 0; 4964 } 4965 4966 static void 4967 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4968 { 4969 #define N(a) (sizeof(a)/sizeof(a[0])) 4970 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4971 static const struct { 4972 u_int rate; /* tx/rx 802.11 rate */ 4973 u_int16_t timeOn; /* LED on time (ms) */ 4974 u_int16_t timeOff; /* LED off time (ms) */ 4975 } blinkrates[] = { 4976 { 108, 40, 10 }, 4977 { 96, 44, 11 }, 4978 { 72, 50, 13 }, 4979 { 48, 57, 14 }, 4980 { 36, 67, 16 }, 4981 { 24, 80, 20 }, 4982 { 22, 100, 25 }, 4983 { 18, 133, 34 }, 4984 { 12, 160, 40 }, 4985 { 10, 200, 50 }, 4986 { 6, 240, 58 }, 4987 { 4, 267, 66 }, 4988 { 2, 400, 100 }, 4989 { 0, 500, 130 }, 4990 }; 4991 const HAL_RATE_TABLE *rt; 4992 int i, j; 4993 4994 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4995 rt = sc->sc_rates[mode]; 4996 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4997 for (i = 0; i < rt->rateCount; i++) 4998 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4999 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5000 for (i = 0; i < 32; i++) { 5001 u_int8_t ix = rt->rateCodeToIndex[i]; 5002 if (ix == 0xff) { 5003 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5004 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5005 continue; 5006 } 5007 sc->sc_hwmap[i].ieeerate = 5008 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5009 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5010 if (rt->info[ix].shortPreamble || 5011 rt->info[ix].phy == IEEE80211_T_OFDM) 5012 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5013 /* NB: receive frames include FCS */ 5014 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5015 IEEE80211_RADIOTAP_F_FCS; 5016 /* setup blink rate table to avoid per-packet lookup */ 5017 for (j = 0; j < N(blinkrates)-1; j++) 5018 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5019 break; 5020 /* NB: this uses the last entry if the rate isn't found */ 5021 /* XXX beware of overlow */ 5022 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5023 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5024 } 5025 sc->sc_currates = rt; 5026 sc->sc_curmode = mode; 5027 /* 5028 * All protection frames are transmited at 2Mb/s for 5029 * 11g, otherwise at 1Mb/s. 5030 */ 5031 if (mode == IEEE80211_MODE_11G) 5032 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5033 else 5034 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5035 /* rate index used to send management frames */ 5036 sc->sc_minrateix = 0; 5037 /* 5038 * Setup multicast rate state. 5039 */ 5040 /* XXX layering violation */ 5041 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5042 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5043 /* NB: caller is responsible for reseting rate control state */ 5044 #undef N 5045 } 5046 5047 #ifdef AR_DEBUG 5048 static void 5049 ath_printrxbuf(struct ath_buf *bf, int done) 5050 { 5051 struct ath_desc *ds; 5052 int i; 5053 5054 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5055 printf("R%d (%p %" PRIx64 5056 ") %08x %08x %08x %08x %08x %08x %c\n", i, ds, 5057 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5058 ds->ds_link, ds->ds_data, 5059 ds->ds_ctl0, ds->ds_ctl1, 5060 ds->ds_hw[0], ds->ds_hw[1], 5061 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5062 } 5063 } 5064 5065 static void 5066 ath_printtxbuf(struct ath_buf *bf, int done) 5067 { 5068 struct ath_desc *ds; 5069 int i; 5070 5071 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5072 printf("T%d (%p %" PRIx64 5073 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5074 i, ds, 5075 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5076 ds->ds_link, ds->ds_data, 5077 ds->ds_ctl0, ds->ds_ctl1, 5078 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5079 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5080 } 5081 } 5082 #endif /* AR_DEBUG */ 5083 5084 static void 5085 ath_watchdog(struct ifnet *ifp) 5086 { 5087 struct ath_softc *sc = ifp->if_softc; 5088 struct ieee80211com *ic = &sc->sc_ic; 5089 struct ath_txq *axq; 5090 int i; 5091 5092 ifp->if_timer = 0; 5093 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 5094 return; 5095 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5096 if (!ATH_TXQ_SETUP(sc, i)) 5097 continue; 5098 axq = &sc->sc_txq[i]; 5099 ATH_TXQ_LOCK(axq); 5100 if (axq->axq_timer == 0) 5101 ; 5102 else if (--axq->axq_timer == 0) { 5103 ATH_TXQ_UNLOCK(axq); 5104 if_printf(ifp, "device timeout (txq %d)\n", i); 5105 ath_reset(ifp); 5106 ifp->if_oerrors++; 5107 sc->sc_stats.ast_watchdog++; 5108 break; 5109 } else 5110 ifp->if_timer = 1; 5111 ATH_TXQ_UNLOCK(axq); 5112 } 5113 ieee80211_watchdog(ic); 5114 } 5115 5116 /* 5117 * Diagnostic interface to the HAL. This is used by various 5118 * tools to do things like retrieve register contents for 5119 * debugging. The mechanism is intentionally opaque so that 5120 * it can change frequently w/o concern for compatiblity. 5121 */ 5122 static int 5123 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5124 { 5125 struct ath_hal *ah = sc->sc_ah; 5126 u_int id = ad->ad_id & ATH_DIAG_ID; 5127 void *indata = NULL; 5128 void *outdata = NULL; 5129 u_int32_t insize = ad->ad_in_size; 5130 u_int32_t outsize = ad->ad_out_size; 5131 int error = 0; 5132 5133 if (ad->ad_id & ATH_DIAG_IN) { 5134 /* 5135 * Copy in data. 5136 */ 5137 indata = malloc(insize, M_TEMP, M_NOWAIT); 5138 if (indata == NULL) { 5139 error = ENOMEM; 5140 goto bad; 5141 } 5142 error = copyin(ad->ad_in_data, indata, insize); 5143 if (error) 5144 goto bad; 5145 } 5146 if (ad->ad_id & ATH_DIAG_DYN) { 5147 /* 5148 * Allocate a buffer for the results (otherwise the HAL 5149 * returns a pointer to a buffer where we can read the 5150 * results). Note that we depend on the HAL leaving this 5151 * pointer for us to use below in reclaiming the buffer; 5152 * may want to be more defensive. 5153 */ 5154 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5155 if (outdata == NULL) { 5156 error = ENOMEM; 5157 goto bad; 5158 } 5159 } 5160 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5161 if (outsize < ad->ad_out_size) 5162 ad->ad_out_size = outsize; 5163 if (outdata != NULL) 5164 error = copyout(outdata, ad->ad_out_data, 5165 ad->ad_out_size); 5166 } else { 5167 error = EINVAL; 5168 } 5169 bad: 5170 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5171 free(indata, M_TEMP); 5172 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5173 free(outdata, M_TEMP); 5174 return error; 5175 } 5176 5177 static int 5178 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5179 { 5180 #define IS_RUNNING(ifp) \ 5181 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5182 struct ath_softc *sc = ifp->if_softc; 5183 struct ieee80211com *ic = &sc->sc_ic; 5184 struct ifreq *ifr = (struct ifreq *)data; 5185 int error = 0; 5186 5187 ATH_LOCK(sc); 5188 switch (cmd) { 5189 case SIOCSIFFLAGS: 5190 if (IS_RUNNING(ifp)) { 5191 /* 5192 * To avoid rescanning another access point, 5193 * do not call ath_init() here. Instead, 5194 * only reflect promisc mode settings. 5195 */ 5196 ath_mode_init(sc); 5197 } else if (ifp->if_flags & IFF_UP) { 5198 /* 5199 * Beware of being called during attach/detach 5200 * to reset promiscuous mode. In that case we 5201 * will still be marked UP but not RUNNING. 5202 * However trying to re-init the interface 5203 * is the wrong thing to do as we've already 5204 * torn down much of our state. There's 5205 * probably a better way to deal with this. 5206 */ 5207 if (!sc->sc_invalid && ic->ic_bss != NULL) 5208 ath_init(sc); /* XXX lose error */ 5209 } else 5210 ath_stop_locked(ifp, 1); 5211 break; 5212 case SIOCADDMULTI: 5213 case SIOCDELMULTI: 5214 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5215 if (ifp->if_flags & IFF_RUNNING) 5216 ath_mode_init(sc); 5217 error = 0; 5218 } 5219 break; 5220 case SIOCGATHSTATS: 5221 /* NB: embed these numbers to get a consistent view */ 5222 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5223 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5224 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5225 ATH_UNLOCK(sc); 5226 /* 5227 * NB: Drop the softc lock in case of a page fault; 5228 * we'll accept any potential inconsisentcy in the 5229 * statistics. The alternative is to copy the data 5230 * to a local structure. 5231 */ 5232 return copyout(&sc->sc_stats, 5233 ifr->ifr_data, sizeof (sc->sc_stats)); 5234 case SIOCGATHDIAG: 5235 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5236 break; 5237 default: 5238 error = ieee80211_ioctl(ic, cmd, data); 5239 if (error == ENETRESET) { 5240 if (IS_RUNNING(ifp) && 5241 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5242 ath_init(sc); /* XXX lose error */ 5243 error = 0; 5244 } 5245 if (error == ERESTART) 5246 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5247 break; 5248 } 5249 ATH_UNLOCK(sc); 5250 return error; 5251 #undef IS_RUNNING 5252 } 5253 5254 #if NBPFILTER > 0 5255 static void 5256 ath_bpfattach(struct ath_softc *sc) 5257 { 5258 struct ifnet *ifp = &sc->sc_if; 5259 5260 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5261 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5262 &sc->sc_drvbpf); 5263 /* 5264 * Initialize constant fields. 5265 * XXX make header lengths a multiple of 32-bits so subsequent 5266 * headers are properly aligned; this is a kludge to keep 5267 * certain applications happy. 5268 * 5269 * NB: the channel is setup each time we transition to the 5270 * RUN state to avoid filling it in for each frame. 5271 */ 5272 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5273 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5274 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5275 5276 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5277 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5278 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5279 } 5280 #endif 5281 5282 /* 5283 * Announce various information on device/driver attach. 5284 */ 5285 static void 5286 ath_announce(struct ath_softc *sc) 5287 { 5288 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5289 struct ifnet *ifp = &sc->sc_if; 5290 struct ath_hal *ah = sc->sc_ah; 5291 u_int modes, cc; 5292 5293 if_printf(ifp, "mac %d.%d phy %d.%d", 5294 ah->ah_macVersion, ah->ah_macRev, 5295 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5296 /* 5297 * Print radio revision(s). We check the wireless modes 5298 * to avoid falsely printing revs for inoperable parts. 5299 * Dual-band radio revs are returned in the 5 GHz rev number. 5300 */ 5301 ath_hal_getcountrycode(ah, &cc); 5302 modes = ath_hal_getwirelessmodes(ah, cc); 5303 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5304 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5305 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5306 ah->ah_analog5GhzRev >> 4, 5307 ah->ah_analog5GhzRev & 0xf, 5308 ah->ah_analog2GhzRev >> 4, 5309 ah->ah_analog2GhzRev & 0xf); 5310 else 5311 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5312 ah->ah_analog5GhzRev & 0xf); 5313 } else 5314 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5315 ah->ah_analog5GhzRev & 0xf); 5316 printf("\n"); 5317 if (bootverbose) { 5318 int i; 5319 for (i = 0; i <= WME_AC_VO; i++) { 5320 struct ath_txq *txq = sc->sc_ac2q[i]; 5321 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5322 txq->axq_qnum, ieee80211_wme_acnames[i]); 5323 } 5324 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5325 sc->sc_cabq->axq_qnum); 5326 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5327 } 5328 if (ath_rxbuf != ATH_RXBUF) 5329 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5330 if (ath_txbuf != ATH_TXBUF) 5331 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5332 #undef HAL_MODE_DUALBAND 5333 } 5334