1 /* $NetBSD: ath.c,v 1.87 2007/10/19 11:59:47 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.87 2007/10/19 11:59:47 ad Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/lock.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sockio.h> 71 #include <sys/errno.h> 72 #include <sys/callout.h> 73 #include <sys/bus.h> 74 #include <sys/endian.h> 75 76 #include <net/if.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/if_ether.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_netbsd.h> 85 #include <net80211/ieee80211_var.h> 86 87 #if NBPFILTER > 0 88 #include <net/bpf.h> 89 #endif 90 91 #ifdef INET 92 #include <netinet/in.h> 93 #endif 94 95 #include <sys/device.h> 96 #include <dev/ic/ath_netbsd.h> 97 98 #define AR_DEBUG 99 #include <dev/ic/athvar.h> 100 #include <contrib/dev/ath/ah_desc.h> 101 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 102 #include "athhal_options.h" 103 104 #ifdef ATH_TX99_DIAG 105 #include <dev/ath/ath_tx99/ath_tx99.h> 106 #endif 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 enum { 118 ATH_LED_TX, 119 ATH_LED_RX, 120 ATH_LED_POLL, 121 }; 122 123 #ifdef AH_NEED_DESC_SWAP 124 #define HTOAH32(x) htole32(x) 125 #else 126 #define HTOAH32(x) (x) 127 #endif 128 129 static int ath_ifinit(struct ifnet *); 130 static int ath_init(struct ath_softc *); 131 static void ath_stop_locked(struct ifnet *, int); 132 static void ath_stop(struct ifnet *, int); 133 static void ath_start(struct ifnet *); 134 static int ath_media_change(struct ifnet *); 135 static void ath_watchdog(struct ifnet *); 136 static int ath_ioctl(struct ifnet *, u_long, void *); 137 static void ath_fatal_proc(void *, int); 138 static void ath_rxorn_proc(void *, int); 139 static void ath_bmiss_proc(void *, int); 140 static void ath_radar_proc(void *, int); 141 static int ath_key_alloc(struct ieee80211com *, 142 const struct ieee80211_key *, 143 ieee80211_keyix *, ieee80211_keyix *); 144 static int ath_key_delete(struct ieee80211com *, 145 const struct ieee80211_key *); 146 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 147 const u_int8_t mac[IEEE80211_ADDR_LEN]); 148 static void ath_key_update_begin(struct ieee80211com *); 149 static void ath_key_update_end(struct ieee80211com *); 150 static void ath_mode_init(struct ath_softc *); 151 static void ath_setslottime(struct ath_softc *); 152 static void ath_updateslot(struct ifnet *); 153 static int ath_beaconq_setup(struct ath_hal *); 154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 155 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 156 static void ath_beacon_proc(void *, int); 157 static void ath_bstuck_proc(void *, int); 158 static void ath_beacon_free(struct ath_softc *); 159 static void ath_beacon_config(struct ath_softc *); 160 static void ath_descdma_cleanup(struct ath_softc *sc, 161 struct ath_descdma *, ath_bufhead *); 162 static int ath_desc_alloc(struct ath_softc *); 163 static void ath_desc_free(struct ath_softc *); 164 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 165 static void ath_node_free(struct ieee80211_node *); 166 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 167 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 168 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 169 struct ieee80211_node *ni, 170 int subtype, int rssi, u_int32_t rstamp); 171 static void ath_setdefantenna(struct ath_softc *, u_int); 172 static void ath_rx_proc(void *, int); 173 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 174 static int ath_tx_setup(struct ath_softc *, int, int); 175 static int ath_wme_update(struct ieee80211com *); 176 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 177 static void ath_tx_cleanup(struct ath_softc *); 178 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 179 struct ath_buf *, struct mbuf *); 180 static void ath_tx_proc_q0(void *, int); 181 static void ath_tx_proc_q0123(void *, int); 182 static void ath_tx_proc(void *, int); 183 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 184 static void ath_draintxq(struct ath_softc *); 185 static void ath_stoprecv(struct ath_softc *); 186 static int ath_startrecv(struct ath_softc *); 187 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 188 static void ath_next_scan(void *); 189 static void ath_calibrate(void *); 190 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 191 static void ath_setup_stationkey(struct ieee80211_node *); 192 static void ath_newassoc(struct ieee80211_node *, int); 193 static int ath_getchannels(struct ath_softc *, u_int cc, 194 HAL_BOOL outdoor, HAL_BOOL xchanmode); 195 static void ath_led_event(struct ath_softc *, int); 196 static void ath_update_txpow(struct ath_softc *); 197 static void ath_freetx(struct mbuf *); 198 199 static int ath_rate_setup(struct ath_softc *, u_int mode); 200 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 201 202 #ifdef __NetBSD__ 203 int ath_enable(struct ath_softc *); 204 void ath_disable(struct ath_softc *); 205 void ath_power(int, void *); 206 #endif 207 208 #if NBPFILTER > 0 209 static void ath_bpfattach(struct ath_softc *); 210 #endif 211 static void ath_announce(struct ath_softc *); 212 213 int ath_dwelltime = 200; /* 5 channels/second */ 214 int ath_calinterval = 30; /* calibrate every 30 secs */ 215 int ath_outdoor = AH_TRUE; /* outdoor operation */ 216 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 217 int ath_countrycode = CTRY_DEFAULT; /* country code */ 218 int ath_regdomain = 0; /* regulatory domain */ 219 int ath_debug = 0; 220 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 221 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 222 223 #ifdef AR_DEBUG 224 enum { 225 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 226 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 227 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 228 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 229 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 230 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 231 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 232 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 233 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 234 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 235 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 236 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 237 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 238 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 239 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 240 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 241 ATH_DEBUG_NODE = 0x00080000, /* node management */ 242 ATH_DEBUG_LED = 0x00100000, /* led management */ 243 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 244 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 245 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 246 ATH_DEBUG_ANY = 0xffffffff 247 }; 248 #define IFF_DUMPPKTS(sc, m) \ 249 ((sc->sc_debug & (m)) || \ 250 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 251 #define DPRINTF(sc, m, fmt, ...) do { \ 252 if (sc->sc_debug & (m)) \ 253 printf(fmt, __VA_ARGS__); \ 254 } while (0) 255 #define KEYPRINTF(sc, ix, hk, mac) do { \ 256 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 257 ath_keyprint(__func__, ix, hk, mac); \ 258 } while (0) 259 static void ath_printrxbuf(struct ath_buf *bf, int); 260 static void ath_printtxbuf(struct ath_buf *bf, int); 261 #else 262 #define IFF_DUMPPKTS(sc, m) \ 263 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 264 #define DPRINTF(m, fmt, ...) 265 #define KEYPRINTF(sc, k, ix, mac) 266 #endif 267 268 #ifdef __NetBSD__ 269 int 270 ath_activate(struct device *self, enum devact act) 271 { 272 struct ath_softc *sc = (struct ath_softc *)self; 273 int rv = 0, s; 274 275 s = splnet(); 276 switch (act) { 277 case DVACT_ACTIVATE: 278 rv = EOPNOTSUPP; 279 break; 280 case DVACT_DEACTIVATE: 281 if_deactivate(&sc->sc_if); 282 break; 283 } 284 splx(s); 285 return rv; 286 } 287 288 int 289 ath_enable(struct ath_softc *sc) 290 { 291 if (ATH_IS_ENABLED(sc) == 0) { 292 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 293 printf("%s: device enable failed\n", 294 sc->sc_dev.dv_xname); 295 return (EIO); 296 } 297 sc->sc_flags |= ATH_ENABLED; 298 } 299 return (0); 300 } 301 302 void 303 ath_disable(struct ath_softc *sc) 304 { 305 if (!ATH_IS_ENABLED(sc)) 306 return; 307 if (sc->sc_disable != NULL) 308 (*sc->sc_disable)(sc); 309 sc->sc_flags &= ~ATH_ENABLED; 310 } 311 #endif /* __NetBSD__ */ 312 313 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 314 315 int 316 ath_attach(u_int16_t devid, struct ath_softc *sc) 317 { 318 struct ifnet *ifp = &sc->sc_if; 319 struct ieee80211com *ic = &sc->sc_ic; 320 struct ath_hal *ah = NULL; 321 HAL_STATUS status; 322 int error = 0, i; 323 324 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 325 326 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 327 328 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 329 if (ah == NULL) { 330 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 331 status); 332 error = ENXIO; 333 goto bad; 334 } 335 if (ah->ah_abi != HAL_ABI_VERSION) { 336 if_printf(ifp, "HAL ABI mismatch detected " 337 "(HAL:0x%x != driver:0x%x)\n", 338 ah->ah_abi, HAL_ABI_VERSION); 339 error = ENXIO; 340 goto bad; 341 } 342 sc->sc_ah = ah; 343 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 344 345 /* 346 * Check if the MAC has multi-rate retry support. 347 * We do this by trying to setup a fake extended 348 * descriptor. MAC's that don't have support will 349 * return false w/o doing anything. MAC's that do 350 * support it will return true w/o doing anything. 351 */ 352 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 353 354 /* 355 * Check if the device has hardware counters for PHY 356 * errors. If so we need to enable the MIB interrupt 357 * so we can act on stat triggers. 358 */ 359 if (ath_hal_hwphycounters(ah)) 360 sc->sc_needmib = 1; 361 362 /* 363 * Get the hardware key cache size. 364 */ 365 sc->sc_keymax = ath_hal_keycachesize(ah); 366 if (sc->sc_keymax > ATH_KEYMAX) { 367 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 368 ATH_KEYMAX, sc->sc_keymax); 369 sc->sc_keymax = ATH_KEYMAX; 370 } 371 /* 372 * Reset the key cache since some parts do not 373 * reset the contents on initial power up. 374 */ 375 for (i = 0; i < sc->sc_keymax; i++) 376 ath_hal_keyreset(ah, i); 377 /* 378 * Mark key cache slots associated with global keys 379 * as in use. If we knew TKIP was not to be used we 380 * could leave the +32, +64, and +32+64 slots free. 381 * XXX only for splitmic. 382 */ 383 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 384 setbit(sc->sc_keymap, i); 385 setbit(sc->sc_keymap, i+32); 386 setbit(sc->sc_keymap, i+64); 387 setbit(sc->sc_keymap, i+32+64); 388 } 389 390 /* 391 * Collect the channel list using the default country 392 * code and including outdoor channels. The 802.11 layer 393 * is resposible for filtering this list based on settings 394 * like the phy mode. 395 */ 396 error = ath_getchannels(sc, ath_countrycode, 397 ath_outdoor, ath_xchanmode); 398 if (error != 0) 399 goto bad; 400 401 /* 402 * Setup rate tables for all potential media types. 403 */ 404 ath_rate_setup(sc, IEEE80211_MODE_11A); 405 ath_rate_setup(sc, IEEE80211_MODE_11B); 406 ath_rate_setup(sc, IEEE80211_MODE_11G); 407 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 408 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 409 /* NB: setup here so ath_rate_update is happy */ 410 ath_setcurmode(sc, IEEE80211_MODE_11A); 411 412 /* 413 * Allocate tx+rx descriptors and populate the lists. 414 */ 415 error = ath_desc_alloc(sc); 416 if (error != 0) { 417 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 418 goto bad; 419 } 420 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 421 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 422 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 423 424 ATH_TXBUF_LOCK_INIT(sc); 425 426 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 427 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 428 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 429 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 430 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 431 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 432 433 /* 434 * Allocate hardware transmit queues: one queue for 435 * beacon frames and one data queue for each QoS 436 * priority. Note that the hal handles reseting 437 * these queues at the needed time. 438 * 439 * XXX PS-Poll 440 */ 441 sc->sc_bhalq = ath_beaconq_setup(ah); 442 if (sc->sc_bhalq == (u_int) -1) { 443 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 444 error = EIO; 445 goto bad2; 446 } 447 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 448 if (sc->sc_cabq == NULL) { 449 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 450 error = EIO; 451 goto bad2; 452 } 453 /* NB: insure BK queue is the lowest priority h/w queue */ 454 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 455 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 456 ieee80211_wme_acnames[WME_AC_BK]); 457 error = EIO; 458 goto bad2; 459 } 460 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 461 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 462 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 463 /* 464 * Not enough hardware tx queues to properly do WME; 465 * just punt and assign them all to the same h/w queue. 466 * We could do a better job of this if, for example, 467 * we allocate queues when we switch from station to 468 * AP mode. 469 */ 470 if (sc->sc_ac2q[WME_AC_VI] != NULL) 471 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 472 if (sc->sc_ac2q[WME_AC_BE] != NULL) 473 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 474 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 475 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 476 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 477 } 478 479 /* 480 * Special case certain configurations. Note the 481 * CAB queue is handled by these specially so don't 482 * include them when checking the txq setup mask. 483 */ 484 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 485 case 0x01: 486 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 487 break; 488 case 0x0f: 489 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 490 break; 491 default: 492 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 493 break; 494 } 495 496 /* 497 * Setup rate control. Some rate control modules 498 * call back to change the anntena state so expose 499 * the necessary entry points. 500 * XXX maybe belongs in struct ath_ratectrl? 501 */ 502 sc->sc_setdefantenna = ath_setdefantenna; 503 sc->sc_rc = ath_rate_attach(sc); 504 if (sc->sc_rc == NULL) { 505 error = EIO; 506 goto bad2; 507 } 508 509 sc->sc_blinking = 0; 510 sc->sc_ledstate = 1; 511 sc->sc_ledon = 0; /* low true */ 512 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 513 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 514 /* 515 * Auto-enable soft led processing for IBM cards and for 516 * 5211 minipci cards. Users can also manually enable/disable 517 * support with a sysctl. 518 */ 519 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 520 if (sc->sc_softled) { 521 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 522 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 523 } 524 525 ifp->if_softc = sc; 526 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 527 ifp->if_start = ath_start; 528 ifp->if_watchdog = ath_watchdog; 529 ifp->if_ioctl = ath_ioctl; 530 ifp->if_init = ath_ifinit; 531 IFQ_SET_READY(&ifp->if_snd); 532 533 ic->ic_ifp = ifp; 534 ic->ic_reset = ath_reset; 535 ic->ic_newassoc = ath_newassoc; 536 ic->ic_updateslot = ath_updateslot; 537 ic->ic_wme.wme_update = ath_wme_update; 538 /* XXX not right but it's not used anywhere important */ 539 ic->ic_phytype = IEEE80211_T_OFDM; 540 ic->ic_opmode = IEEE80211_M_STA; 541 ic->ic_caps = 542 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 543 | IEEE80211_C_HOSTAP /* hostap mode */ 544 | IEEE80211_C_MONITOR /* monitor mode */ 545 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 546 | IEEE80211_C_SHSLOT /* short slot time supported */ 547 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 548 | IEEE80211_C_TXFRAG /* handle tx frags */ 549 ; 550 /* 551 * Query the hal to figure out h/w crypto support. 552 */ 553 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 554 ic->ic_caps |= IEEE80211_C_WEP; 555 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 556 ic->ic_caps |= IEEE80211_C_AES; 557 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 558 ic->ic_caps |= IEEE80211_C_AES_CCM; 559 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 560 ic->ic_caps |= IEEE80211_C_CKIP; 561 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 562 ic->ic_caps |= IEEE80211_C_TKIP; 563 /* 564 * Check if h/w does the MIC and/or whether the 565 * separate key cache entries are required to 566 * handle both tx+rx MIC keys. 567 */ 568 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 569 ic->ic_caps |= IEEE80211_C_TKIPMIC; 570 if (ath_hal_tkipsplit(ah)) 571 sc->sc_splitmic = 1; 572 } 573 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 574 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 575 /* 576 * TPC support can be done either with a global cap or 577 * per-packet support. The latter is not available on 578 * all parts. We're a bit pedantic here as all parts 579 * support a global cap. 580 */ 581 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 582 ic->ic_caps |= IEEE80211_C_TXPMGT; 583 584 /* 585 * Mark WME capability only if we have sufficient 586 * hardware queues to do proper priority scheduling. 587 */ 588 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 589 ic->ic_caps |= IEEE80211_C_WME; 590 /* 591 * Check for misc other capabilities. 592 */ 593 if (ath_hal_hasbursting(ah)) 594 ic->ic_caps |= IEEE80211_C_BURST; 595 596 /* 597 * Indicate we need the 802.11 header padded to a 598 * 32-bit boundary for 4-address and QoS frames. 599 */ 600 ic->ic_flags |= IEEE80211_F_DATAPAD; 601 602 /* 603 * Query the hal about antenna support. 604 */ 605 sc->sc_defant = ath_hal_getdefantenna(ah); 606 607 /* 608 * Not all chips have the VEOL support we want to 609 * use with IBSS beacons; check here for it. 610 */ 611 sc->sc_hasveol = ath_hal_hasveol(ah); 612 613 /* get mac address from hardware */ 614 ath_hal_getmac(ah, ic->ic_myaddr); 615 616 if_attach(ifp); 617 /* call MI attach routine. */ 618 ieee80211_ifattach(ic); 619 /* override default methods */ 620 ic->ic_node_alloc = ath_node_alloc; 621 sc->sc_node_free = ic->ic_node_free; 622 ic->ic_node_free = ath_node_free; 623 ic->ic_node_getrssi = ath_node_getrssi; 624 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 625 ic->ic_recv_mgmt = ath_recv_mgmt; 626 sc->sc_newstate = ic->ic_newstate; 627 ic->ic_newstate = ath_newstate; 628 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 629 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 630 ic->ic_crypto.cs_key_delete = ath_key_delete; 631 ic->ic_crypto.cs_key_set = ath_key_set; 632 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 633 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 634 /* complete initialization */ 635 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 636 637 #if NBPFILTER > 0 638 ath_bpfattach(sc); 639 #endif 640 641 #ifdef __NetBSD__ 642 sc->sc_flags |= ATH_ATTACHED; 643 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 644 ath_power, sc); 645 if (sc->sc_powerhook == NULL) 646 printf("%s: WARNING: unable to establish power hook\n", 647 sc->sc_dev.dv_xname); 648 #endif 649 650 /* 651 * Setup dynamic sysctl's now that country code and 652 * regdomain are available from the hal. 653 */ 654 ath_sysctlattach(sc); 655 656 ieee80211_announce(ic); 657 ath_announce(sc); 658 return 0; 659 bad2: 660 ath_tx_cleanup(sc); 661 ath_desc_free(sc); 662 bad: 663 if (ah) 664 ath_hal_detach(ah); 665 sc->sc_invalid = 1; 666 return error; 667 } 668 669 int 670 ath_detach(struct ath_softc *sc) 671 { 672 struct ifnet *ifp = &sc->sc_if; 673 int s; 674 675 if ((sc->sc_flags & ATH_ATTACHED) == 0) 676 return (0); 677 678 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 679 __func__, ifp->if_flags); 680 681 s = splnet(); 682 ath_stop(ifp, 1); 683 #if NBPFILTER > 0 684 bpfdetach(ifp); 685 #endif 686 /* 687 * NB: the order of these is important: 688 * o call the 802.11 layer before detaching the hal to 689 * insure callbacks into the driver to delete global 690 * key cache entries can be handled 691 * o reclaim the tx queue data structures after calling 692 * the 802.11 layer as we'll get called back to reclaim 693 * node state and potentially want to use them 694 * o to cleanup the tx queues the hal is called, so detach 695 * it last 696 * Other than that, it's straightforward... 697 */ 698 ieee80211_ifdetach(&sc->sc_ic); 699 #ifdef ATH_TX99_DIAG 700 if (sc->sc_tx99 != NULL) 701 sc->sc_tx99->detach(sc->sc_tx99); 702 #endif 703 ath_rate_detach(sc->sc_rc); 704 ath_desc_free(sc); 705 ath_tx_cleanup(sc); 706 sysctl_teardown(&sc->sc_sysctllog); 707 ath_hal_detach(sc->sc_ah); 708 if_detach(ifp); 709 splx(s); 710 powerhook_disestablish(sc->sc_powerhook); 711 712 return 0; 713 } 714 715 #ifdef __NetBSD__ 716 void 717 ath_power(int why, void *arg) 718 { 719 struct ath_softc *sc = arg; 720 int s; 721 722 DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 723 724 s = splnet(); 725 switch (why) { 726 case PWR_SUSPEND: 727 case PWR_STANDBY: 728 ath_suspend(sc, why); 729 break; 730 case PWR_RESUME: 731 ath_resume(sc, why); 732 break; 733 case PWR_SOFTSUSPEND: 734 case PWR_SOFTSTANDBY: 735 case PWR_SOFTRESUME: 736 break; 737 } 738 splx(s); 739 } 740 #endif 741 742 void 743 ath_suspend(struct ath_softc *sc, int why) 744 { 745 struct ifnet *ifp = &sc->sc_if; 746 747 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 748 __func__, ifp->if_flags); 749 750 ath_stop(ifp, 1); 751 if (sc->sc_power != NULL) 752 (*sc->sc_power)(sc, why); 753 } 754 755 void 756 ath_resume(struct ath_softc *sc, int why) 757 { 758 struct ifnet *ifp = &sc->sc_if; 759 760 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 761 __func__, ifp->if_flags); 762 763 if (ifp->if_flags & IFF_UP) { 764 ath_init(sc); 765 #if 0 766 (void)ath_intr(sc); 767 #endif 768 if (sc->sc_power != NULL) 769 (*sc->sc_power)(sc, why); 770 if (ifp->if_flags & IFF_RUNNING) 771 ath_start(ifp); 772 } 773 if (sc->sc_softled) { 774 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 775 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 776 } 777 } 778 779 void 780 ath_shutdown(void *arg) 781 { 782 struct ath_softc *sc = arg; 783 784 ath_stop(&sc->sc_if, 1); 785 } 786 787 /* 788 * Interrupt handler. Most of the actual processing is deferred. 789 */ 790 int 791 ath_intr(void *arg) 792 { 793 struct ath_softc *sc = arg; 794 struct ifnet *ifp = &sc->sc_if; 795 struct ath_hal *ah = sc->sc_ah; 796 HAL_INT status; 797 798 if (sc->sc_invalid) { 799 /* 800 * The hardware is not ready/present, don't touch anything. 801 * Note this can happen early on if the IRQ is shared. 802 */ 803 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 804 return 0; 805 } 806 807 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 808 return 0; 809 810 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 811 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 812 __func__, ifp->if_flags); 813 ath_hal_getisr(ah, &status); /* clear ISR */ 814 ath_hal_intrset(ah, 0); /* disable further intr's */ 815 return 1; /* XXX */ 816 } 817 /* 818 * Figure out the reason(s) for the interrupt. Note 819 * that the hal returns a pseudo-ISR that may include 820 * bits we haven't explicitly enabled so we mask the 821 * value to insure we only process bits we requested. 822 */ 823 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 824 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 825 status &= sc->sc_imask; /* discard unasked for bits */ 826 if (status & HAL_INT_FATAL) { 827 /* 828 * Fatal errors are unrecoverable. Typically 829 * these are caused by DMA errors. Unfortunately 830 * the exact reason is not (presently) returned 831 * by the hal. 832 */ 833 sc->sc_stats.ast_hardware++; 834 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 835 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 836 } else if (status & HAL_INT_RXORN) { 837 sc->sc_stats.ast_rxorn++; 838 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 839 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 840 } else { 841 if (status & HAL_INT_SWBA) { 842 /* 843 * Software beacon alert--time to send a beacon. 844 * Handle beacon transmission directly; deferring 845 * this is too slow to meet timing constraints 846 * under load. 847 */ 848 ath_beacon_proc(sc, 0); 849 } 850 if (status & HAL_INT_RXEOL) { 851 /* 852 * NB: the hardware should re-read the link when 853 * RXE bit is written, but it doesn't work at 854 * least on older hardware revs. 855 */ 856 sc->sc_stats.ast_rxeol++; 857 sc->sc_rxlink = NULL; 858 } 859 if (status & HAL_INT_TXURN) { 860 sc->sc_stats.ast_txurn++; 861 /* bump tx trigger level */ 862 ath_hal_updatetxtriglevel(ah, AH_TRUE); 863 } 864 if (status & HAL_INT_RX) 865 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 866 if (status & HAL_INT_TX) 867 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 868 if (status & HAL_INT_BMISS) { 869 sc->sc_stats.ast_bmiss++; 870 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 871 } 872 if (status & HAL_INT_MIB) { 873 sc->sc_stats.ast_mib++; 874 /* 875 * Disable interrupts until we service the MIB 876 * interrupt; otherwise it will continue to fire. 877 */ 878 ath_hal_intrset(ah, 0); 879 /* 880 * Let the hal handle the event. We assume it will 881 * clear whatever condition caused the interrupt. 882 */ 883 ath_hal_mibevent(ah, &sc->sc_halstats); 884 ath_hal_intrset(ah, sc->sc_imask); 885 } 886 } 887 return 1; 888 } 889 890 /* Swap transmit descriptor. 891 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 892 * function. 893 */ 894 static inline void 895 ath_desc_swap(struct ath_desc *ds) 896 { 897 #ifdef AH_NEED_DESC_SWAP 898 ds->ds_link = htole32(ds->ds_link); 899 ds->ds_data = htole32(ds->ds_data); 900 ds->ds_ctl0 = htole32(ds->ds_ctl0); 901 ds->ds_ctl1 = htole32(ds->ds_ctl1); 902 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 903 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 904 #endif 905 } 906 907 static void 908 ath_fatal_proc(void *arg, int pending) 909 { 910 struct ath_softc *sc = arg; 911 struct ifnet *ifp = &sc->sc_if; 912 913 if_printf(ifp, "hardware error; resetting\n"); 914 ath_reset(ifp); 915 } 916 917 static void 918 ath_rxorn_proc(void *arg, int pending) 919 { 920 struct ath_softc *sc = arg; 921 struct ifnet *ifp = &sc->sc_if; 922 923 if_printf(ifp, "rx FIFO overrun; resetting\n"); 924 ath_reset(ifp); 925 } 926 927 static void 928 ath_bmiss_proc(void *arg, int pending) 929 { 930 struct ath_softc *sc = arg; 931 struct ieee80211com *ic = &sc->sc_ic; 932 933 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 934 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 935 ("unexpect operating mode %u", ic->ic_opmode)); 936 if (ic->ic_state == IEEE80211_S_RUN) { 937 u_int64_t lastrx = sc->sc_lastrx; 938 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 939 940 DPRINTF(sc, ATH_DEBUG_BEACON, 941 "%s: tsf %" PRIu64 " lastrx %" PRId64 942 " (%" PRIu64 ") bmiss %u\n", 943 __func__, tsf, tsf - lastrx, lastrx, 944 ic->ic_bmisstimeout*1024); 945 /* 946 * Workaround phantom bmiss interrupts by sanity-checking 947 * the time of our last rx'd frame. If it is within the 948 * beacon miss interval then ignore the interrupt. If it's 949 * truly a bmiss we'll get another interrupt soon and that'll 950 * be dispatched up for processing. 951 */ 952 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 953 NET_LOCK_GIANT(); 954 ieee80211_beacon_miss(ic); 955 NET_UNLOCK_GIANT(); 956 } else 957 sc->sc_stats.ast_bmiss_phantom++; 958 } 959 } 960 961 static void 962 ath_radar_proc(void *arg, int pending) 963 { 964 struct ath_softc *sc = arg; 965 struct ifnet *ifp = &sc->sc_if; 966 struct ath_hal *ah = sc->sc_ah; 967 HAL_CHANNEL hchan; 968 969 if (ath_hal_procdfs(ah, &hchan)) { 970 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 971 hchan.channel, hchan.channelFlags, hchan.privFlags); 972 /* 973 * Initiate channel change. 974 */ 975 /* XXX not yet */ 976 } 977 } 978 979 static u_int 980 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 981 { 982 #define N(a) (sizeof(a) / sizeof(a[0])) 983 static const u_int modeflags[] = { 984 0, /* IEEE80211_MODE_AUTO */ 985 CHANNEL_A, /* IEEE80211_MODE_11A */ 986 CHANNEL_B, /* IEEE80211_MODE_11B */ 987 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 988 0, /* IEEE80211_MODE_FH */ 989 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 990 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 991 }; 992 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 993 994 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 995 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 996 return modeflags[mode]; 997 #undef N 998 } 999 1000 static int 1001 ath_ifinit(struct ifnet *ifp) 1002 { 1003 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 1004 1005 return ath_init(sc); 1006 } 1007 1008 static int 1009 ath_init(struct ath_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->sc_if; 1012 struct ieee80211com *ic = &sc->sc_ic; 1013 struct ath_hal *ah = sc->sc_ah; 1014 HAL_STATUS status; 1015 int error = 0; 1016 1017 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1018 __func__, ifp->if_flags); 1019 1020 ATH_LOCK(sc); 1021 1022 if ((error = ath_enable(sc)) != 0) 1023 return error; 1024 1025 /* 1026 * Stop anything previously setup. This is safe 1027 * whether this is the first time through or not. 1028 */ 1029 ath_stop_locked(ifp, 0); 1030 1031 /* 1032 * The basic interface to setting the hardware in a good 1033 * state is ``reset''. On return the hardware is known to 1034 * be powered up and with interrupts disabled. This must 1035 * be followed by initialization of the appropriate bits 1036 * and then setup of the interrupt mask. 1037 */ 1038 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1039 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1040 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1041 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1042 status); 1043 error = EIO; 1044 goto done; 1045 } 1046 1047 /* 1048 * This is needed only to setup initial state 1049 * but it's best done after a reset. 1050 */ 1051 ath_update_txpow(sc); 1052 /* 1053 * Likewise this is set during reset so update 1054 * state cached in the driver. 1055 */ 1056 sc->sc_diversity = ath_hal_getdiversity(ah); 1057 sc->sc_calinterval = 1; 1058 sc->sc_caltries = 0; 1059 1060 /* 1061 * Setup the hardware after reset: the key cache 1062 * is filled as needed and the receive engine is 1063 * set going. Frame transmit is handled entirely 1064 * in the frame output path; there's nothing to do 1065 * here except setup the interrupt mask. 1066 */ 1067 if ((error = ath_startrecv(sc)) != 0) { 1068 if_printf(ifp, "unable to start recv logic\n"); 1069 goto done; 1070 } 1071 1072 /* 1073 * Enable interrupts. 1074 */ 1075 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1076 | HAL_INT_RXEOL | HAL_INT_RXORN 1077 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1078 /* 1079 * Enable MIB interrupts when there are hardware phy counters. 1080 * Note we only do this (at the moment) for station mode. 1081 */ 1082 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1083 sc->sc_imask |= HAL_INT_MIB; 1084 ath_hal_intrset(ah, sc->sc_imask); 1085 1086 ifp->if_flags |= IFF_RUNNING; 1087 ic->ic_state = IEEE80211_S_INIT; 1088 1089 /* 1090 * The hardware should be ready to go now so it's safe 1091 * to kick the 802.11 state machine as it's likely to 1092 * immediately call back to us to send mgmt frames. 1093 */ 1094 ath_chan_change(sc, ic->ic_curchan); 1095 #ifdef ATH_TX99_DIAG 1096 if (sc->sc_tx99 != NULL) 1097 sc->sc_tx99->start(sc->sc_tx99); 1098 else 1099 #endif 1100 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1101 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1102 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1103 } else 1104 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1105 done: 1106 ATH_UNLOCK(sc); 1107 return error; 1108 } 1109 1110 static void 1111 ath_stop_locked(struct ifnet *ifp, int disable) 1112 { 1113 struct ath_softc *sc = ifp->if_softc; 1114 struct ieee80211com *ic = &sc->sc_ic; 1115 struct ath_hal *ah = sc->sc_ah; 1116 1117 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1118 __func__, sc->sc_invalid, ifp->if_flags); 1119 1120 ATH_LOCK_ASSERT(sc); 1121 if (ifp->if_flags & IFF_RUNNING) { 1122 /* 1123 * Shutdown the hardware and driver: 1124 * reset 802.11 state machine 1125 * turn off timers 1126 * disable interrupts 1127 * turn off the radio 1128 * clear transmit machinery 1129 * clear receive machinery 1130 * drain and release tx queues 1131 * reclaim beacon resources 1132 * power down hardware 1133 * 1134 * Note that some of this work is not possible if the 1135 * hardware is gone (invalid). 1136 */ 1137 #ifdef ATH_TX99_DIAG 1138 if (sc->sc_tx99 != NULL) 1139 sc->sc_tx99->stop(sc->sc_tx99); 1140 #endif 1141 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1142 ifp->if_flags &= ~IFF_RUNNING; 1143 ifp->if_timer = 0; 1144 if (!sc->sc_invalid) { 1145 if (sc->sc_softled) { 1146 callout_stop(&sc->sc_ledtimer); 1147 ath_hal_gpioset(ah, sc->sc_ledpin, 1148 !sc->sc_ledon); 1149 sc->sc_blinking = 0; 1150 } 1151 ath_hal_intrset(ah, 0); 1152 } 1153 ath_draintxq(sc); 1154 if (!sc->sc_invalid) { 1155 ath_stoprecv(sc); 1156 ath_hal_phydisable(ah); 1157 } else 1158 sc->sc_rxlink = NULL; 1159 IF_PURGE(&ifp->if_snd); 1160 ath_beacon_free(sc); 1161 if (disable) 1162 ath_disable(sc); 1163 } 1164 } 1165 1166 static void 1167 ath_stop(struct ifnet *ifp, int disable) 1168 { 1169 struct ath_softc *sc = ifp->if_softc; 1170 1171 ATH_LOCK(sc); 1172 ath_stop_locked(ifp, disable); 1173 if (!sc->sc_invalid) { 1174 /* 1175 * Set the chip in full sleep mode. Note that we are 1176 * careful to do this only when bringing the interface 1177 * completely to a stop. When the chip is in this state 1178 * it must be carefully woken up or references to 1179 * registers in the PCI clock domain may freeze the bus 1180 * (and system). This varies by chip and is mostly an 1181 * issue with newer parts that go to sleep more quickly. 1182 */ 1183 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1184 } 1185 ATH_UNLOCK(sc); 1186 } 1187 1188 /* 1189 * Reset the hardware w/o losing operational state. This is 1190 * basically a more efficient way of doing ath_stop, ath_init, 1191 * followed by state transitions to the current 802.11 1192 * operational state. Used to recover from various errors and 1193 * to reset or reload hardware state. 1194 */ 1195 int 1196 ath_reset(struct ifnet *ifp) 1197 { 1198 struct ath_softc *sc = ifp->if_softc; 1199 struct ieee80211com *ic = &sc->sc_ic; 1200 struct ath_hal *ah = sc->sc_ah; 1201 struct ieee80211_channel *c; 1202 HAL_STATUS status; 1203 1204 /* 1205 * Convert to a HAL channel description with the flags 1206 * constrained to reflect the current operating mode. 1207 */ 1208 c = ic->ic_curchan; 1209 sc->sc_curchan.channel = c->ic_freq; 1210 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1211 1212 ath_hal_intrset(ah, 0); /* disable interrupts */ 1213 ath_draintxq(sc); /* stop xmit side */ 1214 ath_stoprecv(sc); /* stop recv side */ 1215 /* NB: indicate channel change so we do a full reset */ 1216 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1217 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1218 __func__, status); 1219 ath_update_txpow(sc); /* update tx power state */ 1220 sc->sc_diversity = ath_hal_getdiversity(ah); 1221 sc->sc_calinterval = 1; 1222 sc->sc_caltries = 0; 1223 if (ath_startrecv(sc) != 0) /* restart recv */ 1224 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1225 /* 1226 * We may be doing a reset in response to an ioctl 1227 * that changes the channel so update any state that 1228 * might change as a result. 1229 */ 1230 ath_chan_change(sc, c); 1231 if (ic->ic_state == IEEE80211_S_RUN) 1232 ath_beacon_config(sc); /* restart beacons */ 1233 ath_hal_intrset(ah, sc->sc_imask); 1234 1235 ath_start(ifp); /* restart xmit */ 1236 return 0; 1237 } 1238 1239 /* 1240 * Cleanup driver resources when we run out of buffers 1241 * while processing fragments; return the tx buffers 1242 * allocated and drop node references. 1243 */ 1244 static void 1245 ath_txfrag_cleanup(struct ath_softc *sc, 1246 ath_bufhead *frags, struct ieee80211_node *ni) 1247 { 1248 struct ath_buf *bf; 1249 1250 ATH_TXBUF_LOCK_ASSERT(sc); 1251 1252 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1253 STAILQ_REMOVE_HEAD(frags, bf_list); 1254 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1255 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1256 ieee80211_node_decref(ni); 1257 } 1258 } 1259 1260 /* 1261 * Setup xmit of a fragmented frame. Allocate a buffer 1262 * for each frag and bump the node reference count to 1263 * reflect the held reference to be setup by ath_tx_start. 1264 */ 1265 static int 1266 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1267 struct mbuf *m0, struct ieee80211_node *ni) 1268 { 1269 struct mbuf *m; 1270 struct ath_buf *bf; 1271 1272 ATH_TXBUF_LOCK(sc); 1273 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1274 bf = STAILQ_FIRST(&sc->sc_txbuf); 1275 if (bf == NULL) { /* out of buffers, cleanup */ 1276 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1277 __func__); 1278 sc->sc_if.if_flags |= IFF_OACTIVE; 1279 ath_txfrag_cleanup(sc, frags, ni); 1280 break; 1281 } 1282 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1283 ieee80211_node_incref(ni); 1284 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1285 } 1286 ATH_TXBUF_UNLOCK(sc); 1287 1288 return !STAILQ_EMPTY(frags); 1289 } 1290 1291 static void 1292 ath_start(struct ifnet *ifp) 1293 { 1294 struct ath_softc *sc = ifp->if_softc; 1295 struct ath_hal *ah = sc->sc_ah; 1296 struct ieee80211com *ic = &sc->sc_ic; 1297 struct ieee80211_node *ni; 1298 struct ath_buf *bf; 1299 struct mbuf *m, *next; 1300 struct ieee80211_frame *wh; 1301 struct ether_header *eh; 1302 ath_bufhead frags; 1303 1304 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1305 return; 1306 for (;;) { 1307 /* 1308 * Grab a TX buffer and associated resources. 1309 */ 1310 ATH_TXBUF_LOCK(sc); 1311 bf = STAILQ_FIRST(&sc->sc_txbuf); 1312 if (bf != NULL) 1313 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1314 ATH_TXBUF_UNLOCK(sc); 1315 if (bf == NULL) { 1316 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1317 __func__); 1318 sc->sc_stats.ast_tx_qstop++; 1319 ifp->if_flags |= IFF_OACTIVE; 1320 break; 1321 } 1322 /* 1323 * Poll the management queue for frames; they 1324 * have priority over normal data frames. 1325 */ 1326 IF_DEQUEUE(&ic->ic_mgtq, m); 1327 if (m == NULL) { 1328 /* 1329 * No data frames go out unless we're associated. 1330 */ 1331 if (ic->ic_state != IEEE80211_S_RUN) { 1332 DPRINTF(sc, ATH_DEBUG_XMIT, 1333 "%s: discard data packet, state %s\n", 1334 __func__, 1335 ieee80211_state_name[ic->ic_state]); 1336 sc->sc_stats.ast_tx_discard++; 1337 ATH_TXBUF_LOCK(sc); 1338 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1339 ATH_TXBUF_UNLOCK(sc); 1340 break; 1341 } 1342 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1343 if (m == NULL) { 1344 ATH_TXBUF_LOCK(sc); 1345 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1346 ATH_TXBUF_UNLOCK(sc); 1347 break; 1348 } 1349 STAILQ_INIT(&frags); 1350 /* 1351 * Find the node for the destination so we can do 1352 * things like power save and fast frames aggregation. 1353 */ 1354 if (m->m_len < sizeof(struct ether_header) && 1355 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1356 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1357 ni = NULL; 1358 goto bad; 1359 } 1360 eh = mtod(m, struct ether_header *); 1361 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1362 if (ni == NULL) { 1363 /* NB: ieee80211_find_txnode does stat+msg */ 1364 m_freem(m); 1365 goto bad; 1366 } 1367 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1368 (m->m_flags & M_PWR_SAV) == 0) { 1369 /* 1370 * Station in power save mode; pass the frame 1371 * to the 802.11 layer and continue. We'll get 1372 * the frame back when the time is right. 1373 */ 1374 ieee80211_pwrsave(ic, ni, m); 1375 goto reclaim; 1376 } 1377 /* calculate priority so we can find the tx queue */ 1378 if (ieee80211_classify(ic, m, ni)) { 1379 DPRINTF(sc, ATH_DEBUG_XMIT, 1380 "%s: discard, classification failure\n", 1381 __func__); 1382 m_freem(m); 1383 goto bad; 1384 } 1385 ifp->if_opackets++; 1386 1387 #if NBPFILTER > 0 1388 if (ifp->if_bpf) 1389 bpf_mtap(ifp->if_bpf, m); 1390 #endif 1391 /* 1392 * Encapsulate the packet in prep for transmission. 1393 */ 1394 m = ieee80211_encap(ic, m, ni); 1395 if (m == NULL) { 1396 DPRINTF(sc, ATH_DEBUG_XMIT, 1397 "%s: encapsulation failure\n", 1398 __func__); 1399 sc->sc_stats.ast_tx_encap++; 1400 goto bad; 1401 } 1402 /* 1403 * Check for fragmentation. If this has frame 1404 * has been broken up verify we have enough 1405 * buffers to send all the fragments so all 1406 * go out or none... 1407 */ 1408 if ((m->m_flags & M_FRAG) && 1409 !ath_txfrag_setup(sc, &frags, m, ni)) { 1410 DPRINTF(sc, ATH_DEBUG_ANY, 1411 "%s: out of txfrag buffers\n", __func__); 1412 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1413 ath_freetx(m); 1414 goto bad; 1415 } 1416 } else { 1417 /* 1418 * Hack! The referenced node pointer is in the 1419 * rcvif field of the packet header. This is 1420 * placed there by ieee80211_mgmt_output because 1421 * we need to hold the reference with the frame 1422 * and there's no other way (other than packet 1423 * tags which we consider too expensive to use) 1424 * to pass it along. 1425 */ 1426 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1427 m->m_pkthdr.rcvif = NULL; 1428 1429 wh = mtod(m, struct ieee80211_frame *); 1430 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1431 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1432 /* fill time stamp */ 1433 u_int64_t tsf; 1434 u_int32_t *tstamp; 1435 1436 tsf = ath_hal_gettsf64(ah); 1437 /* XXX: adjust 100us delay to xmit */ 1438 tsf += 100; 1439 tstamp = (u_int32_t *)&wh[1]; 1440 tstamp[0] = htole32(tsf & 0xffffffff); 1441 tstamp[1] = htole32(tsf >> 32); 1442 } 1443 sc->sc_stats.ast_tx_mgmt++; 1444 } 1445 1446 nextfrag: 1447 next = m->m_nextpkt; 1448 if (ath_tx_start(sc, ni, bf, m)) { 1449 bad: 1450 ifp->if_oerrors++; 1451 reclaim: 1452 ATH_TXBUF_LOCK(sc); 1453 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1454 ath_txfrag_cleanup(sc, &frags, ni); 1455 ATH_TXBUF_UNLOCK(sc); 1456 if (ni != NULL) 1457 ieee80211_free_node(ni); 1458 continue; 1459 } 1460 if (next != NULL) { 1461 m = next; 1462 bf = STAILQ_FIRST(&frags); 1463 KASSERT(bf != NULL, ("no buf for txfrag")); 1464 STAILQ_REMOVE_HEAD(&frags, bf_list); 1465 goto nextfrag; 1466 } 1467 1468 ifp->if_timer = 1; 1469 } 1470 } 1471 1472 static int 1473 ath_media_change(struct ifnet *ifp) 1474 { 1475 #define IS_UP(ifp) \ 1476 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1477 int error; 1478 1479 error = ieee80211_media_change(ifp); 1480 if (error == ENETRESET) { 1481 if (IS_UP(ifp)) 1482 ath_init(ifp->if_softc); /* XXX lose error */ 1483 error = 0; 1484 } 1485 return error; 1486 #undef IS_UP 1487 } 1488 1489 #ifdef AR_DEBUG 1490 static void 1491 ath_keyprint(const char *tag, u_int ix, 1492 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1493 { 1494 static const char *ciphers[] = { 1495 "WEP", 1496 "AES-OCB", 1497 "AES-CCM", 1498 "CKIP", 1499 "TKIP", 1500 "CLR", 1501 }; 1502 int i, n; 1503 1504 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1505 for (i = 0, n = hk->kv_len; i < n; i++) 1506 printf("%02x", hk->kv_val[i]); 1507 printf(" mac %s", ether_sprintf(mac)); 1508 if (hk->kv_type == HAL_CIPHER_TKIP) { 1509 printf(" mic "); 1510 for (i = 0; i < sizeof(hk->kv_mic); i++) 1511 printf("%02x", hk->kv_mic[i]); 1512 } 1513 printf("\n"); 1514 } 1515 #endif 1516 1517 /* 1518 * Set a TKIP key into the hardware. This handles the 1519 * potential distribution of key state to multiple key 1520 * cache slots for TKIP. 1521 */ 1522 static int 1523 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1524 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1525 { 1526 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1527 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1528 struct ath_hal *ah = sc->sc_ah; 1529 1530 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1531 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1532 KASSERT(sc->sc_splitmic, ("key cache !split")); 1533 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1534 /* 1535 * TX key goes at first index, RX key at the rx index. 1536 * The hal handles the MIC keys at index+64. 1537 */ 1538 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1539 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1540 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1541 return 0; 1542 1543 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1544 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1545 /* XXX delete tx key on failure? */ 1546 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1547 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1548 /* 1549 * TX/RX key goes at first index. 1550 * The hal handles the MIC keys are index+64. 1551 */ 1552 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1553 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1554 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1555 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1556 } 1557 return 0; 1558 #undef IEEE80211_KEY_XR 1559 } 1560 1561 /* 1562 * Set a net80211 key into the hardware. This handles the 1563 * potential distribution of key state to multiple key 1564 * cache slots for TKIP with hardware MIC support. 1565 */ 1566 static int 1567 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1568 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1569 struct ieee80211_node *bss) 1570 { 1571 #define N(a) (sizeof(a)/sizeof(a[0])) 1572 static const u_int8_t ciphermap[] = { 1573 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1574 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1575 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1576 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1577 (u_int8_t) -1, /* 4 is not allocated */ 1578 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1579 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1580 }; 1581 struct ath_hal *ah = sc->sc_ah; 1582 const struct ieee80211_cipher *cip = k->wk_cipher; 1583 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1584 const u_int8_t *mac; 1585 HAL_KEYVAL hk; 1586 1587 memset(&hk, 0, sizeof(hk)); 1588 /* 1589 * Software crypto uses a "clear key" so non-crypto 1590 * state kept in the key cache are maintained and 1591 * so that rx frames have an entry to match. 1592 */ 1593 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1594 KASSERT(cip->ic_cipher < N(ciphermap), 1595 ("invalid cipher type %u", cip->ic_cipher)); 1596 hk.kv_type = ciphermap[cip->ic_cipher]; 1597 hk.kv_len = k->wk_keylen; 1598 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1599 } else 1600 hk.kv_type = HAL_CIPHER_CLR; 1601 1602 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1603 /* 1604 * Group keys on hardware that supports multicast frame 1605 * key search use a mac that is the sender's address with 1606 * the high bit set instead of the app-specified address. 1607 */ 1608 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1609 gmac[0] |= 0x80; 1610 mac = gmac; 1611 } else 1612 mac = mac0; 1613 1614 if (hk.kv_type == HAL_CIPHER_TKIP && 1615 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1616 sc->sc_splitmic) { 1617 return ath_keyset_tkip(sc, k, &hk, mac); 1618 } else { 1619 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1620 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1621 } 1622 #undef N 1623 } 1624 1625 /* 1626 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1627 * each key, one for decrypt/encrypt and the other for the MIC. 1628 */ 1629 static u_int16_t 1630 key_alloc_2pair(struct ath_softc *sc, 1631 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1632 { 1633 #define N(a) (sizeof(a)/sizeof(a[0])) 1634 u_int i, keyix; 1635 1636 KASSERT(sc->sc_splitmic, ("key cache !split")); 1637 /* XXX could optimize */ 1638 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1639 u_int8_t b = sc->sc_keymap[i]; 1640 if (b != 0xff) { 1641 /* 1642 * One or more slots in this byte are free. 1643 */ 1644 keyix = i*NBBY; 1645 while (b & 1) { 1646 again: 1647 keyix++; 1648 b >>= 1; 1649 } 1650 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1651 if (isset(sc->sc_keymap, keyix+32) || 1652 isset(sc->sc_keymap, keyix+64) || 1653 isset(sc->sc_keymap, keyix+32+64)) { 1654 /* full pair unavailable */ 1655 /* XXX statistic */ 1656 if (keyix == (i+1)*NBBY) { 1657 /* no slots were appropriate, advance */ 1658 continue; 1659 } 1660 goto again; 1661 } 1662 setbit(sc->sc_keymap, keyix); 1663 setbit(sc->sc_keymap, keyix+64); 1664 setbit(sc->sc_keymap, keyix+32); 1665 setbit(sc->sc_keymap, keyix+32+64); 1666 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1667 "%s: key pair %u,%u %u,%u\n", 1668 __func__, keyix, keyix+64, 1669 keyix+32, keyix+32+64); 1670 *txkeyix = keyix; 1671 *rxkeyix = keyix+32; 1672 return 1; 1673 } 1674 } 1675 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1676 return 0; 1677 #undef N 1678 } 1679 1680 /* 1681 * Allocate a single key cache slot. 1682 */ 1683 static int 1684 key_alloc_single(struct ath_softc *sc, 1685 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1686 { 1687 #define N(a) (sizeof(a)/sizeof(a[0])) 1688 u_int i, keyix; 1689 1690 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1691 for (i = 0; i < N(sc->sc_keymap); i++) { 1692 u_int8_t b = sc->sc_keymap[i]; 1693 if (b != 0xff) { 1694 /* 1695 * One or more slots are free. 1696 */ 1697 keyix = i*NBBY; 1698 while (b & 1) 1699 keyix++, b >>= 1; 1700 setbit(sc->sc_keymap, keyix); 1701 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1702 __func__, keyix); 1703 *txkeyix = *rxkeyix = keyix; 1704 return 1; 1705 } 1706 } 1707 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1708 return 0; 1709 #undef N 1710 } 1711 1712 /* 1713 * Allocate one or more key cache slots for a uniacst key. The 1714 * key itself is needed only to identify the cipher. For hardware 1715 * TKIP with split cipher+MIC keys we allocate two key cache slot 1716 * pairs so that we can setup separate TX and RX MIC keys. Note 1717 * that the MIC key for a TKIP key at slot i is assumed by the 1718 * hardware to be at slot i+64. This limits TKIP keys to the first 1719 * 64 entries. 1720 */ 1721 static int 1722 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1723 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1724 { 1725 struct ath_softc *sc = ic->ic_ifp->if_softc; 1726 1727 /* 1728 * Group key allocation must be handled specially for 1729 * parts that do not support multicast key cache search 1730 * functionality. For those parts the key id must match 1731 * the h/w key index so lookups find the right key. On 1732 * parts w/ the key search facility we install the sender's 1733 * mac address (with the high bit set) and let the hardware 1734 * find the key w/o using the key id. This is preferred as 1735 * it permits us to support multiple users for adhoc and/or 1736 * multi-station operation. 1737 */ 1738 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1739 if (!(&ic->ic_nw_keys[0] <= k && 1740 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1741 /* should not happen */ 1742 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1743 "%s: bogus group key\n", __func__); 1744 return 0; 1745 } 1746 /* 1747 * XXX we pre-allocate the global keys so 1748 * have no way to check if they've already been allocated. 1749 */ 1750 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1751 return 1; 1752 } 1753 1754 /* 1755 * We allocate two pair for TKIP when using the h/w to do 1756 * the MIC. For everything else, including software crypto, 1757 * we allocate a single entry. Note that s/w crypto requires 1758 * a pass-through slot on the 5211 and 5212. The 5210 does 1759 * not support pass-through cache entries and we map all 1760 * those requests to slot 0. 1761 */ 1762 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1763 return key_alloc_single(sc, keyix, rxkeyix); 1764 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1765 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1766 return key_alloc_2pair(sc, keyix, rxkeyix); 1767 } else { 1768 return key_alloc_single(sc, keyix, rxkeyix); 1769 } 1770 } 1771 1772 /* 1773 * Delete an entry in the key cache allocated by ath_key_alloc. 1774 */ 1775 static int 1776 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1777 { 1778 struct ath_softc *sc = ic->ic_ifp->if_softc; 1779 struct ath_hal *ah = sc->sc_ah; 1780 const struct ieee80211_cipher *cip = k->wk_cipher; 1781 u_int keyix = k->wk_keyix; 1782 1783 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1784 1785 ath_hal_keyreset(ah, keyix); 1786 /* 1787 * Handle split tx/rx keying required for TKIP with h/w MIC. 1788 */ 1789 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1790 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1791 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1792 if (keyix >= IEEE80211_WEP_NKID) { 1793 /* 1794 * Don't touch keymap entries for global keys so 1795 * they are never considered for dynamic allocation. 1796 */ 1797 clrbit(sc->sc_keymap, keyix); 1798 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1799 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1800 sc->sc_splitmic) { 1801 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1802 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1803 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1804 } 1805 } 1806 return 1; 1807 } 1808 1809 /* 1810 * Set the key cache contents for the specified key. Key cache 1811 * slot(s) must already have been allocated by ath_key_alloc. 1812 */ 1813 static int 1814 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1815 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1816 { 1817 struct ath_softc *sc = ic->ic_ifp->if_softc; 1818 1819 return ath_keyset(sc, k, mac, ic->ic_bss); 1820 } 1821 1822 /* 1823 * Block/unblock tx+rx processing while a key change is done. 1824 * We assume the caller serializes key management operations 1825 * so we only need to worry about synchronization with other 1826 * uses that originate in the driver. 1827 */ 1828 static void 1829 ath_key_update_begin(struct ieee80211com *ic) 1830 { 1831 struct ifnet *ifp = ic->ic_ifp; 1832 struct ath_softc *sc = ifp->if_softc; 1833 1834 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1835 #if 0 1836 tasklet_disable(&sc->sc_rxtq); 1837 #endif 1838 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1839 } 1840 1841 static void 1842 ath_key_update_end(struct ieee80211com *ic) 1843 { 1844 struct ifnet *ifp = ic->ic_ifp; 1845 struct ath_softc *sc = ifp->if_softc; 1846 1847 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1848 IF_UNLOCK(&ifp->if_snd); 1849 #if 0 1850 tasklet_enable(&sc->sc_rxtq); 1851 #endif 1852 } 1853 1854 /* 1855 * Calculate the receive filter according to the 1856 * operating mode and state: 1857 * 1858 * o always accept unicast, broadcast, and multicast traffic 1859 * o maintain current state of phy error reception (the hal 1860 * may enable phy error frames for noise immunity work) 1861 * o probe request frames are accepted only when operating in 1862 * hostap, adhoc, or monitor modes 1863 * o enable promiscuous mode according to the interface state 1864 * o accept beacons: 1865 * - when operating in adhoc mode so the 802.11 layer creates 1866 * node table entries for peers, 1867 * - when operating in station mode for collecting rssi data when 1868 * the station is otherwise quiet, or 1869 * - when scanning 1870 */ 1871 static u_int32_t 1872 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1873 { 1874 struct ieee80211com *ic = &sc->sc_ic; 1875 struct ath_hal *ah = sc->sc_ah; 1876 struct ifnet *ifp = &sc->sc_if; 1877 u_int32_t rfilt; 1878 1879 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1880 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1881 if (ic->ic_opmode != IEEE80211_M_STA) 1882 rfilt |= HAL_RX_FILTER_PROBEREQ; 1883 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1884 (ifp->if_flags & IFF_PROMISC)) 1885 rfilt |= HAL_RX_FILTER_PROM; 1886 if (ic->ic_opmode == IEEE80211_M_STA || 1887 ic->ic_opmode == IEEE80211_M_IBSS || 1888 state == IEEE80211_S_SCAN) 1889 rfilt |= HAL_RX_FILTER_BEACON; 1890 return rfilt; 1891 } 1892 1893 static void 1894 ath_mcastfilter_accum(void *dl, u_int32_t *mfilt) 1895 { 1896 u_int32_t val; 1897 u_int8_t pos; 1898 1899 /* calculate XOR of eight 6bit values */ 1900 val = LE_READ_4((char *)dl + 0); 1901 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1902 val = LE_READ_4((char *)dl + 3); 1903 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1904 pos &= 0x3f; 1905 mfilt[pos / 32] |= (1 << (pos % 32)); 1906 } 1907 1908 static void 1909 ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1910 { 1911 struct ifnet *ifp = &sc->sc_if; 1912 struct ether_multi *enm; 1913 struct ether_multistep estep; 1914 1915 mfilt[0] = mfilt[1] = 0; 1916 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1917 while (enm != NULL) { 1918 /* XXX Punt on ranges. */ 1919 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1920 mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1921 ifp->if_flags |= IFF_ALLMULTI; 1922 return; 1923 } 1924 ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1925 ETHER_NEXT_MULTI(estep, enm); 1926 } 1927 ifp->if_flags &= ~IFF_ALLMULTI; 1928 } 1929 1930 static void 1931 ath_mode_init(struct ath_softc *sc) 1932 { 1933 struct ieee80211com *ic = &sc->sc_ic; 1934 struct ath_hal *ah = sc->sc_ah; 1935 u_int32_t rfilt, mfilt[2]; 1936 int i; 1937 1938 /* configure rx filter */ 1939 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1940 ath_hal_setrxfilter(ah, rfilt); 1941 1942 /* configure operational mode */ 1943 ath_hal_setopmode(ah); 1944 1945 /* Write keys to hardware; it may have been powered down. */ 1946 ath_key_update_begin(ic); 1947 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1948 ath_key_set(ic, 1949 &ic->ic_crypto.cs_nw_keys[i], 1950 ic->ic_myaddr); 1951 } 1952 ath_key_update_end(ic); 1953 1954 /* 1955 * Handle any link-level address change. Note that we only 1956 * need to force ic_myaddr; any other addresses are handled 1957 * as a byproduct of the ifnet code marking the interface 1958 * down then up. 1959 * 1960 * XXX should get from lladdr instead of arpcom but that's more work 1961 */ 1962 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1963 ath_hal_setmac(ah, ic->ic_myaddr); 1964 1965 /* calculate and install multicast filter */ 1966 #ifdef __FreeBSD__ 1967 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1968 mfilt[0] = mfilt[1] = 0; 1969 IF_ADDR_LOCK(ifp); 1970 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1971 void *dl; 1972 1973 /* calculate XOR of eight 6bit values */ 1974 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1975 val = LE_READ_4((char *)dl + 0); 1976 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1977 val = LE_READ_4((char *)dl + 3); 1978 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1979 pos &= 0x3f; 1980 mfilt[pos / 32] |= (1 << (pos % 32)); 1981 } 1982 IF_ADDR_UNLOCK(ifp); 1983 } else { 1984 mfilt[0] = mfilt[1] = ~0; 1985 } 1986 #endif 1987 #ifdef __NetBSD__ 1988 ath_mcastfilter_compute(sc, mfilt); 1989 #endif 1990 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1991 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1992 __func__, rfilt, mfilt[0], mfilt[1]); 1993 } 1994 1995 /* 1996 * Set the slot time based on the current setting. 1997 */ 1998 static void 1999 ath_setslottime(struct ath_softc *sc) 2000 { 2001 struct ieee80211com *ic = &sc->sc_ic; 2002 struct ath_hal *ah = sc->sc_ah; 2003 2004 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2005 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2006 else 2007 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2008 sc->sc_updateslot = OK; 2009 } 2010 2011 /* 2012 * Callback from the 802.11 layer to update the 2013 * slot time based on the current setting. 2014 */ 2015 static void 2016 ath_updateslot(struct ifnet *ifp) 2017 { 2018 struct ath_softc *sc = ifp->if_softc; 2019 struct ieee80211com *ic = &sc->sc_ic; 2020 2021 /* 2022 * When not coordinating the BSS, change the hardware 2023 * immediately. For other operation we defer the change 2024 * until beacon updates have propagated to the stations. 2025 */ 2026 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2027 sc->sc_updateslot = UPDATE; 2028 else 2029 ath_setslottime(sc); 2030 } 2031 2032 /* 2033 * Setup a h/w transmit queue for beacons. 2034 */ 2035 static int 2036 ath_beaconq_setup(struct ath_hal *ah) 2037 { 2038 HAL_TXQ_INFO qi; 2039 2040 memset(&qi, 0, sizeof(qi)); 2041 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2042 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2043 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2044 /* NB: for dynamic turbo, don't enable any other interrupts */ 2045 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2046 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2047 } 2048 2049 /* 2050 * Setup the transmit queue parameters for the beacon queue. 2051 */ 2052 static int 2053 ath_beaconq_config(struct ath_softc *sc) 2054 { 2055 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2056 struct ieee80211com *ic = &sc->sc_ic; 2057 struct ath_hal *ah = sc->sc_ah; 2058 HAL_TXQ_INFO qi; 2059 2060 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2061 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2062 /* 2063 * Always burst out beacon and CAB traffic. 2064 */ 2065 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2066 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2067 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2068 } else { 2069 struct wmeParams *wmep = 2070 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2071 /* 2072 * Adhoc mode; important thing is to use 2x cwmin. 2073 */ 2074 qi.tqi_aifs = wmep->wmep_aifsn; 2075 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2076 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2077 } 2078 2079 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2080 device_printf(sc->sc_dev, "unable to update parameters for " 2081 "beacon hardware queue!\n"); 2082 return 0; 2083 } else { 2084 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2085 return 1; 2086 } 2087 #undef ATH_EXPONENT_TO_VALUE 2088 } 2089 2090 /* 2091 * Allocate and setup an initial beacon frame. 2092 */ 2093 static int 2094 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2095 { 2096 struct ieee80211com *ic = ni->ni_ic; 2097 struct ath_buf *bf; 2098 struct mbuf *m; 2099 int error; 2100 2101 bf = STAILQ_FIRST(&sc->sc_bbuf); 2102 if (bf == NULL) { 2103 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2104 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2105 return ENOMEM; /* XXX */ 2106 } 2107 /* 2108 * NB: the beacon data buffer must be 32-bit aligned; 2109 * we assume the mbuf routines will return us something 2110 * with this alignment (perhaps should assert). 2111 */ 2112 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2113 if (m == NULL) { 2114 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2115 __func__); 2116 sc->sc_stats.ast_be_nombuf++; 2117 return ENOMEM; 2118 } 2119 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2120 BUS_DMA_NOWAIT); 2121 if (error == 0) { 2122 bf->bf_m = m; 2123 bf->bf_node = ieee80211_ref_node(ni); 2124 } else { 2125 m_freem(m); 2126 } 2127 return error; 2128 } 2129 2130 /* 2131 * Setup the beacon frame for transmit. 2132 */ 2133 static void 2134 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2135 { 2136 #define USE_SHPREAMBLE(_ic) \ 2137 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2138 == IEEE80211_F_SHPREAMBLE) 2139 struct ieee80211_node *ni = bf->bf_node; 2140 struct ieee80211com *ic = ni->ni_ic; 2141 struct mbuf *m = bf->bf_m; 2142 struct ath_hal *ah = sc->sc_ah; 2143 struct ath_desc *ds; 2144 int flags, antenna; 2145 const HAL_RATE_TABLE *rt; 2146 u_int8_t rix, rate; 2147 2148 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2149 __func__, m, m->m_len); 2150 2151 /* setup descriptors */ 2152 ds = bf->bf_desc; 2153 2154 flags = HAL_TXDESC_NOACK; 2155 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2156 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2157 flags |= HAL_TXDESC_VEOL; 2158 /* 2159 * Let hardware handle antenna switching unless 2160 * the user has selected a transmit antenna 2161 * (sc_txantenna is not 0). 2162 */ 2163 antenna = sc->sc_txantenna; 2164 } else { 2165 ds->ds_link = 0; 2166 /* 2167 * Switch antenna every 4 beacons, unless the user 2168 * has selected a transmit antenna (sc_txantenna 2169 * is not 0). 2170 * 2171 * XXX assumes two antenna 2172 */ 2173 if (sc->sc_txantenna == 0) 2174 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2175 else 2176 antenna = sc->sc_txantenna; 2177 } 2178 2179 KASSERT(bf->bf_nseg == 1, 2180 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2181 ds->ds_data = bf->bf_segs[0].ds_addr; 2182 /* 2183 * Calculate rate code. 2184 * XXX everything at min xmit rate 2185 */ 2186 rix = sc->sc_minrateix; 2187 rt = sc->sc_currates; 2188 rate = rt->info[rix].rateCode; 2189 if (USE_SHPREAMBLE(ic)) 2190 rate |= rt->info[rix].shortPreamble; 2191 ath_hal_setuptxdesc(ah, ds 2192 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2193 , sizeof(struct ieee80211_frame)/* header length */ 2194 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2195 , ni->ni_txpower /* txpower XXX */ 2196 , rate, 1 /* series 0 rate/tries */ 2197 , HAL_TXKEYIX_INVALID /* no encryption */ 2198 , antenna /* antenna mode */ 2199 , flags /* no ack, veol for beacons */ 2200 , 0 /* rts/cts rate */ 2201 , 0 /* rts/cts duration */ 2202 ); 2203 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2204 ath_hal_filltxdesc(ah, ds 2205 , roundup(m->m_len, 4) /* buffer length */ 2206 , AH_TRUE /* first segment */ 2207 , AH_TRUE /* last segment */ 2208 , ds /* first descriptor */ 2209 ); 2210 2211 /* NB: The desc swap function becomes void, 2212 * if descriptor swapping is not enabled 2213 */ 2214 ath_desc_swap(ds); 2215 2216 #undef USE_SHPREAMBLE 2217 } 2218 2219 /* 2220 * Transmit a beacon frame at SWBA. Dynamic updates to the 2221 * frame contents are done as needed and the slot time is 2222 * also adjusted based on current state. 2223 */ 2224 static void 2225 ath_beacon_proc(void *arg, int pending) 2226 { 2227 struct ath_softc *sc = arg; 2228 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2229 struct ieee80211_node *ni = bf->bf_node; 2230 struct ieee80211com *ic = ni->ni_ic; 2231 struct ath_hal *ah = sc->sc_ah; 2232 struct mbuf *m; 2233 int ncabq, error, otherant; 2234 2235 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2236 __func__, pending); 2237 2238 if (ic->ic_opmode == IEEE80211_M_STA || 2239 ic->ic_opmode == IEEE80211_M_MONITOR || 2240 bf == NULL || bf->bf_m == NULL) { 2241 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2242 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2243 return; 2244 } 2245 /* 2246 * Check if the previous beacon has gone out. If 2247 * not don't try to post another, skip this period 2248 * and wait for the next. Missed beacons indicate 2249 * a problem and should not occur. If we miss too 2250 * many consecutive beacons reset the device. 2251 */ 2252 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2253 sc->sc_bmisscount++; 2254 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2255 "%s: missed %u consecutive beacons\n", 2256 __func__, sc->sc_bmisscount); 2257 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2258 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2259 return; 2260 } 2261 if (sc->sc_bmisscount != 0) { 2262 DPRINTF(sc, ATH_DEBUG_BEACON, 2263 "%s: resume beacon xmit after %u misses\n", 2264 __func__, sc->sc_bmisscount); 2265 sc->sc_bmisscount = 0; 2266 } 2267 2268 /* 2269 * Update dynamic beacon contents. If this returns 2270 * non-zero then we need to remap the memory because 2271 * the beacon frame changed size (probably because 2272 * of the TIM bitmap). 2273 */ 2274 m = bf->bf_m; 2275 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2276 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2277 /* XXX too conservative? */ 2278 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2279 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2280 BUS_DMA_NOWAIT); 2281 if (error != 0) { 2282 if_printf(&sc->sc_if, 2283 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2284 __func__, error); 2285 return; 2286 } 2287 } 2288 2289 /* 2290 * Handle slot time change when a non-ERP station joins/leaves 2291 * an 11g network. The 802.11 layer notifies us via callback, 2292 * we mark updateslot, then wait one beacon before effecting 2293 * the change. This gives associated stations at least one 2294 * beacon interval to note the state change. 2295 */ 2296 /* XXX locking */ 2297 if (sc->sc_updateslot == UPDATE) 2298 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2299 else if (sc->sc_updateslot == COMMIT) 2300 ath_setslottime(sc); /* commit change to h/w */ 2301 2302 /* 2303 * Check recent per-antenna transmit statistics and flip 2304 * the default antenna if noticeably more frames went out 2305 * on the non-default antenna. 2306 * XXX assumes 2 anntenae 2307 */ 2308 otherant = sc->sc_defant & 1 ? 2 : 1; 2309 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2310 ath_setdefantenna(sc, otherant); 2311 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2312 2313 /* 2314 * Construct tx descriptor. 2315 */ 2316 ath_beacon_setup(sc, bf); 2317 2318 /* 2319 * Stop any current dma and put the new frame on the queue. 2320 * This should never fail since we check above that no frames 2321 * are still pending on the queue. 2322 */ 2323 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2324 DPRINTF(sc, ATH_DEBUG_ANY, 2325 "%s: beacon queue %u did not stop?\n", 2326 __func__, sc->sc_bhalq); 2327 } 2328 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2329 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2330 2331 /* 2332 * Enable the CAB queue before the beacon queue to 2333 * insure cab frames are triggered by this beacon. 2334 */ 2335 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2336 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2337 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2338 ath_hal_txstart(ah, sc->sc_bhalq); 2339 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2340 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2341 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2342 2343 sc->sc_stats.ast_be_xmit++; 2344 } 2345 2346 /* 2347 * Reset the hardware after detecting beacons have stopped. 2348 */ 2349 static void 2350 ath_bstuck_proc(void *arg, int pending) 2351 { 2352 struct ath_softc *sc = arg; 2353 struct ifnet *ifp = &sc->sc_if; 2354 2355 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2356 sc->sc_bmisscount); 2357 ath_reset(ifp); 2358 } 2359 2360 /* 2361 * Reclaim beacon resources. 2362 */ 2363 static void 2364 ath_beacon_free(struct ath_softc *sc) 2365 { 2366 struct ath_buf *bf; 2367 2368 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2369 if (bf->bf_m != NULL) { 2370 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2371 m_freem(bf->bf_m); 2372 bf->bf_m = NULL; 2373 } 2374 if (bf->bf_node != NULL) { 2375 ieee80211_free_node(bf->bf_node); 2376 bf->bf_node = NULL; 2377 } 2378 } 2379 } 2380 2381 /* 2382 * Configure the beacon and sleep timers. 2383 * 2384 * When operating as an AP this resets the TSF and sets 2385 * up the hardware to notify us when we need to issue beacons. 2386 * 2387 * When operating in station mode this sets up the beacon 2388 * timers according to the timestamp of the last received 2389 * beacon and the current TSF, configures PCF and DTIM 2390 * handling, programs the sleep registers so the hardware 2391 * will wakeup in time to receive beacons, and configures 2392 * the beacon miss handling so we'll receive a BMISS 2393 * interrupt when we stop seeing beacons from the AP 2394 * we've associated with. 2395 */ 2396 static void 2397 ath_beacon_config(struct ath_softc *sc) 2398 { 2399 #define TSF_TO_TU(_h,_l) \ 2400 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2401 #define FUDGE 2 2402 struct ath_hal *ah = sc->sc_ah; 2403 struct ieee80211com *ic = &sc->sc_ic; 2404 struct ieee80211_node *ni = ic->ic_bss; 2405 u_int32_t nexttbtt, intval, tsftu; 2406 u_int64_t tsf; 2407 2408 /* extract tstamp from last beacon and convert to TU */ 2409 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2410 LE_READ_4(ni->ni_tstamp.data)); 2411 /* NB: the beacon interval is kept internally in TU's */ 2412 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2413 if (nexttbtt == 0) /* e.g. for ap mode */ 2414 nexttbtt = intval; 2415 else if (intval) /* NB: can be 0 for monitor mode */ 2416 nexttbtt = roundup(nexttbtt, intval); 2417 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2418 __func__, nexttbtt, intval, ni->ni_intval); 2419 if (ic->ic_opmode == IEEE80211_M_STA) { 2420 HAL_BEACON_STATE bs; 2421 int dtimperiod, dtimcount; 2422 int cfpperiod, cfpcount; 2423 2424 /* 2425 * Setup dtim and cfp parameters according to 2426 * last beacon we received (which may be none). 2427 */ 2428 dtimperiod = ni->ni_dtim_period; 2429 if (dtimperiod <= 0) /* NB: 0 if not known */ 2430 dtimperiod = 1; 2431 dtimcount = ni->ni_dtim_count; 2432 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2433 dtimcount = 0; /* XXX? */ 2434 cfpperiod = 1; /* NB: no PCF support yet */ 2435 cfpcount = 0; 2436 /* 2437 * Pull nexttbtt forward to reflect the current 2438 * TSF and calculate dtim+cfp state for the result. 2439 */ 2440 tsf = ath_hal_gettsf64(ah); 2441 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2442 do { 2443 nexttbtt += intval; 2444 if (--dtimcount < 0) { 2445 dtimcount = dtimperiod - 1; 2446 if (--cfpcount < 0) 2447 cfpcount = cfpperiod - 1; 2448 } 2449 } while (nexttbtt < tsftu); 2450 memset(&bs, 0, sizeof(bs)); 2451 bs.bs_intval = intval; 2452 bs.bs_nexttbtt = nexttbtt; 2453 bs.bs_dtimperiod = dtimperiod*intval; 2454 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2455 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2456 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2457 bs.bs_cfpmaxduration = 0; 2458 #if 0 2459 /* 2460 * The 802.11 layer records the offset to the DTIM 2461 * bitmap while receiving beacons; use it here to 2462 * enable h/w detection of our AID being marked in 2463 * the bitmap vector (to indicate frames for us are 2464 * pending at the AP). 2465 * XXX do DTIM handling in s/w to WAR old h/w bugs 2466 * XXX enable based on h/w rev for newer chips 2467 */ 2468 bs.bs_timoffset = ni->ni_timoff; 2469 #endif 2470 /* 2471 * Calculate the number of consecutive beacons to miss 2472 * before taking a BMISS interrupt. The configuration 2473 * is specified in ms, so we need to convert that to 2474 * TU's and then calculate based on the beacon interval. 2475 * Note that we clamp the result to at most 10 beacons. 2476 */ 2477 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2478 if (bs.bs_bmissthreshold > 10) 2479 bs.bs_bmissthreshold = 10; 2480 else if (bs.bs_bmissthreshold <= 0) 2481 bs.bs_bmissthreshold = 1; 2482 2483 /* 2484 * Calculate sleep duration. The configuration is 2485 * given in ms. We insure a multiple of the beacon 2486 * period is used. Also, if the sleep duration is 2487 * greater than the DTIM period then it makes senses 2488 * to make it a multiple of that. 2489 * 2490 * XXX fixed at 100ms 2491 */ 2492 bs.bs_sleepduration = 2493 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2494 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2495 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2496 2497 DPRINTF(sc, ATH_DEBUG_BEACON, 2498 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2499 , __func__ 2500 , tsf, tsftu 2501 , bs.bs_intval 2502 , bs.bs_nexttbtt 2503 , bs.bs_dtimperiod 2504 , bs.bs_nextdtim 2505 , bs.bs_bmissthreshold 2506 , bs.bs_sleepduration 2507 , bs.bs_cfpperiod 2508 , bs.bs_cfpmaxduration 2509 , bs.bs_cfpnext 2510 , bs.bs_timoffset 2511 ); 2512 ath_hal_intrset(ah, 0); 2513 ath_hal_beacontimers(ah, &bs); 2514 sc->sc_imask |= HAL_INT_BMISS; 2515 ath_hal_intrset(ah, sc->sc_imask); 2516 } else { 2517 ath_hal_intrset(ah, 0); 2518 if (nexttbtt == intval) 2519 intval |= HAL_BEACON_RESET_TSF; 2520 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2521 /* 2522 * In IBSS mode enable the beacon timers but only 2523 * enable SWBA interrupts if we need to manually 2524 * prepare beacon frames. Otherwise we use a 2525 * self-linked tx descriptor and let the hardware 2526 * deal with things. 2527 */ 2528 intval |= HAL_BEACON_ENA; 2529 if (!sc->sc_hasveol) 2530 sc->sc_imask |= HAL_INT_SWBA; 2531 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2532 /* 2533 * Pull nexttbtt forward to reflect 2534 * the current TSF. 2535 */ 2536 tsf = ath_hal_gettsf64(ah); 2537 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2538 do { 2539 nexttbtt += intval; 2540 } while (nexttbtt < tsftu); 2541 } 2542 ath_beaconq_config(sc); 2543 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2544 /* 2545 * In AP mode we enable the beacon timers and 2546 * SWBA interrupts to prepare beacon frames. 2547 */ 2548 intval |= HAL_BEACON_ENA; 2549 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2550 ath_beaconq_config(sc); 2551 } 2552 ath_hal_beaconinit(ah, nexttbtt, intval); 2553 sc->sc_bmisscount = 0; 2554 ath_hal_intrset(ah, sc->sc_imask); 2555 /* 2556 * When using a self-linked beacon descriptor in 2557 * ibss mode load it once here. 2558 */ 2559 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2560 ath_beacon_proc(sc, 0); 2561 } 2562 sc->sc_syncbeacon = 0; 2563 #undef UNDEF 2564 #undef TSF_TO_TU 2565 } 2566 2567 static int 2568 ath_descdma_setup(struct ath_softc *sc, 2569 struct ath_descdma *dd, ath_bufhead *head, 2570 const char *name, int nbuf, int ndesc) 2571 { 2572 #define DS2PHYS(_dd, _ds) \ 2573 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2574 struct ifnet *ifp = &sc->sc_if; 2575 struct ath_desc *ds; 2576 struct ath_buf *bf; 2577 int i, bsize, error; 2578 2579 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2580 __func__, name, nbuf, ndesc); 2581 2582 dd->dd_name = name; 2583 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2584 2585 /* 2586 * Setup DMA descriptor area. 2587 */ 2588 dd->dd_dmat = sc->sc_dmat; 2589 2590 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2591 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2592 2593 if (error != 0) { 2594 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2595 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2596 goto fail0; 2597 } 2598 2599 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2600 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2601 if (error != 0) { 2602 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2603 nbuf * ndesc, dd->dd_name, error); 2604 goto fail1; 2605 } 2606 2607 /* allocate descriptors */ 2608 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2609 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2610 if (error != 0) { 2611 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2612 "error %u\n", dd->dd_name, error); 2613 goto fail2; 2614 } 2615 2616 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2617 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2618 if (error != 0) { 2619 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2620 dd->dd_name, error); 2621 goto fail3; 2622 } 2623 2624 ds = dd->dd_desc; 2625 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2626 DPRINTF(sc, ATH_DEBUG_RESET, 2627 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2628 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2629 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2630 2631 /* allocate rx buffers */ 2632 bsize = sizeof(struct ath_buf) * nbuf; 2633 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2634 if (bf == NULL) { 2635 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2636 dd->dd_name, bsize); 2637 goto fail4; 2638 } 2639 dd->dd_bufptr = bf; 2640 2641 STAILQ_INIT(head); 2642 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2643 bf->bf_desc = ds; 2644 bf->bf_daddr = DS2PHYS(dd, ds); 2645 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2646 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2647 if (error != 0) { 2648 if_printf(ifp, "unable to create dmamap for %s " 2649 "buffer %u, error %u\n", dd->dd_name, i, error); 2650 ath_descdma_cleanup(sc, dd, head); 2651 return error; 2652 } 2653 STAILQ_INSERT_TAIL(head, bf, bf_list); 2654 } 2655 return 0; 2656 fail4: 2657 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2658 fail3: 2659 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2660 fail2: 2661 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2662 fail1: 2663 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2664 fail0: 2665 memset(dd, 0, sizeof(*dd)); 2666 return error; 2667 #undef DS2PHYS 2668 } 2669 2670 static void 2671 ath_descdma_cleanup(struct ath_softc *sc, 2672 struct ath_descdma *dd, ath_bufhead *head) 2673 { 2674 struct ath_buf *bf; 2675 struct ieee80211_node *ni; 2676 2677 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2678 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2679 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2680 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2681 2682 STAILQ_FOREACH(bf, head, bf_list) { 2683 if (bf->bf_m) { 2684 m_freem(bf->bf_m); 2685 bf->bf_m = NULL; 2686 } 2687 if (bf->bf_dmamap != NULL) { 2688 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2689 bf->bf_dmamap = NULL; 2690 } 2691 ni = bf->bf_node; 2692 bf->bf_node = NULL; 2693 if (ni != NULL) { 2694 /* 2695 * Reclaim node reference. 2696 */ 2697 ieee80211_free_node(ni); 2698 } 2699 } 2700 2701 STAILQ_INIT(head); 2702 free(dd->dd_bufptr, M_ATHDEV); 2703 memset(dd, 0, sizeof(*dd)); 2704 } 2705 2706 static int 2707 ath_desc_alloc(struct ath_softc *sc) 2708 { 2709 int error; 2710 2711 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2712 "rx", ath_rxbuf, 1); 2713 if (error != 0) 2714 return error; 2715 2716 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2717 "tx", ath_txbuf, ATH_TXDESC); 2718 if (error != 0) { 2719 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2720 return error; 2721 } 2722 2723 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2724 "beacon", 1, 1); 2725 if (error != 0) { 2726 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2727 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2728 return error; 2729 } 2730 return 0; 2731 } 2732 2733 static void 2734 ath_desc_free(struct ath_softc *sc) 2735 { 2736 2737 if (sc->sc_bdma.dd_desc_len != 0) 2738 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2739 if (sc->sc_txdma.dd_desc_len != 0) 2740 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2741 if (sc->sc_rxdma.dd_desc_len != 0) 2742 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2743 } 2744 2745 static struct ieee80211_node * 2746 ath_node_alloc(struct ieee80211_node_table *nt) 2747 { 2748 struct ieee80211com *ic = nt->nt_ic; 2749 struct ath_softc *sc = ic->ic_ifp->if_softc; 2750 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2751 struct ath_node *an; 2752 2753 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2754 if (an == NULL) { 2755 /* XXX stat+msg */ 2756 return NULL; 2757 } 2758 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2759 ath_rate_node_init(sc, an); 2760 2761 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2762 return &an->an_node; 2763 } 2764 2765 static void 2766 ath_node_free(struct ieee80211_node *ni) 2767 { 2768 struct ieee80211com *ic = ni->ni_ic; 2769 struct ath_softc *sc = ic->ic_ifp->if_softc; 2770 2771 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2772 2773 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2774 sc->sc_node_free(ni); 2775 } 2776 2777 static u_int8_t 2778 ath_node_getrssi(const struct ieee80211_node *ni) 2779 { 2780 #define HAL_EP_RND(x, mul) \ 2781 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2782 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2783 int32_t rssi; 2784 2785 /* 2786 * When only one frame is received there will be no state in 2787 * avgrssi so fallback on the value recorded by the 802.11 layer. 2788 */ 2789 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2790 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2791 else 2792 rssi = ni->ni_rssi; 2793 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2794 #undef HAL_EP_RND 2795 } 2796 2797 static int 2798 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2799 { 2800 struct ath_hal *ah = sc->sc_ah; 2801 int error; 2802 struct mbuf *m; 2803 struct ath_desc *ds; 2804 2805 m = bf->bf_m; 2806 if (m == NULL) { 2807 /* 2808 * NB: by assigning a page to the rx dma buffer we 2809 * implicitly satisfy the Atheros requirement that 2810 * this buffer be cache-line-aligned and sized to be 2811 * multiple of the cache line size. Not doing this 2812 * causes weird stuff to happen (for the 5210 at least). 2813 */ 2814 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2815 if (m == NULL) { 2816 DPRINTF(sc, ATH_DEBUG_ANY, 2817 "%s: no mbuf/cluster\n", __func__); 2818 sc->sc_stats.ast_rx_nombuf++; 2819 return ENOMEM; 2820 } 2821 bf->bf_m = m; 2822 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2823 2824 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2825 bf->bf_dmamap, m, 2826 BUS_DMA_NOWAIT); 2827 if (error != 0) { 2828 DPRINTF(sc, ATH_DEBUG_ANY, 2829 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2830 __func__, error); 2831 sc->sc_stats.ast_rx_busdma++; 2832 return error; 2833 } 2834 KASSERT(bf->bf_nseg == 1, 2835 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2836 } 2837 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2838 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2839 2840 /* 2841 * Setup descriptors. For receive we always terminate 2842 * the descriptor list with a self-linked entry so we'll 2843 * not get overrun under high load (as can happen with a 2844 * 5212 when ANI processing enables PHY error frames). 2845 * 2846 * To insure the last descriptor is self-linked we create 2847 * each descriptor as self-linked and add it to the end. As 2848 * each additional descriptor is added the previous self-linked 2849 * entry is ``fixed'' naturally. This should be safe even 2850 * if DMA is happening. When processing RX interrupts we 2851 * never remove/process the last, self-linked, entry on the 2852 * descriptor list. This insures the hardware always has 2853 * someplace to write a new frame. 2854 */ 2855 ds = bf->bf_desc; 2856 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2857 ds->ds_data = bf->bf_segs[0].ds_addr; 2858 ds->ds_vdata = mtod(m, void *); /* for radar */ 2859 ath_hal_setuprxdesc(ah, ds 2860 , m->m_len /* buffer size */ 2861 , 0 2862 ); 2863 2864 if (sc->sc_rxlink != NULL) 2865 *sc->sc_rxlink = bf->bf_daddr; 2866 sc->sc_rxlink = &ds->ds_link; 2867 return 0; 2868 } 2869 2870 /* 2871 * Extend 15-bit time stamp from rx descriptor to 2872 * a full 64-bit TSF using the specified TSF. 2873 */ 2874 static inline u_int64_t 2875 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2876 { 2877 if ((tsf & 0x7fff) < rstamp) 2878 tsf -= 0x8000; 2879 return ((tsf &~ 0x7fff) | rstamp); 2880 } 2881 2882 /* 2883 * Intercept management frames to collect beacon rssi data 2884 * and to do ibss merges. 2885 */ 2886 static void 2887 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2888 struct ieee80211_node *ni, 2889 int subtype, int rssi, u_int32_t rstamp) 2890 { 2891 struct ath_softc *sc = ic->ic_ifp->if_softc; 2892 2893 /* 2894 * Call up first so subsequent work can use information 2895 * potentially stored in the node (e.g. for ibss merge). 2896 */ 2897 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2898 switch (subtype) { 2899 case IEEE80211_FC0_SUBTYPE_BEACON: 2900 /* update rssi statistics for use by the hal */ 2901 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2902 if (sc->sc_syncbeacon && 2903 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2904 /* 2905 * Resync beacon timers using the tsf of the beacon 2906 * frame we just received. 2907 */ 2908 ath_beacon_config(sc); 2909 } 2910 /* fall thru... */ 2911 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2912 if (ic->ic_opmode == IEEE80211_M_IBSS && 2913 ic->ic_state == IEEE80211_S_RUN) { 2914 u_int64_t tsf = ath_extend_tsf(rstamp, 2915 ath_hal_gettsf64(sc->sc_ah)); 2916 2917 /* 2918 * Handle ibss merge as needed; check the tsf on the 2919 * frame before attempting the merge. The 802.11 spec 2920 * says the station should change it's bssid to match 2921 * the oldest station with the same ssid, where oldest 2922 * is determined by the tsf. Note that hardware 2923 * reconfiguration happens through callback to 2924 * ath_newstate as the state machine will go from 2925 * RUN -> RUN when this happens. 2926 */ 2927 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2928 DPRINTF(sc, ATH_DEBUG_STATE, 2929 "ibss merge, rstamp %u tsf %ju " 2930 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2931 (uintmax_t)ni->ni_tstamp.tsf); 2932 (void) ieee80211_ibss_merge(ni); 2933 } 2934 } 2935 break; 2936 } 2937 } 2938 2939 /* 2940 * Set the default antenna. 2941 */ 2942 static void 2943 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2944 { 2945 struct ath_hal *ah = sc->sc_ah; 2946 2947 /* XXX block beacon interrupts */ 2948 ath_hal_setdefantenna(ah, antenna); 2949 if (sc->sc_defant != antenna) 2950 sc->sc_stats.ast_ant_defswitch++; 2951 sc->sc_defant = antenna; 2952 sc->sc_rxotherant = 0; 2953 } 2954 2955 static void 2956 ath_rx_proc(void *arg, int npending) 2957 { 2958 #define PA2DESC(_sc, _pa) \ 2959 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2960 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2961 struct ath_softc *sc = arg; 2962 struct ath_buf *bf; 2963 struct ieee80211com *ic = &sc->sc_ic; 2964 struct ifnet *ifp = &sc->sc_if; 2965 struct ath_hal *ah = sc->sc_ah; 2966 struct ath_desc *ds; 2967 struct mbuf *m; 2968 struct ieee80211_node *ni; 2969 struct ath_node *an; 2970 int len, type, ngood; 2971 u_int phyerr; 2972 HAL_STATUS status; 2973 int16_t nf; 2974 u_int64_t tsf; 2975 2976 NET_LOCK_GIANT(); /* XXX */ 2977 2978 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2979 ngood = 0; 2980 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2981 tsf = ath_hal_gettsf64(ah); 2982 do { 2983 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2984 if (bf == NULL) { /* NB: shouldn't happen */ 2985 if_printf(ifp, "%s: no buffer!\n", __func__); 2986 break; 2987 } 2988 ds = bf->bf_desc; 2989 if (ds->ds_link == bf->bf_daddr) { 2990 /* NB: never process the self-linked entry at the end */ 2991 break; 2992 } 2993 m = bf->bf_m; 2994 if (m == NULL) { /* NB: shouldn't happen */ 2995 if_printf(ifp, "%s: no mbuf!\n", __func__); 2996 break; 2997 } 2998 /* XXX sync descriptor memory */ 2999 /* 3000 * Must provide the virtual address of the current 3001 * descriptor, the physical address, and the virtual 3002 * address of the next descriptor in the h/w chain. 3003 * This allows the HAL to look ahead to see if the 3004 * hardware is done with a descriptor by checking the 3005 * done bit in the following descriptor and the address 3006 * of the current descriptor the DMA engine is working 3007 * on. All this is necessary because of our use of 3008 * a self-linked list to avoid rx overruns. 3009 */ 3010 status = ath_hal_rxprocdesc(ah, ds, 3011 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3012 #ifdef AR_DEBUG 3013 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3014 ath_printrxbuf(bf, status == HAL_OK); 3015 #endif 3016 if (status == HAL_EINPROGRESS) 3017 break; 3018 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3019 if (ds->ds_rxstat.rs_more) { 3020 /* 3021 * Frame spans multiple descriptors; this 3022 * cannot happen yet as we don't support 3023 * jumbograms. If not in monitor mode, 3024 * discard the frame. 3025 */ 3026 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3027 sc->sc_stats.ast_rx_toobig++; 3028 goto rx_next; 3029 } 3030 /* fall thru for monitor mode handling... */ 3031 } else if (ds->ds_rxstat.rs_status != 0) { 3032 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3033 sc->sc_stats.ast_rx_crcerr++; 3034 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3035 sc->sc_stats.ast_rx_fifoerr++; 3036 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3037 sc->sc_stats.ast_rx_phyerr++; 3038 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3039 sc->sc_stats.ast_rx_phy[phyerr]++; 3040 goto rx_next; 3041 } 3042 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3043 /* 3044 * Decrypt error. If the error occurred 3045 * because there was no hardware key, then 3046 * let the frame through so the upper layers 3047 * can process it. This is necessary for 5210 3048 * parts which have no way to setup a ``clear'' 3049 * key cache entry. 3050 * 3051 * XXX do key cache faulting 3052 */ 3053 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3054 goto rx_accept; 3055 sc->sc_stats.ast_rx_badcrypt++; 3056 } 3057 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3058 sc->sc_stats.ast_rx_badmic++; 3059 /* 3060 * Do minimal work required to hand off 3061 * the 802.11 header for notifcation. 3062 */ 3063 /* XXX frag's and qos frames */ 3064 len = ds->ds_rxstat.rs_datalen; 3065 if (len >= sizeof (struct ieee80211_frame)) { 3066 bus_dmamap_sync(sc->sc_dmat, 3067 bf->bf_dmamap, 3068 0, bf->bf_dmamap->dm_mapsize, 3069 BUS_DMASYNC_POSTREAD); 3070 ieee80211_notify_michael_failure(ic, 3071 mtod(m, struct ieee80211_frame *), 3072 sc->sc_splitmic ? 3073 ds->ds_rxstat.rs_keyix-32 : 3074 ds->ds_rxstat.rs_keyix 3075 ); 3076 } 3077 } 3078 ifp->if_ierrors++; 3079 /* 3080 * Reject error frames, we normally don't want 3081 * to see them in monitor mode (in monitor mode 3082 * allow through packets that have crypto problems). 3083 */ 3084 if ((ds->ds_rxstat.rs_status &~ 3085 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 3086 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 3087 goto rx_next; 3088 } 3089 rx_accept: 3090 /* 3091 * Sync and unmap the frame. At this point we're 3092 * committed to passing the mbuf somewhere so clear 3093 * bf_m; this means a new sk_buff must be allocated 3094 * when the rx descriptor is setup again to receive 3095 * another frame. 3096 */ 3097 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3098 0, bf->bf_dmamap->dm_mapsize, 3099 BUS_DMASYNC_POSTREAD); 3100 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3101 bf->bf_m = NULL; 3102 3103 m->m_pkthdr.rcvif = ifp; 3104 len = ds->ds_rxstat.rs_datalen; 3105 m->m_pkthdr.len = m->m_len = len; 3106 3107 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3108 3109 #if NBPFILTER > 0 3110 if (sc->sc_drvbpf) { 3111 u_int8_t rix; 3112 3113 /* 3114 * Discard anything shorter than an ack or cts. 3115 */ 3116 if (len < IEEE80211_ACK_LEN) { 3117 DPRINTF(sc, ATH_DEBUG_RECV, 3118 "%s: runt packet %d\n", 3119 __func__, len); 3120 sc->sc_stats.ast_rx_tooshort++; 3121 m_freem(m); 3122 goto rx_next; 3123 } 3124 rix = ds->ds_rxstat.rs_rate; 3125 sc->sc_rx_th.wr_tsf = htole64( 3126 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3127 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3128 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3129 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3130 sc->sc_rx_th.wr_antnoise = nf; 3131 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3132 3133 bpf_mtap2(sc->sc_drvbpf, 3134 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3135 } 3136 #endif 3137 3138 /* 3139 * From this point on we assume the frame is at least 3140 * as large as ieee80211_frame_min; verify that. 3141 */ 3142 if (len < IEEE80211_MIN_LEN) { 3143 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3144 __func__, len); 3145 sc->sc_stats.ast_rx_tooshort++; 3146 m_freem(m); 3147 goto rx_next; 3148 } 3149 3150 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3151 ieee80211_dump_pkt(mtod(m, void *), len, 3152 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3153 ds->ds_rxstat.rs_rssi); 3154 } 3155 3156 m_adj(m, -IEEE80211_CRC_LEN); 3157 3158 /* 3159 * Locate the node for sender, track state, and then 3160 * pass the (referenced) node up to the 802.11 layer 3161 * for its use. 3162 */ 3163 ni = ieee80211_find_rxnode_withkey(ic, 3164 mtod(m, const struct ieee80211_frame_min *), 3165 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3166 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3167 /* 3168 * Track rx rssi and do any rx antenna management. 3169 */ 3170 an = ATH_NODE(ni); 3171 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3172 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3173 /* 3174 * Send frame up for processing. 3175 */ 3176 type = ieee80211_input(ic, m, ni, 3177 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3178 ieee80211_free_node(ni); 3179 if (sc->sc_diversity) { 3180 /* 3181 * When using fast diversity, change the default rx 3182 * antenna if diversity chooses the other antenna 3 3183 * times in a row. 3184 */ 3185 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3186 if (++sc->sc_rxotherant >= 3) 3187 ath_setdefantenna(sc, 3188 ds->ds_rxstat.rs_antenna); 3189 } else 3190 sc->sc_rxotherant = 0; 3191 } 3192 if (sc->sc_softled) { 3193 /* 3194 * Blink for any data frame. Otherwise do a 3195 * heartbeat-style blink when idle. The latter 3196 * is mainly for station mode where we depend on 3197 * periodic beacon frames to trigger the poll event. 3198 */ 3199 if (type == IEEE80211_FC0_TYPE_DATA) { 3200 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3201 ath_led_event(sc, ATH_LED_RX); 3202 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3203 ath_led_event(sc, ATH_LED_POLL); 3204 } 3205 /* 3206 * Arrange to update the last rx timestamp only for 3207 * frames from our ap when operating in station mode. 3208 * This assumes the rx key is always setup when associated. 3209 */ 3210 if (ic->ic_opmode == IEEE80211_M_STA && 3211 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3212 ngood++; 3213 rx_next: 3214 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3215 } while (ath_rxbuf_init(sc, bf) == 0); 3216 3217 /* rx signal state monitoring */ 3218 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3219 if (ath_hal_radar_event(ah)) 3220 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3221 if (ngood) 3222 sc->sc_lastrx = tsf; 3223 3224 #ifdef __NetBSD__ 3225 /* XXX Why isn't this necessary in FreeBSD? */ 3226 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3227 ath_start(ifp); 3228 #endif /* __NetBSD__ */ 3229 3230 NET_UNLOCK_GIANT(); /* XXX */ 3231 #undef PA2DESC 3232 } 3233 3234 /* 3235 * Setup a h/w transmit queue. 3236 */ 3237 static struct ath_txq * 3238 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3239 { 3240 #define N(a) (sizeof(a)/sizeof(a[0])) 3241 struct ath_hal *ah = sc->sc_ah; 3242 HAL_TXQ_INFO qi; 3243 int qnum; 3244 3245 memset(&qi, 0, sizeof(qi)); 3246 qi.tqi_subtype = subtype; 3247 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3248 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3249 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3250 /* 3251 * Enable interrupts only for EOL and DESC conditions. 3252 * We mark tx descriptors to receive a DESC interrupt 3253 * when a tx queue gets deep; otherwise waiting for the 3254 * EOL to reap descriptors. Note that this is done to 3255 * reduce interrupt load and this only defers reaping 3256 * descriptors, never transmitting frames. Aside from 3257 * reducing interrupts this also permits more concurrency. 3258 * The only potential downside is if the tx queue backs 3259 * up in which case the top half of the kernel may backup 3260 * due to a lack of tx descriptors. 3261 */ 3262 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3263 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3264 if (qnum == -1) { 3265 /* 3266 * NB: don't print a message, this happens 3267 * normally on parts with too few tx queues 3268 */ 3269 return NULL; 3270 } 3271 if (qnum >= N(sc->sc_txq)) { 3272 device_printf(sc->sc_dev, 3273 "hal qnum %u out of range, max %zu!\n", 3274 qnum, N(sc->sc_txq)); 3275 ath_hal_releasetxqueue(ah, qnum); 3276 return NULL; 3277 } 3278 if (!ATH_TXQ_SETUP(sc, qnum)) { 3279 struct ath_txq *txq = &sc->sc_txq[qnum]; 3280 3281 txq->axq_qnum = qnum; 3282 txq->axq_depth = 0; 3283 txq->axq_intrcnt = 0; 3284 txq->axq_link = NULL; 3285 STAILQ_INIT(&txq->axq_q); 3286 ATH_TXQ_LOCK_INIT(sc, txq); 3287 sc->sc_txqsetup |= 1<<qnum; 3288 } 3289 return &sc->sc_txq[qnum]; 3290 #undef N 3291 } 3292 3293 /* 3294 * Setup a hardware data transmit queue for the specified 3295 * access control. The hal may not support all requested 3296 * queues in which case it will return a reference to a 3297 * previously setup queue. We record the mapping from ac's 3298 * to h/w queues for use by ath_tx_start and also track 3299 * the set of h/w queues being used to optimize work in the 3300 * transmit interrupt handler and related routines. 3301 */ 3302 static int 3303 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3304 { 3305 #define N(a) (sizeof(a)/sizeof(a[0])) 3306 struct ath_txq *txq; 3307 3308 if (ac >= N(sc->sc_ac2q)) { 3309 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3310 ac, N(sc->sc_ac2q)); 3311 return 0; 3312 } 3313 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3314 if (txq != NULL) { 3315 sc->sc_ac2q[ac] = txq; 3316 return 1; 3317 } else 3318 return 0; 3319 #undef N 3320 } 3321 3322 /* 3323 * Update WME parameters for a transmit queue. 3324 */ 3325 static int 3326 ath_txq_update(struct ath_softc *sc, int ac) 3327 { 3328 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3329 #define ATH_TXOP_TO_US(v) (v<<5) 3330 struct ieee80211com *ic = &sc->sc_ic; 3331 struct ath_txq *txq = sc->sc_ac2q[ac]; 3332 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3333 struct ath_hal *ah = sc->sc_ah; 3334 HAL_TXQ_INFO qi; 3335 3336 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3337 qi.tqi_aifs = wmep->wmep_aifsn; 3338 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3339 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3340 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3341 3342 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3343 device_printf(sc->sc_dev, "unable to update hardware queue " 3344 "parameters for %s traffic!\n", 3345 ieee80211_wme_acnames[ac]); 3346 return 0; 3347 } else { 3348 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3349 return 1; 3350 } 3351 #undef ATH_TXOP_TO_US 3352 #undef ATH_EXPONENT_TO_VALUE 3353 } 3354 3355 /* 3356 * Callback from the 802.11 layer to update WME parameters. 3357 */ 3358 static int 3359 ath_wme_update(struct ieee80211com *ic) 3360 { 3361 struct ath_softc *sc = ic->ic_ifp->if_softc; 3362 3363 return !ath_txq_update(sc, WME_AC_BE) || 3364 !ath_txq_update(sc, WME_AC_BK) || 3365 !ath_txq_update(sc, WME_AC_VI) || 3366 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3367 } 3368 3369 /* 3370 * Reclaim resources for a setup queue. 3371 */ 3372 static void 3373 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3374 { 3375 3376 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3377 ATH_TXQ_LOCK_DESTROY(txq); 3378 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3379 } 3380 3381 /* 3382 * Reclaim all tx queue resources. 3383 */ 3384 static void 3385 ath_tx_cleanup(struct ath_softc *sc) 3386 { 3387 int i; 3388 3389 ATH_TXBUF_LOCK_DESTROY(sc); 3390 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3391 if (ATH_TXQ_SETUP(sc, i)) 3392 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3393 } 3394 3395 /* 3396 * Defragment an mbuf chain, returning at most maxfrags separate 3397 * mbufs+clusters. If this is not possible NULL is returned and 3398 * the original mbuf chain is left in it's present (potentially 3399 * modified) state. We use two techniques: collapsing consecutive 3400 * mbufs and replacing consecutive mbufs by a cluster. 3401 */ 3402 static struct mbuf * 3403 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3404 { 3405 struct mbuf *m, *n, *n2, **prev; 3406 u_int curfrags; 3407 3408 /* 3409 * Calculate the current number of frags. 3410 */ 3411 curfrags = 0; 3412 for (m = m0; m != NULL; m = m->m_next) 3413 curfrags++; 3414 /* 3415 * First, try to collapse mbufs. Note that we always collapse 3416 * towards the front so we don't need to deal with moving the 3417 * pkthdr. This may be suboptimal if the first mbuf has much 3418 * less data than the following. 3419 */ 3420 m = m0; 3421 again: 3422 for (;;) { 3423 n = m->m_next; 3424 if (n == NULL) 3425 break; 3426 if ((m->m_flags & M_RDONLY) == 0 && 3427 n->m_len < M_TRAILINGSPACE(m)) { 3428 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3429 n->m_len); 3430 m->m_len += n->m_len; 3431 m->m_next = n->m_next; 3432 m_free(n); 3433 if (--curfrags <= maxfrags) 3434 return m0; 3435 } else 3436 m = n; 3437 } 3438 KASSERT(maxfrags > 1, 3439 ("maxfrags %u, but normal collapse failed", maxfrags)); 3440 /* 3441 * Collapse consecutive mbufs to a cluster. 3442 */ 3443 prev = &m0->m_next; /* NB: not the first mbuf */ 3444 while ((n = *prev) != NULL) { 3445 if ((n2 = n->m_next) != NULL && 3446 n->m_len + n2->m_len < MCLBYTES) { 3447 m = m_getcl(how, MT_DATA, 0); 3448 if (m == NULL) 3449 goto bad; 3450 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3451 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3452 n2->m_len); 3453 m->m_len = n->m_len + n2->m_len; 3454 m->m_next = n2->m_next; 3455 *prev = m; 3456 m_free(n); 3457 m_free(n2); 3458 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3459 return m0; 3460 /* 3461 * Still not there, try the normal collapse 3462 * again before we allocate another cluster. 3463 */ 3464 goto again; 3465 } 3466 prev = &n->m_next; 3467 } 3468 /* 3469 * No place where we can collapse to a cluster; punt. 3470 * This can occur if, for example, you request 2 frags 3471 * but the packet requires that both be clusters (we 3472 * never reallocate the first mbuf to avoid moving the 3473 * packet header). 3474 */ 3475 bad: 3476 return NULL; 3477 } 3478 3479 /* 3480 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3481 */ 3482 static int 3483 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3484 { 3485 int i; 3486 3487 for (i = 0; i < rt->rateCount; i++) 3488 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3489 return i; 3490 return 0; /* NB: lowest rate */ 3491 } 3492 3493 static void 3494 ath_freetx(struct mbuf *m) 3495 { 3496 struct mbuf *next; 3497 3498 do { 3499 next = m->m_nextpkt; 3500 m->m_nextpkt = NULL; 3501 m_freem(m); 3502 } while ((m = next) != NULL); 3503 } 3504 3505 static int 3506 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3507 struct mbuf *m0) 3508 { 3509 struct ieee80211com *ic = &sc->sc_ic; 3510 struct ath_hal *ah = sc->sc_ah; 3511 struct ifnet *ifp = &sc->sc_if; 3512 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3513 int i, error, iswep, ismcast, isfrag, ismrr; 3514 int keyix, hdrlen, pktlen, try0; 3515 u_int8_t rix, txrate, ctsrate; 3516 u_int8_t cix = 0xff; /* NB: silence compiler */ 3517 struct ath_desc *ds, *ds0; 3518 struct ath_txq *txq; 3519 struct ieee80211_frame *wh; 3520 u_int subtype, flags, ctsduration; 3521 HAL_PKT_TYPE atype; 3522 const HAL_RATE_TABLE *rt; 3523 HAL_BOOL shortPreamble; 3524 struct ath_node *an; 3525 struct mbuf *m; 3526 u_int pri; 3527 3528 wh = mtod(m0, struct ieee80211_frame *); 3529 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3530 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3531 isfrag = m0->m_flags & M_FRAG; 3532 hdrlen = ieee80211_anyhdrsize(wh); 3533 /* 3534 * Packet length must not include any 3535 * pad bytes; deduct them here. 3536 */ 3537 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3538 3539 if (iswep) { 3540 const struct ieee80211_cipher *cip; 3541 struct ieee80211_key *k; 3542 3543 /* 3544 * Construct the 802.11 header+trailer for an encrypted 3545 * frame. The only reason this can fail is because of an 3546 * unknown or unsupported cipher/key type. 3547 */ 3548 k = ieee80211_crypto_encap(ic, ni, m0); 3549 if (k == NULL) { 3550 /* 3551 * This can happen when the key is yanked after the 3552 * frame was queued. Just discard the frame; the 3553 * 802.11 layer counts failures and provides 3554 * debugging/diagnostics. 3555 */ 3556 ath_freetx(m0); 3557 return EIO; 3558 } 3559 /* 3560 * Adjust the packet + header lengths for the crypto 3561 * additions and calculate the h/w key index. When 3562 * a s/w mic is done the frame will have had any mic 3563 * added to it prior to entry so m0->m_pkthdr.len above will 3564 * account for it. Otherwise we need to add it to the 3565 * packet length. 3566 */ 3567 cip = k->wk_cipher; 3568 hdrlen += cip->ic_header; 3569 pktlen += cip->ic_header + cip->ic_trailer; 3570 /* NB: frags always have any TKIP MIC done in s/w */ 3571 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3572 pktlen += cip->ic_miclen; 3573 keyix = k->wk_keyix; 3574 3575 /* packet header may have moved, reset our local pointer */ 3576 wh = mtod(m0, struct ieee80211_frame *); 3577 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3578 /* 3579 * Use station key cache slot, if assigned. 3580 */ 3581 keyix = ni->ni_ucastkey.wk_keyix; 3582 if (keyix == IEEE80211_KEYIX_NONE) 3583 keyix = HAL_TXKEYIX_INVALID; 3584 } else 3585 keyix = HAL_TXKEYIX_INVALID; 3586 3587 pktlen += IEEE80211_CRC_LEN; 3588 3589 /* 3590 * Load the DMA map so any coalescing is done. This 3591 * also calculates the number of descriptors we need. 3592 */ 3593 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3594 BUS_DMA_NOWAIT); 3595 if (error == EFBIG) { 3596 /* XXX packet requires too many descriptors */ 3597 bf->bf_nseg = ATH_TXDESC+1; 3598 } else if (error != 0) { 3599 sc->sc_stats.ast_tx_busdma++; 3600 ath_freetx(m0); 3601 return error; 3602 } 3603 /* 3604 * Discard null packets and check for packets that 3605 * require too many TX descriptors. We try to convert 3606 * the latter to a cluster. 3607 */ 3608 if (error == EFBIG) { /* too many desc's, linearize */ 3609 sc->sc_stats.ast_tx_linear++; 3610 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3611 if (m == NULL) { 3612 ath_freetx(m0); 3613 sc->sc_stats.ast_tx_nombuf++; 3614 return ENOMEM; 3615 } 3616 m0 = m; 3617 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3618 BUS_DMA_NOWAIT); 3619 if (error != 0) { 3620 sc->sc_stats.ast_tx_busdma++; 3621 ath_freetx(m0); 3622 return error; 3623 } 3624 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3625 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3626 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3627 sc->sc_stats.ast_tx_nodata++; 3628 ath_freetx(m0); 3629 return EIO; 3630 } 3631 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3632 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3633 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3634 bf->bf_m = m0; 3635 bf->bf_node = ni; /* NB: held reference */ 3636 3637 /* setup descriptors */ 3638 ds = bf->bf_desc; 3639 rt = sc->sc_currates; 3640 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3641 3642 /* 3643 * NB: the 802.11 layer marks whether or not we should 3644 * use short preamble based on the current mode and 3645 * negotiated parameters. 3646 */ 3647 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3648 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3649 shortPreamble = AH_TRUE; 3650 sc->sc_stats.ast_tx_shortpre++; 3651 } else { 3652 shortPreamble = AH_FALSE; 3653 } 3654 3655 an = ATH_NODE(ni); 3656 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3657 ismrr = 0; /* default no multi-rate retry*/ 3658 /* 3659 * Calculate Atheros packet type from IEEE80211 packet header, 3660 * setup for rate calculations, and select h/w transmit queue. 3661 */ 3662 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3663 case IEEE80211_FC0_TYPE_MGT: 3664 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3665 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3666 atype = HAL_PKT_TYPE_BEACON; 3667 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3668 atype = HAL_PKT_TYPE_PROBE_RESP; 3669 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3670 atype = HAL_PKT_TYPE_ATIM; 3671 else 3672 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3673 rix = sc->sc_minrateix; 3674 txrate = rt->info[rix].rateCode; 3675 if (shortPreamble) 3676 txrate |= rt->info[rix].shortPreamble; 3677 try0 = ATH_TXMGTTRY; 3678 /* NB: force all management frames to highest queue */ 3679 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3680 /* NB: force all management frames to highest queue */ 3681 pri = WME_AC_VO; 3682 } else 3683 pri = WME_AC_BE; 3684 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3685 break; 3686 case IEEE80211_FC0_TYPE_CTL: 3687 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3688 rix = sc->sc_minrateix; 3689 txrate = rt->info[rix].rateCode; 3690 if (shortPreamble) 3691 txrate |= rt->info[rix].shortPreamble; 3692 try0 = ATH_TXMGTTRY; 3693 /* NB: force all ctl frames to highest queue */ 3694 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3695 /* NB: force all ctl frames to highest queue */ 3696 pri = WME_AC_VO; 3697 } else 3698 pri = WME_AC_BE; 3699 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3700 break; 3701 case IEEE80211_FC0_TYPE_DATA: 3702 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3703 /* 3704 * Data frames: multicast frames go out at a fixed rate, 3705 * otherwise consult the rate control module for the 3706 * rate to use. 3707 */ 3708 if (ismcast) { 3709 /* 3710 * Check mcast rate setting in case it's changed. 3711 * XXX move out of fastpath 3712 */ 3713 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3714 sc->sc_mcastrix = 3715 ath_tx_findrix(rt, ic->ic_mcast_rate); 3716 sc->sc_mcastrate = ic->ic_mcast_rate; 3717 } 3718 rix = sc->sc_mcastrix; 3719 txrate = rt->info[rix].rateCode; 3720 try0 = 1; 3721 } else { 3722 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3723 &rix, &try0, &txrate); 3724 sc->sc_txrate = txrate; /* for LED blinking */ 3725 if (try0 != ATH_TXMAXTRY) 3726 ismrr = 1; 3727 } 3728 pri = M_WME_GETAC(m0); 3729 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3730 flags |= HAL_TXDESC_NOACK; 3731 break; 3732 default: 3733 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3734 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3735 /* XXX statistic */ 3736 ath_freetx(m0); 3737 return EIO; 3738 } 3739 txq = sc->sc_ac2q[pri]; 3740 3741 /* 3742 * When servicing one or more stations in power-save mode 3743 * multicast frames must be buffered until after the beacon. 3744 * We use the CAB queue for that. 3745 */ 3746 if (ismcast && ic->ic_ps_sta) { 3747 txq = sc->sc_cabq; 3748 /* XXX? more bit in 802.11 frame header */ 3749 } 3750 3751 /* 3752 * Calculate miscellaneous flags. 3753 */ 3754 if (ismcast) { 3755 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3756 } else if (pktlen > ic->ic_rtsthreshold) { 3757 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3758 cix = rt->info[rix].controlRate; 3759 sc->sc_stats.ast_tx_rts++; 3760 } 3761 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3762 sc->sc_stats.ast_tx_noack++; 3763 3764 /* 3765 * If 802.11g protection is enabled, determine whether 3766 * to use RTS/CTS or just CTS. Note that this is only 3767 * done for OFDM unicast frames. 3768 */ 3769 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3770 rt->info[rix].phy == IEEE80211_T_OFDM && 3771 (flags & HAL_TXDESC_NOACK) == 0) { 3772 /* XXX fragments must use CCK rates w/ protection */ 3773 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3774 flags |= HAL_TXDESC_RTSENA; 3775 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3776 flags |= HAL_TXDESC_CTSENA; 3777 if (isfrag) { 3778 /* 3779 * For frags it would be desirable to use the 3780 * highest CCK rate for RTS/CTS. But stations 3781 * farther away may detect it at a lower CCK rate 3782 * so use the configured protection rate instead 3783 * (for now). 3784 */ 3785 cix = rt->info[sc->sc_protrix].controlRate; 3786 } else 3787 cix = rt->info[sc->sc_protrix].controlRate; 3788 sc->sc_stats.ast_tx_protect++; 3789 } 3790 3791 /* 3792 * Calculate duration. This logically belongs in the 802.11 3793 * layer but it lacks sufficient information to calculate it. 3794 */ 3795 if ((flags & HAL_TXDESC_NOACK) == 0 && 3796 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3797 u_int16_t dur; 3798 /* 3799 * XXX not right with fragmentation. 3800 */ 3801 if (shortPreamble) 3802 dur = rt->info[rix].spAckDuration; 3803 else 3804 dur = rt->info[rix].lpAckDuration; 3805 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3806 dur += dur; /* additional SIFS+ACK */ 3807 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3808 /* 3809 * Include the size of next fragment so NAV is 3810 * updated properly. The last fragment uses only 3811 * the ACK duration 3812 */ 3813 dur += ath_hal_computetxtime(ah, rt, 3814 m0->m_nextpkt->m_pkthdr.len, 3815 rix, shortPreamble); 3816 } 3817 if (isfrag) { 3818 /* 3819 * Force hardware to use computed duration for next 3820 * fragment by disabling multi-rate retry which updates 3821 * duration based on the multi-rate duration table. 3822 */ 3823 try0 = ATH_TXMAXTRY; 3824 } 3825 *(u_int16_t *)wh->i_dur = htole16(dur); 3826 } 3827 3828 /* 3829 * Calculate RTS/CTS rate and duration if needed. 3830 */ 3831 ctsduration = 0; 3832 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3833 /* 3834 * CTS transmit rate is derived from the transmit rate 3835 * by looking in the h/w rate table. We must also factor 3836 * in whether or not a short preamble is to be used. 3837 */ 3838 /* NB: cix is set above where RTS/CTS is enabled */ 3839 KASSERT(cix != 0xff, ("cix not setup")); 3840 ctsrate = rt->info[cix].rateCode; 3841 /* 3842 * Compute the transmit duration based on the frame 3843 * size and the size of an ACK frame. We call into the 3844 * HAL to do the computation since it depends on the 3845 * characteristics of the actual PHY being used. 3846 * 3847 * NB: CTS is assumed the same size as an ACK so we can 3848 * use the precalculated ACK durations. 3849 */ 3850 if (shortPreamble) { 3851 ctsrate |= rt->info[cix].shortPreamble; 3852 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3853 ctsduration += rt->info[cix].spAckDuration; 3854 ctsduration += ath_hal_computetxtime(ah, 3855 rt, pktlen, rix, AH_TRUE); 3856 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3857 ctsduration += rt->info[rix].spAckDuration; 3858 } else { 3859 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3860 ctsduration += rt->info[cix].lpAckDuration; 3861 ctsduration += ath_hal_computetxtime(ah, 3862 rt, pktlen, rix, AH_FALSE); 3863 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3864 ctsduration += rt->info[rix].lpAckDuration; 3865 } 3866 /* 3867 * Must disable multi-rate retry when using RTS/CTS. 3868 */ 3869 ismrr = 0; 3870 try0 = ATH_TXMGTTRY; /* XXX */ 3871 } else 3872 ctsrate = 0; 3873 3874 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3875 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3876 sc->sc_hwmap[txrate].ieeerate, -1); 3877 #if NBPFILTER > 0 3878 if (ic->ic_rawbpf) 3879 bpf_mtap(ic->ic_rawbpf, m0); 3880 if (sc->sc_drvbpf) { 3881 u_int64_t tsf = ath_hal_gettsf64(ah); 3882 3883 sc->sc_tx_th.wt_tsf = htole64(tsf); 3884 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3885 if (iswep) 3886 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3887 if (isfrag) 3888 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3889 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3890 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3891 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3892 3893 bpf_mtap2(sc->sc_drvbpf, 3894 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3895 } 3896 #endif 3897 3898 /* 3899 * Determine if a tx interrupt should be generated for 3900 * this descriptor. We take a tx interrupt to reap 3901 * descriptors when the h/w hits an EOL condition or 3902 * when the descriptor is specifically marked to generate 3903 * an interrupt. We periodically mark descriptors in this 3904 * way to insure timely replenishing of the supply needed 3905 * for sending frames. Defering interrupts reduces system 3906 * load and potentially allows more concurrent work to be 3907 * done but if done to aggressively can cause senders to 3908 * backup. 3909 * 3910 * NB: use >= to deal with sc_txintrperiod changing 3911 * dynamically through sysctl. 3912 */ 3913 if (flags & HAL_TXDESC_INTREQ) { 3914 txq->axq_intrcnt = 0; 3915 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3916 flags |= HAL_TXDESC_INTREQ; 3917 txq->axq_intrcnt = 0; 3918 } 3919 3920 /* 3921 * Formulate first tx descriptor with tx controls. 3922 */ 3923 /* XXX check return value? */ 3924 ath_hal_setuptxdesc(ah, ds 3925 , pktlen /* packet length */ 3926 , hdrlen /* header length */ 3927 , atype /* Atheros packet type */ 3928 , ni->ni_txpower /* txpower */ 3929 , txrate, try0 /* series 0 rate/tries */ 3930 , keyix /* key cache index */ 3931 , sc->sc_txantenna /* antenna mode */ 3932 , flags /* flags */ 3933 , ctsrate /* rts/cts rate */ 3934 , ctsduration /* rts/cts duration */ 3935 ); 3936 bf->bf_flags = flags; 3937 /* 3938 * Setup the multi-rate retry state only when we're 3939 * going to use it. This assumes ath_hal_setuptxdesc 3940 * initializes the descriptors (so we don't have to) 3941 * when the hardware supports multi-rate retry and 3942 * we don't use it. 3943 */ 3944 if (ismrr) 3945 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3946 3947 /* 3948 * Fillin the remainder of the descriptor info. 3949 */ 3950 ds0 = ds; 3951 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3952 ds->ds_data = bf->bf_segs[i].ds_addr; 3953 if (i == bf->bf_nseg - 1) 3954 ds->ds_link = 0; 3955 else 3956 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3957 ath_hal_filltxdesc(ah, ds 3958 , bf->bf_segs[i].ds_len /* segment length */ 3959 , i == 0 /* first segment */ 3960 , i == bf->bf_nseg - 1 /* last segment */ 3961 , ds0 /* first descriptor */ 3962 ); 3963 3964 /* NB: The desc swap function becomes void, 3965 * if descriptor swapping is not enabled 3966 */ 3967 ath_desc_swap(ds); 3968 3969 DPRINTF(sc, ATH_DEBUG_XMIT, 3970 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3971 __func__, i, ds->ds_link, ds->ds_data, 3972 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3973 } 3974 /* 3975 * Insert the frame on the outbound list and 3976 * pass it on to the hardware. 3977 */ 3978 ATH_TXQ_LOCK(txq); 3979 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3980 if (txq->axq_link == NULL) { 3981 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3982 DPRINTF(sc, ATH_DEBUG_XMIT, 3983 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3984 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3985 txq->axq_depth); 3986 } else { 3987 *txq->axq_link = HTOAH32(bf->bf_daddr); 3988 DPRINTF(sc, ATH_DEBUG_XMIT, 3989 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3990 __func__, txq->axq_qnum, txq->axq_link, 3991 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3992 } 3993 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3994 /* 3995 * The CAB queue is started from the SWBA handler since 3996 * frames only go out on DTIM and to avoid possible races. 3997 */ 3998 if (txq != sc->sc_cabq) 3999 ath_hal_txstart(ah, txq->axq_qnum); 4000 ATH_TXQ_UNLOCK(txq); 4001 4002 return 0; 4003 } 4004 4005 /* 4006 * Process completed xmit descriptors from the specified queue. 4007 */ 4008 static int 4009 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4010 { 4011 struct ath_hal *ah = sc->sc_ah; 4012 struct ieee80211com *ic = &sc->sc_ic; 4013 struct ath_buf *bf; 4014 struct ath_desc *ds, *ds0; 4015 struct ieee80211_node *ni; 4016 struct ath_node *an; 4017 int sr, lr, pri, nacked; 4018 HAL_STATUS status; 4019 4020 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4021 __func__, txq->axq_qnum, 4022 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4023 txq->axq_link); 4024 nacked = 0; 4025 for (;;) { 4026 ATH_TXQ_LOCK(txq); 4027 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4028 bf = STAILQ_FIRST(&txq->axq_q); 4029 if (bf == NULL) { 4030 txq->axq_link = NULL; 4031 ATH_TXQ_UNLOCK(txq); 4032 break; 4033 } 4034 ds0 = &bf->bf_desc[0]; 4035 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4036 status = ath_hal_txprocdesc(ah, ds); 4037 #ifdef AR_DEBUG 4038 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4039 ath_printtxbuf(bf, status == HAL_OK); 4040 #endif 4041 if (status == HAL_EINPROGRESS) { 4042 ATH_TXQ_UNLOCK(txq); 4043 break; 4044 } 4045 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4046 ATH_TXQ_UNLOCK(txq); 4047 4048 ni = bf->bf_node; 4049 if (ni != NULL) { 4050 an = ATH_NODE(ni); 4051 if (ds->ds_txstat.ts_status == 0) { 4052 u_int8_t txant = ds->ds_txstat.ts_antenna; 4053 sc->sc_stats.ast_ant_tx[txant]++; 4054 sc->sc_ant_tx[txant]++; 4055 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4056 sc->sc_stats.ast_tx_altrate++; 4057 sc->sc_stats.ast_tx_rssi = 4058 ds->ds_txstat.ts_rssi; 4059 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4060 ds->ds_txstat.ts_rssi); 4061 pri = M_WME_GETAC(bf->bf_m); 4062 if (pri >= WME_AC_VO) 4063 ic->ic_wme.wme_hipri_traffic++; 4064 ni->ni_inact = ni->ni_inact_reload; 4065 } else { 4066 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4067 sc->sc_stats.ast_tx_xretries++; 4068 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4069 sc->sc_stats.ast_tx_fifoerr++; 4070 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4071 sc->sc_stats.ast_tx_filtered++; 4072 } 4073 sr = ds->ds_txstat.ts_shortretry; 4074 lr = ds->ds_txstat.ts_longretry; 4075 sc->sc_stats.ast_tx_shortretry += sr; 4076 sc->sc_stats.ast_tx_longretry += lr; 4077 /* 4078 * Hand the descriptor to the rate control algorithm. 4079 */ 4080 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4081 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4082 /* 4083 * If frame was ack'd update the last rx time 4084 * used to workaround phantom bmiss interrupts. 4085 */ 4086 if (ds->ds_txstat.ts_status == 0) 4087 nacked++; 4088 ath_rate_tx_complete(sc, an, ds, ds0); 4089 } 4090 /* 4091 * Reclaim reference to node. 4092 * 4093 * NB: the node may be reclaimed here if, for example 4094 * this is a DEAUTH message that was sent and the 4095 * node was timed out due to inactivity. 4096 */ 4097 ieee80211_free_node(ni); 4098 } 4099 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4100 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4101 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4102 m_freem(bf->bf_m); 4103 bf->bf_m = NULL; 4104 bf->bf_node = NULL; 4105 4106 ATH_TXBUF_LOCK(sc); 4107 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4108 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4109 ATH_TXBUF_UNLOCK(sc); 4110 } 4111 return nacked; 4112 } 4113 4114 static inline int 4115 txqactive(struct ath_hal *ah, int qnum) 4116 { 4117 u_int32_t txqs = 1<<qnum; 4118 ath_hal_gettxintrtxqs(ah, &txqs); 4119 return (txqs & (1<<qnum)); 4120 } 4121 4122 /* 4123 * Deferred processing of transmit interrupt; special-cased 4124 * for a single hardware transmit queue (e.g. 5210 and 5211). 4125 */ 4126 static void 4127 ath_tx_proc_q0(void *arg, int npending) 4128 { 4129 struct ath_softc *sc = arg; 4130 struct ifnet *ifp = &sc->sc_if; 4131 4132 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4133 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4134 } 4135 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4136 ath_tx_processq(sc, sc->sc_cabq); 4137 4138 if (sc->sc_softled) 4139 ath_led_event(sc, ATH_LED_TX); 4140 4141 ath_start(ifp); 4142 } 4143 4144 /* 4145 * Deferred processing of transmit interrupt; special-cased 4146 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4147 */ 4148 static void 4149 ath_tx_proc_q0123(void *arg, int npending) 4150 { 4151 struct ath_softc *sc = arg; 4152 struct ifnet *ifp = &sc->sc_if; 4153 int nacked; 4154 4155 /* 4156 * Process each active queue. 4157 */ 4158 nacked = 0; 4159 if (txqactive(sc->sc_ah, 0)) 4160 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4161 if (txqactive(sc->sc_ah, 1)) 4162 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4163 if (txqactive(sc->sc_ah, 2)) 4164 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4165 if (txqactive(sc->sc_ah, 3)) 4166 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4167 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4168 ath_tx_processq(sc, sc->sc_cabq); 4169 if (nacked) { 4170 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4171 } 4172 ath_tx_processq(sc, sc->sc_cabq); 4173 4174 if (sc->sc_softled) 4175 ath_led_event(sc, ATH_LED_TX); 4176 4177 ath_start(ifp); 4178 } 4179 4180 /* 4181 * Deferred processing of transmit interrupt. 4182 */ 4183 static void 4184 ath_tx_proc(void *arg, int npending) 4185 { 4186 struct ath_softc *sc = arg; 4187 struct ifnet *ifp = &sc->sc_if; 4188 int i, nacked; 4189 4190 /* 4191 * Process each active queue. 4192 */ 4193 nacked = 0; 4194 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4195 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4196 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4197 if (nacked) { 4198 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4199 } 4200 4201 if (sc->sc_softled) 4202 ath_led_event(sc, ATH_LED_TX); 4203 4204 ath_start(ifp); 4205 } 4206 4207 static void 4208 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4209 { 4210 struct ath_hal *ah = sc->sc_ah; 4211 struct ieee80211_node *ni; 4212 struct ath_buf *bf; 4213 4214 /* 4215 * NB: this assumes output has been stopped and 4216 * we do not need to block ath_tx_tasklet 4217 */ 4218 for (;;) { 4219 ATH_TXQ_LOCK(txq); 4220 bf = STAILQ_FIRST(&txq->axq_q); 4221 if (bf == NULL) { 4222 txq->axq_link = NULL; 4223 ATH_TXQ_UNLOCK(txq); 4224 break; 4225 } 4226 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4227 ATH_TXQ_UNLOCK(txq); 4228 #ifdef AR_DEBUG 4229 if (sc->sc_debug & ATH_DEBUG_RESET) 4230 ath_printtxbuf(bf, 4231 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4232 #endif /* AR_DEBUG */ 4233 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4234 m_freem(bf->bf_m); 4235 bf->bf_m = NULL; 4236 ni = bf->bf_node; 4237 bf->bf_node = NULL; 4238 if (ni != NULL) { 4239 /* 4240 * Reclaim node reference. 4241 */ 4242 ieee80211_free_node(ni); 4243 } 4244 ATH_TXBUF_LOCK(sc); 4245 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4246 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4247 ATH_TXBUF_UNLOCK(sc); 4248 } 4249 } 4250 4251 static void 4252 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4253 { 4254 struct ath_hal *ah = sc->sc_ah; 4255 4256 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4257 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4258 __func__, txq->axq_qnum, 4259 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4260 txq->axq_link); 4261 } 4262 4263 /* 4264 * Drain the transmit queues and reclaim resources. 4265 */ 4266 static void 4267 ath_draintxq(struct ath_softc *sc) 4268 { 4269 struct ath_hal *ah = sc->sc_ah; 4270 int i; 4271 4272 /* XXX return value */ 4273 if (!sc->sc_invalid) { 4274 /* don't touch the hardware if marked invalid */ 4275 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4276 DPRINTF(sc, ATH_DEBUG_RESET, 4277 "%s: beacon queue %p\n", __func__, 4278 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4279 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4280 if (ATH_TXQ_SETUP(sc, i)) 4281 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4282 } 4283 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4284 if (ATH_TXQ_SETUP(sc, i)) 4285 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4286 } 4287 4288 /* 4289 * Disable the receive h/w in preparation for a reset. 4290 */ 4291 static void 4292 ath_stoprecv(struct ath_softc *sc) 4293 { 4294 #define PA2DESC(_sc, _pa) \ 4295 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4296 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4297 struct ath_hal *ah = sc->sc_ah; 4298 4299 ath_hal_stoppcurecv(ah); /* disable PCU */ 4300 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4301 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4302 DELAY(3000); /* 3ms is long enough for 1 frame */ 4303 #ifdef AR_DEBUG 4304 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4305 struct ath_buf *bf; 4306 4307 printf("%s: rx queue %p, link %p\n", __func__, 4308 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4309 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4310 struct ath_desc *ds = bf->bf_desc; 4311 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4312 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4313 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4314 ath_printrxbuf(bf, status == HAL_OK); 4315 } 4316 } 4317 #endif 4318 sc->sc_rxlink = NULL; /* just in case */ 4319 #undef PA2DESC 4320 } 4321 4322 /* 4323 * Enable the receive h/w following a reset. 4324 */ 4325 static int 4326 ath_startrecv(struct ath_softc *sc) 4327 { 4328 struct ath_hal *ah = sc->sc_ah; 4329 struct ath_buf *bf; 4330 4331 sc->sc_rxlink = NULL; 4332 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4333 int error = ath_rxbuf_init(sc, bf); 4334 if (error != 0) { 4335 DPRINTF(sc, ATH_DEBUG_RECV, 4336 "%s: ath_rxbuf_init failed %d\n", 4337 __func__, error); 4338 return error; 4339 } 4340 } 4341 4342 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4343 ath_hal_putrxbuf(ah, bf->bf_daddr); 4344 ath_hal_rxena(ah); /* enable recv descriptors */ 4345 ath_mode_init(sc); /* set filters, etc. */ 4346 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4347 return 0; 4348 } 4349 4350 /* 4351 * Update internal state after a channel change. 4352 */ 4353 static void 4354 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4355 { 4356 struct ieee80211com *ic = &sc->sc_ic; 4357 enum ieee80211_phymode mode; 4358 u_int16_t flags; 4359 4360 /* 4361 * Change channels and update the h/w rate map 4362 * if we're switching; e.g. 11a to 11b/g. 4363 */ 4364 mode = ieee80211_chan2mode(ic, chan); 4365 if (mode != sc->sc_curmode) 4366 ath_setcurmode(sc, mode); 4367 /* 4368 * Update BPF state. NB: ethereal et. al. don't handle 4369 * merged flags well so pick a unique mode for their use. 4370 */ 4371 if (IEEE80211_IS_CHAN_A(chan)) 4372 flags = IEEE80211_CHAN_A; 4373 /* XXX 11g schizophrenia */ 4374 else if (IEEE80211_IS_CHAN_G(chan) || 4375 IEEE80211_IS_CHAN_PUREG(chan)) 4376 flags = IEEE80211_CHAN_G; 4377 else 4378 flags = IEEE80211_CHAN_B; 4379 if (IEEE80211_IS_CHAN_T(chan)) 4380 flags |= IEEE80211_CHAN_TURBO; 4381 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4382 htole16(chan->ic_freq); 4383 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4384 htole16(flags); 4385 } 4386 4387 /* 4388 * Poll for a channel clear indication; this is required 4389 * for channels requiring DFS and not previously visited 4390 * and/or with a recent radar detection. 4391 */ 4392 static void 4393 ath_dfswait(void *arg) 4394 { 4395 struct ath_softc *sc = arg; 4396 struct ath_hal *ah = sc->sc_ah; 4397 HAL_CHANNEL hchan; 4398 4399 ath_hal_radar_wait(ah, &hchan); 4400 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4401 if_printf(&sc->sc_if, 4402 "channel %u/0x%x/0x%x has interference\n", 4403 hchan.channel, hchan.channelFlags, hchan.privFlags); 4404 return; 4405 } 4406 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4407 /* XXX should not happen */ 4408 return; 4409 } 4410 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4411 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4412 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4413 if_printf(&sc->sc_if, 4414 "channel %u/0x%x/0x%x marked clear\n", 4415 hchan.channel, hchan.channelFlags, hchan.privFlags); 4416 } else 4417 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4418 } 4419 4420 /* 4421 * Set/change channels. If the channel is really being changed, 4422 * it's done by reseting the chip. To accomplish this we must 4423 * first cleanup any pending DMA, then restart stuff after a la 4424 * ath_init. 4425 */ 4426 static int 4427 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4428 { 4429 struct ath_hal *ah = sc->sc_ah; 4430 struct ieee80211com *ic = &sc->sc_ic; 4431 HAL_CHANNEL hchan; 4432 4433 /* 4434 * Convert to a HAL channel description with 4435 * the flags constrained to reflect the current 4436 * operating mode. 4437 */ 4438 hchan.channel = chan->ic_freq; 4439 hchan.channelFlags = ath_chan2flags(ic, chan); 4440 4441 DPRINTF(sc, ATH_DEBUG_RESET, 4442 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4443 __func__, 4444 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4445 sc->sc_curchan.channelFlags), 4446 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4447 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4448 hchan.channel, hchan.channelFlags); 4449 if (hchan.channel != sc->sc_curchan.channel || 4450 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4451 HAL_STATUS status; 4452 4453 /* 4454 * To switch channels clear any pending DMA operations; 4455 * wait long enough for the RX fifo to drain, reset the 4456 * hardware at the new frequency, and then re-enable 4457 * the relevant bits of the h/w. 4458 */ 4459 ath_hal_intrset(ah, 0); /* disable interrupts */ 4460 ath_draintxq(sc); /* clear pending tx frames */ 4461 ath_stoprecv(sc); /* turn off frame recv */ 4462 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4463 if_printf(ic->ic_ifp, "%s: unable to reset " 4464 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4465 __func__, ieee80211_chan2ieee(ic, chan), 4466 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4467 return EIO; 4468 } 4469 sc->sc_curchan = hchan; 4470 ath_update_txpow(sc); /* update tx power state */ 4471 sc->sc_diversity = ath_hal_getdiversity(ah); 4472 sc->sc_calinterval = 1; 4473 sc->sc_caltries = 0; 4474 4475 /* 4476 * Re-enable rx framework. 4477 */ 4478 if (ath_startrecv(sc) != 0) { 4479 if_printf(&sc->sc_if, 4480 "%s: unable to restart recv logic\n", __func__); 4481 return EIO; 4482 } 4483 4484 /* 4485 * Change channels and update the h/w rate map 4486 * if we're switching; e.g. 11a to 11b/g. 4487 */ 4488 ic->ic_ibss_chan = chan; 4489 ath_chan_change(sc, chan); 4490 4491 /* 4492 * Handle DFS required waiting period to determine 4493 * if channel is clear of radar traffic. 4494 */ 4495 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4496 #define DFS_AND_NOT_CLEAR(_c) \ 4497 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4498 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4499 if_printf(&sc->sc_if, 4500 "wait for DFS clear channel signal\n"); 4501 /* XXX stop sndq */ 4502 sc->sc_if.if_flags |= IFF_OACTIVE; 4503 callout_reset(&sc->sc_dfs_ch, 4504 2 * hz, ath_dfswait, sc); 4505 } else 4506 callout_stop(&sc->sc_dfs_ch); 4507 #undef DFS_NOT_CLEAR 4508 } 4509 4510 /* 4511 * Re-enable interrupts. 4512 */ 4513 ath_hal_intrset(ah, sc->sc_imask); 4514 } 4515 return 0; 4516 } 4517 4518 static void 4519 ath_next_scan(void *arg) 4520 { 4521 struct ath_softc *sc = arg; 4522 struct ieee80211com *ic = &sc->sc_ic; 4523 int s; 4524 4525 /* don't call ath_start w/o network interrupts blocked */ 4526 s = splnet(); 4527 4528 if (ic->ic_state == IEEE80211_S_SCAN) 4529 ieee80211_next_scan(ic); 4530 splx(s); 4531 } 4532 4533 /* 4534 * Periodically recalibrate the PHY to account 4535 * for temperature/environment changes. 4536 */ 4537 static void 4538 ath_calibrate(void *arg) 4539 { 4540 struct ath_softc *sc = arg; 4541 struct ath_hal *ah = sc->sc_ah; 4542 HAL_BOOL iqCalDone; 4543 4544 sc->sc_stats.ast_per_cal++; 4545 4546 ATH_LOCK(sc); 4547 4548 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4549 /* 4550 * Rfgain is out of bounds, reset the chip 4551 * to load new gain values. 4552 */ 4553 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4554 "%s: rfgain change\n", __func__); 4555 sc->sc_stats.ast_per_rfgain++; 4556 ath_reset(&sc->sc_if); 4557 } 4558 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4559 DPRINTF(sc, ATH_DEBUG_ANY, 4560 "%s: calibration of channel %u failed\n", 4561 __func__, sc->sc_curchan.channel); 4562 sc->sc_stats.ast_per_calfail++; 4563 } 4564 /* 4565 * Calibrate noise floor data again in case of change. 4566 */ 4567 ath_hal_process_noisefloor(ah); 4568 /* 4569 * Poll more frequently when the IQ calibration is in 4570 * progress to speedup loading the final settings. 4571 * We temper this aggressive polling with an exponential 4572 * back off after 4 tries up to ath_calinterval. 4573 */ 4574 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4575 sc->sc_caltries = 0; 4576 sc->sc_calinterval = ath_calinterval; 4577 } else if (sc->sc_caltries > 4) { 4578 sc->sc_caltries = 0; 4579 sc->sc_calinterval <<= 1; 4580 if (sc->sc_calinterval > ath_calinterval) 4581 sc->sc_calinterval = ath_calinterval; 4582 } 4583 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4584 ("bad calibration interval %u", sc->sc_calinterval)); 4585 4586 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4587 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4588 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4589 sc->sc_caltries++; 4590 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4591 ath_calibrate, sc); 4592 ATH_UNLOCK(sc); 4593 } 4594 4595 static int 4596 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4597 { 4598 struct ifnet *ifp = ic->ic_ifp; 4599 struct ath_softc *sc = ifp->if_softc; 4600 struct ath_hal *ah = sc->sc_ah; 4601 struct ieee80211_node *ni; 4602 int i, error; 4603 const u_int8_t *bssid; 4604 u_int32_t rfilt; 4605 static const HAL_LED_STATE leds[] = { 4606 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4607 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4608 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4609 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4610 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4611 }; 4612 4613 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4614 ieee80211_state_name[ic->ic_state], 4615 ieee80211_state_name[nstate]); 4616 4617 callout_stop(&sc->sc_scan_ch); 4618 callout_stop(&sc->sc_cal_ch); 4619 callout_stop(&sc->sc_dfs_ch); 4620 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4621 4622 if (nstate == IEEE80211_S_INIT) { 4623 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4624 /* 4625 * NB: disable interrupts so we don't rx frames. 4626 */ 4627 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4628 /* 4629 * Notify the rate control algorithm. 4630 */ 4631 ath_rate_newstate(sc, nstate); 4632 goto done; 4633 } 4634 ni = ic->ic_bss; 4635 error = ath_chan_set(sc, ic->ic_curchan); 4636 if (error != 0) 4637 goto bad; 4638 rfilt = ath_calcrxfilter(sc, nstate); 4639 if (nstate == IEEE80211_S_SCAN) 4640 bssid = ifp->if_broadcastaddr; 4641 else 4642 bssid = ni->ni_bssid; 4643 ath_hal_setrxfilter(ah, rfilt); 4644 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4645 __func__, rfilt, ether_sprintf(bssid)); 4646 4647 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4648 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4649 else 4650 ath_hal_setassocid(ah, bssid, 0); 4651 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4652 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4653 if (ath_hal_keyisvalid(ah, i)) 4654 ath_hal_keysetmac(ah, i, bssid); 4655 } 4656 4657 /* 4658 * Notify the rate control algorithm so rates 4659 * are setup should ath_beacon_alloc be called. 4660 */ 4661 ath_rate_newstate(sc, nstate); 4662 4663 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4664 /* nothing to do */; 4665 } else if (nstate == IEEE80211_S_RUN) { 4666 DPRINTF(sc, ATH_DEBUG_STATE, 4667 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4668 "capinfo=0x%04x chan=%d\n" 4669 , __func__ 4670 , ic->ic_flags 4671 , ni->ni_intval 4672 , ether_sprintf(ni->ni_bssid) 4673 , ni->ni_capinfo 4674 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4675 4676 switch (ic->ic_opmode) { 4677 case IEEE80211_M_HOSTAP: 4678 case IEEE80211_M_IBSS: 4679 /* 4680 * Allocate and setup the beacon frame. 4681 * 4682 * Stop any previous beacon DMA. This may be 4683 * necessary, for example, when an ibss merge 4684 * causes reconfiguration; there will be a state 4685 * transition from RUN->RUN that means we may 4686 * be called with beacon transmission active. 4687 */ 4688 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4689 ath_beacon_free(sc); 4690 error = ath_beacon_alloc(sc, ni); 4691 if (error != 0) 4692 goto bad; 4693 /* 4694 * If joining an adhoc network defer beacon timer 4695 * configuration to the next beacon frame so we 4696 * have a current TSF to use. Otherwise we're 4697 * starting an ibss/bss so there's no need to delay. 4698 */ 4699 if (ic->ic_opmode == IEEE80211_M_IBSS && 4700 ic->ic_bss->ni_tstamp.tsf != 0) 4701 sc->sc_syncbeacon = 1; 4702 else 4703 ath_beacon_config(sc); 4704 break; 4705 case IEEE80211_M_STA: 4706 /* 4707 * Allocate a key cache slot to the station. 4708 */ 4709 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4710 sc->sc_hasclrkey && 4711 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4712 ath_setup_stationkey(ni); 4713 /* 4714 * Defer beacon timer configuration to the next 4715 * beacon frame so we have a current TSF to use 4716 * (any TSF collected when scanning is likely old). 4717 */ 4718 sc->sc_syncbeacon = 1; 4719 break; 4720 default: 4721 break; 4722 } 4723 /* 4724 * Let the hal process statistics collected during a 4725 * scan so it can provide calibrated noise floor data. 4726 */ 4727 ath_hal_process_noisefloor(ah); 4728 /* 4729 * Reset rssi stats; maybe not the best place... 4730 */ 4731 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4732 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4733 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4734 } else { 4735 ath_hal_intrset(ah, 4736 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4737 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4738 } 4739 done: 4740 /* 4741 * Invoke the parent method to complete the work. 4742 */ 4743 error = sc->sc_newstate(ic, nstate, arg); 4744 /* 4745 * Finally, start any timers. 4746 */ 4747 if (nstate == IEEE80211_S_RUN) { 4748 /* start periodic recalibration timer */ 4749 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4750 ath_calibrate, sc); 4751 } else if (nstate == IEEE80211_S_SCAN) { 4752 /* start ap/neighbor scan timer */ 4753 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4754 ath_next_scan, sc); 4755 } 4756 bad: 4757 return error; 4758 } 4759 4760 /* 4761 * Allocate a key cache slot to the station so we can 4762 * setup a mapping from key index to node. The key cache 4763 * slot is needed for managing antenna state and for 4764 * compression when stations do not use crypto. We do 4765 * it uniliaterally here; if crypto is employed this slot 4766 * will be reassigned. 4767 */ 4768 static void 4769 ath_setup_stationkey(struct ieee80211_node *ni) 4770 { 4771 struct ieee80211com *ic = ni->ni_ic; 4772 struct ath_softc *sc = ic->ic_ifp->if_softc; 4773 ieee80211_keyix keyix, rxkeyix; 4774 4775 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4776 /* 4777 * Key cache is full; we'll fall back to doing 4778 * the more expensive lookup in software. Note 4779 * this also means no h/w compression. 4780 */ 4781 /* XXX msg+statistic */ 4782 } else { 4783 /* XXX locking? */ 4784 ni->ni_ucastkey.wk_keyix = keyix; 4785 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4786 /* NB: this will create a pass-thru key entry */ 4787 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4788 } 4789 } 4790 4791 /* 4792 * Setup driver-specific state for a newly associated node. 4793 * Note that we're called also on a re-associate, the isnew 4794 * param tells us if this is the first time or not. 4795 */ 4796 static void 4797 ath_newassoc(struct ieee80211_node *ni, int isnew) 4798 { 4799 struct ieee80211com *ic = ni->ni_ic; 4800 struct ath_softc *sc = ic->ic_ifp->if_softc; 4801 4802 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4803 if (isnew && 4804 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4805 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4806 ("new assoc with a unicast key already setup (keyix %u)", 4807 ni->ni_ucastkey.wk_keyix)); 4808 ath_setup_stationkey(ni); 4809 } 4810 } 4811 4812 static int 4813 ath_getchannels(struct ath_softc *sc, u_int cc, 4814 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4815 { 4816 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4817 struct ieee80211com *ic = &sc->sc_ic; 4818 struct ifnet *ifp = &sc->sc_if; 4819 struct ath_hal *ah = sc->sc_ah; 4820 HAL_CHANNEL *chans; 4821 int i, ix, nchan; 4822 4823 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4824 M_TEMP, M_NOWAIT); 4825 if (chans == NULL) { 4826 if_printf(ifp, "unable to allocate channel table\n"); 4827 return ENOMEM; 4828 } 4829 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4830 NULL, 0, NULL, 4831 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4832 u_int32_t rd; 4833 4834 (void)ath_hal_getregdomain(ah, &rd); 4835 if_printf(ifp, "unable to collect channel list from hal; " 4836 "regdomain likely %u country code %u\n", rd, cc); 4837 free(chans, M_TEMP); 4838 return EINVAL; 4839 } 4840 4841 /* 4842 * Convert HAL channels to ieee80211 ones and insert 4843 * them in the table according to their channel number. 4844 */ 4845 for (i = 0; i < nchan; i++) { 4846 HAL_CHANNEL *c = &chans[i]; 4847 u_int16_t flags; 4848 4849 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4850 if (ix > IEEE80211_CHAN_MAX) { 4851 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4852 ix, c->channel, c->channelFlags); 4853 continue; 4854 } 4855 if (ix < 0) { 4856 /* XXX can't handle stuff <2400 right now */ 4857 if (bootverbose) 4858 if_printf(ifp, "hal channel %d (%u/%x) " 4859 "cannot be handled; ignored\n", 4860 ix, c->channel, c->channelFlags); 4861 continue; 4862 } 4863 /* 4864 * Calculate net80211 flags; most are compatible 4865 * but some need massaging. Note the static turbo 4866 * conversion can be removed once net80211 is updated 4867 * to understand static vs. dynamic turbo. 4868 */ 4869 flags = c->channelFlags & COMPAT; 4870 if (c->channelFlags & CHANNEL_STURBO) 4871 flags |= IEEE80211_CHAN_TURBO; 4872 if (ic->ic_channels[ix].ic_freq == 0) { 4873 ic->ic_channels[ix].ic_freq = c->channel; 4874 ic->ic_channels[ix].ic_flags = flags; 4875 } else { 4876 /* channels overlap; e.g. 11g and 11b */ 4877 ic->ic_channels[ix].ic_flags |= flags; 4878 } 4879 } 4880 free(chans, M_TEMP); 4881 return 0; 4882 #undef COMPAT 4883 } 4884 4885 static void 4886 ath_led_done(void *arg) 4887 { 4888 struct ath_softc *sc = arg; 4889 4890 sc->sc_blinking = 0; 4891 } 4892 4893 /* 4894 * Turn the LED off: flip the pin and then set a timer so no 4895 * update will happen for the specified duration. 4896 */ 4897 static void 4898 ath_led_off(void *arg) 4899 { 4900 struct ath_softc *sc = arg; 4901 4902 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4903 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4904 } 4905 4906 /* 4907 * Blink the LED according to the specified on/off times. 4908 */ 4909 static void 4910 ath_led_blink(struct ath_softc *sc, int on, int off) 4911 { 4912 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4913 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4914 sc->sc_blinking = 1; 4915 sc->sc_ledoff = off; 4916 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4917 } 4918 4919 static void 4920 ath_led_event(struct ath_softc *sc, int event) 4921 { 4922 4923 sc->sc_ledevent = ticks; /* time of last event */ 4924 if (sc->sc_blinking) /* don't interrupt active blink */ 4925 return; 4926 switch (event) { 4927 case ATH_LED_POLL: 4928 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4929 sc->sc_hwmap[0].ledoff); 4930 break; 4931 case ATH_LED_TX: 4932 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4933 sc->sc_hwmap[sc->sc_txrate].ledoff); 4934 break; 4935 case ATH_LED_RX: 4936 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4937 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4938 break; 4939 } 4940 } 4941 4942 static void 4943 ath_update_txpow(struct ath_softc *sc) 4944 { 4945 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4946 struct ieee80211com *ic = &sc->sc_ic; 4947 struct ath_hal *ah = sc->sc_ah; 4948 u_int32_t txpow; 4949 4950 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4951 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4952 /* read back in case value is clamped */ 4953 (void)ath_hal_gettxpowlimit(ah, &txpow); 4954 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4955 } 4956 /* 4957 * Fetch max tx power level for status requests. 4958 */ 4959 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4960 ic->ic_bss->ni_txpower = txpow; 4961 } 4962 4963 static void 4964 rate_setup(struct ath_softc *sc, 4965 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4966 { 4967 int i, maxrates; 4968 4969 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4970 DPRINTF(sc, ATH_DEBUG_ANY, 4971 "%s: rate table too small (%u > %u)\n", 4972 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4973 maxrates = IEEE80211_RATE_MAXSIZE; 4974 } else 4975 maxrates = rt->rateCount; 4976 for (i = 0; i < maxrates; i++) 4977 rs->rs_rates[i] = rt->info[i].dot11Rate; 4978 rs->rs_nrates = maxrates; 4979 } 4980 4981 static int 4982 ath_rate_setup(struct ath_softc *sc, u_int mode) 4983 { 4984 struct ath_hal *ah = sc->sc_ah; 4985 struct ieee80211com *ic = &sc->sc_ic; 4986 const HAL_RATE_TABLE *rt; 4987 4988 switch (mode) { 4989 case IEEE80211_MODE_11A: 4990 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4991 break; 4992 case IEEE80211_MODE_11B: 4993 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4994 break; 4995 case IEEE80211_MODE_11G: 4996 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4997 break; 4998 case IEEE80211_MODE_TURBO_A: 4999 /* XXX until static/dynamic turbo is fixed */ 5000 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5001 break; 5002 case IEEE80211_MODE_TURBO_G: 5003 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5004 break; 5005 default: 5006 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5007 __func__, mode); 5008 return 0; 5009 } 5010 sc->sc_rates[mode] = rt; 5011 if (rt != NULL) { 5012 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5013 return 1; 5014 } else 5015 return 0; 5016 } 5017 5018 static void 5019 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5020 { 5021 #define N(a) (sizeof(a)/sizeof(a[0])) 5022 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5023 static const struct { 5024 u_int rate; /* tx/rx 802.11 rate */ 5025 u_int16_t timeOn; /* LED on time (ms) */ 5026 u_int16_t timeOff; /* LED off time (ms) */ 5027 } blinkrates[] = { 5028 { 108, 40, 10 }, 5029 { 96, 44, 11 }, 5030 { 72, 50, 13 }, 5031 { 48, 57, 14 }, 5032 { 36, 67, 16 }, 5033 { 24, 80, 20 }, 5034 { 22, 100, 25 }, 5035 { 18, 133, 34 }, 5036 { 12, 160, 40 }, 5037 { 10, 200, 50 }, 5038 { 6, 240, 58 }, 5039 { 4, 267, 66 }, 5040 { 2, 400, 100 }, 5041 { 0, 500, 130 }, 5042 }; 5043 const HAL_RATE_TABLE *rt; 5044 int i, j; 5045 5046 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5047 rt = sc->sc_rates[mode]; 5048 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5049 for (i = 0; i < rt->rateCount; i++) 5050 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5051 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5052 for (i = 0; i < 32; i++) { 5053 u_int8_t ix = rt->rateCodeToIndex[i]; 5054 if (ix == 0xff) { 5055 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5056 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5057 continue; 5058 } 5059 sc->sc_hwmap[i].ieeerate = 5060 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5061 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5062 if (rt->info[ix].shortPreamble || 5063 rt->info[ix].phy == IEEE80211_T_OFDM) 5064 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5065 /* NB: receive frames include FCS */ 5066 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5067 IEEE80211_RADIOTAP_F_FCS; 5068 /* setup blink rate table to avoid per-packet lookup */ 5069 for (j = 0; j < N(blinkrates)-1; j++) 5070 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5071 break; 5072 /* NB: this uses the last entry if the rate isn't found */ 5073 /* XXX beware of overlow */ 5074 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5075 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5076 } 5077 sc->sc_currates = rt; 5078 sc->sc_curmode = mode; 5079 /* 5080 * All protection frames are transmited at 2Mb/s for 5081 * 11g, otherwise at 1Mb/s. 5082 */ 5083 if (mode == IEEE80211_MODE_11G) 5084 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5085 else 5086 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5087 /* rate index used to send management frames */ 5088 sc->sc_minrateix = 0; 5089 /* 5090 * Setup multicast rate state. 5091 */ 5092 /* XXX layering violation */ 5093 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5094 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5095 /* NB: caller is responsible for reseting rate control state */ 5096 #undef N 5097 } 5098 5099 #ifdef AR_DEBUG 5100 static void 5101 ath_printrxbuf(struct ath_buf *bf, int done) 5102 { 5103 struct ath_desc *ds; 5104 int i; 5105 5106 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5107 printf("R%d (%p %" PRIx64 5108 ") %08x %08x %08x %08x %08x %08x %c\n", i, ds, 5109 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5110 ds->ds_link, ds->ds_data, 5111 ds->ds_ctl0, ds->ds_ctl1, 5112 ds->ds_hw[0], ds->ds_hw[1], 5113 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5114 } 5115 } 5116 5117 static void 5118 ath_printtxbuf(struct ath_buf *bf, int done) 5119 { 5120 struct ath_desc *ds; 5121 int i; 5122 5123 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5124 printf("T%d (%p %" PRIx64 5125 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5126 i, ds, 5127 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5128 ds->ds_link, ds->ds_data, 5129 ds->ds_ctl0, ds->ds_ctl1, 5130 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5131 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5132 } 5133 } 5134 #endif /* AR_DEBUG */ 5135 5136 static void 5137 ath_watchdog(struct ifnet *ifp) 5138 { 5139 struct ath_softc *sc = ifp->if_softc; 5140 struct ieee80211com *ic = &sc->sc_ic; 5141 struct ath_txq *axq; 5142 int i; 5143 5144 ifp->if_timer = 0; 5145 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 5146 return; 5147 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5148 if (!ATH_TXQ_SETUP(sc, i)) 5149 continue; 5150 axq = &sc->sc_txq[i]; 5151 ATH_TXQ_LOCK(axq); 5152 if (axq->axq_timer == 0) 5153 ; 5154 else if (--axq->axq_timer == 0) { 5155 ATH_TXQ_UNLOCK(axq); 5156 if_printf(ifp, "device timeout (txq %d)\n", i); 5157 ath_reset(ifp); 5158 ifp->if_oerrors++; 5159 sc->sc_stats.ast_watchdog++; 5160 break; 5161 } else 5162 ifp->if_timer = 1; 5163 ATH_TXQ_UNLOCK(axq); 5164 } 5165 ieee80211_watchdog(ic); 5166 } 5167 5168 /* 5169 * Diagnostic interface to the HAL. This is used by various 5170 * tools to do things like retrieve register contents for 5171 * debugging. The mechanism is intentionally opaque so that 5172 * it can change frequently w/o concern for compatiblity. 5173 */ 5174 static int 5175 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5176 { 5177 struct ath_hal *ah = sc->sc_ah; 5178 u_int id = ad->ad_id & ATH_DIAG_ID; 5179 void *indata = NULL; 5180 void *outdata = NULL; 5181 u_int32_t insize = ad->ad_in_size; 5182 u_int32_t outsize = ad->ad_out_size; 5183 int error = 0; 5184 5185 if (ad->ad_id & ATH_DIAG_IN) { 5186 /* 5187 * Copy in data. 5188 */ 5189 indata = malloc(insize, M_TEMP, M_NOWAIT); 5190 if (indata == NULL) { 5191 error = ENOMEM; 5192 goto bad; 5193 } 5194 error = copyin(ad->ad_in_data, indata, insize); 5195 if (error) 5196 goto bad; 5197 } 5198 if (ad->ad_id & ATH_DIAG_DYN) { 5199 /* 5200 * Allocate a buffer for the results (otherwise the HAL 5201 * returns a pointer to a buffer where we can read the 5202 * results). Note that we depend on the HAL leaving this 5203 * pointer for us to use below in reclaiming the buffer; 5204 * may want to be more defensive. 5205 */ 5206 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5207 if (outdata == NULL) { 5208 error = ENOMEM; 5209 goto bad; 5210 } 5211 } 5212 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5213 if (outsize < ad->ad_out_size) 5214 ad->ad_out_size = outsize; 5215 if (outdata != NULL) 5216 error = copyout(outdata, ad->ad_out_data, 5217 ad->ad_out_size); 5218 } else { 5219 error = EINVAL; 5220 } 5221 bad: 5222 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5223 free(indata, M_TEMP); 5224 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5225 free(outdata, M_TEMP); 5226 return error; 5227 } 5228 5229 static int 5230 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5231 { 5232 #define IS_RUNNING(ifp) \ 5233 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5234 struct ath_softc *sc = ifp->if_softc; 5235 struct ieee80211com *ic = &sc->sc_ic; 5236 struct ifreq *ifr = (struct ifreq *)data; 5237 int error = 0; 5238 5239 ATH_LOCK(sc); 5240 switch (cmd) { 5241 case SIOCSIFFLAGS: 5242 if (IS_RUNNING(ifp)) { 5243 /* 5244 * To avoid rescanning another access point, 5245 * do not call ath_init() here. Instead, 5246 * only reflect promisc mode settings. 5247 */ 5248 ath_mode_init(sc); 5249 } else if (ifp->if_flags & IFF_UP) { 5250 /* 5251 * Beware of being called during attach/detach 5252 * to reset promiscuous mode. In that case we 5253 * will still be marked UP but not RUNNING. 5254 * However trying to re-init the interface 5255 * is the wrong thing to do as we've already 5256 * torn down much of our state. There's 5257 * probably a better way to deal with this. 5258 */ 5259 if (!sc->sc_invalid && ic->ic_bss != NULL) 5260 ath_init(sc); /* XXX lose error */ 5261 } else 5262 ath_stop_locked(ifp, 1); 5263 break; 5264 case SIOCADDMULTI: 5265 case SIOCDELMULTI: 5266 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5267 if (ifp->if_flags & IFF_RUNNING) 5268 ath_mode_init(sc); 5269 error = 0; 5270 } 5271 break; 5272 case SIOCGATHSTATS: 5273 /* NB: embed these numbers to get a consistent view */ 5274 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5275 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5276 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5277 ATH_UNLOCK(sc); 5278 /* 5279 * NB: Drop the softc lock in case of a page fault; 5280 * we'll accept any potential inconsisentcy in the 5281 * statistics. The alternative is to copy the data 5282 * to a local structure. 5283 */ 5284 return copyout(&sc->sc_stats, 5285 ifr->ifr_data, sizeof (sc->sc_stats)); 5286 case SIOCGATHDIAG: 5287 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5288 break; 5289 default: 5290 error = ieee80211_ioctl(ic, cmd, data); 5291 if (error == ENETRESET) { 5292 if (IS_RUNNING(ifp) && 5293 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5294 ath_init(sc); /* XXX lose error */ 5295 error = 0; 5296 } 5297 if (error == ERESTART) 5298 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5299 break; 5300 } 5301 ATH_UNLOCK(sc); 5302 return error; 5303 #undef IS_RUNNING 5304 } 5305 5306 #if NBPFILTER > 0 5307 static void 5308 ath_bpfattach(struct ath_softc *sc) 5309 { 5310 struct ifnet *ifp = &sc->sc_if; 5311 5312 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5313 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5314 &sc->sc_drvbpf); 5315 /* 5316 * Initialize constant fields. 5317 * XXX make header lengths a multiple of 32-bits so subsequent 5318 * headers are properly aligned; this is a kludge to keep 5319 * certain applications happy. 5320 * 5321 * NB: the channel is setup each time we transition to the 5322 * RUN state to avoid filling it in for each frame. 5323 */ 5324 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5325 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5326 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5327 5328 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5329 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5330 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5331 } 5332 #endif 5333 5334 /* 5335 * Announce various information on device/driver attach. 5336 */ 5337 static void 5338 ath_announce(struct ath_softc *sc) 5339 { 5340 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5341 struct ifnet *ifp = &sc->sc_if; 5342 struct ath_hal *ah = sc->sc_ah; 5343 u_int modes, cc; 5344 5345 if_printf(ifp, "mac %d.%d phy %d.%d", 5346 ah->ah_macVersion, ah->ah_macRev, 5347 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5348 /* 5349 * Print radio revision(s). We check the wireless modes 5350 * to avoid falsely printing revs for inoperable parts. 5351 * Dual-band radio revs are returned in the 5 GHz rev number. 5352 */ 5353 ath_hal_getcountrycode(ah, &cc); 5354 modes = ath_hal_getwirelessmodes(ah, cc); 5355 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5356 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5357 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5358 ah->ah_analog5GhzRev >> 4, 5359 ah->ah_analog5GhzRev & 0xf, 5360 ah->ah_analog2GhzRev >> 4, 5361 ah->ah_analog2GhzRev & 0xf); 5362 else 5363 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5364 ah->ah_analog5GhzRev & 0xf); 5365 } else 5366 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5367 ah->ah_analog5GhzRev & 0xf); 5368 printf("\n"); 5369 if (bootverbose) { 5370 int i; 5371 for (i = 0; i <= WME_AC_VO; i++) { 5372 struct ath_txq *txq = sc->sc_ac2q[i]; 5373 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5374 txq->axq_qnum, ieee80211_wme_acnames[i]); 5375 } 5376 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5377 sc->sc_cabq->axq_qnum); 5378 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5379 } 5380 if (ath_rxbuf != ATH_RXBUF) 5381 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5382 if (ath_txbuf != ATH_TXBUF) 5383 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5384 #undef HAL_MODE_DUALBAND 5385 } 5386