1 /* $NetBSD: ath.c,v 1.113 2011/11/28 00:30:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.113 2011/11/28 00:30:17 jmcneill Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #ifdef _KERNEL_OPT 55 #include "opt_inet.h" 56 #endif 57 58 #include <sys/param.h> 59 #include <sys/reboot.h> 60 #include <sys/systm.h> 61 #include <sys/types.h> 62 #include <sys/sysctl.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/errno.h> 69 #include <sys/callout.h> 70 #include <sys/bus.h> 71 #include <sys/endian.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_arp.h> 78 #include <net/if_ether.h> 79 #include <net/if_llc.h> 80 81 #include <net80211/ieee80211_netbsd.h> 82 #include <net80211/ieee80211_var.h> 83 84 #include <net/bpf.h> 85 86 #ifdef INET 87 #include <netinet/in.h> 88 #endif 89 90 #include <sys/device.h> 91 #include <dev/ic/ath_netbsd.h> 92 93 #define AR_DEBUG 94 #include <dev/ic/athvar.h> 95 #include "ah_desc.h" 96 #include "ah_devid.h" /* XXX for softled */ 97 #include "opt_ah.h" 98 99 #ifdef ATH_TX99_DIAG 100 #include <dev/ath/ath_tx99/ath_tx99.h> 101 #endif 102 103 /* unaligned little endian access */ 104 #define LE_READ_2(p) \ 105 ((u_int16_t) \ 106 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 107 #define LE_READ_4(p) \ 108 ((u_int32_t) \ 109 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 110 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 111 112 enum { 113 ATH_LED_TX, 114 ATH_LED_RX, 115 ATH_LED_POLL, 116 }; 117 118 #ifdef AH_NEED_DESC_SWAP 119 #define HTOAH32(x) htole32(x) 120 #else 121 #define HTOAH32(x) (x) 122 #endif 123 124 static int ath_ifinit(struct ifnet *); 125 static int ath_init(struct ath_softc *); 126 static void ath_stop_locked(struct ifnet *, int); 127 static void ath_stop(struct ifnet *, int); 128 static void ath_start(struct ifnet *); 129 static int ath_media_change(struct ifnet *); 130 static void ath_watchdog(struct ifnet *); 131 static int ath_ioctl(struct ifnet *, u_long, void *); 132 static void ath_fatal_proc(void *, int); 133 static void ath_rxorn_proc(void *, int); 134 static void ath_bmiss_proc(void *, int); 135 static void ath_radar_proc(void *, int); 136 static int ath_key_alloc(struct ieee80211com *, 137 const struct ieee80211_key *, 138 ieee80211_keyix *, ieee80211_keyix *); 139 static int ath_key_delete(struct ieee80211com *, 140 const struct ieee80211_key *); 141 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 142 const u_int8_t mac[IEEE80211_ADDR_LEN]); 143 static void ath_key_update_begin(struct ieee80211com *); 144 static void ath_key_update_end(struct ieee80211com *); 145 static void ath_mode_init(struct ath_softc *); 146 static void ath_setslottime(struct ath_softc *); 147 static void ath_updateslot(struct ifnet *); 148 static int ath_beaconq_setup(struct ath_hal *); 149 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 150 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 151 static void ath_beacon_proc(void *, int); 152 static void ath_bstuck_proc(void *, int); 153 static void ath_beacon_free(struct ath_softc *); 154 static void ath_beacon_config(struct ath_softc *); 155 static void ath_descdma_cleanup(struct ath_softc *sc, 156 struct ath_descdma *, ath_bufhead *); 157 static int ath_desc_alloc(struct ath_softc *); 158 static void ath_desc_free(struct ath_softc *); 159 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 160 static void ath_node_free(struct ieee80211_node *); 161 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 162 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 163 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 164 struct ieee80211_node *ni, 165 int subtype, int rssi, u_int32_t rstamp); 166 static void ath_setdefantenna(struct ath_softc *, u_int); 167 static void ath_rx_proc(void *, int); 168 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 169 static int ath_tx_setup(struct ath_softc *, int, int); 170 static int ath_wme_update(struct ieee80211com *); 171 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 172 static void ath_tx_cleanup(struct ath_softc *); 173 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 174 struct ath_buf *, struct mbuf *); 175 static void ath_tx_proc_q0(void *, int); 176 static void ath_tx_proc_q0123(void *, int); 177 static void ath_tx_proc(void *, int); 178 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 179 static void ath_draintxq(struct ath_softc *); 180 static void ath_stoprecv(struct ath_softc *); 181 static int ath_startrecv(struct ath_softc *); 182 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_next_scan(void *); 184 static void ath_calibrate(void *); 185 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 186 static void ath_setup_stationkey(struct ieee80211_node *); 187 static void ath_newassoc(struct ieee80211_node *, int); 188 static int ath_getchannels(struct ath_softc *, u_int cc, 189 HAL_BOOL outdoor, HAL_BOOL xchanmode); 190 static void ath_led_event(struct ath_softc *, int); 191 static void ath_update_txpow(struct ath_softc *); 192 static void ath_freetx(struct mbuf *); 193 static void ath_restore_diversity(struct ath_softc *); 194 195 static int ath_rate_setup(struct ath_softc *, u_int mode); 196 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 197 198 static void ath_bpfattach(struct ath_softc *); 199 static void ath_announce(struct ath_softc *); 200 201 int ath_dwelltime = 200; /* 5 channels/second */ 202 int ath_calinterval = 30; /* calibrate every 30 secs */ 203 int ath_outdoor = AH_TRUE; /* outdoor operation */ 204 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 205 int ath_countrycode = CTRY_DEFAULT; /* country code */ 206 int ath_regdomain = 0; /* regulatory domain */ 207 int ath_debug = 0; 208 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 209 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 210 211 #ifdef AR_DEBUG 212 enum { 213 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 214 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 215 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 216 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 217 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 218 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 219 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 220 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 221 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 222 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 223 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 224 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 225 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 226 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 227 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 228 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 229 ATH_DEBUG_NODE = 0x00080000, /* node management */ 230 ATH_DEBUG_LED = 0x00100000, /* led management */ 231 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 232 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 233 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 234 ATH_DEBUG_ANY = 0xffffffff 235 }; 236 #define IFF_DUMPPKTS(sc, m) \ 237 ((sc->sc_debug & (m)) || \ 238 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 239 #define DPRINTF(sc, m, fmt, ...) do { \ 240 if (sc->sc_debug & (m)) \ 241 printf(fmt, __VA_ARGS__); \ 242 } while (0) 243 #define KEYPRINTF(sc, ix, hk, mac) do { \ 244 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 245 ath_keyprint(__func__, ix, hk, mac); \ 246 } while (0) 247 static void ath_printrxbuf(struct ath_buf *bf, int); 248 static void ath_printtxbuf(struct ath_buf *bf, int); 249 #else 250 #define IFF_DUMPPKTS(sc, m) \ 251 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 252 #define DPRINTF(m, fmt, ...) 253 #define KEYPRINTF(sc, k, ix, mac) 254 #endif 255 256 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 257 258 int 259 ath_attach(u_int16_t devid, struct ath_softc *sc) 260 { 261 struct ifnet *ifp = &sc->sc_if; 262 struct ieee80211com *ic = &sc->sc_ic; 263 struct ath_hal *ah = NULL; 264 HAL_STATUS status; 265 int error = 0, i; 266 267 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 268 269 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 270 271 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 272 273 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 274 if (ah == NULL) { 275 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 276 status); 277 error = ENXIO; 278 goto bad; 279 } 280 if (ah->ah_abi != HAL_ABI_VERSION) { 281 if_printf(ifp, "HAL ABI mismatch detected " 282 "(HAL:0x%x != driver:0x%x)\n", 283 ah->ah_abi, HAL_ABI_VERSION); 284 error = ENXIO; 285 goto bad; 286 } 287 sc->sc_ah = ah; 288 289 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 290 "pmf-powerdown", false)) 291 goto bad; 292 293 /* 294 * Check if the MAC has multi-rate retry support. 295 * We do this by trying to setup a fake extended 296 * descriptor. MAC's that don't have support will 297 * return false w/o doing anything. MAC's that do 298 * support it will return true w/o doing anything. 299 */ 300 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 301 302 /* 303 * Check if the device has hardware counters for PHY 304 * errors. If so we need to enable the MIB interrupt 305 * so we can act on stat triggers. 306 */ 307 if (ath_hal_hwphycounters(ah)) 308 sc->sc_needmib = 1; 309 310 /* 311 * Get the hardware key cache size. 312 */ 313 sc->sc_keymax = ath_hal_keycachesize(ah); 314 if (sc->sc_keymax > ATH_KEYMAX) { 315 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 316 ATH_KEYMAX, sc->sc_keymax); 317 sc->sc_keymax = ATH_KEYMAX; 318 } 319 /* 320 * Reset the key cache since some parts do not 321 * reset the contents on initial power up. 322 */ 323 for (i = 0; i < sc->sc_keymax; i++) 324 ath_hal_keyreset(ah, i); 325 /* 326 * Mark key cache slots associated with global keys 327 * as in use. If we knew TKIP was not to be used we 328 * could leave the +32, +64, and +32+64 slots free. 329 * XXX only for splitmic. 330 */ 331 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 332 setbit(sc->sc_keymap, i); 333 setbit(sc->sc_keymap, i+32); 334 setbit(sc->sc_keymap, i+64); 335 setbit(sc->sc_keymap, i+32+64); 336 } 337 338 /* 339 * Collect the channel list using the default country 340 * code and including outdoor channels. The 802.11 layer 341 * is resposible for filtering this list based on settings 342 * like the phy mode. 343 */ 344 error = ath_getchannels(sc, ath_countrycode, 345 ath_outdoor, ath_xchanmode); 346 if (error != 0) 347 goto bad; 348 349 /* 350 * Setup rate tables for all potential media types. 351 */ 352 ath_rate_setup(sc, IEEE80211_MODE_11A); 353 ath_rate_setup(sc, IEEE80211_MODE_11B); 354 ath_rate_setup(sc, IEEE80211_MODE_11G); 355 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 356 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 357 /* NB: setup here so ath_rate_update is happy */ 358 ath_setcurmode(sc, IEEE80211_MODE_11A); 359 360 /* 361 * Allocate tx+rx descriptors and populate the lists. 362 */ 363 error = ath_desc_alloc(sc); 364 if (error != 0) { 365 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 366 goto bad; 367 } 368 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 369 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 370 #if 0 371 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 372 #endif 373 374 ATH_TXBUF_LOCK_INIT(sc); 375 376 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 377 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 378 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 379 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 380 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 381 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 382 383 /* 384 * Allocate hardware transmit queues: one queue for 385 * beacon frames and one data queue for each QoS 386 * priority. Note that the hal handles reseting 387 * these queues at the needed time. 388 * 389 * XXX PS-Poll 390 */ 391 sc->sc_bhalq = ath_beaconq_setup(ah); 392 if (sc->sc_bhalq == (u_int) -1) { 393 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 394 error = EIO; 395 goto bad2; 396 } 397 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 398 if (sc->sc_cabq == NULL) { 399 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 400 error = EIO; 401 goto bad2; 402 } 403 /* NB: insure BK queue is the lowest priority h/w queue */ 404 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 405 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 406 ieee80211_wme_acnames[WME_AC_BK]); 407 error = EIO; 408 goto bad2; 409 } 410 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 411 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 412 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 413 /* 414 * Not enough hardware tx queues to properly do WME; 415 * just punt and assign them all to the same h/w queue. 416 * We could do a better job of this if, for example, 417 * we allocate queues when we switch from station to 418 * AP mode. 419 */ 420 if (sc->sc_ac2q[WME_AC_VI] != NULL) 421 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 422 if (sc->sc_ac2q[WME_AC_BE] != NULL) 423 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 424 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 425 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 426 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 427 } 428 429 /* 430 * Special case certain configurations. Note the 431 * CAB queue is handled by these specially so don't 432 * include them when checking the txq setup mask. 433 */ 434 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 435 case 0x01: 436 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 437 break; 438 case 0x0f: 439 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 440 break; 441 default: 442 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 443 break; 444 } 445 446 /* 447 * Setup rate control. Some rate control modules 448 * call back to change the anntena state so expose 449 * the necessary entry points. 450 * XXX maybe belongs in struct ath_ratectrl? 451 */ 452 sc->sc_setdefantenna = ath_setdefantenna; 453 sc->sc_rc = ath_rate_attach(sc); 454 if (sc->sc_rc == NULL) { 455 error = EIO; 456 goto bad2; 457 } 458 459 sc->sc_blinking = 0; 460 sc->sc_ledstate = 1; 461 sc->sc_ledon = 0; /* low true */ 462 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 463 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 464 /* 465 * Auto-enable soft led processing for IBM cards and for 466 * 5211 minipci cards. Users can also manually enable/disable 467 * support with a sysctl. 468 */ 469 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 470 if (sc->sc_softled) { 471 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 472 HAL_GPIO_MUX_MAC_NETWORK_LED); 473 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 474 } 475 476 ifp->if_softc = sc; 477 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 478 ifp->if_start = ath_start; 479 ifp->if_stop = ath_stop; 480 ifp->if_watchdog = ath_watchdog; 481 ifp->if_ioctl = ath_ioctl; 482 ifp->if_init = ath_ifinit; 483 IFQ_SET_READY(&ifp->if_snd); 484 485 ic->ic_ifp = ifp; 486 ic->ic_reset = ath_reset; 487 ic->ic_newassoc = ath_newassoc; 488 ic->ic_updateslot = ath_updateslot; 489 ic->ic_wme.wme_update = ath_wme_update; 490 /* XXX not right but it's not used anywhere important */ 491 ic->ic_phytype = IEEE80211_T_OFDM; 492 ic->ic_opmode = IEEE80211_M_STA; 493 ic->ic_caps = 494 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 495 | IEEE80211_C_HOSTAP /* hostap mode */ 496 | IEEE80211_C_MONITOR /* monitor mode */ 497 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 498 | IEEE80211_C_SHSLOT /* short slot time supported */ 499 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 500 | IEEE80211_C_TXFRAG /* handle tx frags */ 501 ; 502 /* 503 * Query the hal to figure out h/w crypto support. 504 */ 505 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 506 ic->ic_caps |= IEEE80211_C_WEP; 507 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 508 ic->ic_caps |= IEEE80211_C_AES; 509 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 510 ic->ic_caps |= IEEE80211_C_AES_CCM; 511 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 512 ic->ic_caps |= IEEE80211_C_CKIP; 513 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 514 ic->ic_caps |= IEEE80211_C_TKIP; 515 /* 516 * Check if h/w does the MIC and/or whether the 517 * separate key cache entries are required to 518 * handle both tx+rx MIC keys. 519 */ 520 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 521 ic->ic_caps |= IEEE80211_C_TKIPMIC; 522 523 /* 524 * If the h/w supports storing tx+rx MIC keys 525 * in one cache slot automatically enable use. 526 */ 527 if (ath_hal_hastkipsplit(ah) || 528 !ath_hal_settkipsplit(ah, AH_FALSE)) 529 sc->sc_splitmic = 1; 530 531 /* 532 * If the h/w can do TKIP MIC together with WME then 533 * we use it; otherwise we force the MIC to be done 534 * in software by the net80211 layer. 535 */ 536 if (ath_hal_haswmetkipmic(ah)) 537 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 538 } 539 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 540 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 541 /* 542 * Mark key cache slots associated with global keys 543 * as in use. If we knew TKIP was not to be used we 544 * could leave the +32, +64, and +32+64 slots free. 545 */ 546 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 547 setbit(sc->sc_keymap, i); 548 setbit(sc->sc_keymap, i+64); 549 if (sc->sc_splitmic) { 550 setbit(sc->sc_keymap, i+32); 551 setbit(sc->sc_keymap, i+32+64); 552 } 553 } 554 /* 555 * TPC support can be done either with a global cap or 556 * per-packet support. The latter is not available on 557 * all parts. We're a bit pedantic here as all parts 558 * support a global cap. 559 */ 560 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 561 ic->ic_caps |= IEEE80211_C_TXPMGT; 562 563 /* 564 * Mark WME capability only if we have sufficient 565 * hardware queues to do proper priority scheduling. 566 */ 567 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 568 ic->ic_caps |= IEEE80211_C_WME; 569 /* 570 * Check for misc other capabilities. 571 */ 572 if (ath_hal_hasbursting(ah)) 573 ic->ic_caps |= IEEE80211_C_BURST; 574 575 /* 576 * Indicate we need the 802.11 header padded to a 577 * 32-bit boundary for 4-address and QoS frames. 578 */ 579 ic->ic_flags |= IEEE80211_F_DATAPAD; 580 581 /* 582 * Query the hal about antenna support. 583 */ 584 sc->sc_defant = ath_hal_getdefantenna(ah); 585 586 /* 587 * Not all chips have the VEOL support we want to 588 * use with IBSS beacons; check here for it. 589 */ 590 sc->sc_hasveol = ath_hal_hasveol(ah); 591 592 /* get mac address from hardware */ 593 ath_hal_getmac(ah, ic->ic_myaddr); 594 595 if_attach(ifp); 596 /* call MI attach routine. */ 597 ieee80211_ifattach(ic); 598 /* override default methods */ 599 ic->ic_node_alloc = ath_node_alloc; 600 sc->sc_node_free = ic->ic_node_free; 601 ic->ic_node_free = ath_node_free; 602 ic->ic_node_getrssi = ath_node_getrssi; 603 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 604 ic->ic_recv_mgmt = ath_recv_mgmt; 605 sc->sc_newstate = ic->ic_newstate; 606 ic->ic_newstate = ath_newstate; 607 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 608 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 609 ic->ic_crypto.cs_key_delete = ath_key_delete; 610 ic->ic_crypto.cs_key_set = ath_key_set; 611 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 612 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 613 /* complete initialization */ 614 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 615 616 ath_bpfattach(sc); 617 618 sc->sc_flags |= ATH_ATTACHED; 619 620 /* 621 * Setup dynamic sysctl's now that country code and 622 * regdomain are available from the hal. 623 */ 624 ath_sysctlattach(sc); 625 626 ieee80211_announce(ic); 627 ath_announce(sc); 628 return 0; 629 bad2: 630 ath_tx_cleanup(sc); 631 ath_desc_free(sc); 632 bad: 633 if (ah) 634 ath_hal_detach(ah); 635 /* XXX don't get under the abstraction like this */ 636 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 637 return error; 638 } 639 640 int 641 ath_detach(struct ath_softc *sc) 642 { 643 struct ifnet *ifp = &sc->sc_if; 644 int s; 645 646 if ((sc->sc_flags & ATH_ATTACHED) == 0) 647 return (0); 648 649 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 650 __func__, ifp->if_flags); 651 652 s = splnet(); 653 ath_stop(ifp, 1); 654 bpf_detach(ifp); 655 /* 656 * NB: the order of these is important: 657 * o call the 802.11 layer before detaching the hal to 658 * insure callbacks into the driver to delete global 659 * key cache entries can be handled 660 * o reclaim the tx queue data structures after calling 661 * the 802.11 layer as we'll get called back to reclaim 662 * node state and potentially want to use them 663 * o to cleanup the tx queues the hal is called, so detach 664 * it last 665 * Other than that, it's straightforward... 666 */ 667 ieee80211_ifdetach(&sc->sc_ic); 668 #ifdef ATH_TX99_DIAG 669 if (sc->sc_tx99 != NULL) 670 sc->sc_tx99->detach(sc->sc_tx99); 671 #endif 672 ath_rate_detach(sc->sc_rc); 673 ath_desc_free(sc); 674 ath_tx_cleanup(sc); 675 sysctl_teardown(&sc->sc_sysctllog); 676 ath_hal_detach(sc->sc_ah); 677 if_detach(ifp); 678 splx(s); 679 680 return 0; 681 } 682 683 void 684 ath_suspend(struct ath_softc *sc) 685 { 686 #if notyet 687 /* 688 * Set the chip in full sleep mode. Note that we are 689 * careful to do this only when bringing the interface 690 * completely to a stop. When the chip is in this state 691 * it must be carefully woken up or references to 692 * registers in the PCI clock domain may freeze the bus 693 * (and system). This varies by chip and is mostly an 694 * issue with newer parts that go to sleep more quickly. 695 */ 696 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 697 #endif 698 } 699 700 bool 701 ath_resume(struct ath_softc *sc) 702 { 703 struct ath_hal *ah = sc->sc_ah; 704 struct ieee80211com *ic = &sc->sc_ic; 705 HAL_STATUS status; 706 int i; 707 708 #if notyet 709 ath_hal_setpower(ah, HAL_PM_AWAKE); 710 #else 711 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 712 #endif 713 714 /* 715 * Reset the key cache since some parts do not 716 * reset the contents on initial power up. 717 */ 718 for (i = 0; i < sc->sc_keymax; i++) 719 ath_hal_keyreset(ah, i); 720 721 ath_hal_resettxqueue(ah, sc->sc_bhalq); 722 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 723 if (ATH_TXQ_SETUP(sc, i)) 724 ath_hal_resettxqueue(ah, i); 725 726 if (sc->sc_softled) { 727 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 728 HAL_GPIO_MUX_MAC_NETWORK_LED); 729 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 730 } 731 return true; 732 } 733 734 /* 735 * Interrupt handler. Most of the actual processing is deferred. 736 */ 737 int 738 ath_intr(void *arg) 739 { 740 struct ath_softc *sc = arg; 741 struct ifnet *ifp = &sc->sc_if; 742 struct ath_hal *ah = sc->sc_ah; 743 HAL_INT status = 0; 744 745 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 746 /* 747 * The hardware is not ready/present, don't touch anything. 748 * Note this can happen early on if the IRQ is shared. 749 */ 750 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 751 return 0; 752 } 753 754 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 755 return 0; 756 757 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 758 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 759 __func__, ifp->if_flags); 760 ath_hal_getisr(ah, &status); /* clear ISR */ 761 ath_hal_intrset(ah, 0); /* disable further intr's */ 762 return 1; /* XXX */ 763 } 764 /* 765 * Figure out the reason(s) for the interrupt. Note 766 * that the hal returns a pseudo-ISR that may include 767 * bits we haven't explicitly enabled so we mask the 768 * value to insure we only process bits we requested. 769 */ 770 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 771 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 772 status &= sc->sc_imask; /* discard unasked for bits */ 773 if (status & HAL_INT_FATAL) { 774 /* 775 * Fatal errors are unrecoverable. Typically 776 * these are caused by DMA errors. Unfortunately 777 * the exact reason is not (presently) returned 778 * by the hal. 779 */ 780 sc->sc_stats.ast_hardware++; 781 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 782 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 783 } else if (status & HAL_INT_RXORN) { 784 sc->sc_stats.ast_rxorn++; 785 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 786 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 787 } else { 788 if (status & HAL_INT_SWBA) { 789 /* 790 * Software beacon alert--time to send a beacon. 791 * Handle beacon transmission directly; deferring 792 * this is too slow to meet timing constraints 793 * under load. 794 */ 795 ath_beacon_proc(sc, 0); 796 } 797 if (status & HAL_INT_RXEOL) { 798 /* 799 * NB: the hardware should re-read the link when 800 * RXE bit is written, but it doesn't work at 801 * least on older hardware revs. 802 */ 803 sc->sc_stats.ast_rxeol++; 804 sc->sc_rxlink = NULL; 805 } 806 if (status & HAL_INT_TXURN) { 807 sc->sc_stats.ast_txurn++; 808 /* bump tx trigger level */ 809 ath_hal_updatetxtriglevel(ah, AH_TRUE); 810 } 811 if (status & HAL_INT_RX) 812 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 813 if (status & HAL_INT_TX) 814 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 815 if (status & HAL_INT_BMISS) { 816 sc->sc_stats.ast_bmiss++; 817 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 818 } 819 if (status & HAL_INT_MIB) { 820 sc->sc_stats.ast_mib++; 821 /* 822 * Disable interrupts until we service the MIB 823 * interrupt; otherwise it will continue to fire. 824 */ 825 ath_hal_intrset(ah, 0); 826 /* 827 * Let the hal handle the event. We assume it will 828 * clear whatever condition caused the interrupt. 829 */ 830 ath_hal_mibevent(ah, &sc->sc_halstats); 831 ath_hal_intrset(ah, sc->sc_imask); 832 } 833 } 834 return 1; 835 } 836 837 /* Swap transmit descriptor. 838 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 839 * function. 840 */ 841 static inline void 842 ath_desc_swap(struct ath_desc *ds) 843 { 844 #ifdef AH_NEED_DESC_SWAP 845 ds->ds_link = htole32(ds->ds_link); 846 ds->ds_data = htole32(ds->ds_data); 847 ds->ds_ctl0 = htole32(ds->ds_ctl0); 848 ds->ds_ctl1 = htole32(ds->ds_ctl1); 849 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 850 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 851 #endif 852 } 853 854 static void 855 ath_fatal_proc(void *arg, int pending) 856 { 857 struct ath_softc *sc = arg; 858 struct ifnet *ifp = &sc->sc_if; 859 860 if_printf(ifp, "hardware error; resetting\n"); 861 ath_reset(ifp); 862 } 863 864 static void 865 ath_rxorn_proc(void *arg, int pending) 866 { 867 struct ath_softc *sc = arg; 868 struct ifnet *ifp = &sc->sc_if; 869 870 if_printf(ifp, "rx FIFO overrun; resetting\n"); 871 ath_reset(ifp); 872 } 873 874 static void 875 ath_bmiss_proc(void *arg, int pending) 876 { 877 struct ath_softc *sc = arg; 878 struct ieee80211com *ic = &sc->sc_ic; 879 880 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 881 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 882 ("unexpect operating mode %u", ic->ic_opmode)); 883 if (ic->ic_state == IEEE80211_S_RUN) { 884 u_int64_t lastrx = sc->sc_lastrx; 885 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 886 887 DPRINTF(sc, ATH_DEBUG_BEACON, 888 "%s: tsf %" PRIu64 " lastrx %" PRId64 889 " (%" PRIu64 ") bmiss %u\n", 890 __func__, tsf, tsf - lastrx, lastrx, 891 ic->ic_bmisstimeout*1024); 892 /* 893 * Workaround phantom bmiss interrupts by sanity-checking 894 * the time of our last rx'd frame. If it is within the 895 * beacon miss interval then ignore the interrupt. If it's 896 * truly a bmiss we'll get another interrupt soon and that'll 897 * be dispatched up for processing. 898 */ 899 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 900 NET_LOCK_GIANT(); 901 ieee80211_beacon_miss(ic); 902 NET_UNLOCK_GIANT(); 903 } else 904 sc->sc_stats.ast_bmiss_phantom++; 905 } 906 } 907 908 static void 909 ath_radar_proc(void *arg, int pending) 910 { 911 #if 0 912 struct ath_softc *sc = arg; 913 struct ifnet *ifp = &sc->sc_if; 914 struct ath_hal *ah = sc->sc_ah; 915 HAL_CHANNEL hchan; 916 917 if (ath_hal_procdfs(ah, &hchan)) { 918 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 919 hchan.channel, hchan.channelFlags, hchan.privFlags); 920 /* 921 * Initiate channel change. 922 */ 923 /* XXX not yet */ 924 } 925 #endif 926 } 927 928 static u_int 929 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 930 { 931 #define N(a) (sizeof(a) / sizeof(a[0])) 932 static const u_int modeflags[] = { 933 0, /* IEEE80211_MODE_AUTO */ 934 CHANNEL_A, /* IEEE80211_MODE_11A */ 935 CHANNEL_B, /* IEEE80211_MODE_11B */ 936 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 937 0, /* IEEE80211_MODE_FH */ 938 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 939 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 940 }; 941 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 942 943 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 944 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 945 return modeflags[mode]; 946 #undef N 947 } 948 949 static int 950 ath_ifinit(struct ifnet *ifp) 951 { 952 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 953 954 return ath_init(sc); 955 } 956 957 static void 958 ath_settkipmic(struct ath_softc *sc) 959 { 960 struct ieee80211com *ic = &sc->sc_ic; 961 struct ath_hal *ah = sc->sc_ah; 962 963 if ((ic->ic_caps & IEEE80211_C_TKIP) && 964 !(ic->ic_caps & IEEE80211_C_WME_TKIPMIC)) { 965 if (ic->ic_flags & IEEE80211_F_WME) { 966 (void)ath_hal_settkipmic(ah, AH_FALSE); 967 ic->ic_caps &= ~IEEE80211_C_TKIPMIC; 968 } else { 969 (void)ath_hal_settkipmic(ah, AH_TRUE); 970 ic->ic_caps |= IEEE80211_C_TKIPMIC; 971 } 972 } 973 } 974 975 static int 976 ath_init(struct ath_softc *sc) 977 { 978 struct ifnet *ifp = &sc->sc_if; 979 struct ieee80211com *ic = &sc->sc_ic; 980 struct ath_hal *ah = sc->sc_ah; 981 HAL_STATUS status; 982 int error = 0, s; 983 984 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 985 __func__, ifp->if_flags); 986 987 if (device_is_active(sc->sc_dev)) { 988 s = splnet(); 989 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 990 !device_is_active(sc->sc_dev)) 991 return 0; 992 else 993 s = splnet(); 994 995 /* 996 * Stop anything previously setup. This is safe 997 * whether this is the first time through or not. 998 */ 999 ath_stop_locked(ifp, 0); 1000 1001 /* 1002 * The basic interface to setting the hardware in a good 1003 * state is ``reset''. On return the hardware is known to 1004 * be powered up and with interrupts disabled. This must 1005 * be followed by initialization of the appropriate bits 1006 * and then setup of the interrupt mask. 1007 */ 1008 ath_settkipmic(sc); 1009 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1010 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1011 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1012 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1013 status); 1014 error = EIO; 1015 goto done; 1016 } 1017 1018 /* 1019 * This is needed only to setup initial state 1020 * but it's best done after a reset. 1021 */ 1022 ath_update_txpow(sc); 1023 /* 1024 * Likewise this is set during reset so update 1025 * state cached in the driver. 1026 */ 1027 ath_restore_diversity(sc); 1028 sc->sc_calinterval = 1; 1029 sc->sc_caltries = 0; 1030 1031 /* 1032 * Setup the hardware after reset: the key cache 1033 * is filled as needed and the receive engine is 1034 * set going. Frame transmit is handled entirely 1035 * in the frame output path; there's nothing to do 1036 * here except setup the interrupt mask. 1037 */ 1038 if ((error = ath_startrecv(sc)) != 0) { 1039 if_printf(ifp, "unable to start recv logic\n"); 1040 goto done; 1041 } 1042 1043 /* 1044 * Enable interrupts. 1045 */ 1046 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1047 | HAL_INT_RXEOL | HAL_INT_RXORN 1048 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1049 /* 1050 * Enable MIB interrupts when there are hardware phy counters. 1051 * Note we only do this (at the moment) for station mode. 1052 */ 1053 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1054 sc->sc_imask |= HAL_INT_MIB; 1055 ath_hal_intrset(ah, sc->sc_imask); 1056 1057 ifp->if_flags |= IFF_RUNNING; 1058 ic->ic_state = IEEE80211_S_INIT; 1059 1060 /* 1061 * The hardware should be ready to go now so it's safe 1062 * to kick the 802.11 state machine as it's likely to 1063 * immediately call back to us to send mgmt frames. 1064 */ 1065 ath_chan_change(sc, ic->ic_curchan); 1066 #ifdef ATH_TX99_DIAG 1067 if (sc->sc_tx99 != NULL) 1068 sc->sc_tx99->start(sc->sc_tx99); 1069 else 1070 #endif 1071 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1072 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1073 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1074 } else 1075 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1076 done: 1077 splx(s); 1078 return error; 1079 } 1080 1081 static void 1082 ath_stop_locked(struct ifnet *ifp, int disable) 1083 { 1084 struct ath_softc *sc = ifp->if_softc; 1085 struct ieee80211com *ic = &sc->sc_ic; 1086 struct ath_hal *ah = sc->sc_ah; 1087 1088 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1089 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1090 1091 /* KASSERT() IPL_NET */ 1092 if (ifp->if_flags & IFF_RUNNING) { 1093 /* 1094 * Shutdown the hardware and driver: 1095 * reset 802.11 state machine 1096 * turn off timers 1097 * disable interrupts 1098 * turn off the radio 1099 * clear transmit machinery 1100 * clear receive machinery 1101 * drain and release tx queues 1102 * reclaim beacon resources 1103 * power down hardware 1104 * 1105 * Note that some of this work is not possible if the 1106 * hardware is gone (invalid). 1107 */ 1108 #ifdef ATH_TX99_DIAG 1109 if (sc->sc_tx99 != NULL) 1110 sc->sc_tx99->stop(sc->sc_tx99); 1111 #endif 1112 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1113 ifp->if_flags &= ~IFF_RUNNING; 1114 ifp->if_timer = 0; 1115 if (device_is_enabled(sc->sc_dev)) { 1116 if (sc->sc_softled) { 1117 callout_stop(&sc->sc_ledtimer); 1118 ath_hal_gpioset(ah, sc->sc_ledpin, 1119 !sc->sc_ledon); 1120 sc->sc_blinking = 0; 1121 } 1122 ath_hal_intrset(ah, 0); 1123 } 1124 ath_draintxq(sc); 1125 if (device_is_enabled(sc->sc_dev)) { 1126 ath_stoprecv(sc); 1127 ath_hal_phydisable(ah); 1128 } else 1129 sc->sc_rxlink = NULL; 1130 IF_PURGE(&ifp->if_snd); 1131 ath_beacon_free(sc); 1132 } 1133 if (disable) 1134 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 1135 } 1136 1137 static void 1138 ath_stop(struct ifnet *ifp, int disable) 1139 { 1140 int s; 1141 1142 s = splnet(); 1143 ath_stop_locked(ifp, disable); 1144 splx(s); 1145 } 1146 1147 static void 1148 ath_restore_diversity(struct ath_softc *sc) 1149 { 1150 struct ifnet *ifp = &sc->sc_if; 1151 struct ath_hal *ah = sc->sc_ah; 1152 1153 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1154 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1155 if_printf(ifp, "could not restore diversity setting %d\n", 1156 sc->sc_diversity); 1157 sc->sc_diversity = ath_hal_getdiversity(ah); 1158 } 1159 } 1160 1161 /* 1162 * Reset the hardware w/o losing operational state. This is 1163 * basically a more efficient way of doing ath_stop, ath_init, 1164 * followed by state transitions to the current 802.11 1165 * operational state. Used to recover from various errors and 1166 * to reset or reload hardware state. 1167 */ 1168 int 1169 ath_reset(struct ifnet *ifp) 1170 { 1171 struct ath_softc *sc = ifp->if_softc; 1172 struct ieee80211com *ic = &sc->sc_ic; 1173 struct ath_hal *ah = sc->sc_ah; 1174 struct ieee80211_channel *c; 1175 HAL_STATUS status; 1176 1177 /* 1178 * Convert to a HAL channel description with the flags 1179 * constrained to reflect the current operating mode. 1180 */ 1181 c = ic->ic_curchan; 1182 sc->sc_curchan.channel = c->ic_freq; 1183 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1184 1185 ath_hal_intrset(ah, 0); /* disable interrupts */ 1186 ath_draintxq(sc); /* stop xmit side */ 1187 ath_stoprecv(sc); /* stop recv side */ 1188 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1189 /* NB: indicate channel change so we do a full reset */ 1190 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1191 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1192 __func__, status); 1193 ath_update_txpow(sc); /* update tx power state */ 1194 ath_restore_diversity(sc); 1195 sc->sc_calinterval = 1; 1196 sc->sc_caltries = 0; 1197 if (ath_startrecv(sc) != 0) /* restart recv */ 1198 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1199 /* 1200 * We may be doing a reset in response to an ioctl 1201 * that changes the channel so update any state that 1202 * might change as a result. 1203 */ 1204 ath_chan_change(sc, c); 1205 if (ic->ic_state == IEEE80211_S_RUN) 1206 ath_beacon_config(sc); /* restart beacons */ 1207 ath_hal_intrset(ah, sc->sc_imask); 1208 1209 ath_start(ifp); /* restart xmit */ 1210 return 0; 1211 } 1212 1213 /* 1214 * Cleanup driver resources when we run out of buffers 1215 * while processing fragments; return the tx buffers 1216 * allocated and drop node references. 1217 */ 1218 static void 1219 ath_txfrag_cleanup(struct ath_softc *sc, 1220 ath_bufhead *frags, struct ieee80211_node *ni) 1221 { 1222 struct ath_buf *bf; 1223 1224 ATH_TXBUF_LOCK_ASSERT(sc); 1225 1226 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1227 STAILQ_REMOVE_HEAD(frags, bf_list); 1228 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1229 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1230 ieee80211_node_decref(ni); 1231 } 1232 } 1233 1234 /* 1235 * Setup xmit of a fragmented frame. Allocate a buffer 1236 * for each frag and bump the node reference count to 1237 * reflect the held reference to be setup by ath_tx_start. 1238 */ 1239 static int 1240 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1241 struct mbuf *m0, struct ieee80211_node *ni) 1242 { 1243 struct mbuf *m; 1244 struct ath_buf *bf; 1245 1246 ATH_TXBUF_LOCK(sc); 1247 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1248 bf = STAILQ_FIRST(&sc->sc_txbuf); 1249 if (bf == NULL) { /* out of buffers, cleanup */ 1250 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1251 __func__); 1252 sc->sc_if.if_flags |= IFF_OACTIVE; 1253 ath_txfrag_cleanup(sc, frags, ni); 1254 break; 1255 } 1256 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1257 ieee80211_node_incref(ni); 1258 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1259 } 1260 ATH_TXBUF_UNLOCK(sc); 1261 1262 return !STAILQ_EMPTY(frags); 1263 } 1264 1265 static void 1266 ath_start(struct ifnet *ifp) 1267 { 1268 struct ath_softc *sc = ifp->if_softc; 1269 struct ath_hal *ah = sc->sc_ah; 1270 struct ieee80211com *ic = &sc->sc_ic; 1271 struct ieee80211_node *ni; 1272 struct ath_buf *bf; 1273 struct mbuf *m, *next; 1274 struct ieee80211_frame *wh; 1275 struct ether_header *eh; 1276 ath_bufhead frags; 1277 1278 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1279 !device_is_active(sc->sc_dev)) 1280 return; 1281 for (;;) { 1282 /* 1283 * Grab a TX buffer and associated resources. 1284 */ 1285 ATH_TXBUF_LOCK(sc); 1286 bf = STAILQ_FIRST(&sc->sc_txbuf); 1287 if (bf != NULL) 1288 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1289 ATH_TXBUF_UNLOCK(sc); 1290 if (bf == NULL) { 1291 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1292 __func__); 1293 sc->sc_stats.ast_tx_qstop++; 1294 ifp->if_flags |= IFF_OACTIVE; 1295 break; 1296 } 1297 /* 1298 * Poll the management queue for frames; they 1299 * have priority over normal data frames. 1300 */ 1301 IF_DEQUEUE(&ic->ic_mgtq, m); 1302 if (m == NULL) { 1303 /* 1304 * No data frames go out unless we're associated. 1305 */ 1306 if (ic->ic_state != IEEE80211_S_RUN) { 1307 DPRINTF(sc, ATH_DEBUG_XMIT, 1308 "%s: discard data packet, state %s\n", 1309 __func__, 1310 ieee80211_state_name[ic->ic_state]); 1311 sc->sc_stats.ast_tx_discard++; 1312 ATH_TXBUF_LOCK(sc); 1313 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1314 ATH_TXBUF_UNLOCK(sc); 1315 break; 1316 } 1317 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1318 if (m == NULL) { 1319 ATH_TXBUF_LOCK(sc); 1320 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1321 ATH_TXBUF_UNLOCK(sc); 1322 break; 1323 } 1324 STAILQ_INIT(&frags); 1325 /* 1326 * Find the node for the destination so we can do 1327 * things like power save and fast frames aggregation. 1328 */ 1329 if (m->m_len < sizeof(struct ether_header) && 1330 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1331 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1332 ni = NULL; 1333 goto bad; 1334 } 1335 eh = mtod(m, struct ether_header *); 1336 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1337 if (ni == NULL) { 1338 /* NB: ieee80211_find_txnode does stat+msg */ 1339 m_freem(m); 1340 goto bad; 1341 } 1342 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1343 (m->m_flags & M_PWR_SAV) == 0) { 1344 /* 1345 * Station in power save mode; pass the frame 1346 * to the 802.11 layer and continue. We'll get 1347 * the frame back when the time is right. 1348 */ 1349 ieee80211_pwrsave(ic, ni, m); 1350 goto reclaim; 1351 } 1352 /* calculate priority so we can find the tx queue */ 1353 if (ieee80211_classify(ic, m, ni)) { 1354 DPRINTF(sc, ATH_DEBUG_XMIT, 1355 "%s: discard, classification failure\n", 1356 __func__); 1357 m_freem(m); 1358 goto bad; 1359 } 1360 ifp->if_opackets++; 1361 1362 bpf_mtap(ifp, m); 1363 /* 1364 * Encapsulate the packet in prep for transmission. 1365 */ 1366 m = ieee80211_encap(ic, m, ni); 1367 if (m == NULL) { 1368 DPRINTF(sc, ATH_DEBUG_XMIT, 1369 "%s: encapsulation failure\n", 1370 __func__); 1371 sc->sc_stats.ast_tx_encap++; 1372 goto bad; 1373 } 1374 /* 1375 * Check for fragmentation. If this has frame 1376 * has been broken up verify we have enough 1377 * buffers to send all the fragments so all 1378 * go out or none... 1379 */ 1380 if ((m->m_flags & M_FRAG) && 1381 !ath_txfrag_setup(sc, &frags, m, ni)) { 1382 DPRINTF(sc, ATH_DEBUG_ANY, 1383 "%s: out of txfrag buffers\n", __func__); 1384 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1385 ath_freetx(m); 1386 goto bad; 1387 } 1388 } else { 1389 /* 1390 * Hack! The referenced node pointer is in the 1391 * rcvif field of the packet header. This is 1392 * placed there by ieee80211_mgmt_output because 1393 * we need to hold the reference with the frame 1394 * and there's no other way (other than packet 1395 * tags which we consider too expensive to use) 1396 * to pass it along. 1397 */ 1398 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1399 m->m_pkthdr.rcvif = NULL; 1400 1401 wh = mtod(m, struct ieee80211_frame *); 1402 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1403 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1404 /* fill time stamp */ 1405 u_int64_t tsf; 1406 u_int32_t *tstamp; 1407 1408 tsf = ath_hal_gettsf64(ah); 1409 /* XXX: adjust 100us delay to xmit */ 1410 tsf += 100; 1411 tstamp = (u_int32_t *)&wh[1]; 1412 tstamp[0] = htole32(tsf & 0xffffffff); 1413 tstamp[1] = htole32(tsf >> 32); 1414 } 1415 sc->sc_stats.ast_tx_mgmt++; 1416 } 1417 1418 nextfrag: 1419 next = m->m_nextpkt; 1420 if (ath_tx_start(sc, ni, bf, m)) { 1421 bad: 1422 ifp->if_oerrors++; 1423 reclaim: 1424 ATH_TXBUF_LOCK(sc); 1425 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1426 ath_txfrag_cleanup(sc, &frags, ni); 1427 ATH_TXBUF_UNLOCK(sc); 1428 if (ni != NULL) 1429 ieee80211_free_node(ni); 1430 continue; 1431 } 1432 if (next != NULL) { 1433 m = next; 1434 bf = STAILQ_FIRST(&frags); 1435 KASSERT(bf != NULL, ("no buf for txfrag")); 1436 STAILQ_REMOVE_HEAD(&frags, bf_list); 1437 goto nextfrag; 1438 } 1439 1440 ifp->if_timer = 1; 1441 } 1442 } 1443 1444 static int 1445 ath_media_change(struct ifnet *ifp) 1446 { 1447 #define IS_UP(ifp) \ 1448 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1449 int error; 1450 1451 error = ieee80211_media_change(ifp); 1452 if (error == ENETRESET) { 1453 if (IS_UP(ifp)) 1454 ath_init(ifp->if_softc); /* XXX lose error */ 1455 error = 0; 1456 } 1457 return error; 1458 #undef IS_UP 1459 } 1460 1461 #ifdef AR_DEBUG 1462 static void 1463 ath_keyprint(const char *tag, u_int ix, 1464 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1465 { 1466 static const char *ciphers[] = { 1467 "WEP", 1468 "AES-OCB", 1469 "AES-CCM", 1470 "CKIP", 1471 "TKIP", 1472 "CLR", 1473 }; 1474 int i, n; 1475 1476 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1477 for (i = 0, n = hk->kv_len; i < n; i++) 1478 printf("%02x", hk->kv_val[i]); 1479 printf(" mac %s", ether_sprintf(mac)); 1480 if (hk->kv_type == HAL_CIPHER_TKIP) { 1481 printf(" mic "); 1482 for (i = 0; i < sizeof(hk->kv_mic); i++) 1483 printf("%02x", hk->kv_mic[i]); 1484 } 1485 printf("\n"); 1486 } 1487 #endif 1488 1489 /* 1490 * Set a TKIP key into the hardware. This handles the 1491 * potential distribution of key state to multiple key 1492 * cache slots for TKIP. 1493 */ 1494 static int 1495 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1496 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1497 { 1498 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1499 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1500 struct ath_hal *ah = sc->sc_ah; 1501 1502 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1503 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1504 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1505 if (sc->sc_splitmic) { 1506 /* 1507 * TX key goes at first index, RX key at the rx index. 1508 * The hal handles the MIC keys at index+64. 1509 */ 1510 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1511 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1512 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1513 zerobssid)) 1514 return 0; 1515 1516 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1517 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1518 /* XXX delete tx key on failure? */ 1519 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1520 hk, mac); 1521 } else { 1522 /* 1523 * Room for both TX+RX MIC keys in one key cache 1524 * slot, just set key at the first index; the HAL 1525 * will handle the reset. 1526 */ 1527 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1528 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1529 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1530 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1531 } 1532 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1533 if (sc->sc_splitmic) { 1534 /* 1535 * NB: must pass MIC key in expected location when 1536 * the keycache only holds one MIC key per entry. 1537 */ 1538 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1539 } else 1540 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1541 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1542 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1543 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1544 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1545 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1546 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1547 } 1548 return 0; 1549 #undef IEEE80211_KEY_XR 1550 } 1551 1552 /* 1553 * Set a net80211 key into the hardware. This handles the 1554 * potential distribution of key state to multiple key 1555 * cache slots for TKIP with hardware MIC support. 1556 */ 1557 static int 1558 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1559 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1560 struct ieee80211_node *bss) 1561 { 1562 #define N(a) (sizeof(a)/sizeof(a[0])) 1563 static const u_int8_t ciphermap[] = { 1564 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1565 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1566 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1567 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1568 (u_int8_t) -1, /* 4 is not allocated */ 1569 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1570 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1571 }; 1572 struct ath_hal *ah = sc->sc_ah; 1573 const struct ieee80211_cipher *cip = k->wk_cipher; 1574 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1575 const u_int8_t *mac; 1576 HAL_KEYVAL hk; 1577 1578 memset(&hk, 0, sizeof(hk)); 1579 /* 1580 * Software crypto uses a "clear key" so non-crypto 1581 * state kept in the key cache are maintained and 1582 * so that rx frames have an entry to match. 1583 */ 1584 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1585 KASSERT(cip->ic_cipher < N(ciphermap), 1586 ("invalid cipher type %u", cip->ic_cipher)); 1587 hk.kv_type = ciphermap[cip->ic_cipher]; 1588 hk.kv_len = k->wk_keylen; 1589 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1590 } else 1591 hk.kv_type = HAL_CIPHER_CLR; 1592 1593 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1594 /* 1595 * Group keys on hardware that supports multicast frame 1596 * key search use a mac that is the sender's address with 1597 * the high bit set instead of the app-specified address. 1598 */ 1599 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1600 gmac[0] |= 0x80; 1601 mac = gmac; 1602 } else 1603 mac = mac0; 1604 1605 if ((hk.kv_type == HAL_CIPHER_TKIP && 1606 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0)) { 1607 return ath_keyset_tkip(sc, k, &hk, mac); 1608 } else { 1609 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1610 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1611 } 1612 #undef N 1613 } 1614 1615 /* 1616 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1617 * each key, one for decrypt/encrypt and the other for the MIC. 1618 */ 1619 static u_int16_t 1620 key_alloc_2pair(struct ath_softc *sc, 1621 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1622 { 1623 #define N(a) (sizeof(a)/sizeof(a[0])) 1624 u_int i, keyix; 1625 1626 KASSERT(sc->sc_splitmic, ("key cache !split")); 1627 /* XXX could optimize */ 1628 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1629 u_int8_t b = sc->sc_keymap[i]; 1630 if (b != 0xff) { 1631 /* 1632 * One or more slots in this byte are free. 1633 */ 1634 keyix = i*NBBY; 1635 while (b & 1) { 1636 again: 1637 keyix++; 1638 b >>= 1; 1639 } 1640 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1641 if (isset(sc->sc_keymap, keyix+32) || 1642 isset(sc->sc_keymap, keyix+64) || 1643 isset(sc->sc_keymap, keyix+32+64)) { 1644 /* full pair unavailable */ 1645 /* XXX statistic */ 1646 if (keyix == (i+1)*NBBY) { 1647 /* no slots were appropriate, advance */ 1648 continue; 1649 } 1650 goto again; 1651 } 1652 setbit(sc->sc_keymap, keyix); 1653 setbit(sc->sc_keymap, keyix+64); 1654 setbit(sc->sc_keymap, keyix+32); 1655 setbit(sc->sc_keymap, keyix+32+64); 1656 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1657 "%s: key pair %u,%u %u,%u\n", 1658 __func__, keyix, keyix+64, 1659 keyix+32, keyix+32+64); 1660 *txkeyix = keyix; 1661 *rxkeyix = keyix+32; 1662 return keyix; 1663 } 1664 } 1665 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1666 return IEEE80211_KEYIX_NONE; 1667 #undef N 1668 } 1669 1670 /* 1671 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1672 * each key, one for decrypt/encrypt and the other for the MIC. 1673 */ 1674 static int 1675 key_alloc_pair(struct ath_softc *sc, ieee80211_keyix *txkeyix, 1676 ieee80211_keyix *rxkeyix) 1677 { 1678 #define N(a) (sizeof(a)/sizeof(a[0])) 1679 u_int i, keyix; 1680 1681 KASSERT(!sc->sc_splitmic, ("key cache split")); 1682 /* XXX could optimize */ 1683 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1684 uint8_t b = sc->sc_keymap[i]; 1685 if (b != 0xff) { 1686 /* 1687 * One or more slots in this byte are free. 1688 */ 1689 keyix = i*NBBY; 1690 while (b & 1) { 1691 again: 1692 keyix++; 1693 b >>= 1; 1694 } 1695 if (isset(sc->sc_keymap, keyix+64)) { 1696 /* full pair unavailable */ 1697 /* XXX statistic */ 1698 if (keyix == (i+1)*NBBY) { 1699 /* no slots were appropriate, advance */ 1700 continue; 1701 } 1702 goto again; 1703 } 1704 setbit(sc->sc_keymap, keyix); 1705 setbit(sc->sc_keymap, keyix+64); 1706 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1707 "%s: key pair %u,%u\n", 1708 __func__, keyix, keyix+64); 1709 *txkeyix = *rxkeyix = keyix; 1710 return 1; 1711 } 1712 } 1713 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1714 return 0; 1715 #undef N 1716 } 1717 1718 /* 1719 * Allocate a single key cache slot. 1720 */ 1721 static int 1722 key_alloc_single(struct ath_softc *sc, 1723 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1724 { 1725 #define N(a) (sizeof(a)/sizeof(a[0])) 1726 u_int i, keyix; 1727 1728 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1729 for (i = 0; i < N(sc->sc_keymap); i++) { 1730 u_int8_t b = sc->sc_keymap[i]; 1731 if (b != 0xff) { 1732 /* 1733 * One or more slots are free. 1734 */ 1735 keyix = i*NBBY; 1736 while (b & 1) 1737 keyix++, b >>= 1; 1738 setbit(sc->sc_keymap, keyix); 1739 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1740 __func__, keyix); 1741 *txkeyix = *rxkeyix = keyix; 1742 return 1; 1743 } 1744 } 1745 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1746 return 0; 1747 #undef N 1748 } 1749 1750 /* 1751 * Allocate one or more key cache slots for a uniacst key. The 1752 * key itself is needed only to identify the cipher. For hardware 1753 * TKIP with split cipher+MIC keys we allocate two key cache slot 1754 * pairs so that we can setup separate TX and RX MIC keys. Note 1755 * that the MIC key for a TKIP key at slot i is assumed by the 1756 * hardware to be at slot i+64. This limits TKIP keys to the first 1757 * 64 entries. 1758 */ 1759 static int 1760 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1761 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1762 { 1763 struct ath_softc *sc = ic->ic_ifp->if_softc; 1764 1765 /* 1766 * Group key allocation must be handled specially for 1767 * parts that do not support multicast key cache search 1768 * functionality. For those parts the key id must match 1769 * the h/w key index so lookups find the right key. On 1770 * parts w/ the key search facility we install the sender's 1771 * mac address (with the high bit set) and let the hardware 1772 * find the key w/o using the key id. This is preferred as 1773 * it permits us to support multiple users for adhoc and/or 1774 * multi-station operation. 1775 */ 1776 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1777 if (!(&ic->ic_nw_keys[0] <= k && 1778 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1779 /* should not happen */ 1780 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1781 "%s: bogus group key\n", __func__); 1782 return 0; 1783 } 1784 /* 1785 * XXX we pre-allocate the global keys so 1786 * have no way to check if they've already been allocated. 1787 */ 1788 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1789 return 1; 1790 } 1791 1792 /* 1793 * We allocate two pair for TKIP when using the h/w to do 1794 * the MIC. For everything else, including software crypto, 1795 * we allocate a single entry. Note that s/w crypto requires 1796 * a pass-through slot on the 5211 and 5212. The 5210 does 1797 * not support pass-through cache entries and we map all 1798 * those requests to slot 0. 1799 */ 1800 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1801 return key_alloc_single(sc, keyix, rxkeyix); 1802 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1803 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1804 if (sc->sc_splitmic) 1805 return key_alloc_2pair(sc, keyix, rxkeyix); 1806 else 1807 return key_alloc_pair(sc, keyix, rxkeyix); 1808 } else { 1809 return key_alloc_single(sc, keyix, rxkeyix); 1810 } 1811 } 1812 1813 /* 1814 * Delete an entry in the key cache allocated by ath_key_alloc. 1815 */ 1816 static int 1817 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1818 { 1819 struct ath_softc *sc = ic->ic_ifp->if_softc; 1820 struct ath_hal *ah = sc->sc_ah; 1821 const struct ieee80211_cipher *cip = k->wk_cipher; 1822 u_int keyix = k->wk_keyix; 1823 1824 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1825 1826 if (!device_has_power(sc->sc_dev)) { 1827 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1828 k->wk_keyix); 1829 } 1830 1831 ath_hal_keyreset(ah, keyix); 1832 /* 1833 * Handle split tx/rx keying required for TKIP with h/w MIC. 1834 */ 1835 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1836 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1837 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1838 if (keyix >= IEEE80211_WEP_NKID) { 1839 /* 1840 * Don't touch keymap entries for global keys so 1841 * they are never considered for dynamic allocation. 1842 */ 1843 clrbit(sc->sc_keymap, keyix); 1844 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1845 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1846 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1847 if (sc->sc_splitmic) { 1848 /* +32 for RX key, +32+64 for RX key MIC */ 1849 clrbit(sc->sc_keymap, keyix+32); 1850 clrbit(sc->sc_keymap, keyix+32+64); 1851 } 1852 } 1853 } 1854 return 1; 1855 } 1856 1857 /* 1858 * Set the key cache contents for the specified key. Key cache 1859 * slot(s) must already have been allocated by ath_key_alloc. 1860 */ 1861 static int 1862 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1863 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1864 { 1865 struct ath_softc *sc = ic->ic_ifp->if_softc; 1866 1867 if (!device_has_power(sc->sc_dev)) { 1868 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1869 k->wk_keyix); 1870 } 1871 return ath_keyset(sc, k, mac, ic->ic_bss); 1872 } 1873 1874 /* 1875 * Block/unblock tx+rx processing while a key change is done. 1876 * We assume the caller serializes key management operations 1877 * so we only need to worry about synchronization with other 1878 * uses that originate in the driver. 1879 */ 1880 static void 1881 ath_key_update_begin(struct ieee80211com *ic) 1882 { 1883 struct ifnet *ifp = ic->ic_ifp; 1884 struct ath_softc *sc = ifp->if_softc; 1885 1886 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1887 #if 0 1888 tasklet_disable(&sc->sc_rxtq); 1889 #endif 1890 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1891 } 1892 1893 static void 1894 ath_key_update_end(struct ieee80211com *ic) 1895 { 1896 struct ifnet *ifp = ic->ic_ifp; 1897 struct ath_softc *sc = ifp->if_softc; 1898 1899 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1900 IF_UNLOCK(&ifp->if_snd); 1901 #if 0 1902 tasklet_enable(&sc->sc_rxtq); 1903 #endif 1904 } 1905 1906 /* 1907 * Calculate the receive filter according to the 1908 * operating mode and state: 1909 * 1910 * o always accept unicast, broadcast, and multicast traffic 1911 * o maintain current state of phy error reception (the hal 1912 * may enable phy error frames for noise immunity work) 1913 * o probe request frames are accepted only when operating in 1914 * hostap, adhoc, or monitor modes 1915 * o enable promiscuous mode according to the interface state 1916 * o accept beacons: 1917 * - when operating in adhoc mode so the 802.11 layer creates 1918 * node table entries for peers, 1919 * - when operating in station mode for collecting rssi data when 1920 * the station is otherwise quiet, or 1921 * - when scanning 1922 */ 1923 static u_int32_t 1924 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1925 { 1926 struct ieee80211com *ic = &sc->sc_ic; 1927 struct ath_hal *ah = sc->sc_ah; 1928 struct ifnet *ifp = &sc->sc_if; 1929 u_int32_t rfilt; 1930 1931 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1932 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1933 if (ic->ic_opmode != IEEE80211_M_STA) 1934 rfilt |= HAL_RX_FILTER_PROBEREQ; 1935 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1936 (ifp->if_flags & IFF_PROMISC)) 1937 rfilt |= HAL_RX_FILTER_PROM; 1938 if (ifp->if_flags & IFF_PROMISC) 1939 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1940 if (ic->ic_opmode == IEEE80211_M_STA || 1941 ic->ic_opmode == IEEE80211_M_IBSS || 1942 state == IEEE80211_S_SCAN) 1943 rfilt |= HAL_RX_FILTER_BEACON; 1944 return rfilt; 1945 } 1946 1947 static void 1948 ath_mode_init(struct ath_softc *sc) 1949 { 1950 struct ifnet *ifp = &sc->sc_if; 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct ath_hal *ah = sc->sc_ah; 1953 struct ether_multi *enm; 1954 struct ether_multistep estep; 1955 u_int32_t rfilt, mfilt[2], val; 1956 int i; 1957 uint8_t pos; 1958 1959 /* configure rx filter */ 1960 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1961 ath_hal_setrxfilter(ah, rfilt); 1962 1963 /* configure operational mode */ 1964 ath_hal_setopmode(ah); 1965 1966 /* Write keys to hardware; it may have been powered down. */ 1967 ath_key_update_begin(ic); 1968 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1969 ath_key_set(ic, 1970 &ic->ic_crypto.cs_nw_keys[i], 1971 ic->ic_myaddr); 1972 } 1973 ath_key_update_end(ic); 1974 1975 /* 1976 * Handle any link-level address change. Note that we only 1977 * need to force ic_myaddr; any other addresses are handled 1978 * as a byproduct of the ifnet code marking the interface 1979 * down then up. 1980 * 1981 * XXX should get from lladdr instead of arpcom but that's more work 1982 */ 1983 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1984 ath_hal_setmac(ah, ic->ic_myaddr); 1985 1986 /* calculate and install multicast filter */ 1987 ifp->if_flags &= ~IFF_ALLMULTI; 1988 mfilt[0] = mfilt[1] = 0; 1989 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1990 while (enm != NULL) { 1991 void *dl; 1992 /* XXX Punt on ranges. */ 1993 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1994 mfilt[0] = mfilt[1] = 0xffffffff; 1995 ifp->if_flags |= IFF_ALLMULTI; 1996 break; 1997 } 1998 dl = enm->enm_addrlo; 1999 val = LE_READ_4((char *)dl + 0); 2000 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2001 val = LE_READ_4((char *)dl + 3); 2002 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2003 pos &= 0x3f; 2004 mfilt[pos / 32] |= (1 << (pos % 32)); 2005 2006 ETHER_NEXT_MULTI(estep, enm); 2007 } 2008 2009 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 2010 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 2011 __func__, rfilt, mfilt[0], mfilt[1]); 2012 } 2013 2014 /* 2015 * Set the slot time based on the current setting. 2016 */ 2017 static void 2018 ath_setslottime(struct ath_softc *sc) 2019 { 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 struct ath_hal *ah = sc->sc_ah; 2022 2023 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2024 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2025 else 2026 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2027 sc->sc_updateslot = OK; 2028 } 2029 2030 /* 2031 * Callback from the 802.11 layer to update the 2032 * slot time based on the current setting. 2033 */ 2034 static void 2035 ath_updateslot(struct ifnet *ifp) 2036 { 2037 struct ath_softc *sc = ifp->if_softc; 2038 struct ieee80211com *ic = &sc->sc_ic; 2039 2040 /* 2041 * When not coordinating the BSS, change the hardware 2042 * immediately. For other operation we defer the change 2043 * until beacon updates have propagated to the stations. 2044 */ 2045 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2046 sc->sc_updateslot = UPDATE; 2047 else 2048 ath_setslottime(sc); 2049 } 2050 2051 /* 2052 * Setup a h/w transmit queue for beacons. 2053 */ 2054 static int 2055 ath_beaconq_setup(struct ath_hal *ah) 2056 { 2057 HAL_TXQ_INFO qi; 2058 2059 memset(&qi, 0, sizeof(qi)); 2060 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2061 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2062 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2063 /* NB: for dynamic turbo, don't enable any other interrupts */ 2064 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2065 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2066 } 2067 2068 /* 2069 * Setup the transmit queue parameters for the beacon queue. 2070 */ 2071 static int 2072 ath_beaconq_config(struct ath_softc *sc) 2073 { 2074 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2075 struct ieee80211com *ic = &sc->sc_ic; 2076 struct ath_hal *ah = sc->sc_ah; 2077 HAL_TXQ_INFO qi; 2078 2079 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2080 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2081 /* 2082 * Always burst out beacon and CAB traffic. 2083 */ 2084 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2085 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2086 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2087 } else { 2088 struct wmeParams *wmep = 2089 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2090 /* 2091 * Adhoc mode; important thing is to use 2x cwmin. 2092 */ 2093 qi.tqi_aifs = wmep->wmep_aifsn; 2094 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2095 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2096 } 2097 2098 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2099 device_printf(sc->sc_dev, "unable to update parameters for " 2100 "beacon hardware queue!\n"); 2101 return 0; 2102 } else { 2103 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2104 return 1; 2105 } 2106 #undef ATH_EXPONENT_TO_VALUE 2107 } 2108 2109 /* 2110 * Allocate and setup an initial beacon frame. 2111 */ 2112 static int 2113 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2114 { 2115 struct ieee80211com *ic = ni->ni_ic; 2116 struct ath_buf *bf; 2117 struct mbuf *m; 2118 int error; 2119 2120 bf = STAILQ_FIRST(&sc->sc_bbuf); 2121 if (bf == NULL) { 2122 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2123 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2124 return ENOMEM; /* XXX */ 2125 } 2126 /* 2127 * NB: the beacon data buffer must be 32-bit aligned; 2128 * we assume the mbuf routines will return us something 2129 * with this alignment (perhaps should assert). 2130 */ 2131 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2132 if (m == NULL) { 2133 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2134 __func__); 2135 sc->sc_stats.ast_be_nombuf++; 2136 return ENOMEM; 2137 } 2138 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2139 BUS_DMA_NOWAIT); 2140 if (error == 0) { 2141 bf->bf_m = m; 2142 bf->bf_node = ieee80211_ref_node(ni); 2143 } else { 2144 m_freem(m); 2145 } 2146 return error; 2147 } 2148 2149 /* 2150 * Setup the beacon frame for transmit. 2151 */ 2152 static void 2153 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2154 { 2155 #define USE_SHPREAMBLE(_ic) \ 2156 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2157 == IEEE80211_F_SHPREAMBLE) 2158 struct ieee80211_node *ni = bf->bf_node; 2159 struct ieee80211com *ic = ni->ni_ic; 2160 struct mbuf *m = bf->bf_m; 2161 struct ath_hal *ah = sc->sc_ah; 2162 struct ath_desc *ds; 2163 int flags, antenna; 2164 const HAL_RATE_TABLE *rt; 2165 u_int8_t rix, rate; 2166 2167 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2168 __func__, m, m->m_len); 2169 2170 /* setup descriptors */ 2171 ds = bf->bf_desc; 2172 2173 flags = HAL_TXDESC_NOACK; 2174 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2175 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2176 flags |= HAL_TXDESC_VEOL; 2177 /* 2178 * Let hardware handle antenna switching unless 2179 * the user has selected a transmit antenna 2180 * (sc_txantenna is not 0). 2181 */ 2182 antenna = sc->sc_txantenna; 2183 } else { 2184 ds->ds_link = 0; 2185 /* 2186 * Switch antenna every 4 beacons, unless the user 2187 * has selected a transmit antenna (sc_txantenna 2188 * is not 0). 2189 * 2190 * XXX assumes two antenna 2191 */ 2192 if (sc->sc_txantenna == 0) 2193 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2194 else 2195 antenna = sc->sc_txantenna; 2196 } 2197 2198 KASSERT(bf->bf_nseg == 1, 2199 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2200 ds->ds_data = bf->bf_segs[0].ds_addr; 2201 /* 2202 * Calculate rate code. 2203 * XXX everything at min xmit rate 2204 */ 2205 rix = sc->sc_minrateix; 2206 rt = sc->sc_currates; 2207 rate = rt->info[rix].rateCode; 2208 if (USE_SHPREAMBLE(ic)) 2209 rate |= rt->info[rix].shortPreamble; 2210 ath_hal_setuptxdesc(ah, ds 2211 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2212 , sizeof(struct ieee80211_frame)/* header length */ 2213 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2214 , ni->ni_txpower /* txpower XXX */ 2215 , rate, 1 /* series 0 rate/tries */ 2216 , HAL_TXKEYIX_INVALID /* no encryption */ 2217 , antenna /* antenna mode */ 2218 , flags /* no ack, veol for beacons */ 2219 , 0 /* rts/cts rate */ 2220 , 0 /* rts/cts duration */ 2221 ); 2222 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2223 ath_hal_filltxdesc(ah, ds 2224 , roundup(m->m_len, 4) /* buffer length */ 2225 , AH_TRUE /* first segment */ 2226 , AH_TRUE /* last segment */ 2227 , ds /* first descriptor */ 2228 ); 2229 2230 /* NB: The desc swap function becomes void, if descriptor swapping 2231 * is not enabled 2232 */ 2233 ath_desc_swap(ds); 2234 2235 #undef USE_SHPREAMBLE 2236 } 2237 2238 /* 2239 * Transmit a beacon frame at SWBA. Dynamic updates to the 2240 * frame contents are done as needed and the slot time is 2241 * also adjusted based on current state. 2242 */ 2243 static void 2244 ath_beacon_proc(void *arg, int pending) 2245 { 2246 struct ath_softc *sc = arg; 2247 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2248 struct ieee80211_node *ni = bf->bf_node; 2249 struct ieee80211com *ic = ni->ni_ic; 2250 struct ath_hal *ah = sc->sc_ah; 2251 struct mbuf *m; 2252 int ncabq, error, otherant; 2253 2254 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2255 __func__, pending); 2256 2257 if (ic->ic_opmode == IEEE80211_M_STA || 2258 ic->ic_opmode == IEEE80211_M_MONITOR || 2259 bf == NULL || bf->bf_m == NULL) { 2260 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2261 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2262 return; 2263 } 2264 /* 2265 * Check if the previous beacon has gone out. If 2266 * not don't try to post another, skip this period 2267 * and wait for the next. Missed beacons indicate 2268 * a problem and should not occur. If we miss too 2269 * many consecutive beacons reset the device. 2270 */ 2271 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2272 sc->sc_bmisscount++; 2273 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2274 "%s: missed %u consecutive beacons\n", 2275 __func__, sc->sc_bmisscount); 2276 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2277 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2278 return; 2279 } 2280 if (sc->sc_bmisscount != 0) { 2281 DPRINTF(sc, ATH_DEBUG_BEACON, 2282 "%s: resume beacon xmit after %u misses\n", 2283 __func__, sc->sc_bmisscount); 2284 sc->sc_bmisscount = 0; 2285 } 2286 2287 /* 2288 * Update dynamic beacon contents. If this returns 2289 * non-zero then we need to remap the memory because 2290 * the beacon frame changed size (probably because 2291 * of the TIM bitmap). 2292 */ 2293 m = bf->bf_m; 2294 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2295 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2296 /* XXX too conservative? */ 2297 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2298 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2299 BUS_DMA_NOWAIT); 2300 if (error != 0) { 2301 if_printf(&sc->sc_if, 2302 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2303 __func__, error); 2304 return; 2305 } 2306 } 2307 2308 /* 2309 * Handle slot time change when a non-ERP station joins/leaves 2310 * an 11g network. The 802.11 layer notifies us via callback, 2311 * we mark updateslot, then wait one beacon before effecting 2312 * the change. This gives associated stations at least one 2313 * beacon interval to note the state change. 2314 */ 2315 /* XXX locking */ 2316 if (sc->sc_updateslot == UPDATE) 2317 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2318 else if (sc->sc_updateslot == COMMIT) 2319 ath_setslottime(sc); /* commit change to h/w */ 2320 2321 /* 2322 * Check recent per-antenna transmit statistics and flip 2323 * the default antenna if noticeably more frames went out 2324 * on the non-default antenna. 2325 * XXX assumes 2 anntenae 2326 */ 2327 otherant = sc->sc_defant & 1 ? 2 : 1; 2328 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2329 ath_setdefantenna(sc, otherant); 2330 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2331 2332 /* 2333 * Construct tx descriptor. 2334 */ 2335 ath_beacon_setup(sc, bf); 2336 2337 /* 2338 * Stop any current dma and put the new frame on the queue. 2339 * This should never fail since we check above that no frames 2340 * are still pending on the queue. 2341 */ 2342 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2343 DPRINTF(sc, ATH_DEBUG_ANY, 2344 "%s: beacon queue %u did not stop?\n", 2345 __func__, sc->sc_bhalq); 2346 } 2347 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2348 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2349 2350 /* 2351 * Enable the CAB queue before the beacon queue to 2352 * insure cab frames are triggered by this beacon. 2353 */ 2354 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2355 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2356 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2357 ath_hal_txstart(ah, sc->sc_bhalq); 2358 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2359 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2360 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2361 2362 sc->sc_stats.ast_be_xmit++; 2363 } 2364 2365 /* 2366 * Reset the hardware after detecting beacons have stopped. 2367 */ 2368 static void 2369 ath_bstuck_proc(void *arg, int pending) 2370 { 2371 struct ath_softc *sc = arg; 2372 struct ifnet *ifp = &sc->sc_if; 2373 2374 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2375 sc->sc_bmisscount); 2376 ath_reset(ifp); 2377 } 2378 2379 /* 2380 * Reclaim beacon resources. 2381 */ 2382 static void 2383 ath_beacon_free(struct ath_softc *sc) 2384 { 2385 struct ath_buf *bf; 2386 2387 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2388 if (bf->bf_m != NULL) { 2389 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2390 m_freem(bf->bf_m); 2391 bf->bf_m = NULL; 2392 } 2393 if (bf->bf_node != NULL) { 2394 ieee80211_free_node(bf->bf_node); 2395 bf->bf_node = NULL; 2396 } 2397 } 2398 } 2399 2400 /* 2401 * Configure the beacon and sleep timers. 2402 * 2403 * When operating as an AP this resets the TSF and sets 2404 * up the hardware to notify us when we need to issue beacons. 2405 * 2406 * When operating in station mode this sets up the beacon 2407 * timers according to the timestamp of the last received 2408 * beacon and the current TSF, configures PCF and DTIM 2409 * handling, programs the sleep registers so the hardware 2410 * will wakeup in time to receive beacons, and configures 2411 * the beacon miss handling so we'll receive a BMISS 2412 * interrupt when we stop seeing beacons from the AP 2413 * we've associated with. 2414 */ 2415 static void 2416 ath_beacon_config(struct ath_softc *sc) 2417 { 2418 #define TSF_TO_TU(_h,_l) \ 2419 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2420 #define FUDGE 2 2421 struct ath_hal *ah = sc->sc_ah; 2422 struct ieee80211com *ic = &sc->sc_ic; 2423 struct ieee80211_node *ni = ic->ic_bss; 2424 u_int32_t nexttbtt, intval, tsftu; 2425 u_int64_t tsf; 2426 2427 /* extract tstamp from last beacon and convert to TU */ 2428 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2429 LE_READ_4(ni->ni_tstamp.data)); 2430 /* NB: the beacon interval is kept internally in TU's */ 2431 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2432 if (nexttbtt == 0) /* e.g. for ap mode */ 2433 nexttbtt = intval; 2434 else if (intval) /* NB: can be 0 for monitor mode */ 2435 nexttbtt = roundup(nexttbtt, intval); 2436 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2437 __func__, nexttbtt, intval, ni->ni_intval); 2438 if (ic->ic_opmode == IEEE80211_M_STA) { 2439 HAL_BEACON_STATE bs; 2440 int dtimperiod, dtimcount; 2441 int cfpperiod, cfpcount; 2442 2443 /* 2444 * Setup dtim and cfp parameters according to 2445 * last beacon we received (which may be none). 2446 */ 2447 dtimperiod = ni->ni_dtim_period; 2448 if (dtimperiod <= 0) /* NB: 0 if not known */ 2449 dtimperiod = 1; 2450 dtimcount = ni->ni_dtim_count; 2451 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2452 dtimcount = 0; /* XXX? */ 2453 cfpperiod = 1; /* NB: no PCF support yet */ 2454 cfpcount = 0; 2455 /* 2456 * Pull nexttbtt forward to reflect the current 2457 * TSF and calculate dtim+cfp state for the result. 2458 */ 2459 tsf = ath_hal_gettsf64(ah); 2460 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2461 do { 2462 nexttbtt += intval; 2463 if (--dtimcount < 0) { 2464 dtimcount = dtimperiod - 1; 2465 if (--cfpcount < 0) 2466 cfpcount = cfpperiod - 1; 2467 } 2468 } while (nexttbtt < tsftu); 2469 memset(&bs, 0, sizeof(bs)); 2470 bs.bs_intval = intval; 2471 bs.bs_nexttbtt = nexttbtt; 2472 bs.bs_dtimperiod = dtimperiod*intval; 2473 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2474 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2475 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2476 bs.bs_cfpmaxduration = 0; 2477 #if 0 2478 /* 2479 * The 802.11 layer records the offset to the DTIM 2480 * bitmap while receiving beacons; use it here to 2481 * enable h/w detection of our AID being marked in 2482 * the bitmap vector (to indicate frames for us are 2483 * pending at the AP). 2484 * XXX do DTIM handling in s/w to WAR old h/w bugs 2485 * XXX enable based on h/w rev for newer chips 2486 */ 2487 bs.bs_timoffset = ni->ni_timoff; 2488 #endif 2489 /* 2490 * Calculate the number of consecutive beacons to miss 2491 * before taking a BMISS interrupt. The configuration 2492 * is specified in ms, so we need to convert that to 2493 * TU's and then calculate based on the beacon interval. 2494 * Note that we clamp the result to at most 10 beacons. 2495 */ 2496 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2497 if (bs.bs_bmissthreshold > 10) 2498 bs.bs_bmissthreshold = 10; 2499 else if (bs.bs_bmissthreshold <= 0) 2500 bs.bs_bmissthreshold = 1; 2501 2502 /* 2503 * Calculate sleep duration. The configuration is 2504 * given in ms. We insure a multiple of the beacon 2505 * period is used. Also, if the sleep duration is 2506 * greater than the DTIM period then it makes senses 2507 * to make it a multiple of that. 2508 * 2509 * XXX fixed at 100ms 2510 */ 2511 bs.bs_sleepduration = 2512 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2513 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2514 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2515 2516 DPRINTF(sc, ATH_DEBUG_BEACON, 2517 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2518 , __func__ 2519 , tsf, tsftu 2520 , bs.bs_intval 2521 , bs.bs_nexttbtt 2522 , bs.bs_dtimperiod 2523 , bs.bs_nextdtim 2524 , bs.bs_bmissthreshold 2525 , bs.bs_sleepduration 2526 , bs.bs_cfpperiod 2527 , bs.bs_cfpmaxduration 2528 , bs.bs_cfpnext 2529 , bs.bs_timoffset 2530 ); 2531 ath_hal_intrset(ah, 0); 2532 ath_hal_beacontimers(ah, &bs); 2533 sc->sc_imask |= HAL_INT_BMISS; 2534 ath_hal_intrset(ah, sc->sc_imask); 2535 } else { 2536 ath_hal_intrset(ah, 0); 2537 if (nexttbtt == intval) 2538 intval |= HAL_BEACON_RESET_TSF; 2539 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2540 /* 2541 * In IBSS mode enable the beacon timers but only 2542 * enable SWBA interrupts if we need to manually 2543 * prepare beacon frames. Otherwise we use a 2544 * self-linked tx descriptor and let the hardware 2545 * deal with things. 2546 */ 2547 intval |= HAL_BEACON_ENA; 2548 if (!sc->sc_hasveol) 2549 sc->sc_imask |= HAL_INT_SWBA; 2550 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2551 /* 2552 * Pull nexttbtt forward to reflect 2553 * the current TSF. 2554 */ 2555 tsf = ath_hal_gettsf64(ah); 2556 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2557 do { 2558 nexttbtt += intval; 2559 } while (nexttbtt < tsftu); 2560 } 2561 ath_beaconq_config(sc); 2562 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2563 /* 2564 * In AP mode we enable the beacon timers and 2565 * SWBA interrupts to prepare beacon frames. 2566 */ 2567 intval |= HAL_BEACON_ENA; 2568 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2569 ath_beaconq_config(sc); 2570 } 2571 ath_hal_beaconinit(ah, nexttbtt, intval); 2572 sc->sc_bmisscount = 0; 2573 ath_hal_intrset(ah, sc->sc_imask); 2574 /* 2575 * When using a self-linked beacon descriptor in 2576 * ibss mode load it once here. 2577 */ 2578 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2579 ath_beacon_proc(sc, 0); 2580 } 2581 sc->sc_syncbeacon = 0; 2582 #undef UNDEF 2583 #undef TSF_TO_TU 2584 } 2585 2586 static int 2587 ath_descdma_setup(struct ath_softc *sc, 2588 struct ath_descdma *dd, ath_bufhead *head, 2589 const char *name, int nbuf, int ndesc) 2590 { 2591 #define DS2PHYS(_dd, _ds) \ 2592 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2593 struct ifnet *ifp = &sc->sc_if; 2594 struct ath_desc *ds; 2595 struct ath_buf *bf; 2596 int i, bsize, error; 2597 2598 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2599 __func__, name, nbuf, ndesc); 2600 2601 dd->dd_name = name; 2602 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2603 2604 /* 2605 * Setup DMA descriptor area. 2606 */ 2607 dd->dd_dmat = sc->sc_dmat; 2608 2609 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2610 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2611 2612 if (error != 0) { 2613 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2614 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2615 goto fail0; 2616 } 2617 2618 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2619 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2620 if (error != 0) { 2621 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2622 nbuf * ndesc, dd->dd_name, error); 2623 goto fail1; 2624 } 2625 2626 /* allocate descriptors */ 2627 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2628 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2629 if (error != 0) { 2630 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2631 "error %u\n", dd->dd_name, error); 2632 goto fail2; 2633 } 2634 2635 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2636 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2637 if (error != 0) { 2638 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2639 dd->dd_name, error); 2640 goto fail3; 2641 } 2642 2643 ds = dd->dd_desc; 2644 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2645 DPRINTF(sc, ATH_DEBUG_RESET, 2646 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2647 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2648 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2649 2650 /* allocate rx buffers */ 2651 bsize = sizeof(struct ath_buf) * nbuf; 2652 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2653 if (bf == NULL) { 2654 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2655 dd->dd_name, bsize); 2656 goto fail4; 2657 } 2658 dd->dd_bufptr = bf; 2659 2660 STAILQ_INIT(head); 2661 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2662 bf->bf_desc = ds; 2663 bf->bf_daddr = DS2PHYS(dd, ds); 2664 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2665 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2666 if (error != 0) { 2667 if_printf(ifp, "unable to create dmamap for %s " 2668 "buffer %u, error %u\n", dd->dd_name, i, error); 2669 ath_descdma_cleanup(sc, dd, head); 2670 return error; 2671 } 2672 STAILQ_INSERT_TAIL(head, bf, bf_list); 2673 } 2674 return 0; 2675 fail4: 2676 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2677 fail3: 2678 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2679 fail2: 2680 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2681 fail1: 2682 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2683 fail0: 2684 memset(dd, 0, sizeof(*dd)); 2685 return error; 2686 #undef DS2PHYS 2687 } 2688 2689 static void 2690 ath_descdma_cleanup(struct ath_softc *sc, 2691 struct ath_descdma *dd, ath_bufhead *head) 2692 { 2693 struct ath_buf *bf; 2694 struct ieee80211_node *ni; 2695 2696 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2697 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2698 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2699 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2700 2701 STAILQ_FOREACH(bf, head, bf_list) { 2702 if (bf->bf_m) { 2703 m_freem(bf->bf_m); 2704 bf->bf_m = NULL; 2705 } 2706 if (bf->bf_dmamap != NULL) { 2707 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2708 bf->bf_dmamap = NULL; 2709 } 2710 ni = bf->bf_node; 2711 bf->bf_node = NULL; 2712 if (ni != NULL) { 2713 /* 2714 * Reclaim node reference. 2715 */ 2716 ieee80211_free_node(ni); 2717 } 2718 } 2719 2720 STAILQ_INIT(head); 2721 free(dd->dd_bufptr, M_ATHDEV); 2722 memset(dd, 0, sizeof(*dd)); 2723 } 2724 2725 static int 2726 ath_desc_alloc(struct ath_softc *sc) 2727 { 2728 int error; 2729 2730 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2731 "rx", ath_rxbuf, 1); 2732 if (error != 0) 2733 return error; 2734 2735 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2736 "tx", ath_txbuf, ATH_TXDESC); 2737 if (error != 0) { 2738 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2739 return error; 2740 } 2741 2742 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2743 "beacon", 1, 1); 2744 if (error != 0) { 2745 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2746 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2747 return error; 2748 } 2749 return 0; 2750 } 2751 2752 static void 2753 ath_desc_free(struct ath_softc *sc) 2754 { 2755 2756 if (sc->sc_bdma.dd_desc_len != 0) 2757 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2758 if (sc->sc_txdma.dd_desc_len != 0) 2759 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2760 if (sc->sc_rxdma.dd_desc_len != 0) 2761 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2762 } 2763 2764 static struct ieee80211_node * 2765 ath_node_alloc(struct ieee80211_node_table *nt) 2766 { 2767 struct ieee80211com *ic = nt->nt_ic; 2768 struct ath_softc *sc = ic->ic_ifp->if_softc; 2769 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2770 struct ath_node *an; 2771 2772 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2773 if (an == NULL) { 2774 /* XXX stat+msg */ 2775 return NULL; 2776 } 2777 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2778 ath_rate_node_init(sc, an); 2779 2780 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2781 return &an->an_node; 2782 } 2783 2784 static void 2785 ath_node_free(struct ieee80211_node *ni) 2786 { 2787 struct ieee80211com *ic = ni->ni_ic; 2788 struct ath_softc *sc = ic->ic_ifp->if_softc; 2789 2790 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2791 2792 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2793 sc->sc_node_free(ni); 2794 } 2795 2796 static u_int8_t 2797 ath_node_getrssi(const struct ieee80211_node *ni) 2798 { 2799 #define HAL_EP_RND(x, mul) \ 2800 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2801 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2802 int32_t rssi; 2803 2804 /* 2805 * When only one frame is received there will be no state in 2806 * avgrssi so fallback on the value recorded by the 802.11 layer. 2807 */ 2808 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2809 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2810 else 2811 rssi = ni->ni_rssi; 2812 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2813 #undef HAL_EP_RND 2814 } 2815 2816 static int 2817 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2818 { 2819 struct ath_hal *ah = sc->sc_ah; 2820 int error; 2821 struct mbuf *m; 2822 struct ath_desc *ds; 2823 2824 m = bf->bf_m; 2825 if (m == NULL) { 2826 /* 2827 * NB: by assigning a page to the rx dma buffer we 2828 * implicitly satisfy the Atheros requirement that 2829 * this buffer be cache-line-aligned and sized to be 2830 * multiple of the cache line size. Not doing this 2831 * causes weird stuff to happen (for the 5210 at least). 2832 */ 2833 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2834 if (m == NULL) { 2835 DPRINTF(sc, ATH_DEBUG_ANY, 2836 "%s: no mbuf/cluster\n", __func__); 2837 sc->sc_stats.ast_rx_nombuf++; 2838 return ENOMEM; 2839 } 2840 bf->bf_m = m; 2841 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2842 2843 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2844 bf->bf_dmamap, m, 2845 BUS_DMA_NOWAIT); 2846 if (error != 0) { 2847 DPRINTF(sc, ATH_DEBUG_ANY, 2848 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2849 __func__, error); 2850 sc->sc_stats.ast_rx_busdma++; 2851 return error; 2852 } 2853 KASSERT(bf->bf_nseg == 1, 2854 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2855 } 2856 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2857 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2858 2859 /* 2860 * Setup descriptors. For receive we always terminate 2861 * the descriptor list with a self-linked entry so we'll 2862 * not get overrun under high load (as can happen with a 2863 * 5212 when ANI processing enables PHY error frames). 2864 * 2865 * To insure the last descriptor is self-linked we create 2866 * each descriptor as self-linked and add it to the end. As 2867 * each additional descriptor is added the previous self-linked 2868 * entry is ``fixed'' naturally. This should be safe even 2869 * if DMA is happening. When processing RX interrupts we 2870 * never remove/process the last, self-linked, entry on the 2871 * descriptor list. This insures the hardware always has 2872 * someplace to write a new frame. 2873 */ 2874 ds = bf->bf_desc; 2875 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2876 ds->ds_data = bf->bf_segs[0].ds_addr; 2877 /* ds->ds_vdata = mtod(m, void *); for radar */ 2878 ath_hal_setuprxdesc(ah, ds 2879 , m->m_len /* buffer size */ 2880 , 0 2881 ); 2882 2883 if (sc->sc_rxlink != NULL) 2884 *sc->sc_rxlink = bf->bf_daddr; 2885 sc->sc_rxlink = &ds->ds_link; 2886 return 0; 2887 } 2888 2889 /* 2890 * Extend 15-bit time stamp from rx descriptor to 2891 * a full 64-bit TSF using the specified TSF. 2892 */ 2893 static inline u_int64_t 2894 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2895 { 2896 if ((tsf & 0x7fff) < rstamp) 2897 tsf -= 0x8000; 2898 return ((tsf &~ 0x7fff) | rstamp); 2899 } 2900 2901 /* 2902 * Intercept management frames to collect beacon rssi data 2903 * and to do ibss merges. 2904 */ 2905 static void 2906 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2907 struct ieee80211_node *ni, 2908 int subtype, int rssi, u_int32_t rstamp) 2909 { 2910 struct ath_softc *sc = ic->ic_ifp->if_softc; 2911 2912 /* 2913 * Call up first so subsequent work can use information 2914 * potentially stored in the node (e.g. for ibss merge). 2915 */ 2916 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2917 switch (subtype) { 2918 case IEEE80211_FC0_SUBTYPE_BEACON: 2919 /* update rssi statistics for use by the hal */ 2920 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2921 if (sc->sc_syncbeacon && 2922 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2923 /* 2924 * Resync beacon timers using the tsf of the beacon 2925 * frame we just received. 2926 */ 2927 ath_beacon_config(sc); 2928 } 2929 /* fall thru... */ 2930 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2931 if (ic->ic_opmode == IEEE80211_M_IBSS && 2932 ic->ic_state == IEEE80211_S_RUN) { 2933 u_int64_t tsf = ath_extend_tsf(rstamp, 2934 ath_hal_gettsf64(sc->sc_ah)); 2935 2936 /* 2937 * Handle ibss merge as needed; check the tsf on the 2938 * frame before attempting the merge. The 802.11 spec 2939 * says the station should change it's bssid to match 2940 * the oldest station with the same ssid, where oldest 2941 * is determined by the tsf. Note that hardware 2942 * reconfiguration happens through callback to 2943 * ath_newstate as the state machine will go from 2944 * RUN -> RUN when this happens. 2945 */ 2946 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2947 DPRINTF(sc, ATH_DEBUG_STATE, 2948 "ibss merge, rstamp %u tsf %ju " 2949 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2950 (uintmax_t)ni->ni_tstamp.tsf); 2951 (void) ieee80211_ibss_merge(ni); 2952 } 2953 } 2954 break; 2955 } 2956 } 2957 2958 /* 2959 * Set the default antenna. 2960 */ 2961 static void 2962 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2963 { 2964 struct ath_hal *ah = sc->sc_ah; 2965 2966 /* XXX block beacon interrupts */ 2967 ath_hal_setdefantenna(ah, antenna); 2968 if (sc->sc_defant != antenna) 2969 sc->sc_stats.ast_ant_defswitch++; 2970 sc->sc_defant = antenna; 2971 sc->sc_rxotherant = 0; 2972 } 2973 2974 static void 2975 ath_handle_micerror(struct ieee80211com *ic, 2976 struct ieee80211_frame *wh, int keyix) 2977 { 2978 struct ieee80211_node *ni; 2979 2980 /* XXX recheck MIC to deal w/ chips that lie */ 2981 /* XXX discard MIC errors on !data frames */ 2982 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 2983 if (ni != NULL) { 2984 ieee80211_notify_michael_failure(ic, wh, keyix); 2985 ieee80211_free_node(ni); 2986 } 2987 } 2988 2989 static void 2990 ath_rx_proc(void *arg, int npending) 2991 { 2992 #define PA2DESC(_sc, _pa) \ 2993 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2994 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2995 struct ath_softc *sc = arg; 2996 struct ath_buf *bf; 2997 struct ieee80211com *ic = &sc->sc_ic; 2998 struct ifnet *ifp = &sc->sc_if; 2999 struct ath_hal *ah = sc->sc_ah; 3000 struct ath_desc *ds; 3001 struct mbuf *m; 3002 struct ieee80211_node *ni; 3003 struct ath_node *an; 3004 int len, ngood, type; 3005 u_int phyerr; 3006 HAL_STATUS status; 3007 int16_t nf; 3008 u_int64_t tsf; 3009 uint8_t rxerr_tap, rxerr_mon; 3010 3011 NET_LOCK_GIANT(); /* XXX */ 3012 3013 rxerr_tap = 3014 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 3015 3016 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 3017 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3018 else if (ifp->if_flags & IFF_PROMISC) 3019 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3020 3021 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3022 ngood = 0; 3023 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3024 tsf = ath_hal_gettsf64(ah); 3025 do { 3026 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3027 if (bf == NULL) { /* NB: shouldn't happen */ 3028 if_printf(ifp, "%s: no buffer!\n", __func__); 3029 break; 3030 } 3031 ds = bf->bf_desc; 3032 if (ds->ds_link == bf->bf_daddr) { 3033 /* NB: never process the self-linked entry at the end */ 3034 break; 3035 } 3036 m = bf->bf_m; 3037 if (m == NULL) { /* NB: shouldn't happen */ 3038 if_printf(ifp, "%s: no mbuf!\n", __func__); 3039 break; 3040 } 3041 /* XXX sync descriptor memory */ 3042 /* 3043 * Must provide the virtual address of the current 3044 * descriptor, the physical address, and the virtual 3045 * address of the next descriptor in the h/w chain. 3046 * This allows the HAL to look ahead to see if the 3047 * hardware is done with a descriptor by checking the 3048 * done bit in the following descriptor and the address 3049 * of the current descriptor the DMA engine is working 3050 * on. All this is necessary because of our use of 3051 * a self-linked list to avoid rx overruns. 3052 */ 3053 status = ath_hal_rxprocdesc(ah, ds, 3054 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 3055 &ds->ds_rxstat); 3056 #ifdef AR_DEBUG 3057 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3058 ath_printrxbuf(bf, status == HAL_OK); 3059 #endif 3060 if (status == HAL_EINPROGRESS) 3061 break; 3062 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3063 if (ds->ds_rxstat.rs_more) { 3064 /* 3065 * Frame spans multiple descriptors; this 3066 * cannot happen yet as we don't support 3067 * jumbograms. If not in monitor mode, 3068 * discard the frame. 3069 */ 3070 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3071 sc->sc_stats.ast_rx_toobig++; 3072 goto rx_next; 3073 } 3074 /* fall thru for monitor mode handling... */ 3075 } else if (ds->ds_rxstat.rs_status != 0) { 3076 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3077 sc->sc_stats.ast_rx_crcerr++; 3078 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3079 sc->sc_stats.ast_rx_fifoerr++; 3080 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3081 sc->sc_stats.ast_rx_phyerr++; 3082 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3083 sc->sc_stats.ast_rx_phy[phyerr]++; 3084 goto rx_next; 3085 } 3086 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3087 /* 3088 * Decrypt error. If the error occurred 3089 * because there was no hardware key, then 3090 * let the frame through so the upper layers 3091 * can process it. This is necessary for 5210 3092 * parts which have no way to setup a ``clear'' 3093 * key cache entry. 3094 * 3095 * XXX do key cache faulting 3096 */ 3097 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3098 goto rx_accept; 3099 sc->sc_stats.ast_rx_badcrypt++; 3100 } 3101 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3102 sc->sc_stats.ast_rx_badmic++; 3103 /* 3104 * Do minimal work required to hand off 3105 * the 802.11 header for notifcation. 3106 */ 3107 /* XXX frag's and qos frames */ 3108 len = ds->ds_rxstat.rs_datalen; 3109 if (len >= sizeof (struct ieee80211_frame)) { 3110 bus_dmamap_sync(sc->sc_dmat, 3111 bf->bf_dmamap, 3112 0, bf->bf_dmamap->dm_mapsize, 3113 BUS_DMASYNC_POSTREAD); 3114 ath_handle_micerror(ic, 3115 mtod(m, struct ieee80211_frame *), 3116 sc->sc_splitmic ? 3117 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3118 } 3119 } 3120 ifp->if_ierrors++; 3121 /* 3122 * Reject error frames, we normally don't want 3123 * to see them in monitor mode (in monitor mode 3124 * allow through packets that have crypto problems). 3125 */ 3126 3127 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3128 goto rx_next; 3129 } 3130 rx_accept: 3131 /* 3132 * Sync and unmap the frame. At this point we're 3133 * committed to passing the mbuf somewhere so clear 3134 * bf_m; this means a new sk_buff must be allocated 3135 * when the rx descriptor is setup again to receive 3136 * another frame. 3137 */ 3138 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3139 0, bf->bf_dmamap->dm_mapsize, 3140 BUS_DMASYNC_POSTREAD); 3141 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3142 bf->bf_m = NULL; 3143 3144 m->m_pkthdr.rcvif = ifp; 3145 len = ds->ds_rxstat.rs_datalen; 3146 m->m_pkthdr.len = m->m_len = len; 3147 3148 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3149 3150 if (sc->sc_drvbpf) { 3151 u_int8_t rix; 3152 3153 /* 3154 * Discard anything shorter than an ack or cts. 3155 */ 3156 if (len < IEEE80211_ACK_LEN) { 3157 DPRINTF(sc, ATH_DEBUG_RECV, 3158 "%s: runt packet %d\n", 3159 __func__, len); 3160 sc->sc_stats.ast_rx_tooshort++; 3161 m_freem(m); 3162 goto rx_next; 3163 } 3164 rix = ds->ds_rxstat.rs_rate; 3165 sc->sc_rx_th.wr_tsf = htole64( 3166 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3167 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3168 if (ds->ds_rxstat.rs_status & 3169 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3170 sc->sc_rx_th.wr_flags |= 3171 IEEE80211_RADIOTAP_F_BADFCS; 3172 } 3173 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3174 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3175 sc->sc_rx_th.wr_antnoise = nf; 3176 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3177 3178 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, 3179 sc->sc_rx_th_len, m); 3180 } 3181 3182 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3183 m_freem(m); 3184 goto rx_next; 3185 } 3186 /* 3187 * From this point on we assume the frame is at least 3188 * as large as ieee80211_frame_min; verify that. 3189 */ 3190 if (len < IEEE80211_MIN_LEN) { 3191 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3192 __func__, len); 3193 sc->sc_stats.ast_rx_tooshort++; 3194 m_freem(m); 3195 goto rx_next; 3196 } 3197 3198 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3199 ieee80211_dump_pkt(mtod(m, void *), len, 3200 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3201 ds->ds_rxstat.rs_rssi); 3202 } 3203 3204 m_adj(m, -IEEE80211_CRC_LEN); 3205 3206 /* 3207 * Locate the node for sender, track state, and then 3208 * pass the (referenced) node up to the 802.11 layer 3209 * for its use. 3210 */ 3211 ni = ieee80211_find_rxnode_withkey(ic, 3212 mtod(m, const struct ieee80211_frame_min *), 3213 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3214 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3215 /* 3216 * Track rx rssi and do any rx antenna management. 3217 */ 3218 an = ATH_NODE(ni); 3219 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3220 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3221 /* 3222 * Send frame up for processing. 3223 */ 3224 type = ieee80211_input(ic, m, ni, 3225 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3226 ieee80211_free_node(ni); 3227 if (sc->sc_diversity) { 3228 /* 3229 * When using fast diversity, change the default rx 3230 * antenna if diversity chooses the other antenna 3 3231 * times in a row. 3232 */ 3233 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3234 if (++sc->sc_rxotherant >= 3) 3235 ath_setdefantenna(sc, 3236 ds->ds_rxstat.rs_antenna); 3237 } else 3238 sc->sc_rxotherant = 0; 3239 } 3240 if (sc->sc_softled) { 3241 /* 3242 * Blink for any data frame. Otherwise do a 3243 * heartbeat-style blink when idle. The latter 3244 * is mainly for station mode where we depend on 3245 * periodic beacon frames to trigger the poll event. 3246 */ 3247 if (type == IEEE80211_FC0_TYPE_DATA) { 3248 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3249 ath_led_event(sc, ATH_LED_RX); 3250 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3251 ath_led_event(sc, ATH_LED_POLL); 3252 } 3253 /* 3254 * Arrange to update the last rx timestamp only for 3255 * frames from our ap when operating in station mode. 3256 * This assumes the rx key is always setup when associated. 3257 */ 3258 if (ic->ic_opmode == IEEE80211_M_STA && 3259 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3260 ngood++; 3261 rx_next: 3262 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3263 } while (ath_rxbuf_init(sc, bf) == 0); 3264 3265 /* rx signal state monitoring */ 3266 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3267 #if 0 3268 if (ath_hal_radar_event(ah)) 3269 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3270 #endif 3271 if (ngood) 3272 sc->sc_lastrx = tsf; 3273 3274 #ifdef __NetBSD__ 3275 /* XXX Why isn't this necessary in FreeBSD? */ 3276 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3277 ath_start(ifp); 3278 #endif /* __NetBSD__ */ 3279 3280 NET_UNLOCK_GIANT(); /* XXX */ 3281 #undef PA2DESC 3282 } 3283 3284 /* 3285 * Setup a h/w transmit queue. 3286 */ 3287 static struct ath_txq * 3288 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3289 { 3290 #define N(a) (sizeof(a)/sizeof(a[0])) 3291 struct ath_hal *ah = sc->sc_ah; 3292 HAL_TXQ_INFO qi; 3293 int qnum; 3294 3295 memset(&qi, 0, sizeof(qi)); 3296 qi.tqi_subtype = subtype; 3297 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3298 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3299 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3300 /* 3301 * Enable interrupts only for EOL and DESC conditions. 3302 * We mark tx descriptors to receive a DESC interrupt 3303 * when a tx queue gets deep; otherwise waiting for the 3304 * EOL to reap descriptors. Note that this is done to 3305 * reduce interrupt load and this only defers reaping 3306 * descriptors, never transmitting frames. Aside from 3307 * reducing interrupts this also permits more concurrency. 3308 * The only potential downside is if the tx queue backs 3309 * up in which case the top half of the kernel may backup 3310 * due to a lack of tx descriptors. 3311 */ 3312 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3313 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3314 if (qnum == -1) { 3315 /* 3316 * NB: don't print a message, this happens 3317 * normally on parts with too few tx queues 3318 */ 3319 return NULL; 3320 } 3321 if (qnum >= N(sc->sc_txq)) { 3322 device_printf(sc->sc_dev, 3323 "hal qnum %u out of range, max %zu!\n", 3324 qnum, N(sc->sc_txq)); 3325 ath_hal_releasetxqueue(ah, qnum); 3326 return NULL; 3327 } 3328 if (!ATH_TXQ_SETUP(sc, qnum)) { 3329 struct ath_txq *txq = &sc->sc_txq[qnum]; 3330 3331 txq->axq_qnum = qnum; 3332 txq->axq_depth = 0; 3333 txq->axq_intrcnt = 0; 3334 txq->axq_link = NULL; 3335 STAILQ_INIT(&txq->axq_q); 3336 ATH_TXQ_LOCK_INIT(sc, txq); 3337 sc->sc_txqsetup |= 1<<qnum; 3338 } 3339 return &sc->sc_txq[qnum]; 3340 #undef N 3341 } 3342 3343 /* 3344 * Setup a hardware data transmit queue for the specified 3345 * access control. The hal may not support all requested 3346 * queues in which case it will return a reference to a 3347 * previously setup queue. We record the mapping from ac's 3348 * to h/w queues for use by ath_tx_start and also track 3349 * the set of h/w queues being used to optimize work in the 3350 * transmit interrupt handler and related routines. 3351 */ 3352 static int 3353 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3354 { 3355 #define N(a) (sizeof(a)/sizeof(a[0])) 3356 struct ath_txq *txq; 3357 3358 if (ac >= N(sc->sc_ac2q)) { 3359 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3360 ac, N(sc->sc_ac2q)); 3361 return 0; 3362 } 3363 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3364 if (txq != NULL) { 3365 sc->sc_ac2q[ac] = txq; 3366 return 1; 3367 } else 3368 return 0; 3369 #undef N 3370 } 3371 3372 /* 3373 * Update WME parameters for a transmit queue. 3374 */ 3375 static int 3376 ath_txq_update(struct ath_softc *sc, int ac) 3377 { 3378 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3379 #define ATH_TXOP_TO_US(v) (v<<5) 3380 struct ieee80211com *ic = &sc->sc_ic; 3381 struct ath_txq *txq = sc->sc_ac2q[ac]; 3382 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3383 struct ath_hal *ah = sc->sc_ah; 3384 HAL_TXQ_INFO qi; 3385 3386 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3387 qi.tqi_aifs = wmep->wmep_aifsn; 3388 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3389 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3390 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3391 3392 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3393 device_printf(sc->sc_dev, "unable to update hardware queue " 3394 "parameters for %s traffic!\n", 3395 ieee80211_wme_acnames[ac]); 3396 return 0; 3397 } else { 3398 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3399 return 1; 3400 } 3401 #undef ATH_TXOP_TO_US 3402 #undef ATH_EXPONENT_TO_VALUE 3403 } 3404 3405 /* 3406 * Callback from the 802.11 layer to update WME parameters. 3407 */ 3408 static int 3409 ath_wme_update(struct ieee80211com *ic) 3410 { 3411 struct ath_softc *sc = ic->ic_ifp->if_softc; 3412 3413 return !ath_txq_update(sc, WME_AC_BE) || 3414 !ath_txq_update(sc, WME_AC_BK) || 3415 !ath_txq_update(sc, WME_AC_VI) || 3416 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3417 } 3418 3419 /* 3420 * Reclaim resources for a setup queue. 3421 */ 3422 static void 3423 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3424 { 3425 3426 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3427 ATH_TXQ_LOCK_DESTROY(txq); 3428 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3429 } 3430 3431 /* 3432 * Reclaim all tx queue resources. 3433 */ 3434 static void 3435 ath_tx_cleanup(struct ath_softc *sc) 3436 { 3437 int i; 3438 3439 ATH_TXBUF_LOCK_DESTROY(sc); 3440 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3441 if (ATH_TXQ_SETUP(sc, i)) 3442 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3443 } 3444 3445 /* 3446 * Defragment an mbuf chain, returning at most maxfrags separate 3447 * mbufs+clusters. If this is not possible NULL is returned and 3448 * the original mbuf chain is left in it's present (potentially 3449 * modified) state. We use two techniques: collapsing consecutive 3450 * mbufs and replacing consecutive mbufs by a cluster. 3451 */ 3452 static struct mbuf * 3453 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3454 { 3455 struct mbuf *m, *n, *n2, **prev; 3456 u_int curfrags; 3457 3458 /* 3459 * Calculate the current number of frags. 3460 */ 3461 curfrags = 0; 3462 for (m = m0; m != NULL; m = m->m_next) 3463 curfrags++; 3464 /* 3465 * First, try to collapse mbufs. Note that we always collapse 3466 * towards the front so we don't need to deal with moving the 3467 * pkthdr. This may be suboptimal if the first mbuf has much 3468 * less data than the following. 3469 */ 3470 m = m0; 3471 again: 3472 for (;;) { 3473 n = m->m_next; 3474 if (n == NULL) 3475 break; 3476 if (n->m_len < M_TRAILINGSPACE(m)) { 3477 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3478 n->m_len); 3479 m->m_len += n->m_len; 3480 m->m_next = n->m_next; 3481 m_free(n); 3482 if (--curfrags <= maxfrags) 3483 return m0; 3484 } else 3485 m = n; 3486 } 3487 KASSERT(maxfrags > 1, 3488 ("maxfrags %u, but normal collapse failed", maxfrags)); 3489 /* 3490 * Collapse consecutive mbufs to a cluster. 3491 */ 3492 prev = &m0->m_next; /* NB: not the first mbuf */ 3493 while ((n = *prev) != NULL) { 3494 if ((n2 = n->m_next) != NULL && 3495 n->m_len + n2->m_len < MCLBYTES) { 3496 m = m_getcl(how, MT_DATA, 0); 3497 if (m == NULL) 3498 goto bad; 3499 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3500 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3501 n2->m_len); 3502 m->m_len = n->m_len + n2->m_len; 3503 m->m_next = n2->m_next; 3504 *prev = m; 3505 m_free(n); 3506 m_free(n2); 3507 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3508 return m0; 3509 /* 3510 * Still not there, try the normal collapse 3511 * again before we allocate another cluster. 3512 */ 3513 goto again; 3514 } 3515 prev = &n->m_next; 3516 } 3517 /* 3518 * No place where we can collapse to a cluster; punt. 3519 * This can occur if, for example, you request 2 frags 3520 * but the packet requires that both be clusters (we 3521 * never reallocate the first mbuf to avoid moving the 3522 * packet header). 3523 */ 3524 bad: 3525 return NULL; 3526 } 3527 3528 /* 3529 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3530 */ 3531 static int 3532 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3533 { 3534 int i; 3535 3536 for (i = 0; i < rt->rateCount; i++) 3537 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3538 return i; 3539 return 0; /* NB: lowest rate */ 3540 } 3541 3542 static void 3543 ath_freetx(struct mbuf *m) 3544 { 3545 struct mbuf *next; 3546 3547 do { 3548 next = m->m_nextpkt; 3549 m->m_nextpkt = NULL; 3550 m_freem(m); 3551 } while ((m = next) != NULL); 3552 } 3553 3554 static int 3555 deduct_pad_bytes(int len, int hdrlen) 3556 { 3557 /* XXX I am suspicious that this code, which I extracted 3558 * XXX from ath_tx_start() for reuse, does the right thing. 3559 */ 3560 return len - (hdrlen & 3); 3561 } 3562 3563 static int 3564 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3565 struct mbuf *m0) 3566 { 3567 struct ieee80211com *ic = &sc->sc_ic; 3568 struct ath_hal *ah = sc->sc_ah; 3569 struct ifnet *ifp = &sc->sc_if; 3570 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3571 int i, error, iswep, ismcast, isfrag, ismrr; 3572 int keyix, hdrlen, pktlen, try0; 3573 u_int8_t rix, txrate, ctsrate; 3574 u_int8_t cix = 0xff; /* NB: silence compiler */ 3575 struct ath_desc *ds, *ds0; 3576 struct ath_txq *txq; 3577 struct ieee80211_frame *wh; 3578 u_int subtype, flags, ctsduration; 3579 HAL_PKT_TYPE atype; 3580 const HAL_RATE_TABLE *rt; 3581 HAL_BOOL shortPreamble; 3582 struct ath_node *an; 3583 struct mbuf *m; 3584 u_int pri; 3585 3586 wh = mtod(m0, struct ieee80211_frame *); 3587 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3588 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3589 isfrag = m0->m_flags & M_FRAG; 3590 hdrlen = ieee80211_anyhdrsize(wh); 3591 /* 3592 * Packet length must not include any 3593 * pad bytes; deduct them here. 3594 */ 3595 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3596 3597 if (iswep) { 3598 const struct ieee80211_cipher *cip; 3599 struct ieee80211_key *k; 3600 3601 /* 3602 * Construct the 802.11 header+trailer for an encrypted 3603 * frame. The only reason this can fail is because of an 3604 * unknown or unsupported cipher/key type. 3605 */ 3606 k = ieee80211_crypto_encap(ic, ni, m0); 3607 if (k == NULL) { 3608 /* 3609 * This can happen when the key is yanked after the 3610 * frame was queued. Just discard the frame; the 3611 * 802.11 layer counts failures and provides 3612 * debugging/diagnostics. 3613 */ 3614 ath_freetx(m0); 3615 return EIO; 3616 } 3617 /* 3618 * Adjust the packet + header lengths for the crypto 3619 * additions and calculate the h/w key index. When 3620 * a s/w mic is done the frame will have had any mic 3621 * added to it prior to entry so m0->m_pkthdr.len above will 3622 * account for it. Otherwise we need to add it to the 3623 * packet length. 3624 */ 3625 cip = k->wk_cipher; 3626 hdrlen += cip->ic_header; 3627 pktlen += cip->ic_header + cip->ic_trailer; 3628 /* NB: frags always have any TKIP MIC done in s/w */ 3629 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3630 pktlen += cip->ic_miclen; 3631 keyix = k->wk_keyix; 3632 3633 /* packet header may have moved, reset our local pointer */ 3634 wh = mtod(m0, struct ieee80211_frame *); 3635 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3636 /* 3637 * Use station key cache slot, if assigned. 3638 */ 3639 keyix = ni->ni_ucastkey.wk_keyix; 3640 if (keyix == IEEE80211_KEYIX_NONE) 3641 keyix = HAL_TXKEYIX_INVALID; 3642 } else 3643 keyix = HAL_TXKEYIX_INVALID; 3644 3645 pktlen += IEEE80211_CRC_LEN; 3646 3647 /* 3648 * Load the DMA map so any coalescing is done. This 3649 * also calculates the number of descriptors we need. 3650 */ 3651 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3652 BUS_DMA_NOWAIT); 3653 if (error == EFBIG) { 3654 /* XXX packet requires too many descriptors */ 3655 bf->bf_nseg = ATH_TXDESC+1; 3656 } else if (error != 0) { 3657 sc->sc_stats.ast_tx_busdma++; 3658 ath_freetx(m0); 3659 return error; 3660 } 3661 /* 3662 * Discard null packets and check for packets that 3663 * require too many TX descriptors. We try to convert 3664 * the latter to a cluster. 3665 */ 3666 if (error == EFBIG) { /* too many desc's, linearize */ 3667 sc->sc_stats.ast_tx_linear++; 3668 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3669 if (m == NULL) { 3670 ath_freetx(m0); 3671 sc->sc_stats.ast_tx_nombuf++; 3672 return ENOMEM; 3673 } 3674 m0 = m; 3675 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3676 BUS_DMA_NOWAIT); 3677 if (error != 0) { 3678 sc->sc_stats.ast_tx_busdma++; 3679 ath_freetx(m0); 3680 return error; 3681 } 3682 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3683 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3684 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3685 sc->sc_stats.ast_tx_nodata++; 3686 ath_freetx(m0); 3687 return EIO; 3688 } 3689 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3690 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3691 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3692 bf->bf_m = m0; 3693 bf->bf_node = ni; /* NB: held reference */ 3694 3695 /* setup descriptors */ 3696 ds = bf->bf_desc; 3697 rt = sc->sc_currates; 3698 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3699 3700 /* 3701 * NB: the 802.11 layer marks whether or not we should 3702 * use short preamble based on the current mode and 3703 * negotiated parameters. 3704 */ 3705 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3706 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3707 shortPreamble = AH_TRUE; 3708 sc->sc_stats.ast_tx_shortpre++; 3709 } else { 3710 shortPreamble = AH_FALSE; 3711 } 3712 3713 an = ATH_NODE(ni); 3714 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3715 ismrr = 0; /* default no multi-rate retry*/ 3716 /* 3717 * Calculate Atheros packet type from IEEE80211 packet header, 3718 * setup for rate calculations, and select h/w transmit queue. 3719 */ 3720 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3721 case IEEE80211_FC0_TYPE_MGT: 3722 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3723 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3724 atype = HAL_PKT_TYPE_BEACON; 3725 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3726 atype = HAL_PKT_TYPE_PROBE_RESP; 3727 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3728 atype = HAL_PKT_TYPE_ATIM; 3729 else 3730 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3731 rix = sc->sc_minrateix; 3732 txrate = rt->info[rix].rateCode; 3733 if (shortPreamble) 3734 txrate |= rt->info[rix].shortPreamble; 3735 try0 = ATH_TXMGTTRY; 3736 /* NB: force all management frames to highest queue */ 3737 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3738 /* NB: force all management frames to highest queue */ 3739 pri = WME_AC_VO; 3740 } else 3741 pri = WME_AC_BE; 3742 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3743 break; 3744 case IEEE80211_FC0_TYPE_CTL: 3745 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3746 rix = sc->sc_minrateix; 3747 txrate = rt->info[rix].rateCode; 3748 if (shortPreamble) 3749 txrate |= rt->info[rix].shortPreamble; 3750 try0 = ATH_TXMGTTRY; 3751 /* NB: force all ctl frames to highest queue */ 3752 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3753 /* NB: force all ctl frames to highest queue */ 3754 pri = WME_AC_VO; 3755 } else 3756 pri = WME_AC_BE; 3757 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3758 break; 3759 case IEEE80211_FC0_TYPE_DATA: 3760 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3761 /* 3762 * Data frames: multicast frames go out at a fixed rate, 3763 * otherwise consult the rate control module for the 3764 * rate to use. 3765 */ 3766 if (ismcast) { 3767 /* 3768 * Check mcast rate setting in case it's changed. 3769 * XXX move out of fastpath 3770 */ 3771 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3772 sc->sc_mcastrix = 3773 ath_tx_findrix(rt, ic->ic_mcast_rate); 3774 sc->sc_mcastrate = ic->ic_mcast_rate; 3775 } 3776 rix = sc->sc_mcastrix; 3777 txrate = rt->info[rix].rateCode; 3778 try0 = 1; 3779 } else { 3780 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3781 &rix, &try0, &txrate); 3782 sc->sc_txrate = txrate; /* for LED blinking */ 3783 if (try0 != ATH_TXMAXTRY) 3784 ismrr = 1; 3785 } 3786 pri = M_WME_GETAC(m0); 3787 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3788 flags |= HAL_TXDESC_NOACK; 3789 break; 3790 default: 3791 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3792 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3793 /* XXX statistic */ 3794 ath_freetx(m0); 3795 return EIO; 3796 } 3797 txq = sc->sc_ac2q[pri]; 3798 3799 /* 3800 * When servicing one or more stations in power-save mode 3801 * multicast frames must be buffered until after the beacon. 3802 * We use the CAB queue for that. 3803 */ 3804 if (ismcast && ic->ic_ps_sta) { 3805 txq = sc->sc_cabq; 3806 /* XXX? more bit in 802.11 frame header */ 3807 } 3808 3809 /* 3810 * Calculate miscellaneous flags. 3811 */ 3812 if (ismcast) { 3813 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3814 } else if (pktlen > ic->ic_rtsthreshold) { 3815 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3816 cix = rt->info[rix].controlRate; 3817 sc->sc_stats.ast_tx_rts++; 3818 } 3819 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3820 sc->sc_stats.ast_tx_noack++; 3821 3822 /* 3823 * If 802.11g protection is enabled, determine whether 3824 * to use RTS/CTS or just CTS. Note that this is only 3825 * done for OFDM unicast frames. 3826 */ 3827 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3828 rt->info[rix].phy == IEEE80211_T_OFDM && 3829 (flags & HAL_TXDESC_NOACK) == 0) { 3830 /* XXX fragments must use CCK rates w/ protection */ 3831 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3832 flags |= HAL_TXDESC_RTSENA; 3833 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3834 flags |= HAL_TXDESC_CTSENA; 3835 if (isfrag) { 3836 /* 3837 * For frags it would be desirable to use the 3838 * highest CCK rate for RTS/CTS. But stations 3839 * farther away may detect it at a lower CCK rate 3840 * so use the configured protection rate instead 3841 * (for now). 3842 */ 3843 cix = rt->info[sc->sc_protrix].controlRate; 3844 } else 3845 cix = rt->info[sc->sc_protrix].controlRate; 3846 sc->sc_stats.ast_tx_protect++; 3847 } 3848 3849 /* 3850 * Calculate duration. This logically belongs in the 802.11 3851 * layer but it lacks sufficient information to calculate it. 3852 */ 3853 if ((flags & HAL_TXDESC_NOACK) == 0 && 3854 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3855 u_int16_t dur; 3856 /* 3857 * XXX not right with fragmentation. 3858 */ 3859 if (shortPreamble) 3860 dur = rt->info[rix].spAckDuration; 3861 else 3862 dur = rt->info[rix].lpAckDuration; 3863 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3864 dur += dur; /* additional SIFS+ACK */ 3865 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3866 /* 3867 * Include the size of next fragment so NAV is 3868 * updated properly. The last fragment uses only 3869 * the ACK duration 3870 */ 3871 dur += ath_hal_computetxtime(ah, rt, 3872 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3873 hdrlen) - 3874 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3875 rix, shortPreamble); 3876 } 3877 if (isfrag) { 3878 /* 3879 * Force hardware to use computed duration for next 3880 * fragment by disabling multi-rate retry which updates 3881 * duration based on the multi-rate duration table. 3882 */ 3883 try0 = ATH_TXMAXTRY; 3884 } 3885 *(u_int16_t *)wh->i_dur = htole16(dur); 3886 } 3887 3888 /* 3889 * Calculate RTS/CTS rate and duration if needed. 3890 */ 3891 ctsduration = 0; 3892 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3893 /* 3894 * CTS transmit rate is derived from the transmit rate 3895 * by looking in the h/w rate table. We must also factor 3896 * in whether or not a short preamble is to be used. 3897 */ 3898 /* NB: cix is set above where RTS/CTS is enabled */ 3899 KASSERT(cix != 0xff, ("cix not setup")); 3900 ctsrate = rt->info[cix].rateCode; 3901 /* 3902 * Compute the transmit duration based on the frame 3903 * size and the size of an ACK frame. We call into the 3904 * HAL to do the computation since it depends on the 3905 * characteristics of the actual PHY being used. 3906 * 3907 * NB: CTS is assumed the same size as an ACK so we can 3908 * use the precalculated ACK durations. 3909 */ 3910 if (shortPreamble) { 3911 ctsrate |= rt->info[cix].shortPreamble; 3912 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3913 ctsduration += rt->info[cix].spAckDuration; 3914 ctsduration += ath_hal_computetxtime(ah, 3915 rt, pktlen, rix, AH_TRUE); 3916 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3917 ctsduration += rt->info[rix].spAckDuration; 3918 } else { 3919 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3920 ctsduration += rt->info[cix].lpAckDuration; 3921 ctsduration += ath_hal_computetxtime(ah, 3922 rt, pktlen, rix, AH_FALSE); 3923 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3924 ctsduration += rt->info[rix].lpAckDuration; 3925 } 3926 /* 3927 * Must disable multi-rate retry when using RTS/CTS. 3928 */ 3929 ismrr = 0; 3930 try0 = ATH_TXMGTTRY; /* XXX */ 3931 } else 3932 ctsrate = 0; 3933 3934 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3935 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3936 sc->sc_hwmap[txrate].ieeerate, -1); 3937 bpf_mtap3(ic->ic_rawbpf, m0); 3938 if (sc->sc_drvbpf) { 3939 u_int64_t tsf = ath_hal_gettsf64(ah); 3940 3941 sc->sc_tx_th.wt_tsf = htole64(tsf); 3942 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3943 if (iswep) 3944 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3945 if (isfrag) 3946 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3947 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3948 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3949 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3950 3951 bpf_mtap2(sc->sc_drvbpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3952 } 3953 3954 /* 3955 * Determine if a tx interrupt should be generated for 3956 * this descriptor. We take a tx interrupt to reap 3957 * descriptors when the h/w hits an EOL condition or 3958 * when the descriptor is specifically marked to generate 3959 * an interrupt. We periodically mark descriptors in this 3960 * way to insure timely replenishing of the supply needed 3961 * for sending frames. Defering interrupts reduces system 3962 * load and potentially allows more concurrent work to be 3963 * done but if done to aggressively can cause senders to 3964 * backup. 3965 * 3966 * NB: use >= to deal with sc_txintrperiod changing 3967 * dynamically through sysctl. 3968 */ 3969 if (flags & HAL_TXDESC_INTREQ) { 3970 txq->axq_intrcnt = 0; 3971 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3972 flags |= HAL_TXDESC_INTREQ; 3973 txq->axq_intrcnt = 0; 3974 } 3975 3976 /* 3977 * Formulate first tx descriptor with tx controls. 3978 */ 3979 /* XXX check return value? */ 3980 ath_hal_setuptxdesc(ah, ds 3981 , pktlen /* packet length */ 3982 , hdrlen /* header length */ 3983 , atype /* Atheros packet type */ 3984 , ni->ni_txpower /* txpower */ 3985 , txrate, try0 /* series 0 rate/tries */ 3986 , keyix /* key cache index */ 3987 , sc->sc_txantenna /* antenna mode */ 3988 , flags /* flags */ 3989 , ctsrate /* rts/cts rate */ 3990 , ctsduration /* rts/cts duration */ 3991 ); 3992 bf->bf_flags = flags; 3993 /* 3994 * Setup the multi-rate retry state only when we're 3995 * going to use it. This assumes ath_hal_setuptxdesc 3996 * initializes the descriptors (so we don't have to) 3997 * when the hardware supports multi-rate retry and 3998 * we don't use it. 3999 */ 4000 if (ismrr) 4001 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4002 4003 /* 4004 * Fillin the remainder of the descriptor info. 4005 */ 4006 ds0 = ds; 4007 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4008 ds->ds_data = bf->bf_segs[i].ds_addr; 4009 if (i == bf->bf_nseg - 1) 4010 ds->ds_link = 0; 4011 else 4012 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4013 ath_hal_filltxdesc(ah, ds 4014 , bf->bf_segs[i].ds_len /* segment length */ 4015 , i == 0 /* first segment */ 4016 , i == bf->bf_nseg - 1 /* last segment */ 4017 , ds0 /* first descriptor */ 4018 ); 4019 4020 /* NB: The desc swap function becomes void, 4021 * if descriptor swapping is not enabled 4022 */ 4023 ath_desc_swap(ds); 4024 4025 DPRINTF(sc, ATH_DEBUG_XMIT, 4026 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4027 __func__, i, ds->ds_link, ds->ds_data, 4028 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4029 } 4030 /* 4031 * Insert the frame on the outbound list and 4032 * pass it on to the hardware. 4033 */ 4034 ATH_TXQ_LOCK(txq); 4035 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4036 if (txq->axq_link == NULL) { 4037 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4038 DPRINTF(sc, ATH_DEBUG_XMIT, 4039 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 4040 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 4041 txq->axq_depth); 4042 } else { 4043 *txq->axq_link = HTOAH32(bf->bf_daddr); 4044 DPRINTF(sc, ATH_DEBUG_XMIT, 4045 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 4046 __func__, txq->axq_qnum, txq->axq_link, 4047 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4048 } 4049 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4050 /* 4051 * The CAB queue is started from the SWBA handler since 4052 * frames only go out on DTIM and to avoid possible races. 4053 */ 4054 if (txq != sc->sc_cabq) 4055 ath_hal_txstart(ah, txq->axq_qnum); 4056 ATH_TXQ_UNLOCK(txq); 4057 4058 return 0; 4059 } 4060 4061 /* 4062 * Process completed xmit descriptors from the specified queue. 4063 */ 4064 static int 4065 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4066 { 4067 struct ath_hal *ah = sc->sc_ah; 4068 struct ieee80211com *ic = &sc->sc_ic; 4069 struct ath_buf *bf; 4070 struct ath_desc *ds, *ds0; 4071 struct ieee80211_node *ni; 4072 struct ath_node *an; 4073 int sr, lr, pri, nacked; 4074 HAL_STATUS status; 4075 4076 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4077 __func__, txq->axq_qnum, 4078 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4079 txq->axq_link); 4080 nacked = 0; 4081 for (;;) { 4082 ATH_TXQ_LOCK(txq); 4083 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4084 bf = STAILQ_FIRST(&txq->axq_q); 4085 if (bf == NULL) { 4086 txq->axq_link = NULL; 4087 ATH_TXQ_UNLOCK(txq); 4088 break; 4089 } 4090 ds0 = &bf->bf_desc[0]; 4091 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4092 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4093 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4094 ath_printtxbuf(bf, status == HAL_OK); 4095 if (status == HAL_EINPROGRESS) { 4096 ATH_TXQ_UNLOCK(txq); 4097 break; 4098 } 4099 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4100 ATH_TXQ_UNLOCK(txq); 4101 4102 ni = bf->bf_node; 4103 if (ni != NULL) { 4104 an = ATH_NODE(ni); 4105 if (ds->ds_txstat.ts_status == 0) { 4106 u_int8_t txant = ds->ds_txstat.ts_antenna; 4107 sc->sc_stats.ast_ant_tx[txant]++; 4108 sc->sc_ant_tx[txant]++; 4109 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4110 sc->sc_stats.ast_tx_altrate++; 4111 sc->sc_stats.ast_tx_rssi = 4112 ds->ds_txstat.ts_rssi; 4113 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4114 ds->ds_txstat.ts_rssi); 4115 pri = M_WME_GETAC(bf->bf_m); 4116 if (pri >= WME_AC_VO) 4117 ic->ic_wme.wme_hipri_traffic++; 4118 ni->ni_inact = ni->ni_inact_reload; 4119 } else { 4120 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4121 sc->sc_stats.ast_tx_xretries++; 4122 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4123 sc->sc_stats.ast_tx_fifoerr++; 4124 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4125 sc->sc_stats.ast_tx_filtered++; 4126 } 4127 sr = ds->ds_txstat.ts_shortretry; 4128 lr = ds->ds_txstat.ts_longretry; 4129 sc->sc_stats.ast_tx_shortretry += sr; 4130 sc->sc_stats.ast_tx_longretry += lr; 4131 /* 4132 * Hand the descriptor to the rate control algorithm. 4133 */ 4134 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4135 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4136 /* 4137 * If frame was ack'd update the last rx time 4138 * used to workaround phantom bmiss interrupts. 4139 */ 4140 if (ds->ds_txstat.ts_status == 0) 4141 nacked++; 4142 ath_rate_tx_complete(sc, an, ds, ds0); 4143 } 4144 /* 4145 * Reclaim reference to node. 4146 * 4147 * NB: the node may be reclaimed here if, for example 4148 * this is a DEAUTH message that was sent and the 4149 * node was timed out due to inactivity. 4150 */ 4151 ieee80211_free_node(ni); 4152 } 4153 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4154 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4155 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4156 m_freem(bf->bf_m); 4157 bf->bf_m = NULL; 4158 bf->bf_node = NULL; 4159 4160 ATH_TXBUF_LOCK(sc); 4161 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4162 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4163 ATH_TXBUF_UNLOCK(sc); 4164 } 4165 return nacked; 4166 } 4167 4168 static inline int 4169 txqactive(struct ath_hal *ah, int qnum) 4170 { 4171 u_int32_t txqs = 1<<qnum; 4172 ath_hal_gettxintrtxqs(ah, &txqs); 4173 return (txqs & (1<<qnum)); 4174 } 4175 4176 /* 4177 * Deferred processing of transmit interrupt; special-cased 4178 * for a single hardware transmit queue (e.g. 5210 and 5211). 4179 */ 4180 static void 4181 ath_tx_proc_q0(void *arg, int npending) 4182 { 4183 struct ath_softc *sc = arg; 4184 struct ifnet *ifp = &sc->sc_if; 4185 4186 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4187 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4188 } 4189 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4190 ath_tx_processq(sc, sc->sc_cabq); 4191 4192 if (sc->sc_softled) 4193 ath_led_event(sc, ATH_LED_TX); 4194 4195 ath_start(ifp); 4196 } 4197 4198 /* 4199 * Deferred processing of transmit interrupt; special-cased 4200 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4201 */ 4202 static void 4203 ath_tx_proc_q0123(void *arg, int npending) 4204 { 4205 struct ath_softc *sc = arg; 4206 struct ifnet *ifp = &sc->sc_if; 4207 int nacked; 4208 4209 /* 4210 * Process each active queue. 4211 */ 4212 nacked = 0; 4213 if (txqactive(sc->sc_ah, 0)) 4214 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4215 if (txqactive(sc->sc_ah, 1)) 4216 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4217 if (txqactive(sc->sc_ah, 2)) 4218 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4219 if (txqactive(sc->sc_ah, 3)) 4220 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4221 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4222 ath_tx_processq(sc, sc->sc_cabq); 4223 if (nacked) { 4224 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4225 } 4226 4227 if (sc->sc_softled) 4228 ath_led_event(sc, ATH_LED_TX); 4229 4230 ath_start(ifp); 4231 } 4232 4233 /* 4234 * Deferred processing of transmit interrupt. 4235 */ 4236 static void 4237 ath_tx_proc(void *arg, int npending) 4238 { 4239 struct ath_softc *sc = arg; 4240 struct ifnet *ifp = &sc->sc_if; 4241 int i, nacked; 4242 4243 /* 4244 * Process each active queue. 4245 */ 4246 nacked = 0; 4247 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4248 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4249 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4250 if (nacked) { 4251 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4252 } 4253 4254 if (sc->sc_softled) 4255 ath_led_event(sc, ATH_LED_TX); 4256 4257 ath_start(ifp); 4258 } 4259 4260 static void 4261 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4262 { 4263 struct ath_hal *ah = sc->sc_ah; 4264 struct ieee80211_node *ni; 4265 struct ath_buf *bf; 4266 struct ath_desc *ds; 4267 4268 /* 4269 * NB: this assumes output has been stopped and 4270 * we do not need to block ath_tx_tasklet 4271 */ 4272 for (;;) { 4273 ATH_TXQ_LOCK(txq); 4274 bf = STAILQ_FIRST(&txq->axq_q); 4275 if (bf == NULL) { 4276 txq->axq_link = NULL; 4277 ATH_TXQ_UNLOCK(txq); 4278 break; 4279 } 4280 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4281 ATH_TXQ_UNLOCK(txq); 4282 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4283 if (sc->sc_debug & ATH_DEBUG_RESET) 4284 ath_printtxbuf(bf, 4285 ath_hal_txprocdesc(ah, bf->bf_desc, 4286 &ds->ds_txstat) == HAL_OK); 4287 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4288 m_freem(bf->bf_m); 4289 bf->bf_m = NULL; 4290 ni = bf->bf_node; 4291 bf->bf_node = NULL; 4292 if (ni != NULL) { 4293 /* 4294 * Reclaim node reference. 4295 */ 4296 ieee80211_free_node(ni); 4297 } 4298 ATH_TXBUF_LOCK(sc); 4299 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4300 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4301 ATH_TXBUF_UNLOCK(sc); 4302 } 4303 } 4304 4305 static void 4306 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4307 { 4308 struct ath_hal *ah = sc->sc_ah; 4309 4310 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4311 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4312 __func__, txq->axq_qnum, 4313 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4314 txq->axq_link); 4315 } 4316 4317 /* 4318 * Drain the transmit queues and reclaim resources. 4319 */ 4320 static void 4321 ath_draintxq(struct ath_softc *sc) 4322 { 4323 struct ath_hal *ah = sc->sc_ah; 4324 int i; 4325 4326 /* XXX return value */ 4327 if (device_is_active(sc->sc_dev)) { 4328 /* don't touch the hardware if marked invalid */ 4329 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4330 DPRINTF(sc, ATH_DEBUG_RESET, 4331 "%s: beacon queue %p\n", __func__, 4332 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4333 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4334 if (ATH_TXQ_SETUP(sc, i)) 4335 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4336 } 4337 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4338 if (ATH_TXQ_SETUP(sc, i)) 4339 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4340 } 4341 4342 /* 4343 * Disable the receive h/w in preparation for a reset. 4344 */ 4345 static void 4346 ath_stoprecv(struct ath_softc *sc) 4347 { 4348 #define PA2DESC(_sc, _pa) \ 4349 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4350 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4351 struct ath_hal *ah = sc->sc_ah; 4352 u_int64_t tsf; 4353 4354 ath_hal_stoppcurecv(ah); /* disable PCU */ 4355 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4356 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4357 DELAY(3000); /* 3ms is long enough for 1 frame */ 4358 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4359 struct ath_buf *bf; 4360 4361 printf("%s: rx queue %p, link %p\n", __func__, 4362 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4363 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4364 struct ath_desc *ds = bf->bf_desc; 4365 tsf = ath_hal_gettsf64(sc->sc_ah); 4366 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4367 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4368 &ds->ds_rxstat); 4369 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4370 ath_printrxbuf(bf, status == HAL_OK); 4371 } 4372 } 4373 sc->sc_rxlink = NULL; /* just in case */ 4374 #undef PA2DESC 4375 } 4376 4377 /* 4378 * Enable the receive h/w following a reset. 4379 */ 4380 static int 4381 ath_startrecv(struct ath_softc *sc) 4382 { 4383 struct ath_hal *ah = sc->sc_ah; 4384 struct ath_buf *bf; 4385 4386 sc->sc_rxlink = NULL; 4387 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4388 int error = ath_rxbuf_init(sc, bf); 4389 if (error != 0) { 4390 DPRINTF(sc, ATH_DEBUG_RECV, 4391 "%s: ath_rxbuf_init failed %d\n", 4392 __func__, error); 4393 return error; 4394 } 4395 } 4396 4397 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4398 ath_hal_putrxbuf(ah, bf->bf_daddr); 4399 ath_hal_rxena(ah); /* enable recv descriptors */ 4400 ath_mode_init(sc); /* set filters, etc. */ 4401 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4402 return 0; 4403 } 4404 4405 /* 4406 * Update internal state after a channel change. 4407 */ 4408 static void 4409 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4410 { 4411 struct ieee80211com *ic = &sc->sc_ic; 4412 enum ieee80211_phymode mode; 4413 u_int16_t flags; 4414 4415 /* 4416 * Change channels and update the h/w rate map 4417 * if we're switching; e.g. 11a to 11b/g. 4418 */ 4419 mode = ieee80211_chan2mode(ic, chan); 4420 if (mode != sc->sc_curmode) 4421 ath_setcurmode(sc, mode); 4422 /* 4423 * Update BPF state. NB: ethereal et. al. don't handle 4424 * merged flags well so pick a unique mode for their use. 4425 */ 4426 if (IEEE80211_IS_CHAN_A(chan)) 4427 flags = IEEE80211_CHAN_A; 4428 /* XXX 11g schizophrenia */ 4429 else if (IEEE80211_IS_CHAN_G(chan) || 4430 IEEE80211_IS_CHAN_PUREG(chan)) 4431 flags = IEEE80211_CHAN_G; 4432 else 4433 flags = IEEE80211_CHAN_B; 4434 if (IEEE80211_IS_CHAN_T(chan)) 4435 flags |= IEEE80211_CHAN_TURBO; 4436 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4437 htole16(chan->ic_freq); 4438 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4439 htole16(flags); 4440 } 4441 4442 #if 0 4443 /* 4444 * Poll for a channel clear indication; this is required 4445 * for channels requiring DFS and not previously visited 4446 * and/or with a recent radar detection. 4447 */ 4448 static void 4449 ath_dfswait(void *arg) 4450 { 4451 struct ath_softc *sc = arg; 4452 struct ath_hal *ah = sc->sc_ah; 4453 HAL_CHANNEL hchan; 4454 4455 ath_hal_radar_wait(ah, &hchan); 4456 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4457 if_printf(&sc->sc_if, 4458 "channel %u/0x%x/0x%x has interference\n", 4459 hchan.channel, hchan.channelFlags, hchan.privFlags); 4460 return; 4461 } 4462 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4463 /* XXX should not happen */ 4464 return; 4465 } 4466 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4467 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4468 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4469 if_printf(&sc->sc_if, 4470 "channel %u/0x%x/0x%x marked clear\n", 4471 hchan.channel, hchan.channelFlags, hchan.privFlags); 4472 } else 4473 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4474 } 4475 #endif 4476 4477 /* 4478 * Set/change channels. If the channel is really being changed, 4479 * it's done by reseting the chip. To accomplish this we must 4480 * first cleanup any pending DMA, then restart stuff after a la 4481 * ath_init. 4482 */ 4483 static int 4484 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4485 { 4486 struct ath_hal *ah = sc->sc_ah; 4487 struct ieee80211com *ic = &sc->sc_ic; 4488 HAL_CHANNEL hchan; 4489 4490 /* 4491 * Convert to a HAL channel description with 4492 * the flags constrained to reflect the current 4493 * operating mode. 4494 */ 4495 hchan.channel = chan->ic_freq; 4496 hchan.channelFlags = ath_chan2flags(ic, chan); 4497 4498 DPRINTF(sc, ATH_DEBUG_RESET, 4499 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4500 __func__, 4501 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4502 sc->sc_curchan.channelFlags), 4503 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4504 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4505 hchan.channel, hchan.channelFlags); 4506 if (hchan.channel != sc->sc_curchan.channel || 4507 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4508 HAL_STATUS status; 4509 4510 /* 4511 * To switch channels clear any pending DMA operations; 4512 * wait long enough for the RX fifo to drain, reset the 4513 * hardware at the new frequency, and then re-enable 4514 * the relevant bits of the h/w. 4515 */ 4516 ath_hal_intrset(ah, 0); /* disable interrupts */ 4517 ath_draintxq(sc); /* clear pending tx frames */ 4518 ath_stoprecv(sc); /* turn off frame recv */ 4519 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4520 if_printf(ic->ic_ifp, "%s: unable to reset " 4521 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4522 __func__, ieee80211_chan2ieee(ic, chan), 4523 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4524 return EIO; 4525 } 4526 sc->sc_curchan = hchan; 4527 ath_update_txpow(sc); /* update tx power state */ 4528 ath_restore_diversity(sc); 4529 sc->sc_calinterval = 1; 4530 sc->sc_caltries = 0; 4531 4532 /* 4533 * Re-enable rx framework. 4534 */ 4535 if (ath_startrecv(sc) != 0) { 4536 if_printf(&sc->sc_if, 4537 "%s: unable to restart recv logic\n", __func__); 4538 return EIO; 4539 } 4540 4541 /* 4542 * Change channels and update the h/w rate map 4543 * if we're switching; e.g. 11a to 11b/g. 4544 */ 4545 ic->ic_ibss_chan = chan; 4546 ath_chan_change(sc, chan); 4547 4548 #if 0 4549 /* 4550 * Handle DFS required waiting period to determine 4551 * if channel is clear of radar traffic. 4552 */ 4553 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4554 #define DFS_AND_NOT_CLEAR(_c) \ 4555 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4556 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4557 if_printf(&sc->sc_if, 4558 "wait for DFS clear channel signal\n"); 4559 /* XXX stop sndq */ 4560 sc->sc_if.if_flags |= IFF_OACTIVE; 4561 callout_reset(&sc->sc_dfs_ch, 4562 2 * hz, ath_dfswait, sc); 4563 } else 4564 callout_stop(&sc->sc_dfs_ch); 4565 #undef DFS_NOT_CLEAR 4566 } 4567 #endif 4568 4569 /* 4570 * Re-enable interrupts. 4571 */ 4572 ath_hal_intrset(ah, sc->sc_imask); 4573 } 4574 return 0; 4575 } 4576 4577 static void 4578 ath_next_scan(void *arg) 4579 { 4580 struct ath_softc *sc = arg; 4581 struct ieee80211com *ic = &sc->sc_ic; 4582 int s; 4583 4584 /* don't call ath_start w/o network interrupts blocked */ 4585 s = splnet(); 4586 4587 if (ic->ic_state == IEEE80211_S_SCAN) 4588 ieee80211_next_scan(ic); 4589 splx(s); 4590 } 4591 4592 /* 4593 * Periodically recalibrate the PHY to account 4594 * for temperature/environment changes. 4595 */ 4596 static void 4597 ath_calibrate(void *arg) 4598 { 4599 struct ath_softc *sc = arg; 4600 struct ath_hal *ah = sc->sc_ah; 4601 HAL_BOOL iqCalDone; 4602 int s; 4603 4604 sc->sc_stats.ast_per_cal++; 4605 4606 s = splnet(); 4607 4608 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4609 /* 4610 * Rfgain is out of bounds, reset the chip 4611 * to load new gain values. 4612 */ 4613 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4614 "%s: rfgain change\n", __func__); 4615 sc->sc_stats.ast_per_rfgain++; 4616 ath_reset(&sc->sc_if); 4617 } 4618 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4619 DPRINTF(sc, ATH_DEBUG_ANY, 4620 "%s: calibration of channel %u failed\n", 4621 __func__, sc->sc_curchan.channel); 4622 sc->sc_stats.ast_per_calfail++; 4623 } 4624 /* 4625 * Calibrate noise floor data again in case of change. 4626 */ 4627 ath_hal_process_noisefloor(ah); 4628 /* 4629 * Poll more frequently when the IQ calibration is in 4630 * progress to speedup loading the final settings. 4631 * We temper this aggressive polling with an exponential 4632 * back off after 4 tries up to ath_calinterval. 4633 */ 4634 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4635 sc->sc_caltries = 0; 4636 sc->sc_calinterval = ath_calinterval; 4637 } else if (sc->sc_caltries > 4) { 4638 sc->sc_caltries = 0; 4639 sc->sc_calinterval <<= 1; 4640 if (sc->sc_calinterval > ath_calinterval) 4641 sc->sc_calinterval = ath_calinterval; 4642 } 4643 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4644 ("bad calibration interval %u", sc->sc_calinterval)); 4645 4646 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4647 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4648 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4649 sc->sc_caltries++; 4650 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4651 ath_calibrate, sc); 4652 splx(s); 4653 } 4654 4655 static int 4656 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4657 { 4658 struct ifnet *ifp = ic->ic_ifp; 4659 struct ath_softc *sc = ifp->if_softc; 4660 struct ath_hal *ah = sc->sc_ah; 4661 struct ieee80211_node *ni; 4662 int i, error; 4663 const u_int8_t *bssid; 4664 u_int32_t rfilt; 4665 static const HAL_LED_STATE leds[] = { 4666 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4667 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4668 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4669 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4670 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4671 }; 4672 4673 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4674 ieee80211_state_name[ic->ic_state], 4675 ieee80211_state_name[nstate]); 4676 4677 callout_stop(&sc->sc_scan_ch); 4678 callout_stop(&sc->sc_cal_ch); 4679 #if 0 4680 callout_stop(&sc->sc_dfs_ch); 4681 #endif 4682 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4683 4684 if (nstate == IEEE80211_S_INIT) { 4685 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4686 /* 4687 * NB: disable interrupts so we don't rx frames. 4688 */ 4689 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4690 /* 4691 * Notify the rate control algorithm. 4692 */ 4693 ath_rate_newstate(sc, nstate); 4694 goto done; 4695 } 4696 ni = ic->ic_bss; 4697 error = ath_chan_set(sc, ic->ic_curchan); 4698 if (error != 0) 4699 goto bad; 4700 rfilt = ath_calcrxfilter(sc, nstate); 4701 if (nstate == IEEE80211_S_SCAN) 4702 bssid = ifp->if_broadcastaddr; 4703 else 4704 bssid = ni->ni_bssid; 4705 ath_hal_setrxfilter(ah, rfilt); 4706 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4707 __func__, rfilt, ether_sprintf(bssid)); 4708 4709 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4710 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4711 else 4712 ath_hal_setassocid(ah, bssid, 0); 4713 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4714 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4715 if (ath_hal_keyisvalid(ah, i)) 4716 ath_hal_keysetmac(ah, i, bssid); 4717 } 4718 4719 /* 4720 * Notify the rate control algorithm so rates 4721 * are setup should ath_beacon_alloc be called. 4722 */ 4723 ath_rate_newstate(sc, nstate); 4724 4725 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4726 /* nothing to do */; 4727 } else if (nstate == IEEE80211_S_RUN) { 4728 DPRINTF(sc, ATH_DEBUG_STATE, 4729 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4730 "capinfo=0x%04x chan=%d\n" 4731 , __func__ 4732 , ic->ic_flags 4733 , ni->ni_intval 4734 , ether_sprintf(ni->ni_bssid) 4735 , ni->ni_capinfo 4736 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4737 4738 switch (ic->ic_opmode) { 4739 case IEEE80211_M_HOSTAP: 4740 case IEEE80211_M_IBSS: 4741 /* 4742 * Allocate and setup the beacon frame. 4743 * 4744 * Stop any previous beacon DMA. This may be 4745 * necessary, for example, when an ibss merge 4746 * causes reconfiguration; there will be a state 4747 * transition from RUN->RUN that means we may 4748 * be called with beacon transmission active. 4749 */ 4750 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4751 ath_beacon_free(sc); 4752 error = ath_beacon_alloc(sc, ni); 4753 if (error != 0) 4754 goto bad; 4755 /* 4756 * If joining an adhoc network defer beacon timer 4757 * configuration to the next beacon frame so we 4758 * have a current TSF to use. Otherwise we're 4759 * starting an ibss/bss so there's no need to delay. 4760 */ 4761 if (ic->ic_opmode == IEEE80211_M_IBSS && 4762 ic->ic_bss->ni_tstamp.tsf != 0) 4763 sc->sc_syncbeacon = 1; 4764 else 4765 ath_beacon_config(sc); 4766 break; 4767 case IEEE80211_M_STA: 4768 /* 4769 * Allocate a key cache slot to the station. 4770 */ 4771 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4772 sc->sc_hasclrkey && 4773 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4774 ath_setup_stationkey(ni); 4775 /* 4776 * Defer beacon timer configuration to the next 4777 * beacon frame so we have a current TSF to use 4778 * (any TSF collected when scanning is likely old). 4779 */ 4780 sc->sc_syncbeacon = 1; 4781 break; 4782 default: 4783 break; 4784 } 4785 /* 4786 * Let the hal process statistics collected during a 4787 * scan so it can provide calibrated noise floor data. 4788 */ 4789 ath_hal_process_noisefloor(ah); 4790 /* 4791 * Reset rssi stats; maybe not the best place... 4792 */ 4793 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4794 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4795 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4796 } else { 4797 ath_hal_intrset(ah, 4798 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4799 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4800 } 4801 done: 4802 /* 4803 * Invoke the parent method to complete the work. 4804 */ 4805 error = sc->sc_newstate(ic, nstate, arg); 4806 /* 4807 * Finally, start any timers. 4808 */ 4809 if (nstate == IEEE80211_S_RUN) { 4810 /* start periodic recalibration timer */ 4811 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4812 ath_calibrate, sc); 4813 } else if (nstate == IEEE80211_S_SCAN) { 4814 /* start ap/neighbor scan timer */ 4815 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4816 ath_next_scan, sc); 4817 } 4818 bad: 4819 return error; 4820 } 4821 4822 /* 4823 * Allocate a key cache slot to the station so we can 4824 * setup a mapping from key index to node. The key cache 4825 * slot is needed for managing antenna state and for 4826 * compression when stations do not use crypto. We do 4827 * it uniliaterally here; if crypto is employed this slot 4828 * will be reassigned. 4829 */ 4830 static void 4831 ath_setup_stationkey(struct ieee80211_node *ni) 4832 { 4833 struct ieee80211com *ic = ni->ni_ic; 4834 struct ath_softc *sc = ic->ic_ifp->if_softc; 4835 ieee80211_keyix keyix, rxkeyix; 4836 4837 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4838 /* 4839 * Key cache is full; we'll fall back to doing 4840 * the more expensive lookup in software. Note 4841 * this also means no h/w compression. 4842 */ 4843 /* XXX msg+statistic */ 4844 } else { 4845 /* XXX locking? */ 4846 ni->ni_ucastkey.wk_keyix = keyix; 4847 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4848 /* NB: this will create a pass-thru key entry */ 4849 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4850 } 4851 } 4852 4853 /* 4854 * Setup driver-specific state for a newly associated node. 4855 * Note that we're called also on a re-associate, the isnew 4856 * param tells us if this is the first time or not. 4857 */ 4858 static void 4859 ath_newassoc(struct ieee80211_node *ni, int isnew) 4860 { 4861 struct ieee80211com *ic = ni->ni_ic; 4862 struct ath_softc *sc = ic->ic_ifp->if_softc; 4863 4864 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4865 if (isnew && 4866 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4867 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4868 ("new assoc with a unicast key already setup (keyix %u)", 4869 ni->ni_ucastkey.wk_keyix)); 4870 ath_setup_stationkey(ni); 4871 } 4872 } 4873 4874 static int 4875 ath_getchannels(struct ath_softc *sc, u_int cc, 4876 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4877 { 4878 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4879 struct ieee80211com *ic = &sc->sc_ic; 4880 struct ifnet *ifp = &sc->sc_if; 4881 struct ath_hal *ah = sc->sc_ah; 4882 HAL_CHANNEL *chans; 4883 int i, ix, nchan; 4884 4885 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4886 M_TEMP, M_NOWAIT); 4887 if (chans == NULL) { 4888 if_printf(ifp, "unable to allocate channel table\n"); 4889 return ENOMEM; 4890 } 4891 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4892 NULL, 0, NULL, 4893 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4894 u_int32_t rd; 4895 4896 (void)ath_hal_getregdomain(ah, &rd); 4897 if_printf(ifp, "unable to collect channel list from hal; " 4898 "regdomain likely %u country code %u\n", rd, cc); 4899 free(chans, M_TEMP); 4900 return EINVAL; 4901 } 4902 4903 /* 4904 * Convert HAL channels to ieee80211 ones and insert 4905 * them in the table according to their channel number. 4906 */ 4907 for (i = 0; i < nchan; i++) { 4908 HAL_CHANNEL *c = &chans[i]; 4909 u_int16_t flags; 4910 4911 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4912 if (ix > IEEE80211_CHAN_MAX) { 4913 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4914 ix, c->channel, c->channelFlags); 4915 continue; 4916 } 4917 if (ix < 0) { 4918 /* XXX can't handle stuff <2400 right now */ 4919 if (bootverbose) 4920 if_printf(ifp, "hal channel %d (%u/%x) " 4921 "cannot be handled; ignored\n", 4922 ix, c->channel, c->channelFlags); 4923 continue; 4924 } 4925 /* 4926 * Calculate net80211 flags; most are compatible 4927 * but some need massaging. Note the static turbo 4928 * conversion can be removed once net80211 is updated 4929 * to understand static vs. dynamic turbo. 4930 */ 4931 flags = c->channelFlags & COMPAT; 4932 if (c->channelFlags & CHANNEL_STURBO) 4933 flags |= IEEE80211_CHAN_TURBO; 4934 if (ic->ic_channels[ix].ic_freq == 0) { 4935 ic->ic_channels[ix].ic_freq = c->channel; 4936 ic->ic_channels[ix].ic_flags = flags; 4937 } else { 4938 /* channels overlap; e.g. 11g and 11b */ 4939 ic->ic_channels[ix].ic_flags |= flags; 4940 } 4941 } 4942 free(chans, M_TEMP); 4943 return 0; 4944 #undef COMPAT 4945 } 4946 4947 static void 4948 ath_led_done(void *arg) 4949 { 4950 struct ath_softc *sc = arg; 4951 4952 sc->sc_blinking = 0; 4953 } 4954 4955 /* 4956 * Turn the LED off: flip the pin and then set a timer so no 4957 * update will happen for the specified duration. 4958 */ 4959 static void 4960 ath_led_off(void *arg) 4961 { 4962 struct ath_softc *sc = arg; 4963 4964 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4965 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4966 } 4967 4968 /* 4969 * Blink the LED according to the specified on/off times. 4970 */ 4971 static void 4972 ath_led_blink(struct ath_softc *sc, int on, int off) 4973 { 4974 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4975 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4976 sc->sc_blinking = 1; 4977 sc->sc_ledoff = off; 4978 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4979 } 4980 4981 static void 4982 ath_led_event(struct ath_softc *sc, int event) 4983 { 4984 4985 sc->sc_ledevent = ticks; /* time of last event */ 4986 if (sc->sc_blinking) /* don't interrupt active blink */ 4987 return; 4988 switch (event) { 4989 case ATH_LED_POLL: 4990 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4991 sc->sc_hwmap[0].ledoff); 4992 break; 4993 case ATH_LED_TX: 4994 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4995 sc->sc_hwmap[sc->sc_txrate].ledoff); 4996 break; 4997 case ATH_LED_RX: 4998 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4999 sc->sc_hwmap[sc->sc_rxrate].ledoff); 5000 break; 5001 } 5002 } 5003 5004 static void 5005 ath_update_txpow(struct ath_softc *sc) 5006 { 5007 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 5008 struct ieee80211com *ic = &sc->sc_ic; 5009 struct ath_hal *ah = sc->sc_ah; 5010 u_int32_t txpow; 5011 5012 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 5013 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 5014 /* read back in case value is clamped */ 5015 (void)ath_hal_gettxpowlimit(ah, &txpow); 5016 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 5017 } 5018 /* 5019 * Fetch max tx power level for status requests. 5020 */ 5021 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 5022 ic->ic_bss->ni_txpower = txpow; 5023 } 5024 5025 static void 5026 rate_setup(struct ath_softc *sc, 5027 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 5028 { 5029 int i, maxrates; 5030 5031 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 5032 DPRINTF(sc, ATH_DEBUG_ANY, 5033 "%s: rate table too small (%u > %u)\n", 5034 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 5035 maxrates = IEEE80211_RATE_MAXSIZE; 5036 } else 5037 maxrates = rt->rateCount; 5038 for (i = 0; i < maxrates; i++) 5039 rs->rs_rates[i] = rt->info[i].dot11Rate; 5040 rs->rs_nrates = maxrates; 5041 } 5042 5043 static int 5044 ath_rate_setup(struct ath_softc *sc, u_int mode) 5045 { 5046 struct ath_hal *ah = sc->sc_ah; 5047 struct ieee80211com *ic = &sc->sc_ic; 5048 const HAL_RATE_TABLE *rt; 5049 5050 switch (mode) { 5051 case IEEE80211_MODE_11A: 5052 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5053 break; 5054 case IEEE80211_MODE_11B: 5055 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5056 break; 5057 case IEEE80211_MODE_11G: 5058 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5059 break; 5060 case IEEE80211_MODE_TURBO_A: 5061 /* XXX until static/dynamic turbo is fixed */ 5062 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5063 break; 5064 case IEEE80211_MODE_TURBO_G: 5065 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5066 break; 5067 default: 5068 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5069 __func__, mode); 5070 return 0; 5071 } 5072 sc->sc_rates[mode] = rt; 5073 if (rt != NULL) { 5074 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5075 return 1; 5076 } else 5077 return 0; 5078 } 5079 5080 static void 5081 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5082 { 5083 #define N(a) (sizeof(a)/sizeof(a[0])) 5084 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5085 static const struct { 5086 u_int rate; /* tx/rx 802.11 rate */ 5087 u_int16_t timeOn; /* LED on time (ms) */ 5088 u_int16_t timeOff; /* LED off time (ms) */ 5089 } blinkrates[] = { 5090 { 108, 40, 10 }, 5091 { 96, 44, 11 }, 5092 { 72, 50, 13 }, 5093 { 48, 57, 14 }, 5094 { 36, 67, 16 }, 5095 { 24, 80, 20 }, 5096 { 22, 100, 25 }, 5097 { 18, 133, 34 }, 5098 { 12, 160, 40 }, 5099 { 10, 200, 50 }, 5100 { 6, 240, 58 }, 5101 { 4, 267, 66 }, 5102 { 2, 400, 100 }, 5103 { 0, 500, 130 }, 5104 }; 5105 const HAL_RATE_TABLE *rt; 5106 int i, j; 5107 5108 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5109 rt = sc->sc_rates[mode]; 5110 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5111 for (i = 0; i < rt->rateCount; i++) 5112 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5113 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5114 for (i = 0; i < 32; i++) { 5115 u_int8_t ix = rt->rateCodeToIndex[i]; 5116 if (ix == 0xff) { 5117 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5118 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5119 continue; 5120 } 5121 sc->sc_hwmap[i].ieeerate = 5122 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5123 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5124 if (rt->info[ix].shortPreamble || 5125 rt->info[ix].phy == IEEE80211_T_OFDM) 5126 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5127 /* NB: receive frames include FCS */ 5128 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5129 IEEE80211_RADIOTAP_F_FCS; 5130 /* setup blink rate table to avoid per-packet lookup */ 5131 for (j = 0; j < N(blinkrates)-1; j++) 5132 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5133 break; 5134 /* NB: this uses the last entry if the rate isn't found */ 5135 /* XXX beware of overlow */ 5136 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5137 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5138 } 5139 sc->sc_currates = rt; 5140 sc->sc_curmode = mode; 5141 /* 5142 * All protection frames are transmited at 2Mb/s for 5143 * 11g, otherwise at 1Mb/s. 5144 */ 5145 if (mode == IEEE80211_MODE_11G) 5146 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5147 else 5148 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5149 /* rate index used to send management frames */ 5150 sc->sc_minrateix = 0; 5151 /* 5152 * Setup multicast rate state. 5153 */ 5154 /* XXX layering violation */ 5155 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5156 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5157 /* NB: caller is responsible for reseting rate control state */ 5158 #undef N 5159 } 5160 5161 #ifdef AR_DEBUG 5162 static void 5163 ath_printrxbuf(struct ath_buf *bf, int done) 5164 { 5165 struct ath_desc *ds; 5166 int i; 5167 5168 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5169 printf("R%d (%p %" PRIx64 5170 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5171 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5172 ds->ds_link, ds->ds_data, 5173 ds->ds_ctl0, ds->ds_ctl1, 5174 ds->ds_hw[0], ds->ds_hw[1], 5175 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5176 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5177 } 5178 } 5179 5180 static void 5181 ath_printtxbuf(struct ath_buf *bf, int done) 5182 { 5183 struct ath_desc *ds; 5184 int i; 5185 5186 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5187 printf("T%d (%p %" PRIx64 5188 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5189 i, ds, 5190 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5191 ds->ds_link, ds->ds_data, 5192 ds->ds_ctl0, ds->ds_ctl1, 5193 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5194 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5195 } 5196 } 5197 #endif /* AR_DEBUG */ 5198 5199 static void 5200 ath_watchdog(struct ifnet *ifp) 5201 { 5202 struct ath_softc *sc = ifp->if_softc; 5203 struct ieee80211com *ic = &sc->sc_ic; 5204 struct ath_txq *axq; 5205 int i; 5206 5207 ifp->if_timer = 0; 5208 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5209 !device_is_active(sc->sc_dev)) 5210 return; 5211 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5212 if (!ATH_TXQ_SETUP(sc, i)) 5213 continue; 5214 axq = &sc->sc_txq[i]; 5215 ATH_TXQ_LOCK(axq); 5216 if (axq->axq_timer == 0) 5217 ; 5218 else if (--axq->axq_timer == 0) { 5219 ATH_TXQ_UNLOCK(axq); 5220 if_printf(ifp, "device timeout (txq %d, " 5221 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5222 if (sc->sc_txintrperiod > 1) 5223 sc->sc_txintrperiod--; 5224 ath_reset(ifp); 5225 ifp->if_oerrors++; 5226 sc->sc_stats.ast_watchdog++; 5227 break; 5228 } else 5229 ifp->if_timer = 1; 5230 ATH_TXQ_UNLOCK(axq); 5231 } 5232 ieee80211_watchdog(ic); 5233 } 5234 5235 /* 5236 * Diagnostic interface to the HAL. This is used by various 5237 * tools to do things like retrieve register contents for 5238 * debugging. The mechanism is intentionally opaque so that 5239 * it can change frequently w/o concern for compatiblity. 5240 */ 5241 static int 5242 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5243 { 5244 struct ath_hal *ah = sc->sc_ah; 5245 u_int id = ad->ad_id & ATH_DIAG_ID; 5246 void *indata = NULL; 5247 void *outdata = NULL; 5248 u_int32_t insize = ad->ad_in_size; 5249 u_int32_t outsize = ad->ad_out_size; 5250 int error = 0; 5251 5252 if (ad->ad_id & ATH_DIAG_IN) { 5253 /* 5254 * Copy in data. 5255 */ 5256 indata = malloc(insize, M_TEMP, M_NOWAIT); 5257 if (indata == NULL) { 5258 error = ENOMEM; 5259 goto bad; 5260 } 5261 error = copyin(ad->ad_in_data, indata, insize); 5262 if (error) 5263 goto bad; 5264 } 5265 if (ad->ad_id & ATH_DIAG_DYN) { 5266 /* 5267 * Allocate a buffer for the results (otherwise the HAL 5268 * returns a pointer to a buffer where we can read the 5269 * results). Note that we depend on the HAL leaving this 5270 * pointer for us to use below in reclaiming the buffer; 5271 * may want to be more defensive. 5272 */ 5273 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5274 if (outdata == NULL) { 5275 error = ENOMEM; 5276 goto bad; 5277 } 5278 } 5279 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5280 if (outsize < ad->ad_out_size) 5281 ad->ad_out_size = outsize; 5282 if (outdata != NULL) 5283 error = copyout(outdata, ad->ad_out_data, 5284 ad->ad_out_size); 5285 } else { 5286 error = EINVAL; 5287 } 5288 bad: 5289 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5290 free(indata, M_TEMP); 5291 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5292 free(outdata, M_TEMP); 5293 return error; 5294 } 5295 5296 static int 5297 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5298 { 5299 #define IS_RUNNING(ifp) \ 5300 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5301 struct ath_softc *sc = ifp->if_softc; 5302 struct ieee80211com *ic = &sc->sc_ic; 5303 struct ifreq *ifr = (struct ifreq *)data; 5304 int error = 0, s; 5305 5306 s = splnet(); 5307 switch (cmd) { 5308 case SIOCSIFFLAGS: 5309 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5310 break; 5311 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 5312 case IFF_UP|IFF_RUNNING: 5313 /* 5314 * To avoid rescanning another access point, 5315 * do not call ath_init() here. Instead, 5316 * only reflect promisc mode settings. 5317 */ 5318 ath_mode_init(sc); 5319 break; 5320 case IFF_UP: 5321 /* 5322 * Beware of being called during attach/detach 5323 * to reset promiscuous mode. In that case we 5324 * will still be marked UP but not RUNNING. 5325 * However trying to re-init the interface 5326 * is the wrong thing to do as we've already 5327 * torn down much of our state. There's 5328 * probably a better way to deal with this. 5329 */ 5330 error = ath_init(sc); 5331 break; 5332 case IFF_RUNNING: 5333 ath_stop_locked(ifp, 1); 5334 break; 5335 case 0: 5336 break; 5337 } 5338 break; 5339 case SIOCADDMULTI: 5340 case SIOCDELMULTI: 5341 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5342 if (ifp->if_flags & IFF_RUNNING) 5343 ath_mode_init(sc); 5344 error = 0; 5345 } 5346 break; 5347 case SIOCGATHSTATS: 5348 /* NB: embed these numbers to get a consistent view */ 5349 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5350 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5351 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5352 splx(s); 5353 /* 5354 * NB: Drop the softc lock in case of a page fault; 5355 * we'll accept any potential inconsisentcy in the 5356 * statistics. The alternative is to copy the data 5357 * to a local structure. 5358 */ 5359 return copyout(&sc->sc_stats, 5360 ifr->ifr_data, sizeof (sc->sc_stats)); 5361 case SIOCGATHDIAG: 5362 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5363 break; 5364 default: 5365 error = ieee80211_ioctl(ic, cmd, data); 5366 if (error != ENETRESET) 5367 ; 5368 else if (IS_RUNNING(ifp) && 5369 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5370 error = ath_init(sc); 5371 else 5372 error = 0; 5373 break; 5374 } 5375 splx(s); 5376 return error; 5377 #undef IS_RUNNING 5378 } 5379 5380 static void 5381 ath_bpfattach(struct ath_softc *sc) 5382 { 5383 struct ifnet *ifp = &sc->sc_if; 5384 5385 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 5386 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5387 &sc->sc_drvbpf); 5388 5389 /* 5390 * Initialize constant fields. 5391 * XXX make header lengths a multiple of 32-bits so subsequent 5392 * headers are properly aligned; this is a kludge to keep 5393 * certain applications happy. 5394 * 5395 * NB: the channel is setup each time we transition to the 5396 * RUN state to avoid filling it in for each frame. 5397 */ 5398 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5399 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5400 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5401 5402 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5403 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5404 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5405 } 5406 5407 /* 5408 * Announce various information on device/driver attach. 5409 */ 5410 static void 5411 ath_announce(struct ath_softc *sc) 5412 { 5413 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5414 struct ifnet *ifp = &sc->sc_if; 5415 struct ath_hal *ah = sc->sc_ah; 5416 u_int modes, cc; 5417 5418 if_printf(ifp, "mac %d.%d phy %d.%d", 5419 ah->ah_macVersion, ah->ah_macRev, 5420 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5421 /* 5422 * Print radio revision(s). We check the wireless modes 5423 * to avoid falsely printing revs for inoperable parts. 5424 * Dual-band radio revs are returned in the 5 GHz rev number. 5425 */ 5426 ath_hal_getcountrycode(ah, &cc); 5427 modes = ath_hal_getwirelessmodes(ah, cc); 5428 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5429 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5430 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5431 ah->ah_analog5GhzRev >> 4, 5432 ah->ah_analog5GhzRev & 0xf, 5433 ah->ah_analog2GhzRev >> 4, 5434 ah->ah_analog2GhzRev & 0xf); 5435 else 5436 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5437 ah->ah_analog5GhzRev & 0xf); 5438 } else 5439 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5440 ah->ah_analog5GhzRev & 0xf); 5441 printf("\n"); 5442 if (bootverbose) { 5443 int i; 5444 for (i = 0; i <= WME_AC_VO; i++) { 5445 struct ath_txq *txq = sc->sc_ac2q[i]; 5446 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5447 txq->axq_qnum, ieee80211_wme_acnames[i]); 5448 } 5449 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5450 sc->sc_cabq->axq_qnum); 5451 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5452 } 5453 if (ath_rxbuf != ATH_RXBUF) 5454 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5455 if (ath_txbuf != ATH_TXBUF) 5456 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5457 #undef HAL_MODE_DUALBAND 5458 } 5459