1 /* $NetBSD: ath.c,v 1.100 2008/05/04 20:02:06 rumble Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.100 2008/05/04 20:02:06 rumble Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/errno.h> 71 #include <sys/callout.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/if_ether.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_netbsd.h> 84 #include <net80211/ieee80211_var.h> 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #endif 93 94 #include <sys/device.h> 95 #include <dev/ic/ath_netbsd.h> 96 97 #define AR_DEBUG 98 #include <dev/ic/athvar.h> 99 #include <contrib/dev/ath/ah_desc.h> 100 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 101 #include "athhal_options.h" 102 103 #ifdef ATH_TX99_DIAG 104 #include <dev/ath/ath_tx99/ath_tx99.h> 105 #endif 106 107 /* unaligned little endian access */ 108 #define LE_READ_2(p) \ 109 ((u_int16_t) \ 110 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 111 #define LE_READ_4(p) \ 112 ((u_int32_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 114 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 115 116 enum { 117 ATH_LED_TX, 118 ATH_LED_RX, 119 ATH_LED_POLL, 120 }; 121 122 #ifdef AH_NEED_DESC_SWAP 123 #define HTOAH32(x) htole32(x) 124 #else 125 #define HTOAH32(x) (x) 126 #endif 127 128 static int ath_ifinit(struct ifnet *); 129 static int ath_init(struct ath_softc *); 130 static void ath_stop_locked(struct ifnet *, int); 131 static void ath_stop(struct ifnet *, int); 132 static void ath_start(struct ifnet *); 133 static int ath_media_change(struct ifnet *); 134 static void ath_watchdog(struct ifnet *); 135 static int ath_ioctl(struct ifnet *, u_long, void *); 136 static void ath_fatal_proc(void *, int); 137 static void ath_rxorn_proc(void *, int); 138 static void ath_bmiss_proc(void *, int); 139 static void ath_radar_proc(void *, int); 140 static int ath_key_alloc(struct ieee80211com *, 141 const struct ieee80211_key *, 142 ieee80211_keyix *, ieee80211_keyix *); 143 static int ath_key_delete(struct ieee80211com *, 144 const struct ieee80211_key *); 145 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 146 const u_int8_t mac[IEEE80211_ADDR_LEN]); 147 static void ath_key_update_begin(struct ieee80211com *); 148 static void ath_key_update_end(struct ieee80211com *); 149 static void ath_mode_init(struct ath_softc *); 150 static void ath_setslottime(struct ath_softc *); 151 static void ath_updateslot(struct ifnet *); 152 static int ath_beaconq_setup(struct ath_hal *); 153 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 154 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 155 static void ath_beacon_proc(void *, int); 156 static void ath_bstuck_proc(void *, int); 157 static void ath_beacon_free(struct ath_softc *); 158 static void ath_beacon_config(struct ath_softc *); 159 static void ath_descdma_cleanup(struct ath_softc *sc, 160 struct ath_descdma *, ath_bufhead *); 161 static int ath_desc_alloc(struct ath_softc *); 162 static void ath_desc_free(struct ath_softc *); 163 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 164 static void ath_node_free(struct ieee80211_node *); 165 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 166 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 167 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 168 struct ieee80211_node *ni, 169 int subtype, int rssi, u_int32_t rstamp); 170 static void ath_setdefantenna(struct ath_softc *, u_int); 171 static void ath_rx_proc(void *, int); 172 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 173 static int ath_tx_setup(struct ath_softc *, int, int); 174 static int ath_wme_update(struct ieee80211com *); 175 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 176 static void ath_tx_cleanup(struct ath_softc *); 177 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 178 struct ath_buf *, struct mbuf *); 179 static void ath_tx_proc_q0(void *, int); 180 static void ath_tx_proc_q0123(void *, int); 181 static void ath_tx_proc(void *, int); 182 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_draintxq(struct ath_softc *); 184 static void ath_stoprecv(struct ath_softc *); 185 static int ath_startrecv(struct ath_softc *); 186 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 187 static void ath_next_scan(void *); 188 static void ath_calibrate(void *); 189 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 190 static void ath_setup_stationkey(struct ieee80211_node *); 191 static void ath_newassoc(struct ieee80211_node *, int); 192 static int ath_getchannels(struct ath_softc *, u_int cc, 193 HAL_BOOL outdoor, HAL_BOOL xchanmode); 194 static void ath_led_event(struct ath_softc *, int); 195 static void ath_update_txpow(struct ath_softc *); 196 static void ath_freetx(struct mbuf *); 197 static void ath_restore_diversity(struct ath_softc *); 198 199 static int ath_rate_setup(struct ath_softc *, u_int mode); 200 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 201 202 #if NBPFILTER > 0 203 static void ath_bpfattach(struct ath_softc *); 204 #endif 205 static void ath_announce(struct ath_softc *); 206 207 int ath_dwelltime = 200; /* 5 channels/second */ 208 int ath_calinterval = 30; /* calibrate every 30 secs */ 209 int ath_outdoor = AH_TRUE; /* outdoor operation */ 210 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 211 int ath_countrycode = CTRY_DEFAULT; /* country code */ 212 int ath_regdomain = 0; /* regulatory domain */ 213 int ath_debug = 0; 214 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 215 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 216 217 #ifdef AR_DEBUG 218 enum { 219 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 220 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 221 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 222 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 223 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 224 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 225 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 226 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 227 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 228 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 229 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 230 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 231 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 232 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 233 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 234 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 235 ATH_DEBUG_NODE = 0x00080000, /* node management */ 236 ATH_DEBUG_LED = 0x00100000, /* led management */ 237 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 238 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 239 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 240 ATH_DEBUG_ANY = 0xffffffff 241 }; 242 #define IFF_DUMPPKTS(sc, m) \ 243 ((sc->sc_debug & (m)) || \ 244 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245 #define DPRINTF(sc, m, fmt, ...) do { \ 246 if (sc->sc_debug & (m)) \ 247 printf(fmt, __VA_ARGS__); \ 248 } while (0) 249 #define KEYPRINTF(sc, ix, hk, mac) do { \ 250 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 251 ath_keyprint(__func__, ix, hk, mac); \ 252 } while (0) 253 static void ath_printrxbuf(struct ath_buf *bf, int); 254 static void ath_printtxbuf(struct ath_buf *bf, int); 255 #else 256 #define IFF_DUMPPKTS(sc, m) \ 257 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 258 #define DPRINTF(m, fmt, ...) 259 #define KEYPRINTF(sc, k, ix, mac) 260 #endif 261 262 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 263 264 int 265 ath_attach(u_int16_t devid, struct ath_softc *sc) 266 { 267 struct ifnet *ifp = &sc->sc_if; 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ath_hal *ah = NULL; 270 HAL_STATUS status; 271 int error = 0, i; 272 273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 274 275 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 276 277 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 278 if (ah == NULL) { 279 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 280 status); 281 error = ENXIO; 282 goto bad; 283 } 284 if (ah->ah_abi != HAL_ABI_VERSION) { 285 if_printf(ifp, "HAL ABI mismatch detected " 286 "(HAL:0x%x != driver:0x%x)\n", 287 ah->ah_abi, HAL_ABI_VERSION); 288 error = ENXIO; 289 goto bad; 290 } 291 sc->sc_ah = ah; 292 293 if (!prop_dictionary_set_bool(device_properties(&sc->sc_dev), 294 "pmf-powerdown", false)) 295 goto bad; 296 297 /* 298 * Check if the MAC has multi-rate retry support. 299 * We do this by trying to setup a fake extended 300 * descriptor. MAC's that don't have support will 301 * return false w/o doing anything. MAC's that do 302 * support it will return true w/o doing anything. 303 */ 304 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 305 306 /* 307 * Check if the device has hardware counters for PHY 308 * errors. If so we need to enable the MIB interrupt 309 * so we can act on stat triggers. 310 */ 311 if (ath_hal_hwphycounters(ah)) 312 sc->sc_needmib = 1; 313 314 /* 315 * Get the hardware key cache size. 316 */ 317 sc->sc_keymax = ath_hal_keycachesize(ah); 318 if (sc->sc_keymax > ATH_KEYMAX) { 319 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 320 ATH_KEYMAX, sc->sc_keymax); 321 sc->sc_keymax = ATH_KEYMAX; 322 } 323 /* 324 * Reset the key cache since some parts do not 325 * reset the contents on initial power up. 326 */ 327 for (i = 0; i < sc->sc_keymax; i++) 328 ath_hal_keyreset(ah, i); 329 /* 330 * Mark key cache slots associated with global keys 331 * as in use. If we knew TKIP was not to be used we 332 * could leave the +32, +64, and +32+64 slots free. 333 * XXX only for splitmic. 334 */ 335 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 336 setbit(sc->sc_keymap, i); 337 setbit(sc->sc_keymap, i+32); 338 setbit(sc->sc_keymap, i+64); 339 setbit(sc->sc_keymap, i+32+64); 340 } 341 342 /* 343 * Collect the channel list using the default country 344 * code and including outdoor channels. The 802.11 layer 345 * is resposible for filtering this list based on settings 346 * like the phy mode. 347 */ 348 error = ath_getchannels(sc, ath_countrycode, 349 ath_outdoor, ath_xchanmode); 350 if (error != 0) 351 goto bad; 352 353 /* 354 * Setup rate tables for all potential media types. 355 */ 356 ath_rate_setup(sc, IEEE80211_MODE_11A); 357 ath_rate_setup(sc, IEEE80211_MODE_11B); 358 ath_rate_setup(sc, IEEE80211_MODE_11G); 359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 360 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 361 /* NB: setup here so ath_rate_update is happy */ 362 ath_setcurmode(sc, IEEE80211_MODE_11A); 363 364 /* 365 * Allocate tx+rx descriptors and populate the lists. 366 */ 367 error = ath_desc_alloc(sc); 368 if (error != 0) { 369 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 370 goto bad; 371 } 372 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 373 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 374 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 375 376 ATH_TXBUF_LOCK_INIT(sc); 377 378 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 379 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 380 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 381 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 382 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 383 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 384 385 /* 386 * Allocate hardware transmit queues: one queue for 387 * beacon frames and one data queue for each QoS 388 * priority. Note that the hal handles reseting 389 * these queues at the needed time. 390 * 391 * XXX PS-Poll 392 */ 393 sc->sc_bhalq = ath_beaconq_setup(ah); 394 if (sc->sc_bhalq == (u_int) -1) { 395 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 396 error = EIO; 397 goto bad2; 398 } 399 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 400 if (sc->sc_cabq == NULL) { 401 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 402 error = EIO; 403 goto bad2; 404 } 405 /* NB: insure BK queue is the lowest priority h/w queue */ 406 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 407 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 408 ieee80211_wme_acnames[WME_AC_BK]); 409 error = EIO; 410 goto bad2; 411 } 412 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 413 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 414 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 415 /* 416 * Not enough hardware tx queues to properly do WME; 417 * just punt and assign them all to the same h/w queue. 418 * We could do a better job of this if, for example, 419 * we allocate queues when we switch from station to 420 * AP mode. 421 */ 422 if (sc->sc_ac2q[WME_AC_VI] != NULL) 423 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 424 if (sc->sc_ac2q[WME_AC_BE] != NULL) 425 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 426 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 427 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 428 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 429 } 430 431 /* 432 * Special case certain configurations. Note the 433 * CAB queue is handled by these specially so don't 434 * include them when checking the txq setup mask. 435 */ 436 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 437 case 0x01: 438 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 439 break; 440 case 0x0f: 441 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 442 break; 443 default: 444 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 445 break; 446 } 447 448 /* 449 * Setup rate control. Some rate control modules 450 * call back to change the anntena state so expose 451 * the necessary entry points. 452 * XXX maybe belongs in struct ath_ratectrl? 453 */ 454 sc->sc_setdefantenna = ath_setdefantenna; 455 sc->sc_rc = ath_rate_attach(sc); 456 if (sc->sc_rc == NULL) { 457 error = EIO; 458 goto bad2; 459 } 460 461 sc->sc_blinking = 0; 462 sc->sc_ledstate = 1; 463 sc->sc_ledon = 0; /* low true */ 464 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 465 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 466 /* 467 * Auto-enable soft led processing for IBM cards and for 468 * 5211 minipci cards. Users can also manually enable/disable 469 * support with a sysctl. 470 */ 471 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 472 if (sc->sc_softled) { 473 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 474 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 475 } 476 477 ifp->if_softc = sc; 478 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 479 ifp->if_start = ath_start; 480 ifp->if_stop = ath_stop; 481 ifp->if_watchdog = ath_watchdog; 482 ifp->if_ioctl = ath_ioctl; 483 ifp->if_init = ath_ifinit; 484 IFQ_SET_READY(&ifp->if_snd); 485 486 ic->ic_ifp = ifp; 487 ic->ic_reset = ath_reset; 488 ic->ic_newassoc = ath_newassoc; 489 ic->ic_updateslot = ath_updateslot; 490 ic->ic_wme.wme_update = ath_wme_update; 491 /* XXX not right but it's not used anywhere important */ 492 ic->ic_phytype = IEEE80211_T_OFDM; 493 ic->ic_opmode = IEEE80211_M_STA; 494 ic->ic_caps = 495 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 496 | IEEE80211_C_HOSTAP /* hostap mode */ 497 | IEEE80211_C_MONITOR /* monitor mode */ 498 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 499 | IEEE80211_C_SHSLOT /* short slot time supported */ 500 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 501 | IEEE80211_C_TXFRAG /* handle tx frags */ 502 ; 503 /* 504 * Query the hal to figure out h/w crypto support. 505 */ 506 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 507 ic->ic_caps |= IEEE80211_C_WEP; 508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 509 ic->ic_caps |= IEEE80211_C_AES; 510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 511 ic->ic_caps |= IEEE80211_C_AES_CCM; 512 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 513 ic->ic_caps |= IEEE80211_C_CKIP; 514 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 515 ic->ic_caps |= IEEE80211_C_TKIP; 516 /* 517 * Check if h/w does the MIC and/or whether the 518 * separate key cache entries are required to 519 * handle both tx+rx MIC keys. 520 */ 521 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 522 ic->ic_caps |= IEEE80211_C_TKIPMIC; 523 if (ath_hal_tkipsplit(ah)) 524 sc->sc_splitmic = 1; 525 } 526 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 527 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 528 /* 529 * TPC support can be done either with a global cap or 530 * per-packet support. The latter is not available on 531 * all parts. We're a bit pedantic here as all parts 532 * support a global cap. 533 */ 534 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 535 ic->ic_caps |= IEEE80211_C_TXPMGT; 536 537 /* 538 * Mark WME capability only if we have sufficient 539 * hardware queues to do proper priority scheduling. 540 */ 541 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 542 ic->ic_caps |= IEEE80211_C_WME; 543 /* 544 * Check for misc other capabilities. 545 */ 546 if (ath_hal_hasbursting(ah)) 547 ic->ic_caps |= IEEE80211_C_BURST; 548 549 /* 550 * Indicate we need the 802.11 header padded to a 551 * 32-bit boundary for 4-address and QoS frames. 552 */ 553 ic->ic_flags |= IEEE80211_F_DATAPAD; 554 555 /* 556 * Query the hal about antenna support. 557 */ 558 sc->sc_defant = ath_hal_getdefantenna(ah); 559 560 /* 561 * Not all chips have the VEOL support we want to 562 * use with IBSS beacons; check here for it. 563 */ 564 sc->sc_hasveol = ath_hal_hasveol(ah); 565 566 /* get mac address from hardware */ 567 ath_hal_getmac(ah, ic->ic_myaddr); 568 569 if_attach(ifp); 570 /* call MI attach routine. */ 571 ieee80211_ifattach(ic); 572 /* override default methods */ 573 ic->ic_node_alloc = ath_node_alloc; 574 sc->sc_node_free = ic->ic_node_free; 575 ic->ic_node_free = ath_node_free; 576 ic->ic_node_getrssi = ath_node_getrssi; 577 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 578 ic->ic_recv_mgmt = ath_recv_mgmt; 579 sc->sc_newstate = ic->ic_newstate; 580 ic->ic_newstate = ath_newstate; 581 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 582 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 583 ic->ic_crypto.cs_key_delete = ath_key_delete; 584 ic->ic_crypto.cs_key_set = ath_key_set; 585 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 586 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 587 /* complete initialization */ 588 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 589 590 #if NBPFILTER > 0 591 ath_bpfattach(sc); 592 #endif 593 594 sc->sc_flags |= ATH_ATTACHED; 595 596 /* 597 * Setup dynamic sysctl's now that country code and 598 * regdomain are available from the hal. 599 */ 600 ath_sysctlattach(sc); 601 602 ieee80211_announce(ic); 603 ath_announce(sc); 604 return 0; 605 bad2: 606 ath_tx_cleanup(sc); 607 ath_desc_free(sc); 608 bad: 609 if (ah) 610 ath_hal_detach(ah); 611 /* XXX don't get under the abstraction like this */ 612 sc->sc_dev.dv_flags &= ~DVF_ACTIVE; 613 return error; 614 } 615 616 int 617 ath_detach(struct ath_softc *sc) 618 { 619 struct ifnet *ifp = &sc->sc_if; 620 int s; 621 622 if ((sc->sc_flags & ATH_ATTACHED) == 0) 623 return (0); 624 625 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 626 __func__, ifp->if_flags); 627 628 s = splnet(); 629 ath_stop(ifp, 1); 630 #if NBPFILTER > 0 631 bpfdetach(ifp); 632 #endif 633 /* 634 * NB: the order of these is important: 635 * o call the 802.11 layer before detaching the hal to 636 * insure callbacks into the driver to delete global 637 * key cache entries can be handled 638 * o reclaim the tx queue data structures after calling 639 * the 802.11 layer as we'll get called back to reclaim 640 * node state and potentially want to use them 641 * o to cleanup the tx queues the hal is called, so detach 642 * it last 643 * Other than that, it's straightforward... 644 */ 645 ieee80211_ifdetach(&sc->sc_ic); 646 #ifdef ATH_TX99_DIAG 647 if (sc->sc_tx99 != NULL) 648 sc->sc_tx99->detach(sc->sc_tx99); 649 #endif 650 ath_rate_detach(sc->sc_rc); 651 ath_desc_free(sc); 652 ath_tx_cleanup(sc); 653 sysctl_teardown(&sc->sc_sysctllog); 654 ath_hal_detach(sc->sc_ah); 655 if_detach(ifp); 656 splx(s); 657 658 return 0; 659 } 660 661 void 662 ath_suspend(struct ath_softc *sc) 663 { 664 /* 665 * Set the chip in full sleep mode. Note that we are 666 * careful to do this only when bringing the interface 667 * completely to a stop. When the chip is in this state 668 * it must be carefully woken up or references to 669 * registers in the PCI clock domain may freeze the bus 670 * (and system). This varies by chip and is mostly an 671 * issue with newer parts that go to sleep more quickly. 672 */ 673 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 674 } 675 676 bool 677 ath_resume(struct ath_softc *sc) 678 { 679 int i; 680 struct ath_hal *ah = sc->sc_ah; 681 682 ath_hal_setpower(ah, HAL_PM_AWAKE); 683 684 /* 685 * Reset the key cache since some parts do not 686 * reset the contents on initial power up. 687 */ 688 for (i = 0; i < sc->sc_keymax; i++) 689 ath_hal_keyreset(ah, i); 690 691 ath_hal_resettxqueue(ah, sc->sc_bhalq); 692 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 693 if (ATH_TXQ_SETUP(sc, i)) 694 ath_hal_resettxqueue(ah, i); 695 696 if (sc->sc_softled) { 697 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 698 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 699 } 700 return true; 701 } 702 703 /* 704 * Interrupt handler. Most of the actual processing is deferred. 705 */ 706 int 707 ath_intr(void *arg) 708 { 709 struct ath_softc *sc = arg; 710 struct ifnet *ifp = &sc->sc_if; 711 struct ath_hal *ah = sc->sc_ah; 712 HAL_INT status; 713 714 if (!device_is_active(&sc->sc_dev)) { 715 /* 716 * The hardware is not ready/present, don't touch anything. 717 * Note this can happen early on if the IRQ is shared. 718 */ 719 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 720 return 0; 721 } 722 723 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 724 return 0; 725 726 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 727 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 728 __func__, ifp->if_flags); 729 ath_hal_getisr(ah, &status); /* clear ISR */ 730 ath_hal_intrset(ah, 0); /* disable further intr's */ 731 return 1; /* XXX */ 732 } 733 /* 734 * Figure out the reason(s) for the interrupt. Note 735 * that the hal returns a pseudo-ISR that may include 736 * bits we haven't explicitly enabled so we mask the 737 * value to insure we only process bits we requested. 738 */ 739 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 740 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 741 status &= sc->sc_imask; /* discard unasked for bits */ 742 if (status & HAL_INT_FATAL) { 743 /* 744 * Fatal errors are unrecoverable. Typically 745 * these are caused by DMA errors. Unfortunately 746 * the exact reason is not (presently) returned 747 * by the hal. 748 */ 749 sc->sc_stats.ast_hardware++; 750 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 751 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 752 } else if (status & HAL_INT_RXORN) { 753 sc->sc_stats.ast_rxorn++; 754 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 755 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 756 } else { 757 if (status & HAL_INT_SWBA) { 758 /* 759 * Software beacon alert--time to send a beacon. 760 * Handle beacon transmission directly; deferring 761 * this is too slow to meet timing constraints 762 * under load. 763 */ 764 ath_beacon_proc(sc, 0); 765 } 766 if (status & HAL_INT_RXEOL) { 767 /* 768 * NB: the hardware should re-read the link when 769 * RXE bit is written, but it doesn't work at 770 * least on older hardware revs. 771 */ 772 sc->sc_stats.ast_rxeol++; 773 sc->sc_rxlink = NULL; 774 } 775 if (status & HAL_INT_TXURN) { 776 sc->sc_stats.ast_txurn++; 777 /* bump tx trigger level */ 778 ath_hal_updatetxtriglevel(ah, AH_TRUE); 779 } 780 if (status & HAL_INT_RX) 781 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 782 if (status & HAL_INT_TX) 783 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 784 if (status & HAL_INT_BMISS) { 785 sc->sc_stats.ast_bmiss++; 786 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 787 } 788 if (status & HAL_INT_MIB) { 789 sc->sc_stats.ast_mib++; 790 /* 791 * Disable interrupts until we service the MIB 792 * interrupt; otherwise it will continue to fire. 793 */ 794 ath_hal_intrset(ah, 0); 795 /* 796 * Let the hal handle the event. We assume it will 797 * clear whatever condition caused the interrupt. 798 */ 799 ath_hal_mibevent(ah, &sc->sc_halstats); 800 ath_hal_intrset(ah, sc->sc_imask); 801 } 802 } 803 return 1; 804 } 805 806 /* Swap transmit descriptor. 807 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 808 * function. 809 */ 810 static inline void 811 ath_desc_swap(struct ath_desc *ds) 812 { 813 #ifdef AH_NEED_DESC_SWAP 814 ds->ds_link = htole32(ds->ds_link); 815 ds->ds_data = htole32(ds->ds_data); 816 ds->ds_ctl0 = htole32(ds->ds_ctl0); 817 ds->ds_ctl1 = htole32(ds->ds_ctl1); 818 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 819 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 820 #endif 821 } 822 823 static void 824 ath_fatal_proc(void *arg, int pending) 825 { 826 struct ath_softc *sc = arg; 827 struct ifnet *ifp = &sc->sc_if; 828 829 if_printf(ifp, "hardware error; resetting\n"); 830 ath_reset(ifp); 831 } 832 833 static void 834 ath_rxorn_proc(void *arg, int pending) 835 { 836 struct ath_softc *sc = arg; 837 struct ifnet *ifp = &sc->sc_if; 838 839 if_printf(ifp, "rx FIFO overrun; resetting\n"); 840 ath_reset(ifp); 841 } 842 843 static void 844 ath_bmiss_proc(void *arg, int pending) 845 { 846 struct ath_softc *sc = arg; 847 struct ieee80211com *ic = &sc->sc_ic; 848 849 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 850 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 851 ("unexpect operating mode %u", ic->ic_opmode)); 852 if (ic->ic_state == IEEE80211_S_RUN) { 853 u_int64_t lastrx = sc->sc_lastrx; 854 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 855 856 DPRINTF(sc, ATH_DEBUG_BEACON, 857 "%s: tsf %" PRIu64 " lastrx %" PRId64 858 " (%" PRIu64 ") bmiss %u\n", 859 __func__, tsf, tsf - lastrx, lastrx, 860 ic->ic_bmisstimeout*1024); 861 /* 862 * Workaround phantom bmiss interrupts by sanity-checking 863 * the time of our last rx'd frame. If it is within the 864 * beacon miss interval then ignore the interrupt. If it's 865 * truly a bmiss we'll get another interrupt soon and that'll 866 * be dispatched up for processing. 867 */ 868 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 869 NET_LOCK_GIANT(); 870 ieee80211_beacon_miss(ic); 871 NET_UNLOCK_GIANT(); 872 } else 873 sc->sc_stats.ast_bmiss_phantom++; 874 } 875 } 876 877 static void 878 ath_radar_proc(void *arg, int pending) 879 { 880 struct ath_softc *sc = arg; 881 struct ifnet *ifp = &sc->sc_if; 882 struct ath_hal *ah = sc->sc_ah; 883 HAL_CHANNEL hchan; 884 885 if (ath_hal_procdfs(ah, &hchan)) { 886 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 887 hchan.channel, hchan.channelFlags, hchan.privFlags); 888 /* 889 * Initiate channel change. 890 */ 891 /* XXX not yet */ 892 } 893 } 894 895 static u_int 896 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 897 { 898 #define N(a) (sizeof(a) / sizeof(a[0])) 899 static const u_int modeflags[] = { 900 0, /* IEEE80211_MODE_AUTO */ 901 CHANNEL_A, /* IEEE80211_MODE_11A */ 902 CHANNEL_B, /* IEEE80211_MODE_11B */ 903 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 904 0, /* IEEE80211_MODE_FH */ 905 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 906 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 907 }; 908 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 909 910 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 911 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 912 return modeflags[mode]; 913 #undef N 914 } 915 916 static int 917 ath_ifinit(struct ifnet *ifp) 918 { 919 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 920 921 return ath_init(sc); 922 } 923 924 static int 925 ath_init(struct ath_softc *sc) 926 { 927 struct ifnet *ifp = &sc->sc_if; 928 struct ieee80211com *ic = &sc->sc_ic; 929 struct ath_hal *ah = sc->sc_ah; 930 HAL_STATUS status; 931 int error = 0; 932 933 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 934 __func__, ifp->if_flags); 935 936 if (device_is_active(&sc->sc_dev)) { 937 ATH_LOCK(sc); 938 } else if (!pmf_device_resume_self(&sc->sc_dev)) 939 return ENXIO; 940 else 941 ATH_LOCK(sc); 942 943 /* 944 * Stop anything previously setup. This is safe 945 * whether this is the first time through or not. 946 */ 947 ath_stop_locked(ifp, 0); 948 949 /* 950 * The basic interface to setting the hardware in a good 951 * state is ``reset''. On return the hardware is known to 952 * be powered up and with interrupts disabled. This must 953 * be followed by initialization of the appropriate bits 954 * and then setup of the interrupt mask. 955 */ 956 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 957 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 958 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 959 if_printf(ifp, "unable to reset hardware; hal status %u\n", 960 status); 961 error = EIO; 962 goto done; 963 } 964 965 /* 966 * This is needed only to setup initial state 967 * but it's best done after a reset. 968 */ 969 ath_update_txpow(sc); 970 /* 971 * Likewise this is set during reset so update 972 * state cached in the driver. 973 */ 974 ath_restore_diversity(sc); 975 sc->sc_calinterval = 1; 976 sc->sc_caltries = 0; 977 978 /* 979 * Setup the hardware after reset: the key cache 980 * is filled as needed and the receive engine is 981 * set going. Frame transmit is handled entirely 982 * in the frame output path; there's nothing to do 983 * here except setup the interrupt mask. 984 */ 985 if ((error = ath_startrecv(sc)) != 0) { 986 if_printf(ifp, "unable to start recv logic\n"); 987 goto done; 988 } 989 990 /* 991 * Enable interrupts. 992 */ 993 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 994 | HAL_INT_RXEOL | HAL_INT_RXORN 995 | HAL_INT_FATAL | HAL_INT_GLOBAL; 996 /* 997 * Enable MIB interrupts when there are hardware phy counters. 998 * Note we only do this (at the moment) for station mode. 999 */ 1000 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1001 sc->sc_imask |= HAL_INT_MIB; 1002 ath_hal_intrset(ah, sc->sc_imask); 1003 1004 ifp->if_flags |= IFF_RUNNING; 1005 ic->ic_state = IEEE80211_S_INIT; 1006 1007 /* 1008 * The hardware should be ready to go now so it's safe 1009 * to kick the 802.11 state machine as it's likely to 1010 * immediately call back to us to send mgmt frames. 1011 */ 1012 ath_chan_change(sc, ic->ic_curchan); 1013 #ifdef ATH_TX99_DIAG 1014 if (sc->sc_tx99 != NULL) 1015 sc->sc_tx99->start(sc->sc_tx99); 1016 else 1017 #endif 1018 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1019 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1020 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1021 } else 1022 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1023 done: 1024 ATH_UNLOCK(sc); 1025 return error; 1026 } 1027 1028 static void 1029 ath_stop_locked(struct ifnet *ifp, int disable) 1030 { 1031 struct ath_softc *sc = ifp->if_softc; 1032 struct ieee80211com *ic = &sc->sc_ic; 1033 struct ath_hal *ah = sc->sc_ah; 1034 1035 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1036 __func__, !device_is_enabled(&sc->sc_dev), ifp->if_flags); 1037 1038 ATH_LOCK_ASSERT(sc); 1039 if (ifp->if_flags & IFF_RUNNING) { 1040 /* 1041 * Shutdown the hardware and driver: 1042 * reset 802.11 state machine 1043 * turn off timers 1044 * disable interrupts 1045 * turn off the radio 1046 * clear transmit machinery 1047 * clear receive machinery 1048 * drain and release tx queues 1049 * reclaim beacon resources 1050 * power down hardware 1051 * 1052 * Note that some of this work is not possible if the 1053 * hardware is gone (invalid). 1054 */ 1055 #ifdef ATH_TX99_DIAG 1056 if (sc->sc_tx99 != NULL) 1057 sc->sc_tx99->stop(sc->sc_tx99); 1058 #endif 1059 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1060 ifp->if_flags &= ~IFF_RUNNING; 1061 ifp->if_timer = 0; 1062 if (device_is_enabled(&sc->sc_dev)) { 1063 if (sc->sc_softled) { 1064 callout_stop(&sc->sc_ledtimer); 1065 ath_hal_gpioset(ah, sc->sc_ledpin, 1066 !sc->sc_ledon); 1067 sc->sc_blinking = 0; 1068 } 1069 ath_hal_intrset(ah, 0); 1070 } 1071 ath_draintxq(sc); 1072 if (device_is_enabled(&sc->sc_dev)) { 1073 ath_stoprecv(sc); 1074 ath_hal_phydisable(ah); 1075 } else 1076 sc->sc_rxlink = NULL; 1077 IF_PURGE(&ifp->if_snd); 1078 ath_beacon_free(sc); 1079 if (disable) 1080 pmf_device_suspend_self(&sc->sc_dev); 1081 } 1082 } 1083 1084 static void 1085 ath_stop(struct ifnet *ifp, int disable) 1086 { 1087 struct ath_softc *sc = ifp->if_softc; 1088 1089 ATH_LOCK(sc); 1090 ath_stop_locked(ifp, disable); 1091 ATH_UNLOCK(sc); 1092 } 1093 1094 static void 1095 ath_restore_diversity(struct ath_softc *sc) 1096 { 1097 struct ifnet *ifp = &sc->sc_if; 1098 struct ath_hal *ah = sc->sc_ah; 1099 1100 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1101 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1102 if_printf(ifp, "could not restore diversity setting %d\n", 1103 sc->sc_diversity); 1104 sc->sc_diversity = ath_hal_getdiversity(ah); 1105 } 1106 } 1107 1108 /* 1109 * Reset the hardware w/o losing operational state. This is 1110 * basically a more efficient way of doing ath_stop, ath_init, 1111 * followed by state transitions to the current 802.11 1112 * operational state. Used to recover from various errors and 1113 * to reset or reload hardware state. 1114 */ 1115 int 1116 ath_reset(struct ifnet *ifp) 1117 { 1118 struct ath_softc *sc = ifp->if_softc; 1119 struct ieee80211com *ic = &sc->sc_ic; 1120 struct ath_hal *ah = sc->sc_ah; 1121 struct ieee80211_channel *c; 1122 HAL_STATUS status; 1123 1124 /* 1125 * Convert to a HAL channel description with the flags 1126 * constrained to reflect the current operating mode. 1127 */ 1128 c = ic->ic_curchan; 1129 sc->sc_curchan.channel = c->ic_freq; 1130 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1131 1132 ath_hal_intrset(ah, 0); /* disable interrupts */ 1133 ath_draintxq(sc); /* stop xmit side */ 1134 ath_stoprecv(sc); /* stop recv side */ 1135 /* NB: indicate channel change so we do a full reset */ 1136 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1137 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1138 __func__, status); 1139 ath_update_txpow(sc); /* update tx power state */ 1140 ath_restore_diversity(sc); 1141 sc->sc_calinterval = 1; 1142 sc->sc_caltries = 0; 1143 if (ath_startrecv(sc) != 0) /* restart recv */ 1144 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1145 /* 1146 * We may be doing a reset in response to an ioctl 1147 * that changes the channel so update any state that 1148 * might change as a result. 1149 */ 1150 ath_chan_change(sc, c); 1151 if (ic->ic_state == IEEE80211_S_RUN) 1152 ath_beacon_config(sc); /* restart beacons */ 1153 ath_hal_intrset(ah, sc->sc_imask); 1154 1155 ath_start(ifp); /* restart xmit */ 1156 return 0; 1157 } 1158 1159 /* 1160 * Cleanup driver resources when we run out of buffers 1161 * while processing fragments; return the tx buffers 1162 * allocated and drop node references. 1163 */ 1164 static void 1165 ath_txfrag_cleanup(struct ath_softc *sc, 1166 ath_bufhead *frags, struct ieee80211_node *ni) 1167 { 1168 struct ath_buf *bf; 1169 1170 ATH_TXBUF_LOCK_ASSERT(sc); 1171 1172 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1173 STAILQ_REMOVE_HEAD(frags, bf_list); 1174 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1175 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1176 ieee80211_node_decref(ni); 1177 } 1178 } 1179 1180 /* 1181 * Setup xmit of a fragmented frame. Allocate a buffer 1182 * for each frag and bump the node reference count to 1183 * reflect the held reference to be setup by ath_tx_start. 1184 */ 1185 static int 1186 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1187 struct mbuf *m0, struct ieee80211_node *ni) 1188 { 1189 struct mbuf *m; 1190 struct ath_buf *bf; 1191 1192 ATH_TXBUF_LOCK(sc); 1193 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1194 bf = STAILQ_FIRST(&sc->sc_txbuf); 1195 if (bf == NULL) { /* out of buffers, cleanup */ 1196 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1197 __func__); 1198 sc->sc_if.if_flags |= IFF_OACTIVE; 1199 ath_txfrag_cleanup(sc, frags, ni); 1200 break; 1201 } 1202 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1203 ieee80211_node_incref(ni); 1204 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1205 } 1206 ATH_TXBUF_UNLOCK(sc); 1207 1208 return !STAILQ_EMPTY(frags); 1209 } 1210 1211 static void 1212 ath_start(struct ifnet *ifp) 1213 { 1214 struct ath_softc *sc = ifp->if_softc; 1215 struct ath_hal *ah = sc->sc_ah; 1216 struct ieee80211com *ic = &sc->sc_ic; 1217 struct ieee80211_node *ni; 1218 struct ath_buf *bf; 1219 struct mbuf *m, *next; 1220 struct ieee80211_frame *wh; 1221 struct ether_header *eh; 1222 ath_bufhead frags; 1223 1224 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1225 !device_is_active(&sc->sc_dev)) 1226 return; 1227 for (;;) { 1228 /* 1229 * Grab a TX buffer and associated resources. 1230 */ 1231 ATH_TXBUF_LOCK(sc); 1232 bf = STAILQ_FIRST(&sc->sc_txbuf); 1233 if (bf != NULL) 1234 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1235 ATH_TXBUF_UNLOCK(sc); 1236 if (bf == NULL) { 1237 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1238 __func__); 1239 sc->sc_stats.ast_tx_qstop++; 1240 ifp->if_flags |= IFF_OACTIVE; 1241 break; 1242 } 1243 /* 1244 * Poll the management queue for frames; they 1245 * have priority over normal data frames. 1246 */ 1247 IF_DEQUEUE(&ic->ic_mgtq, m); 1248 if (m == NULL) { 1249 /* 1250 * No data frames go out unless we're associated. 1251 */ 1252 if (ic->ic_state != IEEE80211_S_RUN) { 1253 DPRINTF(sc, ATH_DEBUG_XMIT, 1254 "%s: discard data packet, state %s\n", 1255 __func__, 1256 ieee80211_state_name[ic->ic_state]); 1257 sc->sc_stats.ast_tx_discard++; 1258 ATH_TXBUF_LOCK(sc); 1259 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1260 ATH_TXBUF_UNLOCK(sc); 1261 break; 1262 } 1263 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1264 if (m == NULL) { 1265 ATH_TXBUF_LOCK(sc); 1266 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1267 ATH_TXBUF_UNLOCK(sc); 1268 break; 1269 } 1270 STAILQ_INIT(&frags); 1271 /* 1272 * Find the node for the destination so we can do 1273 * things like power save and fast frames aggregation. 1274 */ 1275 if (m->m_len < sizeof(struct ether_header) && 1276 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1277 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1278 ni = NULL; 1279 goto bad; 1280 } 1281 eh = mtod(m, struct ether_header *); 1282 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1283 if (ni == NULL) { 1284 /* NB: ieee80211_find_txnode does stat+msg */ 1285 m_freem(m); 1286 goto bad; 1287 } 1288 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1289 (m->m_flags & M_PWR_SAV) == 0) { 1290 /* 1291 * Station in power save mode; pass the frame 1292 * to the 802.11 layer and continue. We'll get 1293 * the frame back when the time is right. 1294 */ 1295 ieee80211_pwrsave(ic, ni, m); 1296 goto reclaim; 1297 } 1298 /* calculate priority so we can find the tx queue */ 1299 if (ieee80211_classify(ic, m, ni)) { 1300 DPRINTF(sc, ATH_DEBUG_XMIT, 1301 "%s: discard, classification failure\n", 1302 __func__); 1303 m_freem(m); 1304 goto bad; 1305 } 1306 ifp->if_opackets++; 1307 1308 #if NBPFILTER > 0 1309 if (ifp->if_bpf) 1310 bpf_mtap(ifp->if_bpf, m); 1311 #endif 1312 /* 1313 * Encapsulate the packet in prep for transmission. 1314 */ 1315 m = ieee80211_encap(ic, m, ni); 1316 if (m == NULL) { 1317 DPRINTF(sc, ATH_DEBUG_XMIT, 1318 "%s: encapsulation failure\n", 1319 __func__); 1320 sc->sc_stats.ast_tx_encap++; 1321 goto bad; 1322 } 1323 /* 1324 * Check for fragmentation. If this has frame 1325 * has been broken up verify we have enough 1326 * buffers to send all the fragments so all 1327 * go out or none... 1328 */ 1329 if ((m->m_flags & M_FRAG) && 1330 !ath_txfrag_setup(sc, &frags, m, ni)) { 1331 DPRINTF(sc, ATH_DEBUG_ANY, 1332 "%s: out of txfrag buffers\n", __func__); 1333 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1334 ath_freetx(m); 1335 goto bad; 1336 } 1337 } else { 1338 /* 1339 * Hack! The referenced node pointer is in the 1340 * rcvif field of the packet header. This is 1341 * placed there by ieee80211_mgmt_output because 1342 * we need to hold the reference with the frame 1343 * and there's no other way (other than packet 1344 * tags which we consider too expensive to use) 1345 * to pass it along. 1346 */ 1347 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1348 m->m_pkthdr.rcvif = NULL; 1349 1350 wh = mtod(m, struct ieee80211_frame *); 1351 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1352 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1353 /* fill time stamp */ 1354 u_int64_t tsf; 1355 u_int32_t *tstamp; 1356 1357 tsf = ath_hal_gettsf64(ah); 1358 /* XXX: adjust 100us delay to xmit */ 1359 tsf += 100; 1360 tstamp = (u_int32_t *)&wh[1]; 1361 tstamp[0] = htole32(tsf & 0xffffffff); 1362 tstamp[1] = htole32(tsf >> 32); 1363 } 1364 sc->sc_stats.ast_tx_mgmt++; 1365 } 1366 1367 nextfrag: 1368 next = m->m_nextpkt; 1369 if (ath_tx_start(sc, ni, bf, m)) { 1370 bad: 1371 ifp->if_oerrors++; 1372 reclaim: 1373 ATH_TXBUF_LOCK(sc); 1374 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1375 ath_txfrag_cleanup(sc, &frags, ni); 1376 ATH_TXBUF_UNLOCK(sc); 1377 if (ni != NULL) 1378 ieee80211_free_node(ni); 1379 continue; 1380 } 1381 if (next != NULL) { 1382 m = next; 1383 bf = STAILQ_FIRST(&frags); 1384 KASSERT(bf != NULL, ("no buf for txfrag")); 1385 STAILQ_REMOVE_HEAD(&frags, bf_list); 1386 goto nextfrag; 1387 } 1388 1389 ifp->if_timer = 1; 1390 } 1391 } 1392 1393 static int 1394 ath_media_change(struct ifnet *ifp) 1395 { 1396 #define IS_UP(ifp) \ 1397 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1398 int error; 1399 1400 error = ieee80211_media_change(ifp); 1401 if (error == ENETRESET) { 1402 if (IS_UP(ifp)) 1403 ath_init(ifp->if_softc); /* XXX lose error */ 1404 error = 0; 1405 } 1406 return error; 1407 #undef IS_UP 1408 } 1409 1410 #ifdef AR_DEBUG 1411 static void 1412 ath_keyprint(const char *tag, u_int ix, 1413 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1414 { 1415 static const char *ciphers[] = { 1416 "WEP", 1417 "AES-OCB", 1418 "AES-CCM", 1419 "CKIP", 1420 "TKIP", 1421 "CLR", 1422 }; 1423 int i, n; 1424 1425 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1426 for (i = 0, n = hk->kv_len; i < n; i++) 1427 printf("%02x", hk->kv_val[i]); 1428 printf(" mac %s", ether_sprintf(mac)); 1429 if (hk->kv_type == HAL_CIPHER_TKIP) { 1430 printf(" mic "); 1431 for (i = 0; i < sizeof(hk->kv_mic); i++) 1432 printf("%02x", hk->kv_mic[i]); 1433 } 1434 printf("\n"); 1435 } 1436 #endif 1437 1438 /* 1439 * Set a TKIP key into the hardware. This handles the 1440 * potential distribution of key state to multiple key 1441 * cache slots for TKIP. 1442 */ 1443 static int 1444 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1445 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1446 { 1447 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1448 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1449 struct ath_hal *ah = sc->sc_ah; 1450 1451 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1452 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1453 KASSERT(sc->sc_splitmic, ("key cache !split")); 1454 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1455 /* 1456 * TX key goes at first index, RX key at the rx index. 1457 * The hal handles the MIC keys at index+64. 1458 */ 1459 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1460 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1461 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1462 return 0; 1463 1464 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1465 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1466 /* XXX delete tx key on failure? */ 1467 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1468 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1469 /* 1470 * TX/RX key goes at first index. 1471 * The hal handles the MIC keys are index+64. 1472 */ 1473 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1474 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1475 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1476 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1477 } 1478 return 0; 1479 #undef IEEE80211_KEY_XR 1480 } 1481 1482 /* 1483 * Set a net80211 key into the hardware. This handles the 1484 * potential distribution of key state to multiple key 1485 * cache slots for TKIP with hardware MIC support. 1486 */ 1487 static int 1488 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1489 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1490 struct ieee80211_node *bss) 1491 { 1492 #define N(a) (sizeof(a)/sizeof(a[0])) 1493 static const u_int8_t ciphermap[] = { 1494 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1495 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1496 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1497 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1498 (u_int8_t) -1, /* 4 is not allocated */ 1499 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1500 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1501 }; 1502 struct ath_hal *ah = sc->sc_ah; 1503 const struct ieee80211_cipher *cip = k->wk_cipher; 1504 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1505 const u_int8_t *mac; 1506 HAL_KEYVAL hk; 1507 1508 memset(&hk, 0, sizeof(hk)); 1509 /* 1510 * Software crypto uses a "clear key" so non-crypto 1511 * state kept in the key cache are maintained and 1512 * so that rx frames have an entry to match. 1513 */ 1514 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1515 KASSERT(cip->ic_cipher < N(ciphermap), 1516 ("invalid cipher type %u", cip->ic_cipher)); 1517 hk.kv_type = ciphermap[cip->ic_cipher]; 1518 hk.kv_len = k->wk_keylen; 1519 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1520 } else 1521 hk.kv_type = HAL_CIPHER_CLR; 1522 1523 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1524 /* 1525 * Group keys on hardware that supports multicast frame 1526 * key search use a mac that is the sender's address with 1527 * the high bit set instead of the app-specified address. 1528 */ 1529 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1530 gmac[0] |= 0x80; 1531 mac = gmac; 1532 } else 1533 mac = mac0; 1534 1535 if (hk.kv_type == HAL_CIPHER_TKIP && 1536 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1537 sc->sc_splitmic) { 1538 return ath_keyset_tkip(sc, k, &hk, mac); 1539 } else { 1540 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1541 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1542 } 1543 #undef N 1544 } 1545 1546 /* 1547 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1548 * each key, one for decrypt/encrypt and the other for the MIC. 1549 */ 1550 static u_int16_t 1551 key_alloc_2pair(struct ath_softc *sc, 1552 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1553 { 1554 #define N(a) (sizeof(a)/sizeof(a[0])) 1555 u_int i, keyix; 1556 1557 KASSERT(sc->sc_splitmic, ("key cache !split")); 1558 /* XXX could optimize */ 1559 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1560 u_int8_t b = sc->sc_keymap[i]; 1561 if (b != 0xff) { 1562 /* 1563 * One or more slots in this byte are free. 1564 */ 1565 keyix = i*NBBY; 1566 while (b & 1) { 1567 again: 1568 keyix++; 1569 b >>= 1; 1570 } 1571 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1572 if (isset(sc->sc_keymap, keyix+32) || 1573 isset(sc->sc_keymap, keyix+64) || 1574 isset(sc->sc_keymap, keyix+32+64)) { 1575 /* full pair unavailable */ 1576 /* XXX statistic */ 1577 if (keyix == (i+1)*NBBY) { 1578 /* no slots were appropriate, advance */ 1579 continue; 1580 } 1581 goto again; 1582 } 1583 setbit(sc->sc_keymap, keyix); 1584 setbit(sc->sc_keymap, keyix+64); 1585 setbit(sc->sc_keymap, keyix+32); 1586 setbit(sc->sc_keymap, keyix+32+64); 1587 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1588 "%s: key pair %u,%u %u,%u\n", 1589 __func__, keyix, keyix+64, 1590 keyix+32, keyix+32+64); 1591 *txkeyix = keyix; 1592 *rxkeyix = keyix+32; 1593 return 1; 1594 } 1595 } 1596 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1597 return 0; 1598 #undef N 1599 } 1600 1601 /* 1602 * Allocate a single key cache slot. 1603 */ 1604 static int 1605 key_alloc_single(struct ath_softc *sc, 1606 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1607 { 1608 #define N(a) (sizeof(a)/sizeof(a[0])) 1609 u_int i, keyix; 1610 1611 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1612 for (i = 0; i < N(sc->sc_keymap); i++) { 1613 u_int8_t b = sc->sc_keymap[i]; 1614 if (b != 0xff) { 1615 /* 1616 * One or more slots are free. 1617 */ 1618 keyix = i*NBBY; 1619 while (b & 1) 1620 keyix++, b >>= 1; 1621 setbit(sc->sc_keymap, keyix); 1622 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1623 __func__, keyix); 1624 *txkeyix = *rxkeyix = keyix; 1625 return 1; 1626 } 1627 } 1628 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1629 return 0; 1630 #undef N 1631 } 1632 1633 /* 1634 * Allocate one or more key cache slots for a uniacst key. The 1635 * key itself is needed only to identify the cipher. For hardware 1636 * TKIP with split cipher+MIC keys we allocate two key cache slot 1637 * pairs so that we can setup separate TX and RX MIC keys. Note 1638 * that the MIC key for a TKIP key at slot i is assumed by the 1639 * hardware to be at slot i+64. This limits TKIP keys to the first 1640 * 64 entries. 1641 */ 1642 static int 1643 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1644 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1645 { 1646 struct ath_softc *sc = ic->ic_ifp->if_softc; 1647 1648 /* 1649 * Group key allocation must be handled specially for 1650 * parts that do not support multicast key cache search 1651 * functionality. For those parts the key id must match 1652 * the h/w key index so lookups find the right key. On 1653 * parts w/ the key search facility we install the sender's 1654 * mac address (with the high bit set) and let the hardware 1655 * find the key w/o using the key id. This is preferred as 1656 * it permits us to support multiple users for adhoc and/or 1657 * multi-station operation. 1658 */ 1659 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1660 if (!(&ic->ic_nw_keys[0] <= k && 1661 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1662 /* should not happen */ 1663 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1664 "%s: bogus group key\n", __func__); 1665 return 0; 1666 } 1667 /* 1668 * XXX we pre-allocate the global keys so 1669 * have no way to check if they've already been allocated. 1670 */ 1671 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1672 return 1; 1673 } 1674 1675 /* 1676 * We allocate two pair for TKIP when using the h/w to do 1677 * the MIC. For everything else, including software crypto, 1678 * we allocate a single entry. Note that s/w crypto requires 1679 * a pass-through slot on the 5211 and 5212. The 5210 does 1680 * not support pass-through cache entries and we map all 1681 * those requests to slot 0. 1682 */ 1683 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1684 return key_alloc_single(sc, keyix, rxkeyix); 1685 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1686 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1687 return key_alloc_2pair(sc, keyix, rxkeyix); 1688 } else { 1689 return key_alloc_single(sc, keyix, rxkeyix); 1690 } 1691 } 1692 1693 /* 1694 * Delete an entry in the key cache allocated by ath_key_alloc. 1695 */ 1696 static int 1697 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1698 { 1699 struct ath_softc *sc = ic->ic_ifp->if_softc; 1700 struct ath_hal *ah = sc->sc_ah; 1701 const struct ieee80211_cipher *cip = k->wk_cipher; 1702 u_int keyix = k->wk_keyix; 1703 1704 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1705 1706 if (!device_has_power(&sc->sc_dev)) { 1707 aprint_error_dev(&sc->sc_dev, "deleting keyix %d w/o power\n", 1708 k->wk_keyix); 1709 } 1710 1711 ath_hal_keyreset(ah, keyix); 1712 /* 1713 * Handle split tx/rx keying required for TKIP with h/w MIC. 1714 */ 1715 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1716 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1717 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1718 if (keyix >= IEEE80211_WEP_NKID) { 1719 /* 1720 * Don't touch keymap entries for global keys so 1721 * they are never considered for dynamic allocation. 1722 */ 1723 clrbit(sc->sc_keymap, keyix); 1724 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1725 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1726 sc->sc_splitmic) { 1727 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1728 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1729 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1730 } 1731 } 1732 return 1; 1733 } 1734 1735 /* 1736 * Set the key cache contents for the specified key. Key cache 1737 * slot(s) must already have been allocated by ath_key_alloc. 1738 */ 1739 static int 1740 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1741 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1742 { 1743 struct ath_softc *sc = ic->ic_ifp->if_softc; 1744 1745 if (!device_has_power(&sc->sc_dev)) { 1746 aprint_error_dev(&sc->sc_dev, "setting keyix %d w/o power\n", 1747 k->wk_keyix); 1748 } 1749 return ath_keyset(sc, k, mac, ic->ic_bss); 1750 } 1751 1752 /* 1753 * Block/unblock tx+rx processing while a key change is done. 1754 * We assume the caller serializes key management operations 1755 * so we only need to worry about synchronization with other 1756 * uses that originate in the driver. 1757 */ 1758 static void 1759 ath_key_update_begin(struct ieee80211com *ic) 1760 { 1761 struct ifnet *ifp = ic->ic_ifp; 1762 struct ath_softc *sc = ifp->if_softc; 1763 1764 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1765 #if 0 1766 tasklet_disable(&sc->sc_rxtq); 1767 #endif 1768 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1769 } 1770 1771 static void 1772 ath_key_update_end(struct ieee80211com *ic) 1773 { 1774 struct ifnet *ifp = ic->ic_ifp; 1775 struct ath_softc *sc = ifp->if_softc; 1776 1777 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1778 IF_UNLOCK(&ifp->if_snd); 1779 #if 0 1780 tasklet_enable(&sc->sc_rxtq); 1781 #endif 1782 } 1783 1784 /* 1785 * Calculate the receive filter according to the 1786 * operating mode and state: 1787 * 1788 * o always accept unicast, broadcast, and multicast traffic 1789 * o maintain current state of phy error reception (the hal 1790 * may enable phy error frames for noise immunity work) 1791 * o probe request frames are accepted only when operating in 1792 * hostap, adhoc, or monitor modes 1793 * o enable promiscuous mode according to the interface state 1794 * o accept beacons: 1795 * - when operating in adhoc mode so the 802.11 layer creates 1796 * node table entries for peers, 1797 * - when operating in station mode for collecting rssi data when 1798 * the station is otherwise quiet, or 1799 * - when scanning 1800 */ 1801 static u_int32_t 1802 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1803 { 1804 struct ieee80211com *ic = &sc->sc_ic; 1805 struct ath_hal *ah = sc->sc_ah; 1806 struct ifnet *ifp = &sc->sc_if; 1807 u_int32_t rfilt; 1808 1809 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1810 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1811 if (ic->ic_opmode != IEEE80211_M_STA) 1812 rfilt |= HAL_RX_FILTER_PROBEREQ; 1813 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1814 (ifp->if_flags & IFF_PROMISC)) 1815 rfilt |= HAL_RX_FILTER_PROM; 1816 if (ic->ic_opmode == IEEE80211_M_STA || 1817 ic->ic_opmode == IEEE80211_M_IBSS || 1818 state == IEEE80211_S_SCAN) 1819 rfilt |= HAL_RX_FILTER_BEACON; 1820 return rfilt; 1821 } 1822 1823 static void 1824 ath_mode_init(struct ath_softc *sc) 1825 { 1826 struct ifnet *ifp = &sc->sc_if; 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ath_hal *ah = sc->sc_ah; 1829 struct ether_multi *enm; 1830 struct ether_multistep estep; 1831 u_int32_t rfilt, mfilt[2], val; 1832 int i; 1833 uint8_t pos; 1834 1835 /* configure rx filter */ 1836 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1837 ath_hal_setrxfilter(ah, rfilt); 1838 1839 /* configure operational mode */ 1840 ath_hal_setopmode(ah); 1841 1842 /* Write keys to hardware; it may have been powered down. */ 1843 ath_key_update_begin(ic); 1844 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1845 ath_key_set(ic, 1846 &ic->ic_crypto.cs_nw_keys[i], 1847 ic->ic_myaddr); 1848 } 1849 ath_key_update_end(ic); 1850 1851 /* 1852 * Handle any link-level address change. Note that we only 1853 * need to force ic_myaddr; any other addresses are handled 1854 * as a byproduct of the ifnet code marking the interface 1855 * down then up. 1856 * 1857 * XXX should get from lladdr instead of arpcom but that's more work 1858 */ 1859 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1860 ath_hal_setmac(ah, ic->ic_myaddr); 1861 1862 /* calculate and install multicast filter */ 1863 ifp->if_flags &= ~IFF_ALLMULTI; 1864 mfilt[0] = mfilt[1] = 0; 1865 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1866 while (enm != NULL) { 1867 void *dl; 1868 /* XXX Punt on ranges. */ 1869 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1870 mfilt[0] = mfilt[1] = 0xffffffff; 1871 ifp->if_flags |= IFF_ALLMULTI; 1872 break; 1873 } 1874 dl = enm->enm_addrlo; 1875 val = LE_READ_4((char *)dl + 0); 1876 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1877 val = LE_READ_4((char *)dl + 3); 1878 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1879 pos &= 0x3f; 1880 mfilt[pos / 32] |= (1 << (pos % 32)); 1881 1882 ETHER_NEXT_MULTI(estep, enm); 1883 } 1884 1885 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1886 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1887 __func__, rfilt, mfilt[0], mfilt[1]); 1888 } 1889 1890 /* 1891 * Set the slot time based on the current setting. 1892 */ 1893 static void 1894 ath_setslottime(struct ath_softc *sc) 1895 { 1896 struct ieee80211com *ic = &sc->sc_ic; 1897 struct ath_hal *ah = sc->sc_ah; 1898 1899 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1900 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1901 else 1902 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1903 sc->sc_updateslot = OK; 1904 } 1905 1906 /* 1907 * Callback from the 802.11 layer to update the 1908 * slot time based on the current setting. 1909 */ 1910 static void 1911 ath_updateslot(struct ifnet *ifp) 1912 { 1913 struct ath_softc *sc = ifp->if_softc; 1914 struct ieee80211com *ic = &sc->sc_ic; 1915 1916 /* 1917 * When not coordinating the BSS, change the hardware 1918 * immediately. For other operation we defer the change 1919 * until beacon updates have propagated to the stations. 1920 */ 1921 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1922 sc->sc_updateslot = UPDATE; 1923 else 1924 ath_setslottime(sc); 1925 } 1926 1927 /* 1928 * Setup a h/w transmit queue for beacons. 1929 */ 1930 static int 1931 ath_beaconq_setup(struct ath_hal *ah) 1932 { 1933 HAL_TXQ_INFO qi; 1934 1935 memset(&qi, 0, sizeof(qi)); 1936 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1937 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1938 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1939 /* NB: for dynamic turbo, don't enable any other interrupts */ 1940 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1941 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1942 } 1943 1944 /* 1945 * Setup the transmit queue parameters for the beacon queue. 1946 */ 1947 static int 1948 ath_beaconq_config(struct ath_softc *sc) 1949 { 1950 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct ath_hal *ah = sc->sc_ah; 1953 HAL_TXQ_INFO qi; 1954 1955 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1956 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1957 /* 1958 * Always burst out beacon and CAB traffic. 1959 */ 1960 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1961 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1962 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1963 } else { 1964 struct wmeParams *wmep = 1965 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1966 /* 1967 * Adhoc mode; important thing is to use 2x cwmin. 1968 */ 1969 qi.tqi_aifs = wmep->wmep_aifsn; 1970 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1971 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1972 } 1973 1974 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1975 device_printf(&sc->sc_dev, "unable to update parameters for " 1976 "beacon hardware queue!\n"); 1977 return 0; 1978 } else { 1979 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1980 return 1; 1981 } 1982 #undef ATH_EXPONENT_TO_VALUE 1983 } 1984 1985 /* 1986 * Allocate and setup an initial beacon frame. 1987 */ 1988 static int 1989 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1990 { 1991 struct ieee80211com *ic = ni->ni_ic; 1992 struct ath_buf *bf; 1993 struct mbuf *m; 1994 int error; 1995 1996 bf = STAILQ_FIRST(&sc->sc_bbuf); 1997 if (bf == NULL) { 1998 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1999 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2000 return ENOMEM; /* XXX */ 2001 } 2002 /* 2003 * NB: the beacon data buffer must be 32-bit aligned; 2004 * we assume the mbuf routines will return us something 2005 * with this alignment (perhaps should assert). 2006 */ 2007 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2008 if (m == NULL) { 2009 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2010 __func__); 2011 sc->sc_stats.ast_be_nombuf++; 2012 return ENOMEM; 2013 } 2014 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2015 BUS_DMA_NOWAIT); 2016 if (error == 0) { 2017 bf->bf_m = m; 2018 bf->bf_node = ieee80211_ref_node(ni); 2019 } else { 2020 m_freem(m); 2021 } 2022 return error; 2023 } 2024 2025 /* 2026 * Setup the beacon frame for transmit. 2027 */ 2028 static void 2029 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2030 { 2031 #define USE_SHPREAMBLE(_ic) \ 2032 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2033 == IEEE80211_F_SHPREAMBLE) 2034 struct ieee80211_node *ni = bf->bf_node; 2035 struct ieee80211com *ic = ni->ni_ic; 2036 struct mbuf *m = bf->bf_m; 2037 struct ath_hal *ah = sc->sc_ah; 2038 struct ath_desc *ds; 2039 int flags, antenna; 2040 const HAL_RATE_TABLE *rt; 2041 u_int8_t rix, rate; 2042 2043 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2044 __func__, m, m->m_len); 2045 2046 /* setup descriptors */ 2047 ds = bf->bf_desc; 2048 2049 flags = HAL_TXDESC_NOACK; 2050 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2051 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2052 flags |= HAL_TXDESC_VEOL; 2053 /* 2054 * Let hardware handle antenna switching unless 2055 * the user has selected a transmit antenna 2056 * (sc_txantenna is not 0). 2057 */ 2058 antenna = sc->sc_txantenna; 2059 } else { 2060 ds->ds_link = 0; 2061 /* 2062 * Switch antenna every 4 beacons, unless the user 2063 * has selected a transmit antenna (sc_txantenna 2064 * is not 0). 2065 * 2066 * XXX assumes two antenna 2067 */ 2068 if (sc->sc_txantenna == 0) 2069 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2070 else 2071 antenna = sc->sc_txantenna; 2072 } 2073 2074 KASSERT(bf->bf_nseg == 1, 2075 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2076 ds->ds_data = bf->bf_segs[0].ds_addr; 2077 /* 2078 * Calculate rate code. 2079 * XXX everything at min xmit rate 2080 */ 2081 rix = sc->sc_minrateix; 2082 rt = sc->sc_currates; 2083 rate = rt->info[rix].rateCode; 2084 if (USE_SHPREAMBLE(ic)) 2085 rate |= rt->info[rix].shortPreamble; 2086 ath_hal_setuptxdesc(ah, ds 2087 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2088 , sizeof(struct ieee80211_frame)/* header length */ 2089 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2090 , ni->ni_txpower /* txpower XXX */ 2091 , rate, 1 /* series 0 rate/tries */ 2092 , HAL_TXKEYIX_INVALID /* no encryption */ 2093 , antenna /* antenna mode */ 2094 , flags /* no ack, veol for beacons */ 2095 , 0 /* rts/cts rate */ 2096 , 0 /* rts/cts duration */ 2097 ); 2098 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2099 ath_hal_filltxdesc(ah, ds 2100 , roundup(m->m_len, 4) /* buffer length */ 2101 , AH_TRUE /* first segment */ 2102 , AH_TRUE /* last segment */ 2103 , ds /* first descriptor */ 2104 ); 2105 2106 /* NB: The desc swap function becomes void, 2107 * if descriptor swapping is not enabled 2108 */ 2109 ath_desc_swap(ds); 2110 2111 #undef USE_SHPREAMBLE 2112 } 2113 2114 /* 2115 * Transmit a beacon frame at SWBA. Dynamic updates to the 2116 * frame contents are done as needed and the slot time is 2117 * also adjusted based on current state. 2118 */ 2119 static void 2120 ath_beacon_proc(void *arg, int pending) 2121 { 2122 struct ath_softc *sc = arg; 2123 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2124 struct ieee80211_node *ni = bf->bf_node; 2125 struct ieee80211com *ic = ni->ni_ic; 2126 struct ath_hal *ah = sc->sc_ah; 2127 struct mbuf *m; 2128 int ncabq, error, otherant; 2129 2130 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2131 __func__, pending); 2132 2133 if (ic->ic_opmode == IEEE80211_M_STA || 2134 ic->ic_opmode == IEEE80211_M_MONITOR || 2135 bf == NULL || bf->bf_m == NULL) { 2136 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2137 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2138 return; 2139 } 2140 /* 2141 * Check if the previous beacon has gone out. If 2142 * not don't try to post another, skip this period 2143 * and wait for the next. Missed beacons indicate 2144 * a problem and should not occur. If we miss too 2145 * many consecutive beacons reset the device. 2146 */ 2147 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2148 sc->sc_bmisscount++; 2149 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2150 "%s: missed %u consecutive beacons\n", 2151 __func__, sc->sc_bmisscount); 2152 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2153 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2154 return; 2155 } 2156 if (sc->sc_bmisscount != 0) { 2157 DPRINTF(sc, ATH_DEBUG_BEACON, 2158 "%s: resume beacon xmit after %u misses\n", 2159 __func__, sc->sc_bmisscount); 2160 sc->sc_bmisscount = 0; 2161 } 2162 2163 /* 2164 * Update dynamic beacon contents. If this returns 2165 * non-zero then we need to remap the memory because 2166 * the beacon frame changed size (probably because 2167 * of the TIM bitmap). 2168 */ 2169 m = bf->bf_m; 2170 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2171 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2172 /* XXX too conservative? */ 2173 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2174 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2175 BUS_DMA_NOWAIT); 2176 if (error != 0) { 2177 if_printf(&sc->sc_if, 2178 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2179 __func__, error); 2180 return; 2181 } 2182 } 2183 2184 /* 2185 * Handle slot time change when a non-ERP station joins/leaves 2186 * an 11g network. The 802.11 layer notifies us via callback, 2187 * we mark updateslot, then wait one beacon before effecting 2188 * the change. This gives associated stations at least one 2189 * beacon interval to note the state change. 2190 */ 2191 /* XXX locking */ 2192 if (sc->sc_updateslot == UPDATE) 2193 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2194 else if (sc->sc_updateslot == COMMIT) 2195 ath_setslottime(sc); /* commit change to h/w */ 2196 2197 /* 2198 * Check recent per-antenna transmit statistics and flip 2199 * the default antenna if noticeably more frames went out 2200 * on the non-default antenna. 2201 * XXX assumes 2 anntenae 2202 */ 2203 otherant = sc->sc_defant & 1 ? 2 : 1; 2204 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2205 ath_setdefantenna(sc, otherant); 2206 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2207 2208 /* 2209 * Construct tx descriptor. 2210 */ 2211 ath_beacon_setup(sc, bf); 2212 2213 /* 2214 * Stop any current dma and put the new frame on the queue. 2215 * This should never fail since we check above that no frames 2216 * are still pending on the queue. 2217 */ 2218 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2219 DPRINTF(sc, ATH_DEBUG_ANY, 2220 "%s: beacon queue %u did not stop?\n", 2221 __func__, sc->sc_bhalq); 2222 } 2223 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2224 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2225 2226 /* 2227 * Enable the CAB queue before the beacon queue to 2228 * insure cab frames are triggered by this beacon. 2229 */ 2230 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2231 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2232 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2233 ath_hal_txstart(ah, sc->sc_bhalq); 2234 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2235 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2236 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2237 2238 sc->sc_stats.ast_be_xmit++; 2239 } 2240 2241 /* 2242 * Reset the hardware after detecting beacons have stopped. 2243 */ 2244 static void 2245 ath_bstuck_proc(void *arg, int pending) 2246 { 2247 struct ath_softc *sc = arg; 2248 struct ifnet *ifp = &sc->sc_if; 2249 2250 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2251 sc->sc_bmisscount); 2252 ath_reset(ifp); 2253 } 2254 2255 /* 2256 * Reclaim beacon resources. 2257 */ 2258 static void 2259 ath_beacon_free(struct ath_softc *sc) 2260 { 2261 struct ath_buf *bf; 2262 2263 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2264 if (bf->bf_m != NULL) { 2265 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2266 m_freem(bf->bf_m); 2267 bf->bf_m = NULL; 2268 } 2269 if (bf->bf_node != NULL) { 2270 ieee80211_free_node(bf->bf_node); 2271 bf->bf_node = NULL; 2272 } 2273 } 2274 } 2275 2276 /* 2277 * Configure the beacon and sleep timers. 2278 * 2279 * When operating as an AP this resets the TSF and sets 2280 * up the hardware to notify us when we need to issue beacons. 2281 * 2282 * When operating in station mode this sets up the beacon 2283 * timers according to the timestamp of the last received 2284 * beacon and the current TSF, configures PCF and DTIM 2285 * handling, programs the sleep registers so the hardware 2286 * will wakeup in time to receive beacons, and configures 2287 * the beacon miss handling so we'll receive a BMISS 2288 * interrupt when we stop seeing beacons from the AP 2289 * we've associated with. 2290 */ 2291 static void 2292 ath_beacon_config(struct ath_softc *sc) 2293 { 2294 #define TSF_TO_TU(_h,_l) \ 2295 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2296 #define FUDGE 2 2297 struct ath_hal *ah = sc->sc_ah; 2298 struct ieee80211com *ic = &sc->sc_ic; 2299 struct ieee80211_node *ni = ic->ic_bss; 2300 u_int32_t nexttbtt, intval, tsftu; 2301 u_int64_t tsf; 2302 2303 /* extract tstamp from last beacon and convert to TU */ 2304 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2305 LE_READ_4(ni->ni_tstamp.data)); 2306 /* NB: the beacon interval is kept internally in TU's */ 2307 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2308 if (nexttbtt == 0) /* e.g. for ap mode */ 2309 nexttbtt = intval; 2310 else if (intval) /* NB: can be 0 for monitor mode */ 2311 nexttbtt = roundup(nexttbtt, intval); 2312 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2313 __func__, nexttbtt, intval, ni->ni_intval); 2314 if (ic->ic_opmode == IEEE80211_M_STA) { 2315 HAL_BEACON_STATE bs; 2316 int dtimperiod, dtimcount; 2317 int cfpperiod, cfpcount; 2318 2319 /* 2320 * Setup dtim and cfp parameters according to 2321 * last beacon we received (which may be none). 2322 */ 2323 dtimperiod = ni->ni_dtim_period; 2324 if (dtimperiod <= 0) /* NB: 0 if not known */ 2325 dtimperiod = 1; 2326 dtimcount = ni->ni_dtim_count; 2327 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2328 dtimcount = 0; /* XXX? */ 2329 cfpperiod = 1; /* NB: no PCF support yet */ 2330 cfpcount = 0; 2331 /* 2332 * Pull nexttbtt forward to reflect the current 2333 * TSF and calculate dtim+cfp state for the result. 2334 */ 2335 tsf = ath_hal_gettsf64(ah); 2336 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2337 do { 2338 nexttbtt += intval; 2339 if (--dtimcount < 0) { 2340 dtimcount = dtimperiod - 1; 2341 if (--cfpcount < 0) 2342 cfpcount = cfpperiod - 1; 2343 } 2344 } while (nexttbtt < tsftu); 2345 memset(&bs, 0, sizeof(bs)); 2346 bs.bs_intval = intval; 2347 bs.bs_nexttbtt = nexttbtt; 2348 bs.bs_dtimperiod = dtimperiod*intval; 2349 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2350 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2351 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2352 bs.bs_cfpmaxduration = 0; 2353 #if 0 2354 /* 2355 * The 802.11 layer records the offset to the DTIM 2356 * bitmap while receiving beacons; use it here to 2357 * enable h/w detection of our AID being marked in 2358 * the bitmap vector (to indicate frames for us are 2359 * pending at the AP). 2360 * XXX do DTIM handling in s/w to WAR old h/w bugs 2361 * XXX enable based on h/w rev for newer chips 2362 */ 2363 bs.bs_timoffset = ni->ni_timoff; 2364 #endif 2365 /* 2366 * Calculate the number of consecutive beacons to miss 2367 * before taking a BMISS interrupt. The configuration 2368 * is specified in ms, so we need to convert that to 2369 * TU's and then calculate based on the beacon interval. 2370 * Note that we clamp the result to at most 10 beacons. 2371 */ 2372 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2373 if (bs.bs_bmissthreshold > 10) 2374 bs.bs_bmissthreshold = 10; 2375 else if (bs.bs_bmissthreshold <= 0) 2376 bs.bs_bmissthreshold = 1; 2377 2378 /* 2379 * Calculate sleep duration. The configuration is 2380 * given in ms. We insure a multiple of the beacon 2381 * period is used. Also, if the sleep duration is 2382 * greater than the DTIM period then it makes senses 2383 * to make it a multiple of that. 2384 * 2385 * XXX fixed at 100ms 2386 */ 2387 bs.bs_sleepduration = 2388 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2389 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2390 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2391 2392 DPRINTF(sc, ATH_DEBUG_BEACON, 2393 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2394 , __func__ 2395 , tsf, tsftu 2396 , bs.bs_intval 2397 , bs.bs_nexttbtt 2398 , bs.bs_dtimperiod 2399 , bs.bs_nextdtim 2400 , bs.bs_bmissthreshold 2401 , bs.bs_sleepduration 2402 , bs.bs_cfpperiod 2403 , bs.bs_cfpmaxduration 2404 , bs.bs_cfpnext 2405 , bs.bs_timoffset 2406 ); 2407 ath_hal_intrset(ah, 0); 2408 ath_hal_beacontimers(ah, &bs); 2409 sc->sc_imask |= HAL_INT_BMISS; 2410 ath_hal_intrset(ah, sc->sc_imask); 2411 } else { 2412 ath_hal_intrset(ah, 0); 2413 if (nexttbtt == intval) 2414 intval |= HAL_BEACON_RESET_TSF; 2415 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2416 /* 2417 * In IBSS mode enable the beacon timers but only 2418 * enable SWBA interrupts if we need to manually 2419 * prepare beacon frames. Otherwise we use a 2420 * self-linked tx descriptor and let the hardware 2421 * deal with things. 2422 */ 2423 intval |= HAL_BEACON_ENA; 2424 if (!sc->sc_hasveol) 2425 sc->sc_imask |= HAL_INT_SWBA; 2426 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2427 /* 2428 * Pull nexttbtt forward to reflect 2429 * the current TSF. 2430 */ 2431 tsf = ath_hal_gettsf64(ah); 2432 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2433 do { 2434 nexttbtt += intval; 2435 } while (nexttbtt < tsftu); 2436 } 2437 ath_beaconq_config(sc); 2438 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2439 /* 2440 * In AP mode we enable the beacon timers and 2441 * SWBA interrupts to prepare beacon frames. 2442 */ 2443 intval |= HAL_BEACON_ENA; 2444 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2445 ath_beaconq_config(sc); 2446 } 2447 ath_hal_beaconinit(ah, nexttbtt, intval); 2448 sc->sc_bmisscount = 0; 2449 ath_hal_intrset(ah, sc->sc_imask); 2450 /* 2451 * When using a self-linked beacon descriptor in 2452 * ibss mode load it once here. 2453 */ 2454 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2455 ath_beacon_proc(sc, 0); 2456 } 2457 sc->sc_syncbeacon = 0; 2458 #undef UNDEF 2459 #undef TSF_TO_TU 2460 } 2461 2462 static int 2463 ath_descdma_setup(struct ath_softc *sc, 2464 struct ath_descdma *dd, ath_bufhead *head, 2465 const char *name, int nbuf, int ndesc) 2466 { 2467 #define DS2PHYS(_dd, _ds) \ 2468 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2469 struct ifnet *ifp = &sc->sc_if; 2470 struct ath_desc *ds; 2471 struct ath_buf *bf; 2472 int i, bsize, error; 2473 2474 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2475 __func__, name, nbuf, ndesc); 2476 2477 dd->dd_name = name; 2478 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2479 2480 /* 2481 * Setup DMA descriptor area. 2482 */ 2483 dd->dd_dmat = sc->sc_dmat; 2484 2485 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2486 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2487 2488 if (error != 0) { 2489 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2490 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2491 goto fail0; 2492 } 2493 2494 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2495 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2496 if (error != 0) { 2497 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2498 nbuf * ndesc, dd->dd_name, error); 2499 goto fail1; 2500 } 2501 2502 /* allocate descriptors */ 2503 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2504 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2505 if (error != 0) { 2506 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2507 "error %u\n", dd->dd_name, error); 2508 goto fail2; 2509 } 2510 2511 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2512 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2513 if (error != 0) { 2514 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2515 dd->dd_name, error); 2516 goto fail3; 2517 } 2518 2519 ds = dd->dd_desc; 2520 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2521 DPRINTF(sc, ATH_DEBUG_RESET, 2522 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2523 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2524 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2525 2526 /* allocate rx buffers */ 2527 bsize = sizeof(struct ath_buf) * nbuf; 2528 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2529 if (bf == NULL) { 2530 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2531 dd->dd_name, bsize); 2532 goto fail4; 2533 } 2534 dd->dd_bufptr = bf; 2535 2536 STAILQ_INIT(head); 2537 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2538 bf->bf_desc = ds; 2539 bf->bf_daddr = DS2PHYS(dd, ds); 2540 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2541 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2542 if (error != 0) { 2543 if_printf(ifp, "unable to create dmamap for %s " 2544 "buffer %u, error %u\n", dd->dd_name, i, error); 2545 ath_descdma_cleanup(sc, dd, head); 2546 return error; 2547 } 2548 STAILQ_INSERT_TAIL(head, bf, bf_list); 2549 } 2550 return 0; 2551 fail4: 2552 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2553 fail3: 2554 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2555 fail2: 2556 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2557 fail1: 2558 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2559 fail0: 2560 memset(dd, 0, sizeof(*dd)); 2561 return error; 2562 #undef DS2PHYS 2563 } 2564 2565 static void 2566 ath_descdma_cleanup(struct ath_softc *sc, 2567 struct ath_descdma *dd, ath_bufhead *head) 2568 { 2569 struct ath_buf *bf; 2570 struct ieee80211_node *ni; 2571 2572 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2573 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2574 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2575 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2576 2577 STAILQ_FOREACH(bf, head, bf_list) { 2578 if (bf->bf_m) { 2579 m_freem(bf->bf_m); 2580 bf->bf_m = NULL; 2581 } 2582 if (bf->bf_dmamap != NULL) { 2583 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2584 bf->bf_dmamap = NULL; 2585 } 2586 ni = bf->bf_node; 2587 bf->bf_node = NULL; 2588 if (ni != NULL) { 2589 /* 2590 * Reclaim node reference. 2591 */ 2592 ieee80211_free_node(ni); 2593 } 2594 } 2595 2596 STAILQ_INIT(head); 2597 free(dd->dd_bufptr, M_ATHDEV); 2598 memset(dd, 0, sizeof(*dd)); 2599 } 2600 2601 static int 2602 ath_desc_alloc(struct ath_softc *sc) 2603 { 2604 int error; 2605 2606 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2607 "rx", ath_rxbuf, 1); 2608 if (error != 0) 2609 return error; 2610 2611 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2612 "tx", ath_txbuf, ATH_TXDESC); 2613 if (error != 0) { 2614 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2615 return error; 2616 } 2617 2618 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2619 "beacon", 1, 1); 2620 if (error != 0) { 2621 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2622 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2623 return error; 2624 } 2625 return 0; 2626 } 2627 2628 static void 2629 ath_desc_free(struct ath_softc *sc) 2630 { 2631 2632 if (sc->sc_bdma.dd_desc_len != 0) 2633 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2634 if (sc->sc_txdma.dd_desc_len != 0) 2635 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2636 if (sc->sc_rxdma.dd_desc_len != 0) 2637 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2638 } 2639 2640 static struct ieee80211_node * 2641 ath_node_alloc(struct ieee80211_node_table *nt) 2642 { 2643 struct ieee80211com *ic = nt->nt_ic; 2644 struct ath_softc *sc = ic->ic_ifp->if_softc; 2645 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2646 struct ath_node *an; 2647 2648 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2649 if (an == NULL) { 2650 /* XXX stat+msg */ 2651 return NULL; 2652 } 2653 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2654 ath_rate_node_init(sc, an); 2655 2656 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2657 return &an->an_node; 2658 } 2659 2660 static void 2661 ath_node_free(struct ieee80211_node *ni) 2662 { 2663 struct ieee80211com *ic = ni->ni_ic; 2664 struct ath_softc *sc = ic->ic_ifp->if_softc; 2665 2666 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2667 2668 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2669 sc->sc_node_free(ni); 2670 } 2671 2672 static u_int8_t 2673 ath_node_getrssi(const struct ieee80211_node *ni) 2674 { 2675 #define HAL_EP_RND(x, mul) \ 2676 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2677 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2678 int32_t rssi; 2679 2680 /* 2681 * When only one frame is received there will be no state in 2682 * avgrssi so fallback on the value recorded by the 802.11 layer. 2683 */ 2684 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2685 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2686 else 2687 rssi = ni->ni_rssi; 2688 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2689 #undef HAL_EP_RND 2690 } 2691 2692 static int 2693 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2694 { 2695 struct ath_hal *ah = sc->sc_ah; 2696 int error; 2697 struct mbuf *m; 2698 struct ath_desc *ds; 2699 2700 m = bf->bf_m; 2701 if (m == NULL) { 2702 /* 2703 * NB: by assigning a page to the rx dma buffer we 2704 * implicitly satisfy the Atheros requirement that 2705 * this buffer be cache-line-aligned and sized to be 2706 * multiple of the cache line size. Not doing this 2707 * causes weird stuff to happen (for the 5210 at least). 2708 */ 2709 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2710 if (m == NULL) { 2711 DPRINTF(sc, ATH_DEBUG_ANY, 2712 "%s: no mbuf/cluster\n", __func__); 2713 sc->sc_stats.ast_rx_nombuf++; 2714 return ENOMEM; 2715 } 2716 bf->bf_m = m; 2717 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2718 2719 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2720 bf->bf_dmamap, m, 2721 BUS_DMA_NOWAIT); 2722 if (error != 0) { 2723 DPRINTF(sc, ATH_DEBUG_ANY, 2724 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2725 __func__, error); 2726 sc->sc_stats.ast_rx_busdma++; 2727 return error; 2728 } 2729 KASSERT(bf->bf_nseg == 1, 2730 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2731 } 2732 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2733 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2734 2735 /* 2736 * Setup descriptors. For receive we always terminate 2737 * the descriptor list with a self-linked entry so we'll 2738 * not get overrun under high load (as can happen with a 2739 * 5212 when ANI processing enables PHY error frames). 2740 * 2741 * To insure the last descriptor is self-linked we create 2742 * each descriptor as self-linked and add it to the end. As 2743 * each additional descriptor is added the previous self-linked 2744 * entry is ``fixed'' naturally. This should be safe even 2745 * if DMA is happening. When processing RX interrupts we 2746 * never remove/process the last, self-linked, entry on the 2747 * descriptor list. This insures the hardware always has 2748 * someplace to write a new frame. 2749 */ 2750 ds = bf->bf_desc; 2751 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2752 ds->ds_data = bf->bf_segs[0].ds_addr; 2753 ds->ds_vdata = mtod(m, void *); /* for radar */ 2754 ath_hal_setuprxdesc(ah, ds 2755 , m->m_len /* buffer size */ 2756 , 0 2757 ); 2758 2759 if (sc->sc_rxlink != NULL) 2760 *sc->sc_rxlink = bf->bf_daddr; 2761 sc->sc_rxlink = &ds->ds_link; 2762 return 0; 2763 } 2764 2765 /* 2766 * Extend 15-bit time stamp from rx descriptor to 2767 * a full 64-bit TSF using the specified TSF. 2768 */ 2769 static inline u_int64_t 2770 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2771 { 2772 if ((tsf & 0x7fff) < rstamp) 2773 tsf -= 0x8000; 2774 return ((tsf &~ 0x7fff) | rstamp); 2775 } 2776 2777 /* 2778 * Intercept management frames to collect beacon rssi data 2779 * and to do ibss merges. 2780 */ 2781 static void 2782 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2783 struct ieee80211_node *ni, 2784 int subtype, int rssi, u_int32_t rstamp) 2785 { 2786 struct ath_softc *sc = ic->ic_ifp->if_softc; 2787 2788 /* 2789 * Call up first so subsequent work can use information 2790 * potentially stored in the node (e.g. for ibss merge). 2791 */ 2792 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2793 switch (subtype) { 2794 case IEEE80211_FC0_SUBTYPE_BEACON: 2795 /* update rssi statistics for use by the hal */ 2796 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2797 if (sc->sc_syncbeacon && 2798 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2799 /* 2800 * Resync beacon timers using the tsf of the beacon 2801 * frame we just received. 2802 */ 2803 ath_beacon_config(sc); 2804 } 2805 /* fall thru... */ 2806 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2807 if (ic->ic_opmode == IEEE80211_M_IBSS && 2808 ic->ic_state == IEEE80211_S_RUN) { 2809 u_int64_t tsf = ath_extend_tsf(rstamp, 2810 ath_hal_gettsf64(sc->sc_ah)); 2811 2812 /* 2813 * Handle ibss merge as needed; check the tsf on the 2814 * frame before attempting the merge. The 802.11 spec 2815 * says the station should change it's bssid to match 2816 * the oldest station with the same ssid, where oldest 2817 * is determined by the tsf. Note that hardware 2818 * reconfiguration happens through callback to 2819 * ath_newstate as the state machine will go from 2820 * RUN -> RUN when this happens. 2821 */ 2822 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2823 DPRINTF(sc, ATH_DEBUG_STATE, 2824 "ibss merge, rstamp %u tsf %ju " 2825 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2826 (uintmax_t)ni->ni_tstamp.tsf); 2827 (void) ieee80211_ibss_merge(ni); 2828 } 2829 } 2830 break; 2831 } 2832 } 2833 2834 /* 2835 * Set the default antenna. 2836 */ 2837 static void 2838 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2839 { 2840 struct ath_hal *ah = sc->sc_ah; 2841 2842 /* XXX block beacon interrupts */ 2843 ath_hal_setdefantenna(ah, antenna); 2844 if (sc->sc_defant != antenna) 2845 sc->sc_stats.ast_ant_defswitch++; 2846 sc->sc_defant = antenna; 2847 sc->sc_rxotherant = 0; 2848 } 2849 2850 static void 2851 ath_rx_proc(void *arg, int npending) 2852 { 2853 #define PA2DESC(_sc, _pa) \ 2854 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2855 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2856 struct ath_softc *sc = arg; 2857 struct ath_buf *bf; 2858 struct ieee80211com *ic = &sc->sc_ic; 2859 struct ifnet *ifp = &sc->sc_if; 2860 struct ath_hal *ah = sc->sc_ah; 2861 struct ath_desc *ds; 2862 struct mbuf *m; 2863 struct ieee80211_node *ni; 2864 struct ath_node *an; 2865 int len, type, ngood; 2866 u_int phyerr; 2867 HAL_STATUS status; 2868 int16_t nf; 2869 u_int64_t tsf; 2870 2871 NET_LOCK_GIANT(); /* XXX */ 2872 2873 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2874 ngood = 0; 2875 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2876 tsf = ath_hal_gettsf64(ah); 2877 do { 2878 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2879 if (bf == NULL) { /* NB: shouldn't happen */ 2880 if_printf(ifp, "%s: no buffer!\n", __func__); 2881 break; 2882 } 2883 ds = bf->bf_desc; 2884 if (ds->ds_link == bf->bf_daddr) { 2885 /* NB: never process the self-linked entry at the end */ 2886 break; 2887 } 2888 m = bf->bf_m; 2889 if (m == NULL) { /* NB: shouldn't happen */ 2890 if_printf(ifp, "%s: no mbuf!\n", __func__); 2891 break; 2892 } 2893 /* XXX sync descriptor memory */ 2894 /* 2895 * Must provide the virtual address of the current 2896 * descriptor, the physical address, and the virtual 2897 * address of the next descriptor in the h/w chain. 2898 * This allows the HAL to look ahead to see if the 2899 * hardware is done with a descriptor by checking the 2900 * done bit in the following descriptor and the address 2901 * of the current descriptor the DMA engine is working 2902 * on. All this is necessary because of our use of 2903 * a self-linked list to avoid rx overruns. 2904 */ 2905 status = ath_hal_rxprocdesc(ah, ds, 2906 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2907 #ifdef AR_DEBUG 2908 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2909 ath_printrxbuf(bf, status == HAL_OK); 2910 #endif 2911 if (status == HAL_EINPROGRESS) 2912 break; 2913 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2914 if (ds->ds_rxstat.rs_more) { 2915 /* 2916 * Frame spans multiple descriptors; this 2917 * cannot happen yet as we don't support 2918 * jumbograms. If not in monitor mode, 2919 * discard the frame. 2920 */ 2921 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2922 sc->sc_stats.ast_rx_toobig++; 2923 goto rx_next; 2924 } 2925 /* fall thru for monitor mode handling... */ 2926 } else if (ds->ds_rxstat.rs_status != 0) { 2927 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2928 sc->sc_stats.ast_rx_crcerr++; 2929 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2930 sc->sc_stats.ast_rx_fifoerr++; 2931 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2932 sc->sc_stats.ast_rx_phyerr++; 2933 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2934 sc->sc_stats.ast_rx_phy[phyerr]++; 2935 goto rx_next; 2936 } 2937 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2938 /* 2939 * Decrypt error. If the error occurred 2940 * because there was no hardware key, then 2941 * let the frame through so the upper layers 2942 * can process it. This is necessary for 5210 2943 * parts which have no way to setup a ``clear'' 2944 * key cache entry. 2945 * 2946 * XXX do key cache faulting 2947 */ 2948 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2949 goto rx_accept; 2950 sc->sc_stats.ast_rx_badcrypt++; 2951 } 2952 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2953 sc->sc_stats.ast_rx_badmic++; 2954 /* 2955 * Do minimal work required to hand off 2956 * the 802.11 header for notifcation. 2957 */ 2958 /* XXX frag's and qos frames */ 2959 len = ds->ds_rxstat.rs_datalen; 2960 if (len >= sizeof (struct ieee80211_frame)) { 2961 bus_dmamap_sync(sc->sc_dmat, 2962 bf->bf_dmamap, 2963 0, bf->bf_dmamap->dm_mapsize, 2964 BUS_DMASYNC_POSTREAD); 2965 ieee80211_notify_michael_failure(ic, 2966 mtod(m, struct ieee80211_frame *), 2967 sc->sc_splitmic ? 2968 ds->ds_rxstat.rs_keyix-32 : 2969 ds->ds_rxstat.rs_keyix 2970 ); 2971 } 2972 } 2973 ifp->if_ierrors++; 2974 /* 2975 * Reject error frames, we normally don't want 2976 * to see them in monitor mode (in monitor mode 2977 * allow through packets that have crypto problems). 2978 */ 2979 if ((ds->ds_rxstat.rs_status &~ 2980 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2981 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2982 goto rx_next; 2983 } 2984 rx_accept: 2985 /* 2986 * Sync and unmap the frame. At this point we're 2987 * committed to passing the mbuf somewhere so clear 2988 * bf_m; this means a new sk_buff must be allocated 2989 * when the rx descriptor is setup again to receive 2990 * another frame. 2991 */ 2992 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2993 0, bf->bf_dmamap->dm_mapsize, 2994 BUS_DMASYNC_POSTREAD); 2995 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2996 bf->bf_m = NULL; 2997 2998 m->m_pkthdr.rcvif = ifp; 2999 len = ds->ds_rxstat.rs_datalen; 3000 m->m_pkthdr.len = m->m_len = len; 3001 3002 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3003 3004 #if NBPFILTER > 0 3005 if (sc->sc_drvbpf) { 3006 u_int8_t rix; 3007 3008 /* 3009 * Discard anything shorter than an ack or cts. 3010 */ 3011 if (len < IEEE80211_ACK_LEN) { 3012 DPRINTF(sc, ATH_DEBUG_RECV, 3013 "%s: runt packet %d\n", 3014 __func__, len); 3015 sc->sc_stats.ast_rx_tooshort++; 3016 m_freem(m); 3017 goto rx_next; 3018 } 3019 rix = ds->ds_rxstat.rs_rate; 3020 sc->sc_rx_th.wr_tsf = htole64( 3021 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3022 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3023 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3024 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3025 sc->sc_rx_th.wr_antnoise = nf; 3026 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3027 3028 bpf_mtap2(sc->sc_drvbpf, 3029 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3030 } 3031 #endif 3032 3033 /* 3034 * From this point on we assume the frame is at least 3035 * as large as ieee80211_frame_min; verify that. 3036 */ 3037 if (len < IEEE80211_MIN_LEN) { 3038 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3039 __func__, len); 3040 sc->sc_stats.ast_rx_tooshort++; 3041 m_freem(m); 3042 goto rx_next; 3043 } 3044 3045 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3046 ieee80211_dump_pkt(mtod(m, void *), len, 3047 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3048 ds->ds_rxstat.rs_rssi); 3049 } 3050 3051 m_adj(m, -IEEE80211_CRC_LEN); 3052 3053 /* 3054 * Locate the node for sender, track state, and then 3055 * pass the (referenced) node up to the 802.11 layer 3056 * for its use. 3057 */ 3058 ni = ieee80211_find_rxnode_withkey(ic, 3059 mtod(m, const struct ieee80211_frame_min *), 3060 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3061 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3062 /* 3063 * Track rx rssi and do any rx antenna management. 3064 */ 3065 an = ATH_NODE(ni); 3066 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3067 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3068 /* 3069 * Send frame up for processing. 3070 */ 3071 type = ieee80211_input(ic, m, ni, 3072 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3073 ieee80211_free_node(ni); 3074 if (sc->sc_diversity) { 3075 /* 3076 * When using fast diversity, change the default rx 3077 * antenna if diversity chooses the other antenna 3 3078 * times in a row. 3079 */ 3080 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3081 if (++sc->sc_rxotherant >= 3) 3082 ath_setdefantenna(sc, 3083 ds->ds_rxstat.rs_antenna); 3084 } else 3085 sc->sc_rxotherant = 0; 3086 } 3087 if (sc->sc_softled) { 3088 /* 3089 * Blink for any data frame. Otherwise do a 3090 * heartbeat-style blink when idle. The latter 3091 * is mainly for station mode where we depend on 3092 * periodic beacon frames to trigger the poll event. 3093 */ 3094 if (type == IEEE80211_FC0_TYPE_DATA) { 3095 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3096 ath_led_event(sc, ATH_LED_RX); 3097 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3098 ath_led_event(sc, ATH_LED_POLL); 3099 } 3100 /* 3101 * Arrange to update the last rx timestamp only for 3102 * frames from our ap when operating in station mode. 3103 * This assumes the rx key is always setup when associated. 3104 */ 3105 if (ic->ic_opmode == IEEE80211_M_STA && 3106 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3107 ngood++; 3108 rx_next: 3109 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3110 } while (ath_rxbuf_init(sc, bf) == 0); 3111 3112 /* rx signal state monitoring */ 3113 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3114 if (ath_hal_radar_event(ah)) 3115 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3116 if (ngood) 3117 sc->sc_lastrx = tsf; 3118 3119 #ifdef __NetBSD__ 3120 /* XXX Why isn't this necessary in FreeBSD? */ 3121 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3122 ath_start(ifp); 3123 #endif /* __NetBSD__ */ 3124 3125 NET_UNLOCK_GIANT(); /* XXX */ 3126 #undef PA2DESC 3127 } 3128 3129 /* 3130 * Setup a h/w transmit queue. 3131 */ 3132 static struct ath_txq * 3133 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3134 { 3135 #define N(a) (sizeof(a)/sizeof(a[0])) 3136 struct ath_hal *ah = sc->sc_ah; 3137 HAL_TXQ_INFO qi; 3138 int qnum; 3139 3140 memset(&qi, 0, sizeof(qi)); 3141 qi.tqi_subtype = subtype; 3142 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3143 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3144 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3145 /* 3146 * Enable interrupts only for EOL and DESC conditions. 3147 * We mark tx descriptors to receive a DESC interrupt 3148 * when a tx queue gets deep; otherwise waiting for the 3149 * EOL to reap descriptors. Note that this is done to 3150 * reduce interrupt load and this only defers reaping 3151 * descriptors, never transmitting frames. Aside from 3152 * reducing interrupts this also permits more concurrency. 3153 * The only potential downside is if the tx queue backs 3154 * up in which case the top half of the kernel may backup 3155 * due to a lack of tx descriptors. 3156 */ 3157 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3158 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3159 if (qnum == -1) { 3160 /* 3161 * NB: don't print a message, this happens 3162 * normally on parts with too few tx queues 3163 */ 3164 return NULL; 3165 } 3166 if (qnum >= N(sc->sc_txq)) { 3167 device_printf(&sc->sc_dev, 3168 "hal qnum %u out of range, max %zu!\n", 3169 qnum, N(sc->sc_txq)); 3170 ath_hal_releasetxqueue(ah, qnum); 3171 return NULL; 3172 } 3173 if (!ATH_TXQ_SETUP(sc, qnum)) { 3174 struct ath_txq *txq = &sc->sc_txq[qnum]; 3175 3176 txq->axq_qnum = qnum; 3177 txq->axq_depth = 0; 3178 txq->axq_intrcnt = 0; 3179 txq->axq_link = NULL; 3180 STAILQ_INIT(&txq->axq_q); 3181 ATH_TXQ_LOCK_INIT(sc, txq); 3182 sc->sc_txqsetup |= 1<<qnum; 3183 } 3184 return &sc->sc_txq[qnum]; 3185 #undef N 3186 } 3187 3188 /* 3189 * Setup a hardware data transmit queue for the specified 3190 * access control. The hal may not support all requested 3191 * queues in which case it will return a reference to a 3192 * previously setup queue. We record the mapping from ac's 3193 * to h/w queues for use by ath_tx_start and also track 3194 * the set of h/w queues being used to optimize work in the 3195 * transmit interrupt handler and related routines. 3196 */ 3197 static int 3198 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3199 { 3200 #define N(a) (sizeof(a)/sizeof(a[0])) 3201 struct ath_txq *txq; 3202 3203 if (ac >= N(sc->sc_ac2q)) { 3204 device_printf(&sc->sc_dev, "AC %u out of range, max %zu!\n", 3205 ac, N(sc->sc_ac2q)); 3206 return 0; 3207 } 3208 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3209 if (txq != NULL) { 3210 sc->sc_ac2q[ac] = txq; 3211 return 1; 3212 } else 3213 return 0; 3214 #undef N 3215 } 3216 3217 /* 3218 * Update WME parameters for a transmit queue. 3219 */ 3220 static int 3221 ath_txq_update(struct ath_softc *sc, int ac) 3222 { 3223 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3224 #define ATH_TXOP_TO_US(v) (v<<5) 3225 struct ieee80211com *ic = &sc->sc_ic; 3226 struct ath_txq *txq = sc->sc_ac2q[ac]; 3227 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3228 struct ath_hal *ah = sc->sc_ah; 3229 HAL_TXQ_INFO qi; 3230 3231 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3232 qi.tqi_aifs = wmep->wmep_aifsn; 3233 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3234 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3235 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3236 3237 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3238 device_printf(&sc->sc_dev, "unable to update hardware queue " 3239 "parameters for %s traffic!\n", 3240 ieee80211_wme_acnames[ac]); 3241 return 0; 3242 } else { 3243 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3244 return 1; 3245 } 3246 #undef ATH_TXOP_TO_US 3247 #undef ATH_EXPONENT_TO_VALUE 3248 } 3249 3250 /* 3251 * Callback from the 802.11 layer to update WME parameters. 3252 */ 3253 static int 3254 ath_wme_update(struct ieee80211com *ic) 3255 { 3256 struct ath_softc *sc = ic->ic_ifp->if_softc; 3257 3258 return !ath_txq_update(sc, WME_AC_BE) || 3259 !ath_txq_update(sc, WME_AC_BK) || 3260 !ath_txq_update(sc, WME_AC_VI) || 3261 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3262 } 3263 3264 /* 3265 * Reclaim resources for a setup queue. 3266 */ 3267 static void 3268 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3269 { 3270 3271 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3272 ATH_TXQ_LOCK_DESTROY(txq); 3273 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3274 } 3275 3276 /* 3277 * Reclaim all tx queue resources. 3278 */ 3279 static void 3280 ath_tx_cleanup(struct ath_softc *sc) 3281 { 3282 int i; 3283 3284 ATH_TXBUF_LOCK_DESTROY(sc); 3285 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3286 if (ATH_TXQ_SETUP(sc, i)) 3287 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3288 } 3289 3290 /* 3291 * Defragment an mbuf chain, returning at most maxfrags separate 3292 * mbufs+clusters. If this is not possible NULL is returned and 3293 * the original mbuf chain is left in it's present (potentially 3294 * modified) state. We use two techniques: collapsing consecutive 3295 * mbufs and replacing consecutive mbufs by a cluster. 3296 */ 3297 static struct mbuf * 3298 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3299 { 3300 struct mbuf *m, *n, *n2, **prev; 3301 u_int curfrags; 3302 3303 /* 3304 * Calculate the current number of frags. 3305 */ 3306 curfrags = 0; 3307 for (m = m0; m != NULL; m = m->m_next) 3308 curfrags++; 3309 /* 3310 * First, try to collapse mbufs. Note that we always collapse 3311 * towards the front so we don't need to deal with moving the 3312 * pkthdr. This may be suboptimal if the first mbuf has much 3313 * less data than the following. 3314 */ 3315 m = m0; 3316 again: 3317 for (;;) { 3318 n = m->m_next; 3319 if (n == NULL) 3320 break; 3321 if (n->m_len < M_TRAILINGSPACE(m)) { 3322 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3323 n->m_len); 3324 m->m_len += n->m_len; 3325 m->m_next = n->m_next; 3326 m_free(n); 3327 if (--curfrags <= maxfrags) 3328 return m0; 3329 } else 3330 m = n; 3331 } 3332 KASSERT(maxfrags > 1, 3333 ("maxfrags %u, but normal collapse failed", maxfrags)); 3334 /* 3335 * Collapse consecutive mbufs to a cluster. 3336 */ 3337 prev = &m0->m_next; /* NB: not the first mbuf */ 3338 while ((n = *prev) != NULL) { 3339 if ((n2 = n->m_next) != NULL && 3340 n->m_len + n2->m_len < MCLBYTES) { 3341 m = m_getcl(how, MT_DATA, 0); 3342 if (m == NULL) 3343 goto bad; 3344 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3345 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3346 n2->m_len); 3347 m->m_len = n->m_len + n2->m_len; 3348 m->m_next = n2->m_next; 3349 *prev = m; 3350 m_free(n); 3351 m_free(n2); 3352 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3353 return m0; 3354 /* 3355 * Still not there, try the normal collapse 3356 * again before we allocate another cluster. 3357 */ 3358 goto again; 3359 } 3360 prev = &n->m_next; 3361 } 3362 /* 3363 * No place where we can collapse to a cluster; punt. 3364 * This can occur if, for example, you request 2 frags 3365 * but the packet requires that both be clusters (we 3366 * never reallocate the first mbuf to avoid moving the 3367 * packet header). 3368 */ 3369 bad: 3370 return NULL; 3371 } 3372 3373 /* 3374 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3375 */ 3376 static int 3377 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3378 { 3379 int i; 3380 3381 for (i = 0; i < rt->rateCount; i++) 3382 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3383 return i; 3384 return 0; /* NB: lowest rate */ 3385 } 3386 3387 static void 3388 ath_freetx(struct mbuf *m) 3389 { 3390 struct mbuf *next; 3391 3392 do { 3393 next = m->m_nextpkt; 3394 m->m_nextpkt = NULL; 3395 m_freem(m); 3396 } while ((m = next) != NULL); 3397 } 3398 3399 static int 3400 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3401 struct mbuf *m0) 3402 { 3403 struct ieee80211com *ic = &sc->sc_ic; 3404 struct ath_hal *ah = sc->sc_ah; 3405 struct ifnet *ifp = &sc->sc_if; 3406 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3407 int i, error, iswep, ismcast, isfrag, ismrr; 3408 int keyix, hdrlen, pktlen, try0; 3409 u_int8_t rix, txrate, ctsrate; 3410 u_int8_t cix = 0xff; /* NB: silence compiler */ 3411 struct ath_desc *ds, *ds0; 3412 struct ath_txq *txq; 3413 struct ieee80211_frame *wh; 3414 u_int subtype, flags, ctsduration; 3415 HAL_PKT_TYPE atype; 3416 const HAL_RATE_TABLE *rt; 3417 HAL_BOOL shortPreamble; 3418 struct ath_node *an; 3419 struct mbuf *m; 3420 u_int pri; 3421 3422 wh = mtod(m0, struct ieee80211_frame *); 3423 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3424 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3425 isfrag = m0->m_flags & M_FRAG; 3426 hdrlen = ieee80211_anyhdrsize(wh); 3427 /* 3428 * Packet length must not include any 3429 * pad bytes; deduct them here. 3430 */ 3431 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3432 3433 if (iswep) { 3434 const struct ieee80211_cipher *cip; 3435 struct ieee80211_key *k; 3436 3437 /* 3438 * Construct the 802.11 header+trailer for an encrypted 3439 * frame. The only reason this can fail is because of an 3440 * unknown or unsupported cipher/key type. 3441 */ 3442 k = ieee80211_crypto_encap(ic, ni, m0); 3443 if (k == NULL) { 3444 /* 3445 * This can happen when the key is yanked after the 3446 * frame was queued. Just discard the frame; the 3447 * 802.11 layer counts failures and provides 3448 * debugging/diagnostics. 3449 */ 3450 ath_freetx(m0); 3451 return EIO; 3452 } 3453 /* 3454 * Adjust the packet + header lengths for the crypto 3455 * additions and calculate the h/w key index. When 3456 * a s/w mic is done the frame will have had any mic 3457 * added to it prior to entry so m0->m_pkthdr.len above will 3458 * account for it. Otherwise we need to add it to the 3459 * packet length. 3460 */ 3461 cip = k->wk_cipher; 3462 hdrlen += cip->ic_header; 3463 pktlen += cip->ic_header + cip->ic_trailer; 3464 /* NB: frags always have any TKIP MIC done in s/w */ 3465 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3466 pktlen += cip->ic_miclen; 3467 keyix = k->wk_keyix; 3468 3469 /* packet header may have moved, reset our local pointer */ 3470 wh = mtod(m0, struct ieee80211_frame *); 3471 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3472 /* 3473 * Use station key cache slot, if assigned. 3474 */ 3475 keyix = ni->ni_ucastkey.wk_keyix; 3476 if (keyix == IEEE80211_KEYIX_NONE) 3477 keyix = HAL_TXKEYIX_INVALID; 3478 } else 3479 keyix = HAL_TXKEYIX_INVALID; 3480 3481 pktlen += IEEE80211_CRC_LEN; 3482 3483 /* 3484 * Load the DMA map so any coalescing is done. This 3485 * also calculates the number of descriptors we need. 3486 */ 3487 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3488 BUS_DMA_NOWAIT); 3489 if (error == EFBIG) { 3490 /* XXX packet requires too many descriptors */ 3491 bf->bf_nseg = ATH_TXDESC+1; 3492 } else if (error != 0) { 3493 sc->sc_stats.ast_tx_busdma++; 3494 ath_freetx(m0); 3495 return error; 3496 } 3497 /* 3498 * Discard null packets and check for packets that 3499 * require too many TX descriptors. We try to convert 3500 * the latter to a cluster. 3501 */ 3502 if (error == EFBIG) { /* too many desc's, linearize */ 3503 sc->sc_stats.ast_tx_linear++; 3504 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3505 if (m == NULL) { 3506 ath_freetx(m0); 3507 sc->sc_stats.ast_tx_nombuf++; 3508 return ENOMEM; 3509 } 3510 m0 = m; 3511 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3512 BUS_DMA_NOWAIT); 3513 if (error != 0) { 3514 sc->sc_stats.ast_tx_busdma++; 3515 ath_freetx(m0); 3516 return error; 3517 } 3518 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3519 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3520 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3521 sc->sc_stats.ast_tx_nodata++; 3522 ath_freetx(m0); 3523 return EIO; 3524 } 3525 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3526 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3527 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3528 bf->bf_m = m0; 3529 bf->bf_node = ni; /* NB: held reference */ 3530 3531 /* setup descriptors */ 3532 ds = bf->bf_desc; 3533 rt = sc->sc_currates; 3534 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3535 3536 /* 3537 * NB: the 802.11 layer marks whether or not we should 3538 * use short preamble based on the current mode and 3539 * negotiated parameters. 3540 */ 3541 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3542 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3543 shortPreamble = AH_TRUE; 3544 sc->sc_stats.ast_tx_shortpre++; 3545 } else { 3546 shortPreamble = AH_FALSE; 3547 } 3548 3549 an = ATH_NODE(ni); 3550 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3551 ismrr = 0; /* default no multi-rate retry*/ 3552 /* 3553 * Calculate Atheros packet type from IEEE80211 packet header, 3554 * setup for rate calculations, and select h/w transmit queue. 3555 */ 3556 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3557 case IEEE80211_FC0_TYPE_MGT: 3558 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3559 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3560 atype = HAL_PKT_TYPE_BEACON; 3561 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3562 atype = HAL_PKT_TYPE_PROBE_RESP; 3563 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3564 atype = HAL_PKT_TYPE_ATIM; 3565 else 3566 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3567 rix = sc->sc_minrateix; 3568 txrate = rt->info[rix].rateCode; 3569 if (shortPreamble) 3570 txrate |= rt->info[rix].shortPreamble; 3571 try0 = ATH_TXMGTTRY; 3572 /* NB: force all management frames to highest queue */ 3573 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3574 /* NB: force all management frames to highest queue */ 3575 pri = WME_AC_VO; 3576 } else 3577 pri = WME_AC_BE; 3578 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3579 break; 3580 case IEEE80211_FC0_TYPE_CTL: 3581 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3582 rix = sc->sc_minrateix; 3583 txrate = rt->info[rix].rateCode; 3584 if (shortPreamble) 3585 txrate |= rt->info[rix].shortPreamble; 3586 try0 = ATH_TXMGTTRY; 3587 /* NB: force all ctl frames to highest queue */ 3588 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3589 /* NB: force all ctl frames to highest queue */ 3590 pri = WME_AC_VO; 3591 } else 3592 pri = WME_AC_BE; 3593 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3594 break; 3595 case IEEE80211_FC0_TYPE_DATA: 3596 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3597 /* 3598 * Data frames: multicast frames go out at a fixed rate, 3599 * otherwise consult the rate control module for the 3600 * rate to use. 3601 */ 3602 if (ismcast) { 3603 /* 3604 * Check mcast rate setting in case it's changed. 3605 * XXX move out of fastpath 3606 */ 3607 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3608 sc->sc_mcastrix = 3609 ath_tx_findrix(rt, ic->ic_mcast_rate); 3610 sc->sc_mcastrate = ic->ic_mcast_rate; 3611 } 3612 rix = sc->sc_mcastrix; 3613 txrate = rt->info[rix].rateCode; 3614 try0 = 1; 3615 } else { 3616 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3617 &rix, &try0, &txrate); 3618 sc->sc_txrate = txrate; /* for LED blinking */ 3619 if (try0 != ATH_TXMAXTRY) 3620 ismrr = 1; 3621 } 3622 pri = M_WME_GETAC(m0); 3623 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3624 flags |= HAL_TXDESC_NOACK; 3625 break; 3626 default: 3627 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3628 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3629 /* XXX statistic */ 3630 ath_freetx(m0); 3631 return EIO; 3632 } 3633 txq = sc->sc_ac2q[pri]; 3634 3635 /* 3636 * When servicing one or more stations in power-save mode 3637 * multicast frames must be buffered until after the beacon. 3638 * We use the CAB queue for that. 3639 */ 3640 if (ismcast && ic->ic_ps_sta) { 3641 txq = sc->sc_cabq; 3642 /* XXX? more bit in 802.11 frame header */ 3643 } 3644 3645 /* 3646 * Calculate miscellaneous flags. 3647 */ 3648 if (ismcast) { 3649 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3650 } else if (pktlen > ic->ic_rtsthreshold) { 3651 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3652 cix = rt->info[rix].controlRate; 3653 sc->sc_stats.ast_tx_rts++; 3654 } 3655 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3656 sc->sc_stats.ast_tx_noack++; 3657 3658 /* 3659 * If 802.11g protection is enabled, determine whether 3660 * to use RTS/CTS or just CTS. Note that this is only 3661 * done for OFDM unicast frames. 3662 */ 3663 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3664 rt->info[rix].phy == IEEE80211_T_OFDM && 3665 (flags & HAL_TXDESC_NOACK) == 0) { 3666 /* XXX fragments must use CCK rates w/ protection */ 3667 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3668 flags |= HAL_TXDESC_RTSENA; 3669 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3670 flags |= HAL_TXDESC_CTSENA; 3671 if (isfrag) { 3672 /* 3673 * For frags it would be desirable to use the 3674 * highest CCK rate for RTS/CTS. But stations 3675 * farther away may detect it at a lower CCK rate 3676 * so use the configured protection rate instead 3677 * (for now). 3678 */ 3679 cix = rt->info[sc->sc_protrix].controlRate; 3680 } else 3681 cix = rt->info[sc->sc_protrix].controlRate; 3682 sc->sc_stats.ast_tx_protect++; 3683 } 3684 3685 /* 3686 * Calculate duration. This logically belongs in the 802.11 3687 * layer but it lacks sufficient information to calculate it. 3688 */ 3689 if ((flags & HAL_TXDESC_NOACK) == 0 && 3690 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3691 u_int16_t dur; 3692 /* 3693 * XXX not right with fragmentation. 3694 */ 3695 if (shortPreamble) 3696 dur = rt->info[rix].spAckDuration; 3697 else 3698 dur = rt->info[rix].lpAckDuration; 3699 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3700 dur += dur; /* additional SIFS+ACK */ 3701 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3702 /* 3703 * Include the size of next fragment so NAV is 3704 * updated properly. The last fragment uses only 3705 * the ACK duration 3706 */ 3707 dur += ath_hal_computetxtime(ah, rt, 3708 m0->m_nextpkt->m_pkthdr.len, 3709 rix, shortPreamble); 3710 } 3711 if (isfrag) { 3712 /* 3713 * Force hardware to use computed duration for next 3714 * fragment by disabling multi-rate retry which updates 3715 * duration based on the multi-rate duration table. 3716 */ 3717 try0 = ATH_TXMAXTRY; 3718 } 3719 *(u_int16_t *)wh->i_dur = htole16(dur); 3720 } 3721 3722 /* 3723 * Calculate RTS/CTS rate and duration if needed. 3724 */ 3725 ctsduration = 0; 3726 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3727 /* 3728 * CTS transmit rate is derived from the transmit rate 3729 * by looking in the h/w rate table. We must also factor 3730 * in whether or not a short preamble is to be used. 3731 */ 3732 /* NB: cix is set above where RTS/CTS is enabled */ 3733 KASSERT(cix != 0xff, ("cix not setup")); 3734 ctsrate = rt->info[cix].rateCode; 3735 /* 3736 * Compute the transmit duration based on the frame 3737 * size and the size of an ACK frame. We call into the 3738 * HAL to do the computation since it depends on the 3739 * characteristics of the actual PHY being used. 3740 * 3741 * NB: CTS is assumed the same size as an ACK so we can 3742 * use the precalculated ACK durations. 3743 */ 3744 if (shortPreamble) { 3745 ctsrate |= rt->info[cix].shortPreamble; 3746 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3747 ctsduration += rt->info[cix].spAckDuration; 3748 ctsduration += ath_hal_computetxtime(ah, 3749 rt, pktlen, rix, AH_TRUE); 3750 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3751 ctsduration += rt->info[rix].spAckDuration; 3752 } else { 3753 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3754 ctsduration += rt->info[cix].lpAckDuration; 3755 ctsduration += ath_hal_computetxtime(ah, 3756 rt, pktlen, rix, AH_FALSE); 3757 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3758 ctsduration += rt->info[rix].lpAckDuration; 3759 } 3760 /* 3761 * Must disable multi-rate retry when using RTS/CTS. 3762 */ 3763 ismrr = 0; 3764 try0 = ATH_TXMGTTRY; /* XXX */ 3765 } else 3766 ctsrate = 0; 3767 3768 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3769 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3770 sc->sc_hwmap[txrate].ieeerate, -1); 3771 #if NBPFILTER > 0 3772 if (ic->ic_rawbpf) 3773 bpf_mtap(ic->ic_rawbpf, m0); 3774 if (sc->sc_drvbpf) { 3775 u_int64_t tsf = ath_hal_gettsf64(ah); 3776 3777 sc->sc_tx_th.wt_tsf = htole64(tsf); 3778 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3779 if (iswep) 3780 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3781 if (isfrag) 3782 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3783 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3784 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3785 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3786 3787 bpf_mtap2(sc->sc_drvbpf, 3788 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3789 } 3790 #endif 3791 3792 /* 3793 * Determine if a tx interrupt should be generated for 3794 * this descriptor. We take a tx interrupt to reap 3795 * descriptors when the h/w hits an EOL condition or 3796 * when the descriptor is specifically marked to generate 3797 * an interrupt. We periodically mark descriptors in this 3798 * way to insure timely replenishing of the supply needed 3799 * for sending frames. Defering interrupts reduces system 3800 * load and potentially allows more concurrent work to be 3801 * done but if done to aggressively can cause senders to 3802 * backup. 3803 * 3804 * NB: use >= to deal with sc_txintrperiod changing 3805 * dynamically through sysctl. 3806 */ 3807 if (flags & HAL_TXDESC_INTREQ) { 3808 txq->axq_intrcnt = 0; 3809 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3810 flags |= HAL_TXDESC_INTREQ; 3811 txq->axq_intrcnt = 0; 3812 } 3813 3814 /* 3815 * Formulate first tx descriptor with tx controls. 3816 */ 3817 /* XXX check return value? */ 3818 ath_hal_setuptxdesc(ah, ds 3819 , pktlen /* packet length */ 3820 , hdrlen /* header length */ 3821 , atype /* Atheros packet type */ 3822 , ni->ni_txpower /* txpower */ 3823 , txrate, try0 /* series 0 rate/tries */ 3824 , keyix /* key cache index */ 3825 , sc->sc_txantenna /* antenna mode */ 3826 , flags /* flags */ 3827 , ctsrate /* rts/cts rate */ 3828 , ctsduration /* rts/cts duration */ 3829 ); 3830 bf->bf_flags = flags; 3831 /* 3832 * Setup the multi-rate retry state only when we're 3833 * going to use it. This assumes ath_hal_setuptxdesc 3834 * initializes the descriptors (so we don't have to) 3835 * when the hardware supports multi-rate retry and 3836 * we don't use it. 3837 */ 3838 if (ismrr) 3839 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3840 3841 /* 3842 * Fillin the remainder of the descriptor info. 3843 */ 3844 ds0 = ds; 3845 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3846 ds->ds_data = bf->bf_segs[i].ds_addr; 3847 if (i == bf->bf_nseg - 1) 3848 ds->ds_link = 0; 3849 else 3850 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3851 ath_hal_filltxdesc(ah, ds 3852 , bf->bf_segs[i].ds_len /* segment length */ 3853 , i == 0 /* first segment */ 3854 , i == bf->bf_nseg - 1 /* last segment */ 3855 , ds0 /* first descriptor */ 3856 ); 3857 3858 /* NB: The desc swap function becomes void, 3859 * if descriptor swapping is not enabled 3860 */ 3861 ath_desc_swap(ds); 3862 3863 DPRINTF(sc, ATH_DEBUG_XMIT, 3864 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3865 __func__, i, ds->ds_link, ds->ds_data, 3866 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3867 } 3868 /* 3869 * Insert the frame on the outbound list and 3870 * pass it on to the hardware. 3871 */ 3872 ATH_TXQ_LOCK(txq); 3873 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3874 if (txq->axq_link == NULL) { 3875 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3876 DPRINTF(sc, ATH_DEBUG_XMIT, 3877 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3878 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3879 txq->axq_depth); 3880 } else { 3881 *txq->axq_link = HTOAH32(bf->bf_daddr); 3882 DPRINTF(sc, ATH_DEBUG_XMIT, 3883 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3884 __func__, txq->axq_qnum, txq->axq_link, 3885 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3886 } 3887 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3888 /* 3889 * The CAB queue is started from the SWBA handler since 3890 * frames only go out on DTIM and to avoid possible races. 3891 */ 3892 if (txq != sc->sc_cabq) 3893 ath_hal_txstart(ah, txq->axq_qnum); 3894 ATH_TXQ_UNLOCK(txq); 3895 3896 return 0; 3897 } 3898 3899 /* 3900 * Process completed xmit descriptors from the specified queue. 3901 */ 3902 static int 3903 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3904 { 3905 struct ath_hal *ah = sc->sc_ah; 3906 struct ieee80211com *ic = &sc->sc_ic; 3907 struct ath_buf *bf; 3908 struct ath_desc *ds, *ds0; 3909 struct ieee80211_node *ni; 3910 struct ath_node *an; 3911 int sr, lr, pri, nacked; 3912 HAL_STATUS status; 3913 3914 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3915 __func__, txq->axq_qnum, 3916 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3917 txq->axq_link); 3918 nacked = 0; 3919 for (;;) { 3920 ATH_TXQ_LOCK(txq); 3921 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3922 bf = STAILQ_FIRST(&txq->axq_q); 3923 if (bf == NULL) { 3924 txq->axq_link = NULL; 3925 ATH_TXQ_UNLOCK(txq); 3926 break; 3927 } 3928 ds0 = &bf->bf_desc[0]; 3929 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3930 status = ath_hal_txprocdesc(ah, ds); 3931 #ifdef AR_DEBUG 3932 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3933 ath_printtxbuf(bf, status == HAL_OK); 3934 #endif 3935 if (status == HAL_EINPROGRESS) { 3936 ATH_TXQ_UNLOCK(txq); 3937 break; 3938 } 3939 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3940 ATH_TXQ_UNLOCK(txq); 3941 3942 ni = bf->bf_node; 3943 if (ni != NULL) { 3944 an = ATH_NODE(ni); 3945 if (ds->ds_txstat.ts_status == 0) { 3946 u_int8_t txant = ds->ds_txstat.ts_antenna; 3947 sc->sc_stats.ast_ant_tx[txant]++; 3948 sc->sc_ant_tx[txant]++; 3949 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3950 sc->sc_stats.ast_tx_altrate++; 3951 sc->sc_stats.ast_tx_rssi = 3952 ds->ds_txstat.ts_rssi; 3953 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3954 ds->ds_txstat.ts_rssi); 3955 pri = M_WME_GETAC(bf->bf_m); 3956 if (pri >= WME_AC_VO) 3957 ic->ic_wme.wme_hipri_traffic++; 3958 ni->ni_inact = ni->ni_inact_reload; 3959 } else { 3960 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3961 sc->sc_stats.ast_tx_xretries++; 3962 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3963 sc->sc_stats.ast_tx_fifoerr++; 3964 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3965 sc->sc_stats.ast_tx_filtered++; 3966 } 3967 sr = ds->ds_txstat.ts_shortretry; 3968 lr = ds->ds_txstat.ts_longretry; 3969 sc->sc_stats.ast_tx_shortretry += sr; 3970 sc->sc_stats.ast_tx_longretry += lr; 3971 /* 3972 * Hand the descriptor to the rate control algorithm. 3973 */ 3974 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3975 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 3976 /* 3977 * If frame was ack'd update the last rx time 3978 * used to workaround phantom bmiss interrupts. 3979 */ 3980 if (ds->ds_txstat.ts_status == 0) 3981 nacked++; 3982 ath_rate_tx_complete(sc, an, ds, ds0); 3983 } 3984 /* 3985 * Reclaim reference to node. 3986 * 3987 * NB: the node may be reclaimed here if, for example 3988 * this is a DEAUTH message that was sent and the 3989 * node was timed out due to inactivity. 3990 */ 3991 ieee80211_free_node(ni); 3992 } 3993 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3994 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3995 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3996 m_freem(bf->bf_m); 3997 bf->bf_m = NULL; 3998 bf->bf_node = NULL; 3999 4000 ATH_TXBUF_LOCK(sc); 4001 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4002 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4003 ATH_TXBUF_UNLOCK(sc); 4004 } 4005 return nacked; 4006 } 4007 4008 static inline int 4009 txqactive(struct ath_hal *ah, int qnum) 4010 { 4011 u_int32_t txqs = 1<<qnum; 4012 ath_hal_gettxintrtxqs(ah, &txqs); 4013 return (txqs & (1<<qnum)); 4014 } 4015 4016 /* 4017 * Deferred processing of transmit interrupt; special-cased 4018 * for a single hardware transmit queue (e.g. 5210 and 5211). 4019 */ 4020 static void 4021 ath_tx_proc_q0(void *arg, int npending) 4022 { 4023 struct ath_softc *sc = arg; 4024 struct ifnet *ifp = &sc->sc_if; 4025 4026 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4027 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4028 } 4029 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4030 ath_tx_processq(sc, sc->sc_cabq); 4031 4032 if (sc->sc_softled) 4033 ath_led_event(sc, ATH_LED_TX); 4034 4035 ath_start(ifp); 4036 } 4037 4038 /* 4039 * Deferred processing of transmit interrupt; special-cased 4040 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4041 */ 4042 static void 4043 ath_tx_proc_q0123(void *arg, int npending) 4044 { 4045 struct ath_softc *sc = arg; 4046 struct ifnet *ifp = &sc->sc_if; 4047 int nacked; 4048 4049 /* 4050 * Process each active queue. 4051 */ 4052 nacked = 0; 4053 if (txqactive(sc->sc_ah, 0)) 4054 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4055 if (txqactive(sc->sc_ah, 1)) 4056 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4057 if (txqactive(sc->sc_ah, 2)) 4058 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4059 if (txqactive(sc->sc_ah, 3)) 4060 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4061 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4062 ath_tx_processq(sc, sc->sc_cabq); 4063 if (nacked) { 4064 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4065 } 4066 4067 if (sc->sc_softled) 4068 ath_led_event(sc, ATH_LED_TX); 4069 4070 ath_start(ifp); 4071 } 4072 4073 /* 4074 * Deferred processing of transmit interrupt. 4075 */ 4076 static void 4077 ath_tx_proc(void *arg, int npending) 4078 { 4079 struct ath_softc *sc = arg; 4080 struct ifnet *ifp = &sc->sc_if; 4081 int i, nacked; 4082 4083 /* 4084 * Process each active queue. 4085 */ 4086 nacked = 0; 4087 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4088 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4089 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4090 if (nacked) { 4091 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4092 } 4093 4094 if (sc->sc_softled) 4095 ath_led_event(sc, ATH_LED_TX); 4096 4097 ath_start(ifp); 4098 } 4099 4100 static void 4101 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4102 { 4103 struct ath_hal *ah = sc->sc_ah; 4104 struct ieee80211_node *ni; 4105 struct ath_buf *bf; 4106 4107 /* 4108 * NB: this assumes output has been stopped and 4109 * we do not need to block ath_tx_tasklet 4110 */ 4111 for (;;) { 4112 ATH_TXQ_LOCK(txq); 4113 bf = STAILQ_FIRST(&txq->axq_q); 4114 if (bf == NULL) { 4115 txq->axq_link = NULL; 4116 ATH_TXQ_UNLOCK(txq); 4117 break; 4118 } 4119 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4120 ATH_TXQ_UNLOCK(txq); 4121 #ifdef AR_DEBUG 4122 if (sc->sc_debug & ATH_DEBUG_RESET) 4123 ath_printtxbuf(bf, 4124 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 4125 #endif /* AR_DEBUG */ 4126 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4127 m_freem(bf->bf_m); 4128 bf->bf_m = NULL; 4129 ni = bf->bf_node; 4130 bf->bf_node = NULL; 4131 if (ni != NULL) { 4132 /* 4133 * Reclaim node reference. 4134 */ 4135 ieee80211_free_node(ni); 4136 } 4137 ATH_TXBUF_LOCK(sc); 4138 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4139 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4140 ATH_TXBUF_UNLOCK(sc); 4141 } 4142 } 4143 4144 static void 4145 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4146 { 4147 struct ath_hal *ah = sc->sc_ah; 4148 4149 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4150 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4151 __func__, txq->axq_qnum, 4152 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4153 txq->axq_link); 4154 } 4155 4156 /* 4157 * Drain the transmit queues and reclaim resources. 4158 */ 4159 static void 4160 ath_draintxq(struct ath_softc *sc) 4161 { 4162 struct ath_hal *ah = sc->sc_ah; 4163 int i; 4164 4165 /* XXX return value */ 4166 if (device_is_active(&sc->sc_dev)) { 4167 /* don't touch the hardware if marked invalid */ 4168 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4169 DPRINTF(sc, ATH_DEBUG_RESET, 4170 "%s: beacon queue %p\n", __func__, 4171 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4172 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4173 if (ATH_TXQ_SETUP(sc, i)) 4174 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4175 } 4176 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4177 if (ATH_TXQ_SETUP(sc, i)) 4178 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4179 } 4180 4181 /* 4182 * Disable the receive h/w in preparation for a reset. 4183 */ 4184 static void 4185 ath_stoprecv(struct ath_softc *sc) 4186 { 4187 #define PA2DESC(_sc, _pa) \ 4188 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4189 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4190 struct ath_hal *ah = sc->sc_ah; 4191 4192 ath_hal_stoppcurecv(ah); /* disable PCU */ 4193 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4194 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4195 DELAY(3000); /* 3ms is long enough for 1 frame */ 4196 #ifdef AR_DEBUG 4197 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4198 struct ath_buf *bf; 4199 4200 printf("%s: rx queue %p, link %p\n", __func__, 4201 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4202 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4203 struct ath_desc *ds = bf->bf_desc; 4204 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4205 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4206 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4207 ath_printrxbuf(bf, status == HAL_OK); 4208 } 4209 } 4210 #endif 4211 sc->sc_rxlink = NULL; /* just in case */ 4212 #undef PA2DESC 4213 } 4214 4215 /* 4216 * Enable the receive h/w following a reset. 4217 */ 4218 static int 4219 ath_startrecv(struct ath_softc *sc) 4220 { 4221 struct ath_hal *ah = sc->sc_ah; 4222 struct ath_buf *bf; 4223 4224 sc->sc_rxlink = NULL; 4225 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4226 int error = ath_rxbuf_init(sc, bf); 4227 if (error != 0) { 4228 DPRINTF(sc, ATH_DEBUG_RECV, 4229 "%s: ath_rxbuf_init failed %d\n", 4230 __func__, error); 4231 return error; 4232 } 4233 } 4234 4235 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4236 ath_hal_putrxbuf(ah, bf->bf_daddr); 4237 ath_hal_rxena(ah); /* enable recv descriptors */ 4238 ath_mode_init(sc); /* set filters, etc. */ 4239 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4240 return 0; 4241 } 4242 4243 /* 4244 * Update internal state after a channel change. 4245 */ 4246 static void 4247 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4248 { 4249 struct ieee80211com *ic = &sc->sc_ic; 4250 enum ieee80211_phymode mode; 4251 u_int16_t flags; 4252 4253 /* 4254 * Change channels and update the h/w rate map 4255 * if we're switching; e.g. 11a to 11b/g. 4256 */ 4257 mode = ieee80211_chan2mode(ic, chan); 4258 if (mode != sc->sc_curmode) 4259 ath_setcurmode(sc, mode); 4260 /* 4261 * Update BPF state. NB: ethereal et. al. don't handle 4262 * merged flags well so pick a unique mode for their use. 4263 */ 4264 if (IEEE80211_IS_CHAN_A(chan)) 4265 flags = IEEE80211_CHAN_A; 4266 /* XXX 11g schizophrenia */ 4267 else if (IEEE80211_IS_CHAN_G(chan) || 4268 IEEE80211_IS_CHAN_PUREG(chan)) 4269 flags = IEEE80211_CHAN_G; 4270 else 4271 flags = IEEE80211_CHAN_B; 4272 if (IEEE80211_IS_CHAN_T(chan)) 4273 flags |= IEEE80211_CHAN_TURBO; 4274 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4275 htole16(chan->ic_freq); 4276 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4277 htole16(flags); 4278 } 4279 4280 /* 4281 * Poll for a channel clear indication; this is required 4282 * for channels requiring DFS and not previously visited 4283 * and/or with a recent radar detection. 4284 */ 4285 static void 4286 ath_dfswait(void *arg) 4287 { 4288 struct ath_softc *sc = arg; 4289 struct ath_hal *ah = sc->sc_ah; 4290 HAL_CHANNEL hchan; 4291 4292 ath_hal_radar_wait(ah, &hchan); 4293 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4294 if_printf(&sc->sc_if, 4295 "channel %u/0x%x/0x%x has interference\n", 4296 hchan.channel, hchan.channelFlags, hchan.privFlags); 4297 return; 4298 } 4299 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4300 /* XXX should not happen */ 4301 return; 4302 } 4303 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4304 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4305 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4306 if_printf(&sc->sc_if, 4307 "channel %u/0x%x/0x%x marked clear\n", 4308 hchan.channel, hchan.channelFlags, hchan.privFlags); 4309 } else 4310 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4311 } 4312 4313 /* 4314 * Set/change channels. If the channel is really being changed, 4315 * it's done by reseting the chip. To accomplish this we must 4316 * first cleanup any pending DMA, then restart stuff after a la 4317 * ath_init. 4318 */ 4319 static int 4320 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4321 { 4322 struct ath_hal *ah = sc->sc_ah; 4323 struct ieee80211com *ic = &sc->sc_ic; 4324 HAL_CHANNEL hchan; 4325 4326 /* 4327 * Convert to a HAL channel description with 4328 * the flags constrained to reflect the current 4329 * operating mode. 4330 */ 4331 hchan.channel = chan->ic_freq; 4332 hchan.channelFlags = ath_chan2flags(ic, chan); 4333 4334 DPRINTF(sc, ATH_DEBUG_RESET, 4335 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4336 __func__, 4337 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4338 sc->sc_curchan.channelFlags), 4339 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4340 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4341 hchan.channel, hchan.channelFlags); 4342 if (hchan.channel != sc->sc_curchan.channel || 4343 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4344 HAL_STATUS status; 4345 4346 /* 4347 * To switch channels clear any pending DMA operations; 4348 * wait long enough for the RX fifo to drain, reset the 4349 * hardware at the new frequency, and then re-enable 4350 * the relevant bits of the h/w. 4351 */ 4352 ath_hal_intrset(ah, 0); /* disable interrupts */ 4353 ath_draintxq(sc); /* clear pending tx frames */ 4354 ath_stoprecv(sc); /* turn off frame recv */ 4355 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4356 if_printf(ic->ic_ifp, "%s: unable to reset " 4357 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4358 __func__, ieee80211_chan2ieee(ic, chan), 4359 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4360 return EIO; 4361 } 4362 sc->sc_curchan = hchan; 4363 ath_update_txpow(sc); /* update tx power state */ 4364 ath_restore_diversity(sc); 4365 sc->sc_calinterval = 1; 4366 sc->sc_caltries = 0; 4367 4368 /* 4369 * Re-enable rx framework. 4370 */ 4371 if (ath_startrecv(sc) != 0) { 4372 if_printf(&sc->sc_if, 4373 "%s: unable to restart recv logic\n", __func__); 4374 return EIO; 4375 } 4376 4377 /* 4378 * Change channels and update the h/w rate map 4379 * if we're switching; e.g. 11a to 11b/g. 4380 */ 4381 ic->ic_ibss_chan = chan; 4382 ath_chan_change(sc, chan); 4383 4384 /* 4385 * Handle DFS required waiting period to determine 4386 * if channel is clear of radar traffic. 4387 */ 4388 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4389 #define DFS_AND_NOT_CLEAR(_c) \ 4390 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4391 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4392 if_printf(&sc->sc_if, 4393 "wait for DFS clear channel signal\n"); 4394 /* XXX stop sndq */ 4395 sc->sc_if.if_flags |= IFF_OACTIVE; 4396 callout_reset(&sc->sc_dfs_ch, 4397 2 * hz, ath_dfswait, sc); 4398 } else 4399 callout_stop(&sc->sc_dfs_ch); 4400 #undef DFS_NOT_CLEAR 4401 } 4402 4403 /* 4404 * Re-enable interrupts. 4405 */ 4406 ath_hal_intrset(ah, sc->sc_imask); 4407 } 4408 return 0; 4409 } 4410 4411 static void 4412 ath_next_scan(void *arg) 4413 { 4414 struct ath_softc *sc = arg; 4415 struct ieee80211com *ic = &sc->sc_ic; 4416 int s; 4417 4418 /* don't call ath_start w/o network interrupts blocked */ 4419 s = splnet(); 4420 4421 if (ic->ic_state == IEEE80211_S_SCAN) 4422 ieee80211_next_scan(ic); 4423 splx(s); 4424 } 4425 4426 /* 4427 * Periodically recalibrate the PHY to account 4428 * for temperature/environment changes. 4429 */ 4430 static void 4431 ath_calibrate(void *arg) 4432 { 4433 struct ath_softc *sc = arg; 4434 struct ath_hal *ah = sc->sc_ah; 4435 HAL_BOOL iqCalDone; 4436 4437 sc->sc_stats.ast_per_cal++; 4438 4439 ATH_LOCK(sc); 4440 4441 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4442 /* 4443 * Rfgain is out of bounds, reset the chip 4444 * to load new gain values. 4445 */ 4446 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4447 "%s: rfgain change\n", __func__); 4448 sc->sc_stats.ast_per_rfgain++; 4449 ath_reset(&sc->sc_if); 4450 } 4451 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4452 DPRINTF(sc, ATH_DEBUG_ANY, 4453 "%s: calibration of channel %u failed\n", 4454 __func__, sc->sc_curchan.channel); 4455 sc->sc_stats.ast_per_calfail++; 4456 } 4457 /* 4458 * Calibrate noise floor data again in case of change. 4459 */ 4460 ath_hal_process_noisefloor(ah); 4461 /* 4462 * Poll more frequently when the IQ calibration is in 4463 * progress to speedup loading the final settings. 4464 * We temper this aggressive polling with an exponential 4465 * back off after 4 tries up to ath_calinterval. 4466 */ 4467 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4468 sc->sc_caltries = 0; 4469 sc->sc_calinterval = ath_calinterval; 4470 } else if (sc->sc_caltries > 4) { 4471 sc->sc_caltries = 0; 4472 sc->sc_calinterval <<= 1; 4473 if (sc->sc_calinterval > ath_calinterval) 4474 sc->sc_calinterval = ath_calinterval; 4475 } 4476 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4477 ("bad calibration interval %u", sc->sc_calinterval)); 4478 4479 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4480 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4481 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4482 sc->sc_caltries++; 4483 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4484 ath_calibrate, sc); 4485 ATH_UNLOCK(sc); 4486 } 4487 4488 static int 4489 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4490 { 4491 struct ifnet *ifp = ic->ic_ifp; 4492 struct ath_softc *sc = ifp->if_softc; 4493 struct ath_hal *ah = sc->sc_ah; 4494 struct ieee80211_node *ni; 4495 int i, error; 4496 const u_int8_t *bssid; 4497 u_int32_t rfilt; 4498 static const HAL_LED_STATE leds[] = { 4499 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4500 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4501 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4502 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4503 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4504 }; 4505 4506 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4507 ieee80211_state_name[ic->ic_state], 4508 ieee80211_state_name[nstate]); 4509 4510 callout_stop(&sc->sc_scan_ch); 4511 callout_stop(&sc->sc_cal_ch); 4512 callout_stop(&sc->sc_dfs_ch); 4513 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4514 4515 if (nstate == IEEE80211_S_INIT) { 4516 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4517 /* 4518 * NB: disable interrupts so we don't rx frames. 4519 */ 4520 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4521 /* 4522 * Notify the rate control algorithm. 4523 */ 4524 ath_rate_newstate(sc, nstate); 4525 goto done; 4526 } 4527 ni = ic->ic_bss; 4528 error = ath_chan_set(sc, ic->ic_curchan); 4529 if (error != 0) 4530 goto bad; 4531 rfilt = ath_calcrxfilter(sc, nstate); 4532 if (nstate == IEEE80211_S_SCAN) 4533 bssid = ifp->if_broadcastaddr; 4534 else 4535 bssid = ni->ni_bssid; 4536 ath_hal_setrxfilter(ah, rfilt); 4537 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4538 __func__, rfilt, ether_sprintf(bssid)); 4539 4540 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4541 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4542 else 4543 ath_hal_setassocid(ah, bssid, 0); 4544 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4545 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4546 if (ath_hal_keyisvalid(ah, i)) 4547 ath_hal_keysetmac(ah, i, bssid); 4548 } 4549 4550 /* 4551 * Notify the rate control algorithm so rates 4552 * are setup should ath_beacon_alloc be called. 4553 */ 4554 ath_rate_newstate(sc, nstate); 4555 4556 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4557 /* nothing to do */; 4558 } else if (nstate == IEEE80211_S_RUN) { 4559 DPRINTF(sc, ATH_DEBUG_STATE, 4560 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4561 "capinfo=0x%04x chan=%d\n" 4562 , __func__ 4563 , ic->ic_flags 4564 , ni->ni_intval 4565 , ether_sprintf(ni->ni_bssid) 4566 , ni->ni_capinfo 4567 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4568 4569 switch (ic->ic_opmode) { 4570 case IEEE80211_M_HOSTAP: 4571 case IEEE80211_M_IBSS: 4572 /* 4573 * Allocate and setup the beacon frame. 4574 * 4575 * Stop any previous beacon DMA. This may be 4576 * necessary, for example, when an ibss merge 4577 * causes reconfiguration; there will be a state 4578 * transition from RUN->RUN that means we may 4579 * be called with beacon transmission active. 4580 */ 4581 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4582 ath_beacon_free(sc); 4583 error = ath_beacon_alloc(sc, ni); 4584 if (error != 0) 4585 goto bad; 4586 /* 4587 * If joining an adhoc network defer beacon timer 4588 * configuration to the next beacon frame so we 4589 * have a current TSF to use. Otherwise we're 4590 * starting an ibss/bss so there's no need to delay. 4591 */ 4592 if (ic->ic_opmode == IEEE80211_M_IBSS && 4593 ic->ic_bss->ni_tstamp.tsf != 0) 4594 sc->sc_syncbeacon = 1; 4595 else 4596 ath_beacon_config(sc); 4597 break; 4598 case IEEE80211_M_STA: 4599 /* 4600 * Allocate a key cache slot to the station. 4601 */ 4602 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4603 sc->sc_hasclrkey && 4604 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4605 ath_setup_stationkey(ni); 4606 /* 4607 * Defer beacon timer configuration to the next 4608 * beacon frame so we have a current TSF to use 4609 * (any TSF collected when scanning is likely old). 4610 */ 4611 sc->sc_syncbeacon = 1; 4612 break; 4613 default: 4614 break; 4615 } 4616 /* 4617 * Let the hal process statistics collected during a 4618 * scan so it can provide calibrated noise floor data. 4619 */ 4620 ath_hal_process_noisefloor(ah); 4621 /* 4622 * Reset rssi stats; maybe not the best place... 4623 */ 4624 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4625 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4626 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4627 } else { 4628 ath_hal_intrset(ah, 4629 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4630 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4631 } 4632 done: 4633 /* 4634 * Invoke the parent method to complete the work. 4635 */ 4636 error = sc->sc_newstate(ic, nstate, arg); 4637 /* 4638 * Finally, start any timers. 4639 */ 4640 if (nstate == IEEE80211_S_RUN) { 4641 /* start periodic recalibration timer */ 4642 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4643 ath_calibrate, sc); 4644 } else if (nstate == IEEE80211_S_SCAN) { 4645 /* start ap/neighbor scan timer */ 4646 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4647 ath_next_scan, sc); 4648 } 4649 bad: 4650 return error; 4651 } 4652 4653 /* 4654 * Allocate a key cache slot to the station so we can 4655 * setup a mapping from key index to node. The key cache 4656 * slot is needed for managing antenna state and for 4657 * compression when stations do not use crypto. We do 4658 * it uniliaterally here; if crypto is employed this slot 4659 * will be reassigned. 4660 */ 4661 static void 4662 ath_setup_stationkey(struct ieee80211_node *ni) 4663 { 4664 struct ieee80211com *ic = ni->ni_ic; 4665 struct ath_softc *sc = ic->ic_ifp->if_softc; 4666 ieee80211_keyix keyix, rxkeyix; 4667 4668 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4669 /* 4670 * Key cache is full; we'll fall back to doing 4671 * the more expensive lookup in software. Note 4672 * this also means no h/w compression. 4673 */ 4674 /* XXX msg+statistic */ 4675 } else { 4676 /* XXX locking? */ 4677 ni->ni_ucastkey.wk_keyix = keyix; 4678 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4679 /* NB: this will create a pass-thru key entry */ 4680 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4681 } 4682 } 4683 4684 /* 4685 * Setup driver-specific state for a newly associated node. 4686 * Note that we're called also on a re-associate, the isnew 4687 * param tells us if this is the first time or not. 4688 */ 4689 static void 4690 ath_newassoc(struct ieee80211_node *ni, int isnew) 4691 { 4692 struct ieee80211com *ic = ni->ni_ic; 4693 struct ath_softc *sc = ic->ic_ifp->if_softc; 4694 4695 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4696 if (isnew && 4697 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4698 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4699 ("new assoc with a unicast key already setup (keyix %u)", 4700 ni->ni_ucastkey.wk_keyix)); 4701 ath_setup_stationkey(ni); 4702 } 4703 } 4704 4705 static int 4706 ath_getchannels(struct ath_softc *sc, u_int cc, 4707 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4708 { 4709 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4710 struct ieee80211com *ic = &sc->sc_ic; 4711 struct ifnet *ifp = &sc->sc_if; 4712 struct ath_hal *ah = sc->sc_ah; 4713 HAL_CHANNEL *chans; 4714 int i, ix, nchan; 4715 4716 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4717 M_TEMP, M_NOWAIT); 4718 if (chans == NULL) { 4719 if_printf(ifp, "unable to allocate channel table\n"); 4720 return ENOMEM; 4721 } 4722 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4723 NULL, 0, NULL, 4724 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4725 u_int32_t rd; 4726 4727 (void)ath_hal_getregdomain(ah, &rd); 4728 if_printf(ifp, "unable to collect channel list from hal; " 4729 "regdomain likely %u country code %u\n", rd, cc); 4730 free(chans, M_TEMP); 4731 return EINVAL; 4732 } 4733 4734 /* 4735 * Convert HAL channels to ieee80211 ones and insert 4736 * them in the table according to their channel number. 4737 */ 4738 for (i = 0; i < nchan; i++) { 4739 HAL_CHANNEL *c = &chans[i]; 4740 u_int16_t flags; 4741 4742 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4743 if (ix > IEEE80211_CHAN_MAX) { 4744 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4745 ix, c->channel, c->channelFlags); 4746 continue; 4747 } 4748 if (ix < 0) { 4749 /* XXX can't handle stuff <2400 right now */ 4750 if (bootverbose) 4751 if_printf(ifp, "hal channel %d (%u/%x) " 4752 "cannot be handled; ignored\n", 4753 ix, c->channel, c->channelFlags); 4754 continue; 4755 } 4756 /* 4757 * Calculate net80211 flags; most are compatible 4758 * but some need massaging. Note the static turbo 4759 * conversion can be removed once net80211 is updated 4760 * to understand static vs. dynamic turbo. 4761 */ 4762 flags = c->channelFlags & COMPAT; 4763 if (c->channelFlags & CHANNEL_STURBO) 4764 flags |= IEEE80211_CHAN_TURBO; 4765 if (ic->ic_channels[ix].ic_freq == 0) { 4766 ic->ic_channels[ix].ic_freq = c->channel; 4767 ic->ic_channels[ix].ic_flags = flags; 4768 } else { 4769 /* channels overlap; e.g. 11g and 11b */ 4770 ic->ic_channels[ix].ic_flags |= flags; 4771 } 4772 } 4773 free(chans, M_TEMP); 4774 return 0; 4775 #undef COMPAT 4776 } 4777 4778 static void 4779 ath_led_done(void *arg) 4780 { 4781 struct ath_softc *sc = arg; 4782 4783 sc->sc_blinking = 0; 4784 } 4785 4786 /* 4787 * Turn the LED off: flip the pin and then set a timer so no 4788 * update will happen for the specified duration. 4789 */ 4790 static void 4791 ath_led_off(void *arg) 4792 { 4793 struct ath_softc *sc = arg; 4794 4795 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4796 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4797 } 4798 4799 /* 4800 * Blink the LED according to the specified on/off times. 4801 */ 4802 static void 4803 ath_led_blink(struct ath_softc *sc, int on, int off) 4804 { 4805 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4806 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4807 sc->sc_blinking = 1; 4808 sc->sc_ledoff = off; 4809 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4810 } 4811 4812 static void 4813 ath_led_event(struct ath_softc *sc, int event) 4814 { 4815 4816 sc->sc_ledevent = ticks; /* time of last event */ 4817 if (sc->sc_blinking) /* don't interrupt active blink */ 4818 return; 4819 switch (event) { 4820 case ATH_LED_POLL: 4821 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4822 sc->sc_hwmap[0].ledoff); 4823 break; 4824 case ATH_LED_TX: 4825 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4826 sc->sc_hwmap[sc->sc_txrate].ledoff); 4827 break; 4828 case ATH_LED_RX: 4829 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4830 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4831 break; 4832 } 4833 } 4834 4835 static void 4836 ath_update_txpow(struct ath_softc *sc) 4837 { 4838 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4839 struct ieee80211com *ic = &sc->sc_ic; 4840 struct ath_hal *ah = sc->sc_ah; 4841 u_int32_t txpow; 4842 4843 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4844 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4845 /* read back in case value is clamped */ 4846 (void)ath_hal_gettxpowlimit(ah, &txpow); 4847 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4848 } 4849 /* 4850 * Fetch max tx power level for status requests. 4851 */ 4852 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4853 ic->ic_bss->ni_txpower = txpow; 4854 } 4855 4856 static void 4857 rate_setup(struct ath_softc *sc, 4858 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4859 { 4860 int i, maxrates; 4861 4862 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4863 DPRINTF(sc, ATH_DEBUG_ANY, 4864 "%s: rate table too small (%u > %u)\n", 4865 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4866 maxrates = IEEE80211_RATE_MAXSIZE; 4867 } else 4868 maxrates = rt->rateCount; 4869 for (i = 0; i < maxrates; i++) 4870 rs->rs_rates[i] = rt->info[i].dot11Rate; 4871 rs->rs_nrates = maxrates; 4872 } 4873 4874 static int 4875 ath_rate_setup(struct ath_softc *sc, u_int mode) 4876 { 4877 struct ath_hal *ah = sc->sc_ah; 4878 struct ieee80211com *ic = &sc->sc_ic; 4879 const HAL_RATE_TABLE *rt; 4880 4881 switch (mode) { 4882 case IEEE80211_MODE_11A: 4883 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4884 break; 4885 case IEEE80211_MODE_11B: 4886 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4887 break; 4888 case IEEE80211_MODE_11G: 4889 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4890 break; 4891 case IEEE80211_MODE_TURBO_A: 4892 /* XXX until static/dynamic turbo is fixed */ 4893 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4894 break; 4895 case IEEE80211_MODE_TURBO_G: 4896 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 4897 break; 4898 default: 4899 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4900 __func__, mode); 4901 return 0; 4902 } 4903 sc->sc_rates[mode] = rt; 4904 if (rt != NULL) { 4905 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 4906 return 1; 4907 } else 4908 return 0; 4909 } 4910 4911 static void 4912 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4913 { 4914 #define N(a) (sizeof(a)/sizeof(a[0])) 4915 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4916 static const struct { 4917 u_int rate; /* tx/rx 802.11 rate */ 4918 u_int16_t timeOn; /* LED on time (ms) */ 4919 u_int16_t timeOff; /* LED off time (ms) */ 4920 } blinkrates[] = { 4921 { 108, 40, 10 }, 4922 { 96, 44, 11 }, 4923 { 72, 50, 13 }, 4924 { 48, 57, 14 }, 4925 { 36, 67, 16 }, 4926 { 24, 80, 20 }, 4927 { 22, 100, 25 }, 4928 { 18, 133, 34 }, 4929 { 12, 160, 40 }, 4930 { 10, 200, 50 }, 4931 { 6, 240, 58 }, 4932 { 4, 267, 66 }, 4933 { 2, 400, 100 }, 4934 { 0, 500, 130 }, 4935 }; 4936 const HAL_RATE_TABLE *rt; 4937 int i, j; 4938 4939 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4940 rt = sc->sc_rates[mode]; 4941 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4942 for (i = 0; i < rt->rateCount; i++) 4943 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4944 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4945 for (i = 0; i < 32; i++) { 4946 u_int8_t ix = rt->rateCodeToIndex[i]; 4947 if (ix == 0xff) { 4948 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4949 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4950 continue; 4951 } 4952 sc->sc_hwmap[i].ieeerate = 4953 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4954 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4955 if (rt->info[ix].shortPreamble || 4956 rt->info[ix].phy == IEEE80211_T_OFDM) 4957 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4958 /* NB: receive frames include FCS */ 4959 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4960 IEEE80211_RADIOTAP_F_FCS; 4961 /* setup blink rate table to avoid per-packet lookup */ 4962 for (j = 0; j < N(blinkrates)-1; j++) 4963 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4964 break; 4965 /* NB: this uses the last entry if the rate isn't found */ 4966 /* XXX beware of overlow */ 4967 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4968 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4969 } 4970 sc->sc_currates = rt; 4971 sc->sc_curmode = mode; 4972 /* 4973 * All protection frames are transmited at 2Mb/s for 4974 * 11g, otherwise at 1Mb/s. 4975 */ 4976 if (mode == IEEE80211_MODE_11G) 4977 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 4978 else 4979 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 4980 /* rate index used to send management frames */ 4981 sc->sc_minrateix = 0; 4982 /* 4983 * Setup multicast rate state. 4984 */ 4985 /* XXX layering violation */ 4986 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 4987 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 4988 /* NB: caller is responsible for reseting rate control state */ 4989 #undef N 4990 } 4991 4992 #ifdef AR_DEBUG 4993 static void 4994 ath_printrxbuf(struct ath_buf *bf, int done) 4995 { 4996 struct ath_desc *ds; 4997 int i; 4998 4999 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5000 printf("R%d (%p %" PRIx64 5001 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5002 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5003 ds->ds_link, ds->ds_data, 5004 ds->ds_ctl0, ds->ds_ctl1, 5005 ds->ds_hw[0], ds->ds_hw[1], 5006 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5007 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5008 } 5009 } 5010 5011 static void 5012 ath_printtxbuf(struct ath_buf *bf, int done) 5013 { 5014 struct ath_desc *ds; 5015 int i; 5016 5017 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5018 printf("T%d (%p %" PRIx64 5019 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5020 i, ds, 5021 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5022 ds->ds_link, ds->ds_data, 5023 ds->ds_ctl0, ds->ds_ctl1, 5024 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5025 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5026 } 5027 } 5028 #endif /* AR_DEBUG */ 5029 5030 static void 5031 ath_watchdog(struct ifnet *ifp) 5032 { 5033 struct ath_softc *sc = ifp->if_softc; 5034 struct ieee80211com *ic = &sc->sc_ic; 5035 struct ath_txq *axq; 5036 int i; 5037 5038 ifp->if_timer = 0; 5039 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5040 !device_is_active(&sc->sc_dev)) 5041 return; 5042 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5043 if (!ATH_TXQ_SETUP(sc, i)) 5044 continue; 5045 axq = &sc->sc_txq[i]; 5046 ATH_TXQ_LOCK(axq); 5047 if (axq->axq_timer == 0) 5048 ; 5049 else if (--axq->axq_timer == 0) { 5050 ATH_TXQ_UNLOCK(axq); 5051 if_printf(ifp, "device timeout (txq %d, " 5052 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5053 if (sc->sc_txintrperiod > 1) 5054 sc->sc_txintrperiod--; 5055 ath_reset(ifp); 5056 ifp->if_oerrors++; 5057 sc->sc_stats.ast_watchdog++; 5058 break; 5059 } else 5060 ifp->if_timer = 1; 5061 ATH_TXQ_UNLOCK(axq); 5062 } 5063 ieee80211_watchdog(ic); 5064 } 5065 5066 /* 5067 * Diagnostic interface to the HAL. This is used by various 5068 * tools to do things like retrieve register contents for 5069 * debugging. The mechanism is intentionally opaque so that 5070 * it can change frequently w/o concern for compatiblity. 5071 */ 5072 static int 5073 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5074 { 5075 struct ath_hal *ah = sc->sc_ah; 5076 u_int id = ad->ad_id & ATH_DIAG_ID; 5077 void *indata = NULL; 5078 void *outdata = NULL; 5079 u_int32_t insize = ad->ad_in_size; 5080 u_int32_t outsize = ad->ad_out_size; 5081 int error = 0; 5082 5083 if (ad->ad_id & ATH_DIAG_IN) { 5084 /* 5085 * Copy in data. 5086 */ 5087 indata = malloc(insize, M_TEMP, M_NOWAIT); 5088 if (indata == NULL) { 5089 error = ENOMEM; 5090 goto bad; 5091 } 5092 error = copyin(ad->ad_in_data, indata, insize); 5093 if (error) 5094 goto bad; 5095 } 5096 if (ad->ad_id & ATH_DIAG_DYN) { 5097 /* 5098 * Allocate a buffer for the results (otherwise the HAL 5099 * returns a pointer to a buffer where we can read the 5100 * results). Note that we depend on the HAL leaving this 5101 * pointer for us to use below in reclaiming the buffer; 5102 * may want to be more defensive. 5103 */ 5104 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5105 if (outdata == NULL) { 5106 error = ENOMEM; 5107 goto bad; 5108 } 5109 } 5110 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5111 if (outsize < ad->ad_out_size) 5112 ad->ad_out_size = outsize; 5113 if (outdata != NULL) 5114 error = copyout(outdata, ad->ad_out_data, 5115 ad->ad_out_size); 5116 } else { 5117 error = EINVAL; 5118 } 5119 bad: 5120 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5121 free(indata, M_TEMP); 5122 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5123 free(outdata, M_TEMP); 5124 return error; 5125 } 5126 5127 static int 5128 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5129 { 5130 #define IS_RUNNING(ifp) \ 5131 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5132 struct ath_softc *sc = ifp->if_softc; 5133 struct ieee80211com *ic = &sc->sc_ic; 5134 struct ifreq *ifr = (struct ifreq *)data; 5135 int error = 0; 5136 5137 ATH_LOCK(sc); 5138 switch (cmd) { 5139 case SIOCSIFFLAGS: 5140 if (IS_RUNNING(ifp)) { 5141 /* 5142 * To avoid rescanning another access point, 5143 * do not call ath_init() here. Instead, 5144 * only reflect promisc mode settings. 5145 */ 5146 ath_mode_init(sc); 5147 } else if (ifp->if_flags & IFF_UP) { 5148 /* 5149 * Beware of being called during attach/detach 5150 * to reset promiscuous mode. In that case we 5151 * will still be marked UP but not RUNNING. 5152 * However trying to re-init the interface 5153 * is the wrong thing to do as we've already 5154 * torn down much of our state. There's 5155 * probably a better way to deal with this. 5156 */ 5157 error = ath_init(sc); 5158 } else if (device_is_active(&sc->sc_dev)) 5159 ath_stop_locked(ifp, 1); 5160 break; 5161 case SIOCADDMULTI: 5162 case SIOCDELMULTI: 5163 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5164 if (ifp->if_flags & IFF_RUNNING) 5165 ath_mode_init(sc); 5166 error = 0; 5167 } 5168 break; 5169 case SIOCGATHSTATS: 5170 /* NB: embed these numbers to get a consistent view */ 5171 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5172 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5173 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5174 ATH_UNLOCK(sc); 5175 /* 5176 * NB: Drop the softc lock in case of a page fault; 5177 * we'll accept any potential inconsisentcy in the 5178 * statistics. The alternative is to copy the data 5179 * to a local structure. 5180 */ 5181 return copyout(&sc->sc_stats, 5182 ifr->ifr_data, sizeof (sc->sc_stats)); 5183 case SIOCGATHDIAG: 5184 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5185 break; 5186 default: 5187 error = ieee80211_ioctl(ic, cmd, data); 5188 if (error != ENETRESET) 5189 ; 5190 else if (IS_RUNNING(ifp) && 5191 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5192 error = ath_init(sc); 5193 else 5194 error = 0; 5195 break; 5196 } 5197 ATH_UNLOCK(sc); 5198 return error; 5199 #undef IS_RUNNING 5200 } 5201 5202 #if NBPFILTER > 0 5203 static void 5204 ath_bpfattach(struct ath_softc *sc) 5205 { 5206 struct ifnet *ifp = &sc->sc_if; 5207 5208 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5209 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5210 &sc->sc_drvbpf); 5211 /* 5212 * Initialize constant fields. 5213 * XXX make header lengths a multiple of 32-bits so subsequent 5214 * headers are properly aligned; this is a kludge to keep 5215 * certain applications happy. 5216 * 5217 * NB: the channel is setup each time we transition to the 5218 * RUN state to avoid filling it in for each frame. 5219 */ 5220 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5221 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5222 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5223 5224 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5225 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5226 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5227 } 5228 #endif 5229 5230 /* 5231 * Announce various information on device/driver attach. 5232 */ 5233 static void 5234 ath_announce(struct ath_softc *sc) 5235 { 5236 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5237 struct ifnet *ifp = &sc->sc_if; 5238 struct ath_hal *ah = sc->sc_ah; 5239 u_int modes, cc; 5240 5241 if_printf(ifp, "mac %d.%d phy %d.%d", 5242 ah->ah_macVersion, ah->ah_macRev, 5243 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5244 /* 5245 * Print radio revision(s). We check the wireless modes 5246 * to avoid falsely printing revs for inoperable parts. 5247 * Dual-band radio revs are returned in the 5 GHz rev number. 5248 */ 5249 ath_hal_getcountrycode(ah, &cc); 5250 modes = ath_hal_getwirelessmodes(ah, cc); 5251 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5252 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5253 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5254 ah->ah_analog5GhzRev >> 4, 5255 ah->ah_analog5GhzRev & 0xf, 5256 ah->ah_analog2GhzRev >> 4, 5257 ah->ah_analog2GhzRev & 0xf); 5258 else 5259 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5260 ah->ah_analog5GhzRev & 0xf); 5261 } else 5262 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5263 ah->ah_analog5GhzRev & 0xf); 5264 printf("\n"); 5265 if (bootverbose) { 5266 int i; 5267 for (i = 0; i <= WME_AC_VO; i++) { 5268 struct ath_txq *txq = sc->sc_ac2q[i]; 5269 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5270 txq->axq_qnum, ieee80211_wme_acnames[i]); 5271 } 5272 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5273 sc->sc_cabq->axq_qnum); 5274 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5275 } 5276 if (ath_rxbuf != ATH_RXBUF) 5277 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5278 if (ath_txbuf != ATH_TXBUF) 5279 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5280 #undef HAL_MODE_DUALBAND 5281 } 5282