1 /* $NetBSD: ath.c,v 1.105 2008/12/11 06:04:01 alc Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.105 2008/12/11 06:04:01 alc Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/errno.h> 71 #include <sys/callout.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/if_ether.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_netbsd.h> 84 #include <net80211/ieee80211_var.h> 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #endif 93 94 #include <sys/device.h> 95 #include <dev/ic/ath_netbsd.h> 96 97 #define AR_DEBUG 98 #include <dev/ic/athvar.h> 99 #include "ah_desc.h" 100 #include "ah_devid.h" /* XXX for softled */ 101 #include "opt_ah.h" 102 103 #ifdef ATH_TX99_DIAG 104 #include <dev/ath/ath_tx99/ath_tx99.h> 105 #endif 106 107 /* unaligned little endian access */ 108 #define LE_READ_2(p) \ 109 ((u_int16_t) \ 110 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 111 #define LE_READ_4(p) \ 112 ((u_int32_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 114 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 115 116 enum { 117 ATH_LED_TX, 118 ATH_LED_RX, 119 ATH_LED_POLL, 120 }; 121 122 #ifdef AH_NEED_DESC_SWAP 123 #define HTOAH32(x) htole32(x) 124 #else 125 #define HTOAH32(x) (x) 126 #endif 127 128 static int ath_ifinit(struct ifnet *); 129 static int ath_init(struct ath_softc *); 130 static void ath_stop_locked(struct ifnet *, int); 131 static void ath_stop(struct ifnet *, int); 132 static void ath_start(struct ifnet *); 133 static int ath_media_change(struct ifnet *); 134 static void ath_watchdog(struct ifnet *); 135 static int ath_ioctl(struct ifnet *, u_long, void *); 136 static void ath_fatal_proc(void *, int); 137 static void ath_rxorn_proc(void *, int); 138 static void ath_bmiss_proc(void *, int); 139 static void ath_radar_proc(void *, int); 140 static int ath_key_alloc(struct ieee80211com *, 141 const struct ieee80211_key *, 142 ieee80211_keyix *, ieee80211_keyix *); 143 static int ath_key_delete(struct ieee80211com *, 144 const struct ieee80211_key *); 145 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 146 const u_int8_t mac[IEEE80211_ADDR_LEN]); 147 static void ath_key_update_begin(struct ieee80211com *); 148 static void ath_key_update_end(struct ieee80211com *); 149 static void ath_mode_init(struct ath_softc *); 150 static void ath_setslottime(struct ath_softc *); 151 static void ath_updateslot(struct ifnet *); 152 static int ath_beaconq_setup(struct ath_hal *); 153 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 154 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 155 static void ath_beacon_proc(void *, int); 156 static void ath_bstuck_proc(void *, int); 157 static void ath_beacon_free(struct ath_softc *); 158 static void ath_beacon_config(struct ath_softc *); 159 static void ath_descdma_cleanup(struct ath_softc *sc, 160 struct ath_descdma *, ath_bufhead *); 161 static int ath_desc_alloc(struct ath_softc *); 162 static void ath_desc_free(struct ath_softc *); 163 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 164 static void ath_node_free(struct ieee80211_node *); 165 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 166 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 167 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 168 struct ieee80211_node *ni, 169 int subtype, int rssi, u_int32_t rstamp); 170 static void ath_setdefantenna(struct ath_softc *, u_int); 171 static void ath_rx_proc(void *, int); 172 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 173 static int ath_tx_setup(struct ath_softc *, int, int); 174 static int ath_wme_update(struct ieee80211com *); 175 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 176 static void ath_tx_cleanup(struct ath_softc *); 177 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 178 struct ath_buf *, struct mbuf *); 179 static void ath_tx_proc_q0(void *, int); 180 static void ath_tx_proc_q0123(void *, int); 181 static void ath_tx_proc(void *, int); 182 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_draintxq(struct ath_softc *); 184 static void ath_stoprecv(struct ath_softc *); 185 static int ath_startrecv(struct ath_softc *); 186 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 187 static void ath_next_scan(void *); 188 static void ath_calibrate(void *); 189 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 190 static void ath_setup_stationkey(struct ieee80211_node *); 191 static void ath_newassoc(struct ieee80211_node *, int); 192 static int ath_getchannels(struct ath_softc *, u_int cc, 193 HAL_BOOL outdoor, HAL_BOOL xchanmode); 194 static void ath_led_event(struct ath_softc *, int); 195 static void ath_update_txpow(struct ath_softc *); 196 static void ath_freetx(struct mbuf *); 197 static void ath_restore_diversity(struct ath_softc *); 198 199 static int ath_rate_setup(struct ath_softc *, u_int mode); 200 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 201 202 #if NBPFILTER > 0 203 static void ath_bpfattach(struct ath_softc *); 204 #endif 205 static void ath_announce(struct ath_softc *); 206 207 int ath_dwelltime = 200; /* 5 channels/second */ 208 int ath_calinterval = 30; /* calibrate every 30 secs */ 209 int ath_outdoor = AH_TRUE; /* outdoor operation */ 210 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 211 int ath_countrycode = CTRY_DEFAULT; /* country code */ 212 int ath_regdomain = 0; /* regulatory domain */ 213 int ath_debug = 0; 214 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 215 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 216 217 #ifdef AR_DEBUG 218 enum { 219 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 220 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 221 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 222 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 223 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 224 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 225 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 226 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 227 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 228 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 229 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 230 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 231 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 232 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 233 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 234 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 235 ATH_DEBUG_NODE = 0x00080000, /* node management */ 236 ATH_DEBUG_LED = 0x00100000, /* led management */ 237 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 238 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 239 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 240 ATH_DEBUG_ANY = 0xffffffff 241 }; 242 #define IFF_DUMPPKTS(sc, m) \ 243 ((sc->sc_debug & (m)) || \ 244 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245 #define DPRINTF(sc, m, fmt, ...) do { \ 246 if (sc->sc_debug & (m)) \ 247 printf(fmt, __VA_ARGS__); \ 248 } while (0) 249 #define KEYPRINTF(sc, ix, hk, mac) do { \ 250 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 251 ath_keyprint(__func__, ix, hk, mac); \ 252 } while (0) 253 static void ath_printrxbuf(struct ath_buf *bf, int); 254 static void ath_printtxbuf(struct ath_buf *bf, int); 255 #else 256 #define IFF_DUMPPKTS(sc, m) \ 257 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 258 #define DPRINTF(m, fmt, ...) 259 #define KEYPRINTF(sc, k, ix, mac) 260 #endif 261 262 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 263 264 int 265 ath_attach(u_int16_t devid, struct ath_softc *sc) 266 { 267 struct ifnet *ifp = &sc->sc_if; 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ath_hal *ah = NULL; 270 HAL_STATUS status; 271 int error = 0, i; 272 273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 274 275 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 276 277 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 278 if (ah == NULL) { 279 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 280 status); 281 error = ENXIO; 282 goto bad; 283 } 284 if (ah->ah_abi != HAL_ABI_VERSION) { 285 if_printf(ifp, "HAL ABI mismatch detected " 286 "(HAL:0x%x != driver:0x%x)\n", 287 ah->ah_abi, HAL_ABI_VERSION); 288 error = ENXIO; 289 goto bad; 290 } 291 sc->sc_ah = ah; 292 293 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 294 "pmf-powerdown", false)) 295 goto bad; 296 297 /* 298 * Check if the MAC has multi-rate retry support. 299 * We do this by trying to setup a fake extended 300 * descriptor. MAC's that don't have support will 301 * return false w/o doing anything. MAC's that do 302 * support it will return true w/o doing anything. 303 */ 304 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 305 306 /* 307 * Check if the device has hardware counters for PHY 308 * errors. If so we need to enable the MIB interrupt 309 * so we can act on stat triggers. 310 */ 311 if (ath_hal_hwphycounters(ah)) 312 sc->sc_needmib = 1; 313 314 /* 315 * Get the hardware key cache size. 316 */ 317 sc->sc_keymax = ath_hal_keycachesize(ah); 318 if (sc->sc_keymax > ATH_KEYMAX) { 319 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 320 ATH_KEYMAX, sc->sc_keymax); 321 sc->sc_keymax = ATH_KEYMAX; 322 } 323 /* 324 * Reset the key cache since some parts do not 325 * reset the contents on initial power up. 326 */ 327 for (i = 0; i < sc->sc_keymax; i++) 328 ath_hal_keyreset(ah, i); 329 /* 330 * Mark key cache slots associated with global keys 331 * as in use. If we knew TKIP was not to be used we 332 * could leave the +32, +64, and +32+64 slots free. 333 * XXX only for splitmic. 334 */ 335 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 336 setbit(sc->sc_keymap, i); 337 setbit(sc->sc_keymap, i+32); 338 setbit(sc->sc_keymap, i+64); 339 setbit(sc->sc_keymap, i+32+64); 340 } 341 342 /* 343 * Collect the channel list using the default country 344 * code and including outdoor channels. The 802.11 layer 345 * is resposible for filtering this list based on settings 346 * like the phy mode. 347 */ 348 error = ath_getchannels(sc, ath_countrycode, 349 ath_outdoor, ath_xchanmode); 350 if (error != 0) 351 goto bad; 352 353 /* 354 * Setup rate tables for all potential media types. 355 */ 356 ath_rate_setup(sc, IEEE80211_MODE_11A); 357 ath_rate_setup(sc, IEEE80211_MODE_11B); 358 ath_rate_setup(sc, IEEE80211_MODE_11G); 359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 360 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 361 /* NB: setup here so ath_rate_update is happy */ 362 ath_setcurmode(sc, IEEE80211_MODE_11A); 363 364 /* 365 * Allocate tx+rx descriptors and populate the lists. 366 */ 367 error = ath_desc_alloc(sc); 368 if (error != 0) { 369 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 370 goto bad; 371 } 372 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 373 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 374 #if 0 375 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 376 #endif 377 378 ATH_TXBUF_LOCK_INIT(sc); 379 380 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 381 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 382 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 383 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 384 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 385 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 386 387 /* 388 * Allocate hardware transmit queues: one queue for 389 * beacon frames and one data queue for each QoS 390 * priority. Note that the hal handles reseting 391 * these queues at the needed time. 392 * 393 * XXX PS-Poll 394 */ 395 sc->sc_bhalq = ath_beaconq_setup(ah); 396 if (sc->sc_bhalq == (u_int) -1) { 397 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 398 error = EIO; 399 goto bad2; 400 } 401 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 402 if (sc->sc_cabq == NULL) { 403 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 404 error = EIO; 405 goto bad2; 406 } 407 /* NB: insure BK queue is the lowest priority h/w queue */ 408 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 409 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 410 ieee80211_wme_acnames[WME_AC_BK]); 411 error = EIO; 412 goto bad2; 413 } 414 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 415 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 416 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 417 /* 418 * Not enough hardware tx queues to properly do WME; 419 * just punt and assign them all to the same h/w queue. 420 * We could do a better job of this if, for example, 421 * we allocate queues when we switch from station to 422 * AP mode. 423 */ 424 if (sc->sc_ac2q[WME_AC_VI] != NULL) 425 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 426 if (sc->sc_ac2q[WME_AC_BE] != NULL) 427 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 428 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 429 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 430 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 431 } 432 433 /* 434 * Special case certain configurations. Note the 435 * CAB queue is handled by these specially so don't 436 * include them when checking the txq setup mask. 437 */ 438 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 439 case 0x01: 440 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 441 break; 442 case 0x0f: 443 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 444 break; 445 default: 446 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 447 break; 448 } 449 450 /* 451 * Setup rate control. Some rate control modules 452 * call back to change the anntena state so expose 453 * the necessary entry points. 454 * XXX maybe belongs in struct ath_ratectrl? 455 */ 456 sc->sc_setdefantenna = ath_setdefantenna; 457 sc->sc_rc = ath_rate_attach(sc); 458 if (sc->sc_rc == NULL) { 459 error = EIO; 460 goto bad2; 461 } 462 463 sc->sc_blinking = 0; 464 sc->sc_ledstate = 1; 465 sc->sc_ledon = 0; /* low true */ 466 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 467 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 468 /* 469 * Auto-enable soft led processing for IBM cards and for 470 * 5211 minipci cards. Users can also manually enable/disable 471 * support with a sysctl. 472 */ 473 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 474 if (sc->sc_softled) { 475 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 476 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 477 } 478 479 ifp->if_softc = sc; 480 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 481 ifp->if_start = ath_start; 482 ifp->if_stop = ath_stop; 483 ifp->if_watchdog = ath_watchdog; 484 ifp->if_ioctl = ath_ioctl; 485 ifp->if_init = ath_ifinit; 486 IFQ_SET_READY(&ifp->if_snd); 487 488 ic->ic_ifp = ifp; 489 ic->ic_reset = ath_reset; 490 ic->ic_newassoc = ath_newassoc; 491 ic->ic_updateslot = ath_updateslot; 492 ic->ic_wme.wme_update = ath_wme_update; 493 /* XXX not right but it's not used anywhere important */ 494 ic->ic_phytype = IEEE80211_T_OFDM; 495 ic->ic_opmode = IEEE80211_M_STA; 496 ic->ic_caps = 497 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 498 | IEEE80211_C_HOSTAP /* hostap mode */ 499 | IEEE80211_C_MONITOR /* monitor mode */ 500 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 501 | IEEE80211_C_SHSLOT /* short slot time supported */ 502 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 503 | IEEE80211_C_TXFRAG /* handle tx frags */ 504 ; 505 /* 506 * Query the hal to figure out h/w crypto support. 507 */ 508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 509 ic->ic_caps |= IEEE80211_C_WEP; 510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 511 ic->ic_caps |= IEEE80211_C_AES; 512 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 513 ic->ic_caps |= IEEE80211_C_AES_CCM; 514 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 515 ic->ic_caps |= IEEE80211_C_CKIP; 516 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 517 ic->ic_caps |= IEEE80211_C_TKIP; 518 /* 519 * Check if h/w does the MIC and/or whether the 520 * separate key cache entries are required to 521 * handle both tx+rx MIC keys. 522 */ 523 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) { 524 ic->ic_caps |= IEEE80211_C_TKIPMIC; 525 /* 526 * Check if h/w does MIC correctly when 527 * WMM is turned on. 528 */ 529 if (ath_hal_wmetkipmic(ah)) 530 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 531 } 532 533 /* 534 * If the h/w supports storing tx+rx MIC keys 535 * in one cache slot automatically enable use. 536 */ 537 if (ath_hal_tkipsplit(ah) || 538 !ath_hal_settkipsplit(ah, AH_FALSE)) 539 sc->sc_splitmic = 1; 540 } 541 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 542 #if 0 543 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 544 #endif 545 /* 546 * TPC support can be done either with a global cap or 547 * per-packet support. The latter is not available on 548 * all parts. We're a bit pedantic here as all parts 549 * support a global cap. 550 */ 551 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 552 ic->ic_caps |= IEEE80211_C_TXPMGT; 553 554 /* 555 * Mark WME capability only if we have sufficient 556 * hardware queues to do proper priority scheduling. 557 */ 558 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 559 ic->ic_caps |= IEEE80211_C_WME; 560 /* 561 * Check for misc other capabilities. 562 */ 563 if (ath_hal_hasbursting(ah)) 564 ic->ic_caps |= IEEE80211_C_BURST; 565 566 /* 567 * Indicate we need the 802.11 header padded to a 568 * 32-bit boundary for 4-address and QoS frames. 569 */ 570 ic->ic_flags |= IEEE80211_F_DATAPAD; 571 572 /* 573 * Query the hal about antenna support. 574 */ 575 sc->sc_defant = ath_hal_getdefantenna(ah); 576 577 /* 578 * Not all chips have the VEOL support we want to 579 * use with IBSS beacons; check here for it. 580 */ 581 sc->sc_hasveol = ath_hal_hasveol(ah); 582 583 /* get mac address from hardware */ 584 ath_hal_getmac(ah, ic->ic_myaddr); 585 586 if_attach(ifp); 587 /* call MI attach routine. */ 588 ieee80211_ifattach(ic); 589 /* override default methods */ 590 ic->ic_node_alloc = ath_node_alloc; 591 sc->sc_node_free = ic->ic_node_free; 592 ic->ic_node_free = ath_node_free; 593 ic->ic_node_getrssi = ath_node_getrssi; 594 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 595 ic->ic_recv_mgmt = ath_recv_mgmt; 596 sc->sc_newstate = ic->ic_newstate; 597 ic->ic_newstate = ath_newstate; 598 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 599 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 600 ic->ic_crypto.cs_key_delete = ath_key_delete; 601 ic->ic_crypto.cs_key_set = ath_key_set; 602 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 603 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 604 /* complete initialization */ 605 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 606 607 #if NBPFILTER > 0 608 ath_bpfattach(sc); 609 #endif 610 611 sc->sc_flags |= ATH_ATTACHED; 612 613 /* 614 * Setup dynamic sysctl's now that country code and 615 * regdomain are available from the hal. 616 */ 617 ath_sysctlattach(sc); 618 619 ieee80211_announce(ic); 620 ath_announce(sc); 621 return 0; 622 bad2: 623 ath_tx_cleanup(sc); 624 ath_desc_free(sc); 625 bad: 626 if (ah) 627 ath_hal_detach(ah); 628 /* XXX don't get under the abstraction like this */ 629 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 630 return error; 631 } 632 633 int 634 ath_detach(struct ath_softc *sc) 635 { 636 struct ifnet *ifp = &sc->sc_if; 637 int s; 638 639 if ((sc->sc_flags & ATH_ATTACHED) == 0) 640 return (0); 641 642 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 643 __func__, ifp->if_flags); 644 645 s = splnet(); 646 ath_stop(ifp, 1); 647 #if NBPFILTER > 0 648 bpfdetach(ifp); 649 #endif 650 /* 651 * NB: the order of these is important: 652 * o call the 802.11 layer before detaching the hal to 653 * insure callbacks into the driver to delete global 654 * key cache entries can be handled 655 * o reclaim the tx queue data structures after calling 656 * the 802.11 layer as we'll get called back to reclaim 657 * node state and potentially want to use them 658 * o to cleanup the tx queues the hal is called, so detach 659 * it last 660 * Other than that, it's straightforward... 661 */ 662 ieee80211_ifdetach(&sc->sc_ic); 663 #ifdef ATH_TX99_DIAG 664 if (sc->sc_tx99 != NULL) 665 sc->sc_tx99->detach(sc->sc_tx99); 666 #endif 667 ath_rate_detach(sc->sc_rc); 668 ath_desc_free(sc); 669 ath_tx_cleanup(sc); 670 sysctl_teardown(&sc->sc_sysctllog); 671 ath_hal_detach(sc->sc_ah); 672 if_detach(ifp); 673 splx(s); 674 675 return 0; 676 } 677 678 void 679 ath_suspend(struct ath_softc *sc) 680 { 681 #if notyet 682 /* 683 * Set the chip in full sleep mode. Note that we are 684 * careful to do this only when bringing the interface 685 * completely to a stop. When the chip is in this state 686 * it must be carefully woken up or references to 687 * registers in the PCI clock domain may freeze the bus 688 * (and system). This varies by chip and is mostly an 689 * issue with newer parts that go to sleep more quickly. 690 */ 691 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 692 #endif 693 } 694 695 bool 696 ath_resume(struct ath_softc *sc) 697 { 698 struct ath_hal *ah = sc->sc_ah; 699 struct ieee80211com *ic = &sc->sc_ic; 700 HAL_STATUS status; 701 int i; 702 703 #if notyet 704 ath_hal_setpower(ah, HAL_PM_AWAKE); 705 #else 706 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 707 #endif 708 709 /* 710 * Reset the key cache since some parts do not 711 * reset the contents on initial power up. 712 */ 713 for (i = 0; i < sc->sc_keymax; i++) 714 ath_hal_keyreset(ah, i); 715 716 ath_hal_resettxqueue(ah, sc->sc_bhalq); 717 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 718 if (ATH_TXQ_SETUP(sc, i)) 719 ath_hal_resettxqueue(ah, i); 720 721 if (sc->sc_softled) { 722 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 723 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 724 } 725 return true; 726 } 727 728 /* 729 * Interrupt handler. Most of the actual processing is deferred. 730 */ 731 int 732 ath_intr(void *arg) 733 { 734 struct ath_softc *sc = arg; 735 struct ifnet *ifp = &sc->sc_if; 736 struct ath_hal *ah = sc->sc_ah; 737 HAL_INT status; 738 739 if (!device_is_active(sc->sc_dev)) { 740 /* 741 * The hardware is not ready/present, don't touch anything. 742 * Note this can happen early on if the IRQ is shared. 743 */ 744 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 745 return 0; 746 } 747 748 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 749 return 0; 750 751 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 752 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 753 __func__, ifp->if_flags); 754 ath_hal_getisr(ah, &status); /* clear ISR */ 755 ath_hal_intrset(ah, 0); /* disable further intr's */ 756 return 1; /* XXX */ 757 } 758 /* 759 * Figure out the reason(s) for the interrupt. Note 760 * that the hal returns a pseudo-ISR that may include 761 * bits we haven't explicitly enabled so we mask the 762 * value to insure we only process bits we requested. 763 */ 764 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 765 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 766 status &= sc->sc_imask; /* discard unasked for bits */ 767 if (status & HAL_INT_FATAL) { 768 /* 769 * Fatal errors are unrecoverable. Typically 770 * these are caused by DMA errors. Unfortunately 771 * the exact reason is not (presently) returned 772 * by the hal. 773 */ 774 sc->sc_stats.ast_hardware++; 775 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 776 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 777 } else if (status & HAL_INT_RXORN) { 778 sc->sc_stats.ast_rxorn++; 779 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 780 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 781 } else { 782 if (status & HAL_INT_SWBA) { 783 /* 784 * Software beacon alert--time to send a beacon. 785 * Handle beacon transmission directly; deferring 786 * this is too slow to meet timing constraints 787 * under load. 788 */ 789 ath_beacon_proc(sc, 0); 790 } 791 if (status & HAL_INT_RXEOL) { 792 /* 793 * NB: the hardware should re-read the link when 794 * RXE bit is written, but it doesn't work at 795 * least on older hardware revs. 796 */ 797 sc->sc_stats.ast_rxeol++; 798 sc->sc_rxlink = NULL; 799 } 800 if (status & HAL_INT_TXURN) { 801 sc->sc_stats.ast_txurn++; 802 /* bump tx trigger level */ 803 ath_hal_updatetxtriglevel(ah, AH_TRUE); 804 } 805 if (status & HAL_INT_RX) 806 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 807 if (status & HAL_INT_TX) 808 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 809 if (status & HAL_INT_BMISS) { 810 sc->sc_stats.ast_bmiss++; 811 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 812 } 813 if (status & HAL_INT_MIB) { 814 sc->sc_stats.ast_mib++; 815 /* 816 * Disable interrupts until we service the MIB 817 * interrupt; otherwise it will continue to fire. 818 */ 819 ath_hal_intrset(ah, 0); 820 /* 821 * Let the hal handle the event. We assume it will 822 * clear whatever condition caused the interrupt. 823 */ 824 ath_hal_mibevent(ah, &sc->sc_halstats); 825 ath_hal_intrset(ah, sc->sc_imask); 826 } 827 } 828 return 1; 829 } 830 831 /* Swap transmit descriptor. 832 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 833 * function. 834 */ 835 static inline void 836 ath_desc_swap(struct ath_desc *ds) 837 { 838 #ifdef AH_NEED_DESC_SWAP 839 ds->ds_link = htole32(ds->ds_link); 840 ds->ds_data = htole32(ds->ds_data); 841 ds->ds_ctl0 = htole32(ds->ds_ctl0); 842 ds->ds_ctl1 = htole32(ds->ds_ctl1); 843 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 844 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 845 #endif 846 } 847 848 static void 849 ath_fatal_proc(void *arg, int pending) 850 { 851 struct ath_softc *sc = arg; 852 struct ifnet *ifp = &sc->sc_if; 853 854 if_printf(ifp, "hardware error; resetting\n"); 855 ath_reset(ifp); 856 } 857 858 static void 859 ath_rxorn_proc(void *arg, int pending) 860 { 861 struct ath_softc *sc = arg; 862 struct ifnet *ifp = &sc->sc_if; 863 864 if_printf(ifp, "rx FIFO overrun; resetting\n"); 865 ath_reset(ifp); 866 } 867 868 static void 869 ath_bmiss_proc(void *arg, int pending) 870 { 871 struct ath_softc *sc = arg; 872 struct ieee80211com *ic = &sc->sc_ic; 873 874 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 875 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 876 ("unexpect operating mode %u", ic->ic_opmode)); 877 if (ic->ic_state == IEEE80211_S_RUN) { 878 u_int64_t lastrx = sc->sc_lastrx; 879 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 880 881 DPRINTF(sc, ATH_DEBUG_BEACON, 882 "%s: tsf %" PRIu64 " lastrx %" PRId64 883 " (%" PRIu64 ") bmiss %u\n", 884 __func__, tsf, tsf - lastrx, lastrx, 885 ic->ic_bmisstimeout*1024); 886 /* 887 * Workaround phantom bmiss interrupts by sanity-checking 888 * the time of our last rx'd frame. If it is within the 889 * beacon miss interval then ignore the interrupt. If it's 890 * truly a bmiss we'll get another interrupt soon and that'll 891 * be dispatched up for processing. 892 */ 893 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 894 NET_LOCK_GIANT(); 895 ieee80211_beacon_miss(ic); 896 NET_UNLOCK_GIANT(); 897 } else 898 sc->sc_stats.ast_bmiss_phantom++; 899 } 900 } 901 902 static void 903 ath_radar_proc(void *arg, int pending) 904 { 905 #if 0 906 struct ath_softc *sc = arg; 907 struct ifnet *ifp = &sc->sc_if; 908 struct ath_hal *ah = sc->sc_ah; 909 HAL_CHANNEL hchan; 910 911 if (ath_hal_procdfs(ah, &hchan)) { 912 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 913 hchan.channel, hchan.channelFlags, hchan.privFlags); 914 /* 915 * Initiate channel change. 916 */ 917 /* XXX not yet */ 918 } 919 #endif 920 } 921 922 static u_int 923 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 924 { 925 #define N(a) (sizeof(a) / sizeof(a[0])) 926 static const u_int modeflags[] = { 927 0, /* IEEE80211_MODE_AUTO */ 928 CHANNEL_A, /* IEEE80211_MODE_11A */ 929 CHANNEL_B, /* IEEE80211_MODE_11B */ 930 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 931 0, /* IEEE80211_MODE_FH */ 932 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 933 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 934 }; 935 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 936 937 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 938 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 939 return modeflags[mode]; 940 #undef N 941 } 942 943 static int 944 ath_ifinit(struct ifnet *ifp) 945 { 946 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 947 948 return ath_init(sc); 949 } 950 951 static int 952 ath_init(struct ath_softc *sc) 953 { 954 struct ifnet *ifp = &sc->sc_if; 955 struct ieee80211com *ic = &sc->sc_ic; 956 struct ath_hal *ah = sc->sc_ah; 957 HAL_STATUS status; 958 int error = 0; 959 960 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 961 __func__, ifp->if_flags); 962 963 if (device_is_active(sc->sc_dev)) { 964 ATH_LOCK(sc); 965 } else if (!pmf_device_resume_self(sc->sc_dev)) 966 return ENXIO; 967 else 968 ATH_LOCK(sc); 969 970 /* 971 * Stop anything previously setup. This is safe 972 * whether this is the first time through or not. 973 */ 974 ath_stop_locked(ifp, 0); 975 976 int dummy; /* XXX: gcc */ 977 /* Whether we should enable h/w TKIP MIC */ 978 if ((ic->ic_caps & IEEE80211_C_WME) && 979 ((ic->ic_caps & IEEE80211_C_WME_TKIPMIC) || 980 !(ic->ic_flags & IEEE80211_F_WME))) { 981 dummy = ath_hal_settkipmic(ah, AH_TRUE); 982 } else { 983 dummy = ath_hal_settkipmic(ah, AH_FALSE); 984 } 985 986 987 /* 988 * The basic interface to setting the hardware in a good 989 * state is ``reset''. On return the hardware is known to 990 * be powered up and with interrupts disabled. This must 991 * be followed by initialization of the appropriate bits 992 * and then setup of the interrupt mask. 993 */ 994 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 995 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 996 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 997 if_printf(ifp, "unable to reset hardware; hal status %u\n", 998 status); 999 error = EIO; 1000 goto done; 1001 } 1002 1003 /* 1004 * This is needed only to setup initial state 1005 * but it's best done after a reset. 1006 */ 1007 ath_update_txpow(sc); 1008 /* 1009 * Likewise this is set during reset so update 1010 * state cached in the driver. 1011 */ 1012 ath_restore_diversity(sc); 1013 sc->sc_calinterval = 1; 1014 sc->sc_caltries = 0; 1015 1016 /* 1017 * Setup the hardware after reset: the key cache 1018 * is filled as needed and the receive engine is 1019 * set going. Frame transmit is handled entirely 1020 * in the frame output path; there's nothing to do 1021 * here except setup the interrupt mask. 1022 */ 1023 if ((error = ath_startrecv(sc)) != 0) { 1024 if_printf(ifp, "unable to start recv logic\n"); 1025 goto done; 1026 } 1027 1028 /* 1029 * Enable interrupts. 1030 */ 1031 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1032 | HAL_INT_RXEOL | HAL_INT_RXORN 1033 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1034 /* 1035 * Enable MIB interrupts when there are hardware phy counters. 1036 * Note we only do this (at the moment) for station mode. 1037 */ 1038 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1039 sc->sc_imask |= HAL_INT_MIB; 1040 ath_hal_intrset(ah, sc->sc_imask); 1041 1042 ifp->if_flags |= IFF_RUNNING; 1043 ic->ic_state = IEEE80211_S_INIT; 1044 1045 /* 1046 * The hardware should be ready to go now so it's safe 1047 * to kick the 802.11 state machine as it's likely to 1048 * immediately call back to us to send mgmt frames. 1049 */ 1050 ath_chan_change(sc, ic->ic_curchan); 1051 #ifdef ATH_TX99_DIAG 1052 if (sc->sc_tx99 != NULL) 1053 sc->sc_tx99->start(sc->sc_tx99); 1054 else 1055 #endif 1056 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1057 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1058 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1059 } else 1060 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1061 done: 1062 ATH_UNLOCK(sc); 1063 return error; 1064 } 1065 1066 static void 1067 ath_stop_locked(struct ifnet *ifp, int disable) 1068 { 1069 struct ath_softc *sc = ifp->if_softc; 1070 struct ieee80211com *ic = &sc->sc_ic; 1071 struct ath_hal *ah = sc->sc_ah; 1072 1073 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1074 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1075 1076 ATH_LOCK_ASSERT(sc); 1077 if (ifp->if_flags & IFF_RUNNING) { 1078 /* 1079 * Shutdown the hardware and driver: 1080 * reset 802.11 state machine 1081 * turn off timers 1082 * disable interrupts 1083 * turn off the radio 1084 * clear transmit machinery 1085 * clear receive machinery 1086 * drain and release tx queues 1087 * reclaim beacon resources 1088 * power down hardware 1089 * 1090 * Note that some of this work is not possible if the 1091 * hardware is gone (invalid). 1092 */ 1093 #ifdef ATH_TX99_DIAG 1094 if (sc->sc_tx99 != NULL) 1095 sc->sc_tx99->stop(sc->sc_tx99); 1096 #endif 1097 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1098 ifp->if_flags &= ~IFF_RUNNING; 1099 ifp->if_timer = 0; 1100 if (device_is_enabled(sc->sc_dev)) { 1101 if (sc->sc_softled) { 1102 callout_stop(&sc->sc_ledtimer); 1103 ath_hal_gpioset(ah, sc->sc_ledpin, 1104 !sc->sc_ledon); 1105 sc->sc_blinking = 0; 1106 } 1107 ath_hal_intrset(ah, 0); 1108 } 1109 ath_draintxq(sc); 1110 if (device_is_enabled(sc->sc_dev)) { 1111 ath_stoprecv(sc); 1112 ath_hal_phydisable(ah); 1113 } else 1114 sc->sc_rxlink = NULL; 1115 IF_PURGE(&ifp->if_snd); 1116 ath_beacon_free(sc); 1117 if (disable) 1118 pmf_device_suspend_self(sc->sc_dev); 1119 } 1120 } 1121 1122 static void 1123 ath_stop(struct ifnet *ifp, int disable) 1124 { 1125 struct ath_softc *sc = ifp->if_softc; 1126 1127 ATH_LOCK(sc); 1128 ath_stop_locked(ifp, disable); 1129 ATH_UNLOCK(sc); 1130 } 1131 1132 static void 1133 ath_restore_diversity(struct ath_softc *sc) 1134 { 1135 struct ifnet *ifp = &sc->sc_if; 1136 struct ath_hal *ah = sc->sc_ah; 1137 1138 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1139 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1140 if_printf(ifp, "could not restore diversity setting %d\n", 1141 sc->sc_diversity); 1142 sc->sc_diversity = ath_hal_getdiversity(ah); 1143 } 1144 } 1145 1146 /* 1147 * Reset the hardware w/o losing operational state. This is 1148 * basically a more efficient way of doing ath_stop, ath_init, 1149 * followed by state transitions to the current 802.11 1150 * operational state. Used to recover from various errors and 1151 * to reset or reload hardware state. 1152 */ 1153 int 1154 ath_reset(struct ifnet *ifp) 1155 { 1156 struct ath_softc *sc = ifp->if_softc; 1157 struct ieee80211com *ic = &sc->sc_ic; 1158 struct ath_hal *ah = sc->sc_ah; 1159 struct ieee80211_channel *c; 1160 HAL_STATUS status; 1161 1162 /* 1163 * Convert to a HAL channel description with the flags 1164 * constrained to reflect the current operating mode. 1165 */ 1166 c = ic->ic_curchan; 1167 sc->sc_curchan.channel = c->ic_freq; 1168 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1169 1170 ath_hal_intrset(ah, 0); /* disable interrupts */ 1171 ath_draintxq(sc); /* stop xmit side */ 1172 ath_stoprecv(sc); /* stop recv side */ 1173 /* NB: indicate channel change so we do a full reset */ 1174 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1175 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1176 __func__, status); 1177 ath_update_txpow(sc); /* update tx power state */ 1178 ath_restore_diversity(sc); 1179 sc->sc_calinterval = 1; 1180 sc->sc_caltries = 0; 1181 if (ath_startrecv(sc) != 0) /* restart recv */ 1182 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1183 /* 1184 * We may be doing a reset in response to an ioctl 1185 * that changes the channel so update any state that 1186 * might change as a result. 1187 */ 1188 ath_chan_change(sc, c); 1189 if (ic->ic_state == IEEE80211_S_RUN) 1190 ath_beacon_config(sc); /* restart beacons */ 1191 ath_hal_intrset(ah, sc->sc_imask); 1192 1193 ath_start(ifp); /* restart xmit */ 1194 return 0; 1195 } 1196 1197 /* 1198 * Cleanup driver resources when we run out of buffers 1199 * while processing fragments; return the tx buffers 1200 * allocated and drop node references. 1201 */ 1202 static void 1203 ath_txfrag_cleanup(struct ath_softc *sc, 1204 ath_bufhead *frags, struct ieee80211_node *ni) 1205 { 1206 struct ath_buf *bf; 1207 1208 ATH_TXBUF_LOCK_ASSERT(sc); 1209 1210 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1211 STAILQ_REMOVE_HEAD(frags, bf_list); 1212 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1213 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1214 ieee80211_node_decref(ni); 1215 } 1216 } 1217 1218 /* 1219 * Setup xmit of a fragmented frame. Allocate a buffer 1220 * for each frag and bump the node reference count to 1221 * reflect the held reference to be setup by ath_tx_start. 1222 */ 1223 static int 1224 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1225 struct mbuf *m0, struct ieee80211_node *ni) 1226 { 1227 struct mbuf *m; 1228 struct ath_buf *bf; 1229 1230 ATH_TXBUF_LOCK(sc); 1231 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1232 bf = STAILQ_FIRST(&sc->sc_txbuf); 1233 if (bf == NULL) { /* out of buffers, cleanup */ 1234 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1235 __func__); 1236 sc->sc_if.if_flags |= IFF_OACTIVE; 1237 ath_txfrag_cleanup(sc, frags, ni); 1238 break; 1239 } 1240 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1241 ieee80211_node_incref(ni); 1242 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1243 } 1244 ATH_TXBUF_UNLOCK(sc); 1245 1246 return !STAILQ_EMPTY(frags); 1247 } 1248 1249 static void 1250 ath_start(struct ifnet *ifp) 1251 { 1252 struct ath_softc *sc = ifp->if_softc; 1253 struct ath_hal *ah = sc->sc_ah; 1254 struct ieee80211com *ic = &sc->sc_ic; 1255 struct ieee80211_node *ni; 1256 struct ath_buf *bf; 1257 struct mbuf *m, *next; 1258 struct ieee80211_frame *wh; 1259 struct ether_header *eh; 1260 ath_bufhead frags; 1261 1262 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1263 !device_is_active(sc->sc_dev)) 1264 return; 1265 for (;;) { 1266 /* 1267 * Grab a TX buffer and associated resources. 1268 */ 1269 ATH_TXBUF_LOCK(sc); 1270 bf = STAILQ_FIRST(&sc->sc_txbuf); 1271 if (bf != NULL) 1272 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1273 ATH_TXBUF_UNLOCK(sc); 1274 if (bf == NULL) { 1275 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1276 __func__); 1277 sc->sc_stats.ast_tx_qstop++; 1278 ifp->if_flags |= IFF_OACTIVE; 1279 break; 1280 } 1281 /* 1282 * Poll the management queue for frames; they 1283 * have priority over normal data frames. 1284 */ 1285 IF_DEQUEUE(&ic->ic_mgtq, m); 1286 if (m == NULL) { 1287 /* 1288 * No data frames go out unless we're associated. 1289 */ 1290 if (ic->ic_state != IEEE80211_S_RUN) { 1291 DPRINTF(sc, ATH_DEBUG_XMIT, 1292 "%s: discard data packet, state %s\n", 1293 __func__, 1294 ieee80211_state_name[ic->ic_state]); 1295 sc->sc_stats.ast_tx_discard++; 1296 ATH_TXBUF_LOCK(sc); 1297 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1298 ATH_TXBUF_UNLOCK(sc); 1299 break; 1300 } 1301 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1302 if (m == NULL) { 1303 ATH_TXBUF_LOCK(sc); 1304 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1305 ATH_TXBUF_UNLOCK(sc); 1306 break; 1307 } 1308 STAILQ_INIT(&frags); 1309 /* 1310 * Find the node for the destination so we can do 1311 * things like power save and fast frames aggregation. 1312 */ 1313 if (m->m_len < sizeof(struct ether_header) && 1314 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1315 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1316 ni = NULL; 1317 goto bad; 1318 } 1319 eh = mtod(m, struct ether_header *); 1320 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1321 if (ni == NULL) { 1322 /* NB: ieee80211_find_txnode does stat+msg */ 1323 m_freem(m); 1324 goto bad; 1325 } 1326 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1327 (m->m_flags & M_PWR_SAV) == 0) { 1328 /* 1329 * Station in power save mode; pass the frame 1330 * to the 802.11 layer and continue. We'll get 1331 * the frame back when the time is right. 1332 */ 1333 ieee80211_pwrsave(ic, ni, m); 1334 goto reclaim; 1335 } 1336 /* calculate priority so we can find the tx queue */ 1337 if (ieee80211_classify(ic, m, ni)) { 1338 DPRINTF(sc, ATH_DEBUG_XMIT, 1339 "%s: discard, classification failure\n", 1340 __func__); 1341 m_freem(m); 1342 goto bad; 1343 } 1344 ifp->if_opackets++; 1345 1346 #if NBPFILTER > 0 1347 if (ifp->if_bpf) 1348 bpf_mtap(ifp->if_bpf, m); 1349 #endif 1350 /* 1351 * Encapsulate the packet in prep for transmission. 1352 */ 1353 m = ieee80211_encap(ic, m, ni); 1354 if (m == NULL) { 1355 DPRINTF(sc, ATH_DEBUG_XMIT, 1356 "%s: encapsulation failure\n", 1357 __func__); 1358 sc->sc_stats.ast_tx_encap++; 1359 goto bad; 1360 } 1361 /* 1362 * Check for fragmentation. If this has frame 1363 * has been broken up verify we have enough 1364 * buffers to send all the fragments so all 1365 * go out or none... 1366 */ 1367 if ((m->m_flags & M_FRAG) && 1368 !ath_txfrag_setup(sc, &frags, m, ni)) { 1369 DPRINTF(sc, ATH_DEBUG_ANY, 1370 "%s: out of txfrag buffers\n", __func__); 1371 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1372 ath_freetx(m); 1373 goto bad; 1374 } 1375 } else { 1376 /* 1377 * Hack! The referenced node pointer is in the 1378 * rcvif field of the packet header. This is 1379 * placed there by ieee80211_mgmt_output because 1380 * we need to hold the reference with the frame 1381 * and there's no other way (other than packet 1382 * tags which we consider too expensive to use) 1383 * to pass it along. 1384 */ 1385 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1386 m->m_pkthdr.rcvif = NULL; 1387 1388 wh = mtod(m, struct ieee80211_frame *); 1389 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1390 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1391 /* fill time stamp */ 1392 u_int64_t tsf; 1393 u_int32_t *tstamp; 1394 1395 tsf = ath_hal_gettsf64(ah); 1396 /* XXX: adjust 100us delay to xmit */ 1397 tsf += 100; 1398 tstamp = (u_int32_t *)&wh[1]; 1399 tstamp[0] = htole32(tsf & 0xffffffff); 1400 tstamp[1] = htole32(tsf >> 32); 1401 } 1402 sc->sc_stats.ast_tx_mgmt++; 1403 } 1404 1405 nextfrag: 1406 next = m->m_nextpkt; 1407 if (ath_tx_start(sc, ni, bf, m)) { 1408 bad: 1409 ifp->if_oerrors++; 1410 reclaim: 1411 ATH_TXBUF_LOCK(sc); 1412 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1413 ath_txfrag_cleanup(sc, &frags, ni); 1414 ATH_TXBUF_UNLOCK(sc); 1415 if (ni != NULL) 1416 ieee80211_free_node(ni); 1417 continue; 1418 } 1419 if (next != NULL) { 1420 m = next; 1421 bf = STAILQ_FIRST(&frags); 1422 KASSERT(bf != NULL, ("no buf for txfrag")); 1423 STAILQ_REMOVE_HEAD(&frags, bf_list); 1424 goto nextfrag; 1425 } 1426 1427 ifp->if_timer = 1; 1428 } 1429 } 1430 1431 static int 1432 ath_media_change(struct ifnet *ifp) 1433 { 1434 #define IS_UP(ifp) \ 1435 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1436 int error; 1437 1438 error = ieee80211_media_change(ifp); 1439 if (error == ENETRESET) { 1440 if (IS_UP(ifp)) 1441 ath_init(ifp->if_softc); /* XXX lose error */ 1442 error = 0; 1443 } 1444 return error; 1445 #undef IS_UP 1446 } 1447 1448 #ifdef AR_DEBUG 1449 static void 1450 ath_keyprint(const char *tag, u_int ix, 1451 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1452 { 1453 static const char *ciphers[] = { 1454 "WEP", 1455 "AES-OCB", 1456 "AES-CCM", 1457 "CKIP", 1458 "TKIP", 1459 "CLR", 1460 }; 1461 int i, n; 1462 1463 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1464 for (i = 0, n = hk->kv_len; i < n; i++) 1465 printf("%02x", hk->kv_val[i]); 1466 printf(" mac %s", ether_sprintf(mac)); 1467 if (hk->kv_type == HAL_CIPHER_TKIP) { 1468 printf(" mic "); 1469 for (i = 0; i < sizeof(hk->kv_mic); i++) 1470 printf("%02x", hk->kv_mic[i]); 1471 } 1472 printf("\n"); 1473 } 1474 #endif 1475 1476 /* 1477 * Set a TKIP key into the hardware. This handles the 1478 * potential distribution of key state to multiple key 1479 * cache slots for TKIP. 1480 */ 1481 static int 1482 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1483 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1484 { 1485 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1486 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1487 struct ath_hal *ah = sc->sc_ah; 1488 1489 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1490 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1491 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1492 if (sc->sc_splitmic) { 1493 /* 1494 * TX key goes at first index, RX key at the rx index. 1495 * The hal handles the MIC keys at index+64. 1496 */ 1497 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1498 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1499 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1500 zerobssid)) 1501 return 0; 1502 1503 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1504 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1505 /* XXX delete tx key on failure? */ 1506 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1507 hk, mac); 1508 } else { 1509 /* 1510 * Room for both TX+RX MIC keys in one key cache 1511 * slot, just set key at the first index; the HAL 1512 * will handle the reset. 1513 */ 1514 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1515 #if HAL_ABI_VERSION > 0x06052200 1516 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1517 #endif 1518 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1519 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1520 } 1521 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1522 /* 1523 * TX/RX key goes at first index. 1524 * The hal handles the MIC keys are index+64. 1525 */ 1526 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1527 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1528 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1529 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1530 } 1531 return 0; 1532 #undef IEEE80211_KEY_XR 1533 } 1534 1535 /* 1536 * Set a net80211 key into the hardware. This handles the 1537 * potential distribution of key state to multiple key 1538 * cache slots for TKIP with hardware MIC support. 1539 */ 1540 static int 1541 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1542 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1543 struct ieee80211_node *bss) 1544 { 1545 #define N(a) (sizeof(a)/sizeof(a[0])) 1546 static const u_int8_t ciphermap[] = { 1547 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1548 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1549 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1550 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1551 (u_int8_t) -1, /* 4 is not allocated */ 1552 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1553 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1554 }; 1555 struct ath_hal *ah = sc->sc_ah; 1556 const struct ieee80211_cipher *cip = k->wk_cipher; 1557 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1558 const u_int8_t *mac; 1559 HAL_KEYVAL hk; 1560 1561 memset(&hk, 0, sizeof(hk)); 1562 /* 1563 * Software crypto uses a "clear key" so non-crypto 1564 * state kept in the key cache are maintained and 1565 * so that rx frames have an entry to match. 1566 */ 1567 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1568 KASSERT(cip->ic_cipher < N(ciphermap), 1569 ("invalid cipher type %u", cip->ic_cipher)); 1570 hk.kv_type = ciphermap[cip->ic_cipher]; 1571 hk.kv_len = k->wk_keylen; 1572 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1573 } else 1574 hk.kv_type = HAL_CIPHER_CLR; 1575 1576 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1577 /* 1578 * Group keys on hardware that supports multicast frame 1579 * key search use a mac that is the sender's address with 1580 * the high bit set instead of the app-specified address. 1581 */ 1582 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1583 gmac[0] |= 0x80; 1584 mac = gmac; 1585 } else 1586 mac = mac0; 1587 1588 if ((hk.kv_type == HAL_CIPHER_TKIP && 1589 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) && sc->sc_splitmic) { 1590 return ath_keyset_tkip(sc, k, &hk, mac); 1591 } else { 1592 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1593 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1594 } 1595 #undef N 1596 } 1597 1598 /* 1599 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1600 * each key, one for decrypt/encrypt and the other for the MIC. 1601 */ 1602 static u_int16_t 1603 key_alloc_2pair(struct ath_softc *sc, 1604 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1605 { 1606 #define N(a) (sizeof(a)/sizeof(a[0])) 1607 u_int i, keyix; 1608 1609 KASSERT(sc->sc_splitmic, ("key cache !split")); 1610 /* XXX could optimize */ 1611 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1612 u_int8_t b = sc->sc_keymap[i]; 1613 if (b != 0xff) { 1614 /* 1615 * One or more slots in this byte are free. 1616 */ 1617 keyix = i*NBBY; 1618 while (b & 1) { 1619 again: 1620 keyix++; 1621 b >>= 1; 1622 } 1623 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1624 if (isset(sc->sc_keymap, keyix+32) || 1625 isset(sc->sc_keymap, keyix+64) || 1626 isset(sc->sc_keymap, keyix+32+64)) { 1627 /* full pair unavailable */ 1628 /* XXX statistic */ 1629 if (keyix == (i+1)*NBBY) { 1630 /* no slots were appropriate, advance */ 1631 continue; 1632 } 1633 goto again; 1634 } 1635 setbit(sc->sc_keymap, keyix); 1636 setbit(sc->sc_keymap, keyix+64); 1637 setbit(sc->sc_keymap, keyix+32); 1638 setbit(sc->sc_keymap, keyix+32+64); 1639 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1640 "%s: key pair %u,%u %u,%u\n", 1641 __func__, keyix, keyix+64, 1642 keyix+32, keyix+32+64); 1643 *txkeyix = keyix; 1644 *rxkeyix = keyix+32; 1645 return keyix; 1646 } 1647 } 1648 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1649 return IEEE80211_KEYIX_NONE; 1650 #undef N 1651 } 1652 1653 /* 1654 * Allocate a single key cache slot. 1655 */ 1656 static int 1657 key_alloc_single(struct ath_softc *sc, 1658 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1659 { 1660 #define N(a) (sizeof(a)/sizeof(a[0])) 1661 u_int i, keyix; 1662 1663 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1664 for (i = 0; i < N(sc->sc_keymap); i++) { 1665 u_int8_t b = sc->sc_keymap[i]; 1666 if (b != 0xff) { 1667 /* 1668 * One or more slots are free. 1669 */ 1670 keyix = i*NBBY; 1671 while (b & 1) 1672 keyix++, b >>= 1; 1673 setbit(sc->sc_keymap, keyix); 1674 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1675 __func__, keyix); 1676 *txkeyix = *rxkeyix = keyix; 1677 return 1; 1678 } 1679 } 1680 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1681 return 0; 1682 #undef N 1683 } 1684 1685 /* 1686 * Allocate one or more key cache slots for a uniacst key. The 1687 * key itself is needed only to identify the cipher. For hardware 1688 * TKIP with split cipher+MIC keys we allocate two key cache slot 1689 * pairs so that we can setup separate TX and RX MIC keys. Note 1690 * that the MIC key for a TKIP key at slot i is assumed by the 1691 * hardware to be at slot i+64. This limits TKIP keys to the first 1692 * 64 entries. 1693 */ 1694 static int 1695 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1696 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1697 { 1698 struct ath_softc *sc = ic->ic_ifp->if_softc; 1699 1700 /* 1701 * Group key allocation must be handled specially for 1702 * parts that do not support multicast key cache search 1703 * functionality. For those parts the key id must match 1704 * the h/w key index so lookups find the right key. On 1705 * parts w/ the key search facility we install the sender's 1706 * mac address (with the high bit set) and let the hardware 1707 * find the key w/o using the key id. This is preferred as 1708 * it permits us to support multiple users for adhoc and/or 1709 * multi-station operation. 1710 */ 1711 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1712 if (!(&ic->ic_nw_keys[0] <= k && 1713 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1714 /* should not happen */ 1715 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1716 "%s: bogus group key\n", __func__); 1717 return 0; 1718 } 1719 /* 1720 * XXX we pre-allocate the global keys so 1721 * have no way to check if they've already been allocated. 1722 */ 1723 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1724 return 1; 1725 } 1726 1727 /* 1728 * We allocate two pair for TKIP when using the h/w to do 1729 * the MIC. For everything else, including software crypto, 1730 * we allocate a single entry. Note that s/w crypto requires 1731 * a pass-through slot on the 5211 and 5212. The 5210 does 1732 * not support pass-through cache entries and we map all 1733 * those requests to slot 0. 1734 */ 1735 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1736 return key_alloc_single(sc, keyix, rxkeyix); 1737 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1738 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1739 return key_alloc_2pair(sc, keyix, rxkeyix); 1740 } else { 1741 return key_alloc_single(sc, keyix, rxkeyix); 1742 } 1743 } 1744 1745 /* 1746 * Delete an entry in the key cache allocated by ath_key_alloc. 1747 */ 1748 static int 1749 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1750 { 1751 struct ath_softc *sc = ic->ic_ifp->if_softc; 1752 struct ath_hal *ah = sc->sc_ah; 1753 const struct ieee80211_cipher *cip = k->wk_cipher; 1754 u_int keyix = k->wk_keyix; 1755 1756 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1757 1758 if (!device_has_power(sc->sc_dev)) { 1759 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1760 k->wk_keyix); 1761 } 1762 1763 ath_hal_keyreset(ah, keyix); 1764 /* 1765 * Handle split tx/rx keying required for TKIP with h/w MIC. 1766 */ 1767 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1768 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1769 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1770 if (keyix >= IEEE80211_WEP_NKID) { 1771 /* 1772 * Don't touch keymap entries for global keys so 1773 * they are never considered for dynamic allocation. 1774 */ 1775 clrbit(sc->sc_keymap, keyix); 1776 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1777 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1778 sc->sc_splitmic) { 1779 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1780 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1781 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1782 } 1783 } 1784 return 1; 1785 } 1786 1787 /* 1788 * Set the key cache contents for the specified key. Key cache 1789 * slot(s) must already have been allocated by ath_key_alloc. 1790 */ 1791 static int 1792 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1793 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1794 { 1795 struct ath_softc *sc = ic->ic_ifp->if_softc; 1796 1797 if (!device_has_power(sc->sc_dev)) { 1798 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1799 k->wk_keyix); 1800 } 1801 return ath_keyset(sc, k, mac, ic->ic_bss); 1802 } 1803 1804 /* 1805 * Block/unblock tx+rx processing while a key change is done. 1806 * We assume the caller serializes key management operations 1807 * so we only need to worry about synchronization with other 1808 * uses that originate in the driver. 1809 */ 1810 static void 1811 ath_key_update_begin(struct ieee80211com *ic) 1812 { 1813 struct ifnet *ifp = ic->ic_ifp; 1814 struct ath_softc *sc = ifp->if_softc; 1815 1816 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1817 #if 0 1818 tasklet_disable(&sc->sc_rxtq); 1819 #endif 1820 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1821 } 1822 1823 static void 1824 ath_key_update_end(struct ieee80211com *ic) 1825 { 1826 struct ifnet *ifp = ic->ic_ifp; 1827 struct ath_softc *sc = ifp->if_softc; 1828 1829 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1830 IF_UNLOCK(&ifp->if_snd); 1831 #if 0 1832 tasklet_enable(&sc->sc_rxtq); 1833 #endif 1834 } 1835 1836 /* 1837 * Calculate the receive filter according to the 1838 * operating mode and state: 1839 * 1840 * o always accept unicast, broadcast, and multicast traffic 1841 * o maintain current state of phy error reception (the hal 1842 * may enable phy error frames for noise immunity work) 1843 * o probe request frames are accepted only when operating in 1844 * hostap, adhoc, or monitor modes 1845 * o enable promiscuous mode according to the interface state 1846 * o accept beacons: 1847 * - when operating in adhoc mode so the 802.11 layer creates 1848 * node table entries for peers, 1849 * - when operating in station mode for collecting rssi data when 1850 * the station is otherwise quiet, or 1851 * - when scanning 1852 */ 1853 static u_int32_t 1854 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1855 { 1856 struct ieee80211com *ic = &sc->sc_ic; 1857 struct ath_hal *ah = sc->sc_ah; 1858 struct ifnet *ifp = &sc->sc_if; 1859 u_int32_t rfilt; 1860 1861 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1862 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1863 if (ic->ic_opmode != IEEE80211_M_STA) 1864 rfilt |= HAL_RX_FILTER_PROBEREQ; 1865 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1866 (ifp->if_flags & IFF_PROMISC)) 1867 rfilt |= HAL_RX_FILTER_PROM; 1868 if (ifp->if_flags & IFF_PROMISC) 1869 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1870 if (ic->ic_opmode == IEEE80211_M_STA || 1871 ic->ic_opmode == IEEE80211_M_IBSS || 1872 state == IEEE80211_S_SCAN) 1873 rfilt |= HAL_RX_FILTER_BEACON; 1874 return rfilt; 1875 } 1876 1877 static void 1878 ath_mode_init(struct ath_softc *sc) 1879 { 1880 struct ifnet *ifp = &sc->sc_if; 1881 struct ieee80211com *ic = &sc->sc_ic; 1882 struct ath_hal *ah = sc->sc_ah; 1883 struct ether_multi *enm; 1884 struct ether_multistep estep; 1885 u_int32_t rfilt, mfilt[2], val; 1886 int i; 1887 uint8_t pos; 1888 1889 /* configure rx filter */ 1890 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1891 ath_hal_setrxfilter(ah, rfilt); 1892 1893 /* configure operational mode */ 1894 ath_hal_setopmode(ah); 1895 1896 /* Write keys to hardware; it may have been powered down. */ 1897 ath_key_update_begin(ic); 1898 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1899 ath_key_set(ic, 1900 &ic->ic_crypto.cs_nw_keys[i], 1901 ic->ic_myaddr); 1902 } 1903 ath_key_update_end(ic); 1904 1905 /* 1906 * Handle any link-level address change. Note that we only 1907 * need to force ic_myaddr; any other addresses are handled 1908 * as a byproduct of the ifnet code marking the interface 1909 * down then up. 1910 * 1911 * XXX should get from lladdr instead of arpcom but that's more work 1912 */ 1913 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1914 ath_hal_setmac(ah, ic->ic_myaddr); 1915 1916 /* calculate and install multicast filter */ 1917 ifp->if_flags &= ~IFF_ALLMULTI; 1918 mfilt[0] = mfilt[1] = 0; 1919 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1920 while (enm != NULL) { 1921 void *dl; 1922 /* XXX Punt on ranges. */ 1923 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1924 mfilt[0] = mfilt[1] = 0xffffffff; 1925 ifp->if_flags |= IFF_ALLMULTI; 1926 break; 1927 } 1928 dl = enm->enm_addrlo; 1929 val = LE_READ_4((char *)dl + 0); 1930 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1931 val = LE_READ_4((char *)dl + 3); 1932 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1933 pos &= 0x3f; 1934 mfilt[pos / 32] |= (1 << (pos % 32)); 1935 1936 ETHER_NEXT_MULTI(estep, enm); 1937 } 1938 1939 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1940 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1941 __func__, rfilt, mfilt[0], mfilt[1]); 1942 } 1943 1944 /* 1945 * Set the slot time based on the current setting. 1946 */ 1947 static void 1948 ath_setslottime(struct ath_softc *sc) 1949 { 1950 struct ieee80211com *ic = &sc->sc_ic; 1951 struct ath_hal *ah = sc->sc_ah; 1952 1953 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1954 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1955 else 1956 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1957 sc->sc_updateslot = OK; 1958 } 1959 1960 /* 1961 * Callback from the 802.11 layer to update the 1962 * slot time based on the current setting. 1963 */ 1964 static void 1965 ath_updateslot(struct ifnet *ifp) 1966 { 1967 struct ath_softc *sc = ifp->if_softc; 1968 struct ieee80211com *ic = &sc->sc_ic; 1969 1970 /* 1971 * When not coordinating the BSS, change the hardware 1972 * immediately. For other operation we defer the change 1973 * until beacon updates have propagated to the stations. 1974 */ 1975 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1976 sc->sc_updateslot = UPDATE; 1977 else 1978 ath_setslottime(sc); 1979 } 1980 1981 /* 1982 * Setup a h/w transmit queue for beacons. 1983 */ 1984 static int 1985 ath_beaconq_setup(struct ath_hal *ah) 1986 { 1987 HAL_TXQ_INFO qi; 1988 1989 memset(&qi, 0, sizeof(qi)); 1990 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1991 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1992 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1993 /* NB: for dynamic turbo, don't enable any other interrupts */ 1994 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1995 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1996 } 1997 1998 /* 1999 * Setup the transmit queue parameters for the beacon queue. 2000 */ 2001 static int 2002 ath_beaconq_config(struct ath_softc *sc) 2003 { 2004 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2005 struct ieee80211com *ic = &sc->sc_ic; 2006 struct ath_hal *ah = sc->sc_ah; 2007 HAL_TXQ_INFO qi; 2008 2009 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2010 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2011 /* 2012 * Always burst out beacon and CAB traffic. 2013 */ 2014 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2015 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2016 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2017 } else { 2018 struct wmeParams *wmep = 2019 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2020 /* 2021 * Adhoc mode; important thing is to use 2x cwmin. 2022 */ 2023 qi.tqi_aifs = wmep->wmep_aifsn; 2024 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2025 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2026 } 2027 2028 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2029 device_printf(sc->sc_dev, "unable to update parameters for " 2030 "beacon hardware queue!\n"); 2031 return 0; 2032 } else { 2033 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2034 return 1; 2035 } 2036 #undef ATH_EXPONENT_TO_VALUE 2037 } 2038 2039 /* 2040 * Allocate and setup an initial beacon frame. 2041 */ 2042 static int 2043 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2044 { 2045 struct ieee80211com *ic = ni->ni_ic; 2046 struct ath_buf *bf; 2047 struct mbuf *m; 2048 int error; 2049 2050 bf = STAILQ_FIRST(&sc->sc_bbuf); 2051 if (bf == NULL) { 2052 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2053 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2054 return ENOMEM; /* XXX */ 2055 } 2056 /* 2057 * NB: the beacon data buffer must be 32-bit aligned; 2058 * we assume the mbuf routines will return us something 2059 * with this alignment (perhaps should assert). 2060 */ 2061 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2062 if (m == NULL) { 2063 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2064 __func__); 2065 sc->sc_stats.ast_be_nombuf++; 2066 return ENOMEM; 2067 } 2068 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2069 BUS_DMA_NOWAIT); 2070 if (error == 0) { 2071 bf->bf_m = m; 2072 bf->bf_node = ieee80211_ref_node(ni); 2073 } else { 2074 m_freem(m); 2075 } 2076 return error; 2077 } 2078 2079 /* 2080 * Setup the beacon frame for transmit. 2081 */ 2082 static void 2083 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2084 { 2085 #define USE_SHPREAMBLE(_ic) \ 2086 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2087 == IEEE80211_F_SHPREAMBLE) 2088 struct ieee80211_node *ni = bf->bf_node; 2089 struct ieee80211com *ic = ni->ni_ic; 2090 struct mbuf *m = bf->bf_m; 2091 struct ath_hal *ah = sc->sc_ah; 2092 struct ath_desc *ds; 2093 int flags, antenna; 2094 const HAL_RATE_TABLE *rt; 2095 u_int8_t rix, rate; 2096 2097 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2098 __func__, m, m->m_len); 2099 2100 /* setup descriptors */ 2101 ds = bf->bf_desc; 2102 2103 flags = HAL_TXDESC_NOACK; 2104 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2105 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2106 flags |= HAL_TXDESC_VEOL; 2107 /* 2108 * Let hardware handle antenna switching unless 2109 * the user has selected a transmit antenna 2110 * (sc_txantenna is not 0). 2111 */ 2112 antenna = sc->sc_txantenna; 2113 } else { 2114 ds->ds_link = 0; 2115 /* 2116 * Switch antenna every 4 beacons, unless the user 2117 * has selected a transmit antenna (sc_txantenna 2118 * is not 0). 2119 * 2120 * XXX assumes two antenna 2121 */ 2122 if (sc->sc_txantenna == 0) 2123 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2124 else 2125 antenna = sc->sc_txantenna; 2126 } 2127 2128 KASSERT(bf->bf_nseg == 1, 2129 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2130 ds->ds_data = bf->bf_segs[0].ds_addr; 2131 /* 2132 * Calculate rate code. 2133 * XXX everything at min xmit rate 2134 */ 2135 rix = sc->sc_minrateix; 2136 rt = sc->sc_currates; 2137 rate = rt->info[rix].rateCode; 2138 if (USE_SHPREAMBLE(ic)) 2139 rate |= rt->info[rix].shortPreamble; 2140 ath_hal_setuptxdesc(ah, ds 2141 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2142 , sizeof(struct ieee80211_frame)/* header length */ 2143 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2144 , ni->ni_txpower /* txpower XXX */ 2145 , rate, 1 /* series 0 rate/tries */ 2146 , HAL_TXKEYIX_INVALID /* no encryption */ 2147 , antenna /* antenna mode */ 2148 , flags /* no ack, veol for beacons */ 2149 , 0 /* rts/cts rate */ 2150 , 0 /* rts/cts duration */ 2151 ); 2152 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2153 ath_hal_filltxdesc(ah, ds 2154 , roundup(m->m_len, 4) /* buffer length */ 2155 , AH_TRUE /* first segment */ 2156 , AH_TRUE /* last segment */ 2157 , ds /* first descriptor */ 2158 ); 2159 2160 /* NB: The desc swap function becomes void, if descriptor swapping 2161 * is not enabled 2162 */ 2163 ath_desc_swap(ds); 2164 2165 #undef USE_SHPREAMBLE 2166 } 2167 2168 /* 2169 * Transmit a beacon frame at SWBA. Dynamic updates to the 2170 * frame contents are done as needed and the slot time is 2171 * also adjusted based on current state. 2172 */ 2173 static void 2174 ath_beacon_proc(void *arg, int pending) 2175 { 2176 struct ath_softc *sc = arg; 2177 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2178 struct ieee80211_node *ni = bf->bf_node; 2179 struct ieee80211com *ic = ni->ni_ic; 2180 struct ath_hal *ah = sc->sc_ah; 2181 struct mbuf *m; 2182 int ncabq, error, otherant; 2183 2184 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2185 __func__, pending); 2186 2187 if (ic->ic_opmode == IEEE80211_M_STA || 2188 ic->ic_opmode == IEEE80211_M_MONITOR || 2189 bf == NULL || bf->bf_m == NULL) { 2190 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2191 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2192 return; 2193 } 2194 /* 2195 * Check if the previous beacon has gone out. If 2196 * not don't try to post another, skip this period 2197 * and wait for the next. Missed beacons indicate 2198 * a problem and should not occur. If we miss too 2199 * many consecutive beacons reset the device. 2200 */ 2201 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2202 sc->sc_bmisscount++; 2203 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2204 "%s: missed %u consecutive beacons\n", 2205 __func__, sc->sc_bmisscount); 2206 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2207 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2208 return; 2209 } 2210 if (sc->sc_bmisscount != 0) { 2211 DPRINTF(sc, ATH_DEBUG_BEACON, 2212 "%s: resume beacon xmit after %u misses\n", 2213 __func__, sc->sc_bmisscount); 2214 sc->sc_bmisscount = 0; 2215 } 2216 2217 /* 2218 * Update dynamic beacon contents. If this returns 2219 * non-zero then we need to remap the memory because 2220 * the beacon frame changed size (probably because 2221 * of the TIM bitmap). 2222 */ 2223 m = bf->bf_m; 2224 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2225 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2226 /* XXX too conservative? */ 2227 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2228 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2229 BUS_DMA_NOWAIT); 2230 if (error != 0) { 2231 if_printf(&sc->sc_if, 2232 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2233 __func__, error); 2234 return; 2235 } 2236 } 2237 2238 /* 2239 * Handle slot time change when a non-ERP station joins/leaves 2240 * an 11g network. The 802.11 layer notifies us via callback, 2241 * we mark updateslot, then wait one beacon before effecting 2242 * the change. This gives associated stations at least one 2243 * beacon interval to note the state change. 2244 */ 2245 /* XXX locking */ 2246 if (sc->sc_updateslot == UPDATE) 2247 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2248 else if (sc->sc_updateslot == COMMIT) 2249 ath_setslottime(sc); /* commit change to h/w */ 2250 2251 /* 2252 * Check recent per-antenna transmit statistics and flip 2253 * the default antenna if noticeably more frames went out 2254 * on the non-default antenna. 2255 * XXX assumes 2 anntenae 2256 */ 2257 otherant = sc->sc_defant & 1 ? 2 : 1; 2258 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2259 ath_setdefantenna(sc, otherant); 2260 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2261 2262 /* 2263 * Construct tx descriptor. 2264 */ 2265 ath_beacon_setup(sc, bf); 2266 2267 /* 2268 * Stop any current dma and put the new frame on the queue. 2269 * This should never fail since we check above that no frames 2270 * are still pending on the queue. 2271 */ 2272 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2273 DPRINTF(sc, ATH_DEBUG_ANY, 2274 "%s: beacon queue %u did not stop?\n", 2275 __func__, sc->sc_bhalq); 2276 } 2277 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2278 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2279 2280 /* 2281 * Enable the CAB queue before the beacon queue to 2282 * insure cab frames are triggered by this beacon. 2283 */ 2284 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2285 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2286 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2287 ath_hal_txstart(ah, sc->sc_bhalq); 2288 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2289 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2290 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2291 2292 sc->sc_stats.ast_be_xmit++; 2293 } 2294 2295 /* 2296 * Reset the hardware after detecting beacons have stopped. 2297 */ 2298 static void 2299 ath_bstuck_proc(void *arg, int pending) 2300 { 2301 struct ath_softc *sc = arg; 2302 struct ifnet *ifp = &sc->sc_if; 2303 2304 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2305 sc->sc_bmisscount); 2306 ath_reset(ifp); 2307 } 2308 2309 /* 2310 * Reclaim beacon resources. 2311 */ 2312 static void 2313 ath_beacon_free(struct ath_softc *sc) 2314 { 2315 struct ath_buf *bf; 2316 2317 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2318 if (bf->bf_m != NULL) { 2319 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2320 m_freem(bf->bf_m); 2321 bf->bf_m = NULL; 2322 } 2323 if (bf->bf_node != NULL) { 2324 ieee80211_free_node(bf->bf_node); 2325 bf->bf_node = NULL; 2326 } 2327 } 2328 } 2329 2330 /* 2331 * Configure the beacon and sleep timers. 2332 * 2333 * When operating as an AP this resets the TSF and sets 2334 * up the hardware to notify us when we need to issue beacons. 2335 * 2336 * When operating in station mode this sets up the beacon 2337 * timers according to the timestamp of the last received 2338 * beacon and the current TSF, configures PCF and DTIM 2339 * handling, programs the sleep registers so the hardware 2340 * will wakeup in time to receive beacons, and configures 2341 * the beacon miss handling so we'll receive a BMISS 2342 * interrupt when we stop seeing beacons from the AP 2343 * we've associated with. 2344 */ 2345 static void 2346 ath_beacon_config(struct ath_softc *sc) 2347 { 2348 #define TSF_TO_TU(_h,_l) \ 2349 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2350 #define FUDGE 2 2351 struct ath_hal *ah = sc->sc_ah; 2352 struct ieee80211com *ic = &sc->sc_ic; 2353 struct ieee80211_node *ni = ic->ic_bss; 2354 u_int32_t nexttbtt, intval, tsftu; 2355 u_int64_t tsf; 2356 2357 /* extract tstamp from last beacon and convert to TU */ 2358 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2359 LE_READ_4(ni->ni_tstamp.data)); 2360 /* NB: the beacon interval is kept internally in TU's */ 2361 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2362 if (nexttbtt == 0) /* e.g. for ap mode */ 2363 nexttbtt = intval; 2364 else if (intval) /* NB: can be 0 for monitor mode */ 2365 nexttbtt = roundup(nexttbtt, intval); 2366 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2367 __func__, nexttbtt, intval, ni->ni_intval); 2368 if (ic->ic_opmode == IEEE80211_M_STA) { 2369 HAL_BEACON_STATE bs; 2370 int dtimperiod, dtimcount; 2371 int cfpperiod, cfpcount; 2372 2373 /* 2374 * Setup dtim and cfp parameters according to 2375 * last beacon we received (which may be none). 2376 */ 2377 dtimperiod = ni->ni_dtim_period; 2378 if (dtimperiod <= 0) /* NB: 0 if not known */ 2379 dtimperiod = 1; 2380 dtimcount = ni->ni_dtim_count; 2381 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2382 dtimcount = 0; /* XXX? */ 2383 cfpperiod = 1; /* NB: no PCF support yet */ 2384 cfpcount = 0; 2385 /* 2386 * Pull nexttbtt forward to reflect the current 2387 * TSF and calculate dtim+cfp state for the result. 2388 */ 2389 tsf = ath_hal_gettsf64(ah); 2390 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2391 do { 2392 nexttbtt += intval; 2393 if (--dtimcount < 0) { 2394 dtimcount = dtimperiod - 1; 2395 if (--cfpcount < 0) 2396 cfpcount = cfpperiod - 1; 2397 } 2398 } while (nexttbtt < tsftu); 2399 memset(&bs, 0, sizeof(bs)); 2400 bs.bs_intval = intval; 2401 bs.bs_nexttbtt = nexttbtt; 2402 bs.bs_dtimperiod = dtimperiod*intval; 2403 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2404 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2405 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2406 bs.bs_cfpmaxduration = 0; 2407 #if 0 2408 /* 2409 * The 802.11 layer records the offset to the DTIM 2410 * bitmap while receiving beacons; use it here to 2411 * enable h/w detection of our AID being marked in 2412 * the bitmap vector (to indicate frames for us are 2413 * pending at the AP). 2414 * XXX do DTIM handling in s/w to WAR old h/w bugs 2415 * XXX enable based on h/w rev for newer chips 2416 */ 2417 bs.bs_timoffset = ni->ni_timoff; 2418 #endif 2419 /* 2420 * Calculate the number of consecutive beacons to miss 2421 * before taking a BMISS interrupt. The configuration 2422 * is specified in ms, so we need to convert that to 2423 * TU's and then calculate based on the beacon interval. 2424 * Note that we clamp the result to at most 10 beacons. 2425 */ 2426 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2427 if (bs.bs_bmissthreshold > 10) 2428 bs.bs_bmissthreshold = 10; 2429 else if (bs.bs_bmissthreshold <= 0) 2430 bs.bs_bmissthreshold = 1; 2431 2432 /* 2433 * Calculate sleep duration. The configuration is 2434 * given in ms. We insure a multiple of the beacon 2435 * period is used. Also, if the sleep duration is 2436 * greater than the DTIM period then it makes senses 2437 * to make it a multiple of that. 2438 * 2439 * XXX fixed at 100ms 2440 */ 2441 bs.bs_sleepduration = 2442 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2443 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2444 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2445 2446 DPRINTF(sc, ATH_DEBUG_BEACON, 2447 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2448 , __func__ 2449 , tsf, tsftu 2450 , bs.bs_intval 2451 , bs.bs_nexttbtt 2452 , bs.bs_dtimperiod 2453 , bs.bs_nextdtim 2454 , bs.bs_bmissthreshold 2455 , bs.bs_sleepduration 2456 , bs.bs_cfpperiod 2457 , bs.bs_cfpmaxduration 2458 , bs.bs_cfpnext 2459 , bs.bs_timoffset 2460 ); 2461 ath_hal_intrset(ah, 0); 2462 ath_hal_beacontimers(ah, &bs); 2463 sc->sc_imask |= HAL_INT_BMISS; 2464 ath_hal_intrset(ah, sc->sc_imask); 2465 } else { 2466 ath_hal_intrset(ah, 0); 2467 if (nexttbtt == intval) 2468 intval |= HAL_BEACON_RESET_TSF; 2469 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2470 /* 2471 * In IBSS mode enable the beacon timers but only 2472 * enable SWBA interrupts if we need to manually 2473 * prepare beacon frames. Otherwise we use a 2474 * self-linked tx descriptor and let the hardware 2475 * deal with things. 2476 */ 2477 intval |= HAL_BEACON_ENA; 2478 if (!sc->sc_hasveol) 2479 sc->sc_imask |= HAL_INT_SWBA; 2480 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2481 /* 2482 * Pull nexttbtt forward to reflect 2483 * the current TSF. 2484 */ 2485 tsf = ath_hal_gettsf64(ah); 2486 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2487 do { 2488 nexttbtt += intval; 2489 } while (nexttbtt < tsftu); 2490 } 2491 ath_beaconq_config(sc); 2492 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2493 /* 2494 * In AP mode we enable the beacon timers and 2495 * SWBA interrupts to prepare beacon frames. 2496 */ 2497 intval |= HAL_BEACON_ENA; 2498 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2499 ath_beaconq_config(sc); 2500 } 2501 ath_hal_beaconinit(ah, nexttbtt, intval); 2502 sc->sc_bmisscount = 0; 2503 ath_hal_intrset(ah, sc->sc_imask); 2504 /* 2505 * When using a self-linked beacon descriptor in 2506 * ibss mode load it once here. 2507 */ 2508 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2509 ath_beacon_proc(sc, 0); 2510 } 2511 sc->sc_syncbeacon = 0; 2512 #undef UNDEF 2513 #undef TSF_TO_TU 2514 } 2515 2516 static int 2517 ath_descdma_setup(struct ath_softc *sc, 2518 struct ath_descdma *dd, ath_bufhead *head, 2519 const char *name, int nbuf, int ndesc) 2520 { 2521 #define DS2PHYS(_dd, _ds) \ 2522 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2523 struct ifnet *ifp = &sc->sc_if; 2524 struct ath_desc *ds; 2525 struct ath_buf *bf; 2526 int i, bsize, error; 2527 2528 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2529 __func__, name, nbuf, ndesc); 2530 2531 dd->dd_name = name; 2532 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2533 2534 /* 2535 * Setup DMA descriptor area. 2536 */ 2537 dd->dd_dmat = sc->sc_dmat; 2538 2539 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2540 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2541 2542 if (error != 0) { 2543 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2544 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2545 goto fail0; 2546 } 2547 2548 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2549 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2550 if (error != 0) { 2551 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2552 nbuf * ndesc, dd->dd_name, error); 2553 goto fail1; 2554 } 2555 2556 /* allocate descriptors */ 2557 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2558 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2559 if (error != 0) { 2560 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2561 "error %u\n", dd->dd_name, error); 2562 goto fail2; 2563 } 2564 2565 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2566 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2567 if (error != 0) { 2568 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2569 dd->dd_name, error); 2570 goto fail3; 2571 } 2572 2573 ds = dd->dd_desc; 2574 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2575 DPRINTF(sc, ATH_DEBUG_RESET, 2576 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2577 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2578 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2579 2580 /* allocate rx buffers */ 2581 bsize = sizeof(struct ath_buf) * nbuf; 2582 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2583 if (bf == NULL) { 2584 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2585 dd->dd_name, bsize); 2586 goto fail4; 2587 } 2588 dd->dd_bufptr = bf; 2589 2590 STAILQ_INIT(head); 2591 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2592 bf->bf_desc = ds; 2593 bf->bf_daddr = DS2PHYS(dd, ds); 2594 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2595 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2596 if (error != 0) { 2597 if_printf(ifp, "unable to create dmamap for %s " 2598 "buffer %u, error %u\n", dd->dd_name, i, error); 2599 ath_descdma_cleanup(sc, dd, head); 2600 return error; 2601 } 2602 STAILQ_INSERT_TAIL(head, bf, bf_list); 2603 } 2604 return 0; 2605 fail4: 2606 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2607 fail3: 2608 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2609 fail2: 2610 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2611 fail1: 2612 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2613 fail0: 2614 memset(dd, 0, sizeof(*dd)); 2615 return error; 2616 #undef DS2PHYS 2617 } 2618 2619 static void 2620 ath_descdma_cleanup(struct ath_softc *sc, 2621 struct ath_descdma *dd, ath_bufhead *head) 2622 { 2623 struct ath_buf *bf; 2624 struct ieee80211_node *ni; 2625 2626 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2627 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2628 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2629 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2630 2631 STAILQ_FOREACH(bf, head, bf_list) { 2632 if (bf->bf_m) { 2633 m_freem(bf->bf_m); 2634 bf->bf_m = NULL; 2635 } 2636 if (bf->bf_dmamap != NULL) { 2637 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2638 bf->bf_dmamap = NULL; 2639 } 2640 ni = bf->bf_node; 2641 bf->bf_node = NULL; 2642 if (ni != NULL) { 2643 /* 2644 * Reclaim node reference. 2645 */ 2646 ieee80211_free_node(ni); 2647 } 2648 } 2649 2650 STAILQ_INIT(head); 2651 free(dd->dd_bufptr, M_ATHDEV); 2652 memset(dd, 0, sizeof(*dd)); 2653 } 2654 2655 static int 2656 ath_desc_alloc(struct ath_softc *sc) 2657 { 2658 int error; 2659 2660 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2661 "rx", ath_rxbuf, 1); 2662 if (error != 0) 2663 return error; 2664 2665 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2666 "tx", ath_txbuf, ATH_TXDESC); 2667 if (error != 0) { 2668 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2669 return error; 2670 } 2671 2672 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2673 "beacon", 1, 1); 2674 if (error != 0) { 2675 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2676 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2677 return error; 2678 } 2679 return 0; 2680 } 2681 2682 static void 2683 ath_desc_free(struct ath_softc *sc) 2684 { 2685 2686 if (sc->sc_bdma.dd_desc_len != 0) 2687 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2688 if (sc->sc_txdma.dd_desc_len != 0) 2689 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2690 if (sc->sc_rxdma.dd_desc_len != 0) 2691 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2692 } 2693 2694 static struct ieee80211_node * 2695 ath_node_alloc(struct ieee80211_node_table *nt) 2696 { 2697 struct ieee80211com *ic = nt->nt_ic; 2698 struct ath_softc *sc = ic->ic_ifp->if_softc; 2699 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2700 struct ath_node *an; 2701 2702 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2703 if (an == NULL) { 2704 /* XXX stat+msg */ 2705 return NULL; 2706 } 2707 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2708 ath_rate_node_init(sc, an); 2709 2710 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2711 return &an->an_node; 2712 } 2713 2714 static void 2715 ath_node_free(struct ieee80211_node *ni) 2716 { 2717 struct ieee80211com *ic = ni->ni_ic; 2718 struct ath_softc *sc = ic->ic_ifp->if_softc; 2719 2720 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2721 2722 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2723 sc->sc_node_free(ni); 2724 } 2725 2726 static u_int8_t 2727 ath_node_getrssi(const struct ieee80211_node *ni) 2728 { 2729 #define HAL_EP_RND(x, mul) \ 2730 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2731 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2732 int32_t rssi; 2733 2734 /* 2735 * When only one frame is received there will be no state in 2736 * avgrssi so fallback on the value recorded by the 802.11 layer. 2737 */ 2738 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2739 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2740 else 2741 rssi = ni->ni_rssi; 2742 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2743 #undef HAL_EP_RND 2744 } 2745 2746 static int 2747 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2748 { 2749 struct ath_hal *ah = sc->sc_ah; 2750 int error; 2751 struct mbuf *m; 2752 struct ath_desc *ds; 2753 2754 m = bf->bf_m; 2755 if (m == NULL) { 2756 /* 2757 * NB: by assigning a page to the rx dma buffer we 2758 * implicitly satisfy the Atheros requirement that 2759 * this buffer be cache-line-aligned and sized to be 2760 * multiple of the cache line size. Not doing this 2761 * causes weird stuff to happen (for the 5210 at least). 2762 */ 2763 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2764 if (m == NULL) { 2765 DPRINTF(sc, ATH_DEBUG_ANY, 2766 "%s: no mbuf/cluster\n", __func__); 2767 sc->sc_stats.ast_rx_nombuf++; 2768 return ENOMEM; 2769 } 2770 bf->bf_m = m; 2771 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2772 2773 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2774 bf->bf_dmamap, m, 2775 BUS_DMA_NOWAIT); 2776 if (error != 0) { 2777 DPRINTF(sc, ATH_DEBUG_ANY, 2778 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2779 __func__, error); 2780 sc->sc_stats.ast_rx_busdma++; 2781 return error; 2782 } 2783 KASSERT(bf->bf_nseg == 1, 2784 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2785 } 2786 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2787 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2788 2789 /* 2790 * Setup descriptors. For receive we always terminate 2791 * the descriptor list with a self-linked entry so we'll 2792 * not get overrun under high load (as can happen with a 2793 * 5212 when ANI processing enables PHY error frames). 2794 * 2795 * To insure the last descriptor is self-linked we create 2796 * each descriptor as self-linked and add it to the end. As 2797 * each additional descriptor is added the previous self-linked 2798 * entry is ``fixed'' naturally. This should be safe even 2799 * if DMA is happening. When processing RX interrupts we 2800 * never remove/process the last, self-linked, entry on the 2801 * descriptor list. This insures the hardware always has 2802 * someplace to write a new frame. 2803 */ 2804 ds = bf->bf_desc; 2805 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2806 ds->ds_data = bf->bf_segs[0].ds_addr; 2807 /* ds->ds_vdata = mtod(m, void *); for radar */ 2808 ath_hal_setuprxdesc(ah, ds 2809 , m->m_len /* buffer size */ 2810 , 0 2811 ); 2812 2813 if (sc->sc_rxlink != NULL) 2814 *sc->sc_rxlink = bf->bf_daddr; 2815 sc->sc_rxlink = &ds->ds_link; 2816 return 0; 2817 } 2818 2819 /* 2820 * Extend 15-bit time stamp from rx descriptor to 2821 * a full 64-bit TSF using the specified TSF. 2822 */ 2823 static inline u_int64_t 2824 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2825 { 2826 if ((tsf & 0x7fff) < rstamp) 2827 tsf -= 0x8000; 2828 return ((tsf &~ 0x7fff) | rstamp); 2829 } 2830 2831 /* 2832 * Intercept management frames to collect beacon rssi data 2833 * and to do ibss merges. 2834 */ 2835 static void 2836 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2837 struct ieee80211_node *ni, 2838 int subtype, int rssi, u_int32_t rstamp) 2839 { 2840 struct ath_softc *sc = ic->ic_ifp->if_softc; 2841 2842 /* 2843 * Call up first so subsequent work can use information 2844 * potentially stored in the node (e.g. for ibss merge). 2845 */ 2846 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2847 switch (subtype) { 2848 case IEEE80211_FC0_SUBTYPE_BEACON: 2849 /* update rssi statistics for use by the hal */ 2850 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2851 if (sc->sc_syncbeacon && 2852 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2853 /* 2854 * Resync beacon timers using the tsf of the beacon 2855 * frame we just received. 2856 */ 2857 ath_beacon_config(sc); 2858 } 2859 /* fall thru... */ 2860 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2861 if (ic->ic_opmode == IEEE80211_M_IBSS && 2862 ic->ic_state == IEEE80211_S_RUN) { 2863 u_int64_t tsf = ath_extend_tsf(rstamp, 2864 ath_hal_gettsf64(sc->sc_ah)); 2865 2866 /* 2867 * Handle ibss merge as needed; check the tsf on the 2868 * frame before attempting the merge. The 802.11 spec 2869 * says the station should change it's bssid to match 2870 * the oldest station with the same ssid, where oldest 2871 * is determined by the tsf. Note that hardware 2872 * reconfiguration happens through callback to 2873 * ath_newstate as the state machine will go from 2874 * RUN -> RUN when this happens. 2875 */ 2876 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2877 DPRINTF(sc, ATH_DEBUG_STATE, 2878 "ibss merge, rstamp %u tsf %ju " 2879 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2880 (uintmax_t)ni->ni_tstamp.tsf); 2881 (void) ieee80211_ibss_merge(ni); 2882 } 2883 } 2884 break; 2885 } 2886 } 2887 2888 /* 2889 * Set the default antenna. 2890 */ 2891 static void 2892 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2893 { 2894 struct ath_hal *ah = sc->sc_ah; 2895 2896 /* XXX block beacon interrupts */ 2897 ath_hal_setdefantenna(ah, antenna); 2898 if (sc->sc_defant != antenna) 2899 sc->sc_stats.ast_ant_defswitch++; 2900 sc->sc_defant = antenna; 2901 sc->sc_rxotherant = 0; 2902 } 2903 2904 static void 2905 ath_handle_micerror(struct ieee80211com *ic, 2906 struct ieee80211_frame *wh, int keyix) 2907 { 2908 struct ieee80211_node *ni; 2909 2910 /* XXX recheck MIC to deal w/ chips that lie */ 2911 /* XXX discard MIC errors on !data frames */ 2912 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 2913 if (ni != NULL) { 2914 ieee80211_notify_michael_failure(ic, wh, keyix); 2915 ieee80211_free_node(ni); 2916 } 2917 } 2918 2919 static void 2920 ath_rx_proc(void *arg, int npending) 2921 { 2922 #define PA2DESC(_sc, _pa) \ 2923 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2924 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2925 struct ath_softc *sc = arg; 2926 struct ath_buf *bf; 2927 struct ieee80211com *ic = &sc->sc_ic; 2928 struct ifnet *ifp = &sc->sc_if; 2929 struct ath_hal *ah = sc->sc_ah; 2930 struct ath_desc *ds; 2931 struct mbuf *m; 2932 struct ieee80211_node *ni; 2933 struct ath_node *an; 2934 int len, ngood, type; 2935 u_int phyerr; 2936 HAL_STATUS status; 2937 int16_t nf; 2938 u_int64_t tsf; 2939 uint8_t rxerr_tap, rxerr_mon; 2940 2941 NET_LOCK_GIANT(); /* XXX */ 2942 2943 rxerr_tap = 2944 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 2945 2946 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 2947 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 2948 else if (ifp->if_flags & IFF_PROMISC) 2949 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 2950 2951 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2952 ngood = 0; 2953 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2954 tsf = ath_hal_gettsf64(ah); 2955 do { 2956 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2957 if (bf == NULL) { /* NB: shouldn't happen */ 2958 if_printf(ifp, "%s: no buffer!\n", __func__); 2959 break; 2960 } 2961 ds = bf->bf_desc; 2962 if (ds->ds_link == bf->bf_daddr) { 2963 /* NB: never process the self-linked entry at the end */ 2964 break; 2965 } 2966 m = bf->bf_m; 2967 if (m == NULL) { /* NB: shouldn't happen */ 2968 if_printf(ifp, "%s: no mbuf!\n", __func__); 2969 break; 2970 } 2971 /* XXX sync descriptor memory */ 2972 /* 2973 * Must provide the virtual address of the current 2974 * descriptor, the physical address, and the virtual 2975 * address of the next descriptor in the h/w chain. 2976 * This allows the HAL to look ahead to see if the 2977 * hardware is done with a descriptor by checking the 2978 * done bit in the following descriptor and the address 2979 * of the current descriptor the DMA engine is working 2980 * on. All this is necessary because of our use of 2981 * a self-linked list to avoid rx overruns. 2982 */ 2983 status = ath_hal_rxprocdesc(ah, ds, 2984 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 2985 tsf, &ds->ds_rxstat); 2986 #ifdef AR_DEBUG 2987 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2988 ath_printrxbuf(bf, status == HAL_OK); 2989 #endif 2990 if (status == HAL_EINPROGRESS) 2991 break; 2992 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2993 if (ds->ds_rxstat.rs_more) { 2994 /* 2995 * Frame spans multiple descriptors; this 2996 * cannot happen yet as we don't support 2997 * jumbograms. If not in monitor mode, 2998 * discard the frame. 2999 */ 3000 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3001 sc->sc_stats.ast_rx_toobig++; 3002 goto rx_next; 3003 } 3004 /* fall thru for monitor mode handling... */ 3005 } else if (ds->ds_rxstat.rs_status != 0) { 3006 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3007 sc->sc_stats.ast_rx_crcerr++; 3008 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3009 sc->sc_stats.ast_rx_fifoerr++; 3010 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3011 sc->sc_stats.ast_rx_phyerr++; 3012 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3013 sc->sc_stats.ast_rx_phy[phyerr]++; 3014 goto rx_next; 3015 } 3016 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3017 /* 3018 * Decrypt error. If the error occurred 3019 * because there was no hardware key, then 3020 * let the frame through so the upper layers 3021 * can process it. This is necessary for 5210 3022 * parts which have no way to setup a ``clear'' 3023 * key cache entry. 3024 * 3025 * XXX do key cache faulting 3026 */ 3027 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3028 goto rx_accept; 3029 sc->sc_stats.ast_rx_badcrypt++; 3030 } 3031 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3032 sc->sc_stats.ast_rx_badmic++; 3033 /* 3034 * Do minimal work required to hand off 3035 * the 802.11 header for notifcation. 3036 */ 3037 /* XXX frag's and qos frames */ 3038 len = ds->ds_rxstat.rs_datalen; 3039 if (len >= sizeof (struct ieee80211_frame)) { 3040 bus_dmamap_sync(sc->sc_dmat, 3041 bf->bf_dmamap, 3042 0, bf->bf_dmamap->dm_mapsize, 3043 BUS_DMASYNC_POSTREAD); 3044 ath_handle_micerror(ic, 3045 mtod(m, struct ieee80211_frame *), 3046 sc->sc_splitmic ? 3047 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3048 } 3049 } 3050 ifp->if_ierrors++; 3051 /* 3052 * Reject error frames, we normally don't want 3053 * to see them in monitor mode (in monitor mode 3054 * allow through packets that have crypto problems). 3055 */ 3056 3057 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3058 goto rx_next; 3059 } 3060 rx_accept: 3061 /* 3062 * Sync and unmap the frame. At this point we're 3063 * committed to passing the mbuf somewhere so clear 3064 * bf_m; this means a new sk_buff must be allocated 3065 * when the rx descriptor is setup again to receive 3066 * another frame. 3067 */ 3068 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3069 0, bf->bf_dmamap->dm_mapsize, 3070 BUS_DMASYNC_POSTREAD); 3071 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3072 bf->bf_m = NULL; 3073 3074 m->m_pkthdr.rcvif = ifp; 3075 len = ds->ds_rxstat.rs_datalen; 3076 m->m_pkthdr.len = m->m_len = len; 3077 3078 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3079 3080 #if NBPFILTER > 0 3081 if (sc->sc_drvbpf) { 3082 u_int8_t rix; 3083 3084 /* 3085 * Discard anything shorter than an ack or cts. 3086 */ 3087 if (len < IEEE80211_ACK_LEN) { 3088 DPRINTF(sc, ATH_DEBUG_RECV, 3089 "%s: runt packet %d\n", 3090 __func__, len); 3091 sc->sc_stats.ast_rx_tooshort++; 3092 m_freem(m); 3093 goto rx_next; 3094 } 3095 rix = ds->ds_rxstat.rs_rate; 3096 sc->sc_rx_th.wr_tsf = htole64( 3097 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3098 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3099 if (ds->ds_rxstat.rs_status & 3100 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3101 sc->sc_rx_th.wr_flags |= 3102 IEEE80211_RADIOTAP_F_BADFCS; 3103 } 3104 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3105 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3106 sc->sc_rx_th.wr_antnoise = nf; 3107 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3108 3109 bpf_mtap2(sc->sc_drvbpf, 3110 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3111 } 3112 #endif 3113 3114 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3115 m_freem(m); 3116 goto rx_next; 3117 } 3118 /* 3119 * From this point on we assume the frame is at least 3120 * as large as ieee80211_frame_min; verify that. 3121 */ 3122 if (len < IEEE80211_MIN_LEN) { 3123 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3124 __func__, len); 3125 sc->sc_stats.ast_rx_tooshort++; 3126 m_freem(m); 3127 goto rx_next; 3128 } 3129 3130 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3131 ieee80211_dump_pkt(mtod(m, void *), len, 3132 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3133 ds->ds_rxstat.rs_rssi); 3134 } 3135 3136 m_adj(m, -IEEE80211_CRC_LEN); 3137 3138 /* 3139 * Locate the node for sender, track state, and then 3140 * pass the (referenced) node up to the 802.11 layer 3141 * for its use. 3142 */ 3143 ni = ieee80211_find_rxnode_withkey(ic, 3144 mtod(m, const struct ieee80211_frame_min *), 3145 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3146 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3147 /* 3148 * Track rx rssi and do any rx antenna management. 3149 */ 3150 an = ATH_NODE(ni); 3151 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3152 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3153 /* 3154 * Send frame up for processing. 3155 */ 3156 type = ieee80211_input(ic, m, ni, 3157 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3158 ieee80211_free_node(ni); 3159 if (sc->sc_diversity) { 3160 /* 3161 * When using fast diversity, change the default rx 3162 * antenna if diversity chooses the other antenna 3 3163 * times in a row. 3164 */ 3165 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3166 if (++sc->sc_rxotherant >= 3) 3167 ath_setdefantenna(sc, 3168 ds->ds_rxstat.rs_antenna); 3169 } else 3170 sc->sc_rxotherant = 0; 3171 } 3172 if (sc->sc_softled) { 3173 /* 3174 * Blink for any data frame. Otherwise do a 3175 * heartbeat-style blink when idle. The latter 3176 * is mainly for station mode where we depend on 3177 * periodic beacon frames to trigger the poll event. 3178 */ 3179 if (type == IEEE80211_FC0_TYPE_DATA) { 3180 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3181 ath_led_event(sc, ATH_LED_RX); 3182 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3183 ath_led_event(sc, ATH_LED_POLL); 3184 } 3185 /* 3186 * Arrange to update the last rx timestamp only for 3187 * frames from our ap when operating in station mode. 3188 * This assumes the rx key is always setup when associated. 3189 */ 3190 if (ic->ic_opmode == IEEE80211_M_STA && 3191 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3192 ngood++; 3193 rx_next: 3194 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3195 } while (ath_rxbuf_init(sc, bf) == 0); 3196 3197 /* rx signal state monitoring */ 3198 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3199 #if 0 3200 if (ath_hal_radar_event(ah)) 3201 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3202 #endif 3203 if (ngood) 3204 sc->sc_lastrx = tsf; 3205 3206 #ifdef __NetBSD__ 3207 /* XXX Why isn't this necessary in FreeBSD? */ 3208 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3209 ath_start(ifp); 3210 #endif /* __NetBSD__ */ 3211 3212 NET_UNLOCK_GIANT(); /* XXX */ 3213 #undef PA2DESC 3214 } 3215 3216 /* 3217 * Setup a h/w transmit queue. 3218 */ 3219 static struct ath_txq * 3220 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3221 { 3222 #define N(a) (sizeof(a)/sizeof(a[0])) 3223 struct ath_hal *ah = sc->sc_ah; 3224 HAL_TXQ_INFO qi; 3225 int qnum; 3226 3227 memset(&qi, 0, sizeof(qi)); 3228 qi.tqi_subtype = subtype; 3229 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3230 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3231 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3232 /* 3233 * Enable interrupts only for EOL and DESC conditions. 3234 * We mark tx descriptors to receive a DESC interrupt 3235 * when a tx queue gets deep; otherwise waiting for the 3236 * EOL to reap descriptors. Note that this is done to 3237 * reduce interrupt load and this only defers reaping 3238 * descriptors, never transmitting frames. Aside from 3239 * reducing interrupts this also permits more concurrency. 3240 * The only potential downside is if the tx queue backs 3241 * up in which case the top half of the kernel may backup 3242 * due to a lack of tx descriptors. 3243 */ 3244 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3245 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3246 if (qnum == -1) { 3247 /* 3248 * NB: don't print a message, this happens 3249 * normally on parts with too few tx queues 3250 */ 3251 return NULL; 3252 } 3253 if (qnum >= N(sc->sc_txq)) { 3254 device_printf(sc->sc_dev, 3255 "hal qnum %u out of range, max %zu!\n", 3256 qnum, N(sc->sc_txq)); 3257 ath_hal_releasetxqueue(ah, qnum); 3258 return NULL; 3259 } 3260 if (!ATH_TXQ_SETUP(sc, qnum)) { 3261 struct ath_txq *txq = &sc->sc_txq[qnum]; 3262 3263 txq->axq_qnum = qnum; 3264 txq->axq_depth = 0; 3265 txq->axq_intrcnt = 0; 3266 txq->axq_link = NULL; 3267 STAILQ_INIT(&txq->axq_q); 3268 ATH_TXQ_LOCK_INIT(sc, txq); 3269 sc->sc_txqsetup |= 1<<qnum; 3270 } 3271 return &sc->sc_txq[qnum]; 3272 #undef N 3273 } 3274 3275 /* 3276 * Setup a hardware data transmit queue for the specified 3277 * access control. The hal may not support all requested 3278 * queues in which case it will return a reference to a 3279 * previously setup queue. We record the mapping from ac's 3280 * to h/w queues for use by ath_tx_start and also track 3281 * the set of h/w queues being used to optimize work in the 3282 * transmit interrupt handler and related routines. 3283 */ 3284 static int 3285 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3286 { 3287 #define N(a) (sizeof(a)/sizeof(a[0])) 3288 struct ath_txq *txq; 3289 3290 if (ac >= N(sc->sc_ac2q)) { 3291 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3292 ac, N(sc->sc_ac2q)); 3293 return 0; 3294 } 3295 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3296 if (txq != NULL) { 3297 sc->sc_ac2q[ac] = txq; 3298 return 1; 3299 } else 3300 return 0; 3301 #undef N 3302 } 3303 3304 /* 3305 * Update WME parameters for a transmit queue. 3306 */ 3307 static int 3308 ath_txq_update(struct ath_softc *sc, int ac) 3309 { 3310 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3311 #define ATH_TXOP_TO_US(v) (v<<5) 3312 struct ieee80211com *ic = &sc->sc_ic; 3313 struct ath_txq *txq = sc->sc_ac2q[ac]; 3314 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3315 struct ath_hal *ah = sc->sc_ah; 3316 HAL_TXQ_INFO qi; 3317 3318 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3319 qi.tqi_aifs = wmep->wmep_aifsn; 3320 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3321 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3322 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3323 3324 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3325 device_printf(sc->sc_dev, "unable to update hardware queue " 3326 "parameters for %s traffic!\n", 3327 ieee80211_wme_acnames[ac]); 3328 return 0; 3329 } else { 3330 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3331 return 1; 3332 } 3333 #undef ATH_TXOP_TO_US 3334 #undef ATH_EXPONENT_TO_VALUE 3335 } 3336 3337 /* 3338 * Callback from the 802.11 layer to update WME parameters. 3339 */ 3340 static int 3341 ath_wme_update(struct ieee80211com *ic) 3342 { 3343 struct ath_softc *sc = ic->ic_ifp->if_softc; 3344 3345 return !ath_txq_update(sc, WME_AC_BE) || 3346 !ath_txq_update(sc, WME_AC_BK) || 3347 !ath_txq_update(sc, WME_AC_VI) || 3348 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3349 } 3350 3351 /* 3352 * Reclaim resources for a setup queue. 3353 */ 3354 static void 3355 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3356 { 3357 3358 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3359 ATH_TXQ_LOCK_DESTROY(txq); 3360 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3361 } 3362 3363 /* 3364 * Reclaim all tx queue resources. 3365 */ 3366 static void 3367 ath_tx_cleanup(struct ath_softc *sc) 3368 { 3369 int i; 3370 3371 ATH_TXBUF_LOCK_DESTROY(sc); 3372 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3373 if (ATH_TXQ_SETUP(sc, i)) 3374 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3375 } 3376 3377 /* 3378 * Defragment an mbuf chain, returning at most maxfrags separate 3379 * mbufs+clusters. If this is not possible NULL is returned and 3380 * the original mbuf chain is left in it's present (potentially 3381 * modified) state. We use two techniques: collapsing consecutive 3382 * mbufs and replacing consecutive mbufs by a cluster. 3383 */ 3384 static struct mbuf * 3385 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3386 { 3387 struct mbuf *m, *n, *n2, **prev; 3388 u_int curfrags; 3389 3390 /* 3391 * Calculate the current number of frags. 3392 */ 3393 curfrags = 0; 3394 for (m = m0; m != NULL; m = m->m_next) 3395 curfrags++; 3396 /* 3397 * First, try to collapse mbufs. Note that we always collapse 3398 * towards the front so we don't need to deal with moving the 3399 * pkthdr. This may be suboptimal if the first mbuf has much 3400 * less data than the following. 3401 */ 3402 m = m0; 3403 again: 3404 for (;;) { 3405 n = m->m_next; 3406 if (n == NULL) 3407 break; 3408 if (n->m_len < M_TRAILINGSPACE(m)) { 3409 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3410 n->m_len); 3411 m->m_len += n->m_len; 3412 m->m_next = n->m_next; 3413 m_free(n); 3414 if (--curfrags <= maxfrags) 3415 return m0; 3416 } else 3417 m = n; 3418 } 3419 KASSERT(maxfrags > 1, 3420 ("maxfrags %u, but normal collapse failed", maxfrags)); 3421 /* 3422 * Collapse consecutive mbufs to a cluster. 3423 */ 3424 prev = &m0->m_next; /* NB: not the first mbuf */ 3425 while ((n = *prev) != NULL) { 3426 if ((n2 = n->m_next) != NULL && 3427 n->m_len + n2->m_len < MCLBYTES) { 3428 m = m_getcl(how, MT_DATA, 0); 3429 if (m == NULL) 3430 goto bad; 3431 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3432 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3433 n2->m_len); 3434 m->m_len = n->m_len + n2->m_len; 3435 m->m_next = n2->m_next; 3436 *prev = m; 3437 m_free(n); 3438 m_free(n2); 3439 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3440 return m0; 3441 /* 3442 * Still not there, try the normal collapse 3443 * again before we allocate another cluster. 3444 */ 3445 goto again; 3446 } 3447 prev = &n->m_next; 3448 } 3449 /* 3450 * No place where we can collapse to a cluster; punt. 3451 * This can occur if, for example, you request 2 frags 3452 * but the packet requires that both be clusters (we 3453 * never reallocate the first mbuf to avoid moving the 3454 * packet header). 3455 */ 3456 bad: 3457 return NULL; 3458 } 3459 3460 /* 3461 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3462 */ 3463 static int 3464 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3465 { 3466 int i; 3467 3468 for (i = 0; i < rt->rateCount; i++) 3469 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3470 return i; 3471 return 0; /* NB: lowest rate */ 3472 } 3473 3474 static void 3475 ath_freetx(struct mbuf *m) 3476 { 3477 struct mbuf *next; 3478 3479 do { 3480 next = m->m_nextpkt; 3481 m->m_nextpkt = NULL; 3482 m_freem(m); 3483 } while ((m = next) != NULL); 3484 } 3485 3486 static int 3487 deduct_pad_bytes(int len, int hdrlen) 3488 { 3489 /* XXX I am suspicious that this code, which I extracted 3490 * XXX from ath_tx_start() for reuse, does the right thing. 3491 */ 3492 return len - (hdrlen & 3); 3493 } 3494 3495 static int 3496 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3497 struct mbuf *m0) 3498 { 3499 struct ieee80211com *ic = &sc->sc_ic; 3500 struct ath_hal *ah = sc->sc_ah; 3501 struct ifnet *ifp = &sc->sc_if; 3502 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3503 int i, error, iswep, ismcast, isfrag, ismrr; 3504 int keyix, hdrlen, pktlen, try0; 3505 u_int8_t rix, txrate, ctsrate; 3506 u_int8_t cix = 0xff; /* NB: silence compiler */ 3507 struct ath_desc *ds, *ds0; 3508 struct ath_txq *txq; 3509 struct ieee80211_frame *wh; 3510 u_int subtype, flags, ctsduration; 3511 HAL_PKT_TYPE atype; 3512 const HAL_RATE_TABLE *rt; 3513 HAL_BOOL shortPreamble; 3514 struct ath_node *an; 3515 struct mbuf *m; 3516 u_int pri; 3517 3518 wh = mtod(m0, struct ieee80211_frame *); 3519 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3520 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3521 isfrag = m0->m_flags & M_FRAG; 3522 hdrlen = ieee80211_anyhdrsize(wh); 3523 /* 3524 * Packet length must not include any 3525 * pad bytes; deduct them here. 3526 */ 3527 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3528 3529 if (iswep) { 3530 const struct ieee80211_cipher *cip; 3531 struct ieee80211_key *k; 3532 3533 /* 3534 * Construct the 802.11 header+trailer for an encrypted 3535 * frame. The only reason this can fail is because of an 3536 * unknown or unsupported cipher/key type. 3537 */ 3538 k = ieee80211_crypto_encap(ic, ni, m0); 3539 if (k == NULL) { 3540 /* 3541 * This can happen when the key is yanked after the 3542 * frame was queued. Just discard the frame; the 3543 * 802.11 layer counts failures and provides 3544 * debugging/diagnostics. 3545 */ 3546 ath_freetx(m0); 3547 return EIO; 3548 } 3549 /* 3550 * Adjust the packet + header lengths for the crypto 3551 * additions and calculate the h/w key index. When 3552 * a s/w mic is done the frame will have had any mic 3553 * added to it prior to entry so m0->m_pkthdr.len above will 3554 * account for it. Otherwise we need to add it to the 3555 * packet length. 3556 */ 3557 cip = k->wk_cipher; 3558 hdrlen += cip->ic_header; 3559 pktlen += cip->ic_header + cip->ic_trailer; 3560 /* NB: frags always have any TKIP MIC done in s/w */ 3561 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3562 pktlen += cip->ic_miclen; 3563 keyix = k->wk_keyix; 3564 3565 /* packet header may have moved, reset our local pointer */ 3566 wh = mtod(m0, struct ieee80211_frame *); 3567 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3568 /* 3569 * Use station key cache slot, if assigned. 3570 */ 3571 keyix = ni->ni_ucastkey.wk_keyix; 3572 if (keyix == IEEE80211_KEYIX_NONE) 3573 keyix = HAL_TXKEYIX_INVALID; 3574 } else 3575 keyix = HAL_TXKEYIX_INVALID; 3576 3577 pktlen += IEEE80211_CRC_LEN; 3578 3579 /* 3580 * Load the DMA map so any coalescing is done. This 3581 * also calculates the number of descriptors we need. 3582 */ 3583 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3584 BUS_DMA_NOWAIT); 3585 if (error == EFBIG) { 3586 /* XXX packet requires too many descriptors */ 3587 bf->bf_nseg = ATH_TXDESC+1; 3588 } else if (error != 0) { 3589 sc->sc_stats.ast_tx_busdma++; 3590 ath_freetx(m0); 3591 return error; 3592 } 3593 /* 3594 * Discard null packets and check for packets that 3595 * require too many TX descriptors. We try to convert 3596 * the latter to a cluster. 3597 */ 3598 if (error == EFBIG) { /* too many desc's, linearize */ 3599 sc->sc_stats.ast_tx_linear++; 3600 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3601 if (m == NULL) { 3602 ath_freetx(m0); 3603 sc->sc_stats.ast_tx_nombuf++; 3604 return ENOMEM; 3605 } 3606 m0 = m; 3607 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3608 BUS_DMA_NOWAIT); 3609 if (error != 0) { 3610 sc->sc_stats.ast_tx_busdma++; 3611 ath_freetx(m0); 3612 return error; 3613 } 3614 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3615 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3616 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3617 sc->sc_stats.ast_tx_nodata++; 3618 ath_freetx(m0); 3619 return EIO; 3620 } 3621 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3622 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3623 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3624 bf->bf_m = m0; 3625 bf->bf_node = ni; /* NB: held reference */ 3626 3627 /* setup descriptors */ 3628 ds = bf->bf_desc; 3629 rt = sc->sc_currates; 3630 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3631 3632 /* 3633 * NB: the 802.11 layer marks whether or not we should 3634 * use short preamble based on the current mode and 3635 * negotiated parameters. 3636 */ 3637 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3638 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3639 shortPreamble = AH_TRUE; 3640 sc->sc_stats.ast_tx_shortpre++; 3641 } else { 3642 shortPreamble = AH_FALSE; 3643 } 3644 3645 an = ATH_NODE(ni); 3646 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3647 ismrr = 0; /* default no multi-rate retry*/ 3648 /* 3649 * Calculate Atheros packet type from IEEE80211 packet header, 3650 * setup for rate calculations, and select h/w transmit queue. 3651 */ 3652 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3653 case IEEE80211_FC0_TYPE_MGT: 3654 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3655 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3656 atype = HAL_PKT_TYPE_BEACON; 3657 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3658 atype = HAL_PKT_TYPE_PROBE_RESP; 3659 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3660 atype = HAL_PKT_TYPE_ATIM; 3661 else 3662 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3663 rix = sc->sc_minrateix; 3664 txrate = rt->info[rix].rateCode; 3665 if (shortPreamble) 3666 txrate |= rt->info[rix].shortPreamble; 3667 try0 = ATH_TXMGTTRY; 3668 /* NB: force all management frames to highest queue */ 3669 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3670 /* NB: force all management frames to highest queue */ 3671 pri = WME_AC_VO; 3672 } else 3673 pri = WME_AC_BE; 3674 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3675 break; 3676 case IEEE80211_FC0_TYPE_CTL: 3677 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3678 rix = sc->sc_minrateix; 3679 txrate = rt->info[rix].rateCode; 3680 if (shortPreamble) 3681 txrate |= rt->info[rix].shortPreamble; 3682 try0 = ATH_TXMGTTRY; 3683 /* NB: force all ctl frames to highest queue */ 3684 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3685 /* NB: force all ctl frames to highest queue */ 3686 pri = WME_AC_VO; 3687 } else 3688 pri = WME_AC_BE; 3689 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3690 break; 3691 case IEEE80211_FC0_TYPE_DATA: 3692 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3693 /* 3694 * Data frames: multicast frames go out at a fixed rate, 3695 * otherwise consult the rate control module for the 3696 * rate to use. 3697 */ 3698 if (ismcast) { 3699 /* 3700 * Check mcast rate setting in case it's changed. 3701 * XXX move out of fastpath 3702 */ 3703 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3704 sc->sc_mcastrix = 3705 ath_tx_findrix(rt, ic->ic_mcast_rate); 3706 sc->sc_mcastrate = ic->ic_mcast_rate; 3707 } 3708 rix = sc->sc_mcastrix; 3709 txrate = rt->info[rix].rateCode; 3710 try0 = 1; 3711 } else { 3712 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3713 &rix, &try0, &txrate); 3714 sc->sc_txrate = txrate; /* for LED blinking */ 3715 if (try0 != ATH_TXMAXTRY) 3716 ismrr = 1; 3717 } 3718 pri = M_WME_GETAC(m0); 3719 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3720 flags |= HAL_TXDESC_NOACK; 3721 break; 3722 default: 3723 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3724 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3725 /* XXX statistic */ 3726 ath_freetx(m0); 3727 return EIO; 3728 } 3729 txq = sc->sc_ac2q[pri]; 3730 3731 /* 3732 * When servicing one or more stations in power-save mode 3733 * multicast frames must be buffered until after the beacon. 3734 * We use the CAB queue for that. 3735 */ 3736 if (ismcast && ic->ic_ps_sta) { 3737 txq = sc->sc_cabq; 3738 /* XXX? more bit in 802.11 frame header */ 3739 } 3740 3741 /* 3742 * Calculate miscellaneous flags. 3743 */ 3744 if (ismcast) { 3745 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3746 } else if (pktlen > ic->ic_rtsthreshold) { 3747 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3748 cix = rt->info[rix].controlRate; 3749 sc->sc_stats.ast_tx_rts++; 3750 } 3751 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3752 sc->sc_stats.ast_tx_noack++; 3753 3754 /* 3755 * If 802.11g protection is enabled, determine whether 3756 * to use RTS/CTS or just CTS. Note that this is only 3757 * done for OFDM unicast frames. 3758 */ 3759 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3760 rt->info[rix].phy == IEEE80211_T_OFDM && 3761 (flags & HAL_TXDESC_NOACK) == 0) { 3762 /* XXX fragments must use CCK rates w/ protection */ 3763 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3764 flags |= HAL_TXDESC_RTSENA; 3765 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3766 flags |= HAL_TXDESC_CTSENA; 3767 if (isfrag) { 3768 /* 3769 * For frags it would be desirable to use the 3770 * highest CCK rate for RTS/CTS. But stations 3771 * farther away may detect it at a lower CCK rate 3772 * so use the configured protection rate instead 3773 * (for now). 3774 */ 3775 cix = rt->info[sc->sc_protrix].controlRate; 3776 } else 3777 cix = rt->info[sc->sc_protrix].controlRate; 3778 sc->sc_stats.ast_tx_protect++; 3779 } 3780 3781 /* 3782 * Calculate duration. This logically belongs in the 802.11 3783 * layer but it lacks sufficient information to calculate it. 3784 */ 3785 if ((flags & HAL_TXDESC_NOACK) == 0 && 3786 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3787 u_int16_t dur; 3788 /* 3789 * XXX not right with fragmentation. 3790 */ 3791 if (shortPreamble) 3792 dur = rt->info[rix].spAckDuration; 3793 else 3794 dur = rt->info[rix].lpAckDuration; 3795 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3796 dur += dur; /* additional SIFS+ACK */ 3797 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3798 /* 3799 * Include the size of next fragment so NAV is 3800 * updated properly. The last fragment uses only 3801 * the ACK duration 3802 */ 3803 dur += ath_hal_computetxtime(ah, rt, 3804 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3805 hdrlen) - 3806 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3807 rix, shortPreamble); 3808 } 3809 if (isfrag) { 3810 /* 3811 * Force hardware to use computed duration for next 3812 * fragment by disabling multi-rate retry which updates 3813 * duration based on the multi-rate duration table. 3814 */ 3815 try0 = ATH_TXMAXTRY; 3816 } 3817 *(u_int16_t *)wh->i_dur = htole16(dur); 3818 } 3819 3820 /* 3821 * Calculate RTS/CTS rate and duration if needed. 3822 */ 3823 ctsduration = 0; 3824 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3825 /* 3826 * CTS transmit rate is derived from the transmit rate 3827 * by looking in the h/w rate table. We must also factor 3828 * in whether or not a short preamble is to be used. 3829 */ 3830 /* NB: cix is set above where RTS/CTS is enabled */ 3831 KASSERT(cix != 0xff, ("cix not setup")); 3832 ctsrate = rt->info[cix].rateCode; 3833 /* 3834 * Compute the transmit duration based on the frame 3835 * size and the size of an ACK frame. We call into the 3836 * HAL to do the computation since it depends on the 3837 * characteristics of the actual PHY being used. 3838 * 3839 * NB: CTS is assumed the same size as an ACK so we can 3840 * use the precalculated ACK durations. 3841 */ 3842 if (shortPreamble) { 3843 ctsrate |= rt->info[cix].shortPreamble; 3844 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3845 ctsduration += rt->info[cix].spAckDuration; 3846 ctsduration += ath_hal_computetxtime(ah, 3847 rt, pktlen, rix, AH_TRUE); 3848 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3849 ctsduration += rt->info[rix].spAckDuration; 3850 } else { 3851 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3852 ctsduration += rt->info[cix].lpAckDuration; 3853 ctsduration += ath_hal_computetxtime(ah, 3854 rt, pktlen, rix, AH_FALSE); 3855 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3856 ctsduration += rt->info[rix].lpAckDuration; 3857 } 3858 /* 3859 * Must disable multi-rate retry when using RTS/CTS. 3860 */ 3861 ismrr = 0; 3862 try0 = ATH_TXMGTTRY; /* XXX */ 3863 } else 3864 ctsrate = 0; 3865 3866 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3867 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3868 sc->sc_hwmap[txrate].ieeerate, -1); 3869 #if NBPFILTER > 0 3870 if (ic->ic_rawbpf) 3871 bpf_mtap(ic->ic_rawbpf, m0); 3872 if (sc->sc_drvbpf) { 3873 u_int64_t tsf = ath_hal_gettsf64(ah); 3874 3875 sc->sc_tx_th.wt_tsf = htole64(tsf); 3876 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3877 if (iswep) 3878 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3879 if (isfrag) 3880 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3881 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3882 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3883 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3884 3885 bpf_mtap2(sc->sc_drvbpf, 3886 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3887 } 3888 #endif 3889 3890 /* 3891 * Determine if a tx interrupt should be generated for 3892 * this descriptor. We take a tx interrupt to reap 3893 * descriptors when the h/w hits an EOL condition or 3894 * when the descriptor is specifically marked to generate 3895 * an interrupt. We periodically mark descriptors in this 3896 * way to insure timely replenishing of the supply needed 3897 * for sending frames. Defering interrupts reduces system 3898 * load and potentially allows more concurrent work to be 3899 * done but if done to aggressively can cause senders to 3900 * backup. 3901 * 3902 * NB: use >= to deal with sc_txintrperiod changing 3903 * dynamically through sysctl. 3904 */ 3905 if (flags & HAL_TXDESC_INTREQ) { 3906 txq->axq_intrcnt = 0; 3907 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3908 flags |= HAL_TXDESC_INTREQ; 3909 txq->axq_intrcnt = 0; 3910 } 3911 3912 /* 3913 * Formulate first tx descriptor with tx controls. 3914 */ 3915 /* XXX check return value? */ 3916 ath_hal_setuptxdesc(ah, ds 3917 , pktlen /* packet length */ 3918 , hdrlen /* header length */ 3919 , atype /* Atheros packet type */ 3920 , ni->ni_txpower /* txpower */ 3921 , txrate, try0 /* series 0 rate/tries */ 3922 , keyix /* key cache index */ 3923 , sc->sc_txantenna /* antenna mode */ 3924 , flags /* flags */ 3925 , ctsrate /* rts/cts rate */ 3926 , ctsduration /* rts/cts duration */ 3927 ); 3928 bf->bf_flags = flags; 3929 /* 3930 * Setup the multi-rate retry state only when we're 3931 * going to use it. This assumes ath_hal_setuptxdesc 3932 * initializes the descriptors (so we don't have to) 3933 * when the hardware supports multi-rate retry and 3934 * we don't use it. 3935 */ 3936 if (ismrr) 3937 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3938 3939 /* 3940 * Fillin the remainder of the descriptor info. 3941 */ 3942 ds0 = ds; 3943 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3944 ds->ds_data = bf->bf_segs[i].ds_addr; 3945 if (i == bf->bf_nseg - 1) 3946 ds->ds_link = 0; 3947 else 3948 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3949 ath_hal_filltxdesc(ah, ds 3950 , bf->bf_segs[i].ds_len /* segment length */ 3951 , i == 0 /* first segment */ 3952 , i == bf->bf_nseg - 1 /* last segment */ 3953 , ds0 /* first descriptor */ 3954 ); 3955 3956 /* NB: The desc swap function becomes void, 3957 * if descriptor swapping is not enabled 3958 */ 3959 ath_desc_swap(ds); 3960 3961 DPRINTF(sc, ATH_DEBUG_XMIT, 3962 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3963 __func__, i, ds->ds_link, ds->ds_data, 3964 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3965 } 3966 /* 3967 * Insert the frame on the outbound list and 3968 * pass it on to the hardware. 3969 */ 3970 ATH_TXQ_LOCK(txq); 3971 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3972 if (txq->axq_link == NULL) { 3973 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3974 DPRINTF(sc, ATH_DEBUG_XMIT, 3975 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3976 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3977 txq->axq_depth); 3978 } else { 3979 *txq->axq_link = HTOAH32(bf->bf_daddr); 3980 DPRINTF(sc, ATH_DEBUG_XMIT, 3981 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3982 __func__, txq->axq_qnum, txq->axq_link, 3983 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3984 } 3985 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3986 /* 3987 * The CAB queue is started from the SWBA handler since 3988 * frames only go out on DTIM and to avoid possible races. 3989 */ 3990 if (txq != sc->sc_cabq) 3991 ath_hal_txstart(ah, txq->axq_qnum); 3992 ATH_TXQ_UNLOCK(txq); 3993 3994 return 0; 3995 } 3996 3997 /* 3998 * Process completed xmit descriptors from the specified queue. 3999 */ 4000 static int 4001 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4002 { 4003 struct ath_hal *ah = sc->sc_ah; 4004 struct ieee80211com *ic = &sc->sc_ic; 4005 struct ath_buf *bf; 4006 struct ath_desc *ds, *ds0; 4007 struct ieee80211_node *ni; 4008 struct ath_node *an; 4009 int sr, lr, pri, nacked; 4010 HAL_STATUS status; 4011 4012 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4013 __func__, txq->axq_qnum, 4014 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4015 txq->axq_link); 4016 nacked = 0; 4017 for (;;) { 4018 ATH_TXQ_LOCK(txq); 4019 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4020 bf = STAILQ_FIRST(&txq->axq_q); 4021 if (bf == NULL) { 4022 txq->axq_link = NULL; 4023 ATH_TXQ_UNLOCK(txq); 4024 break; 4025 } 4026 ds0 = &bf->bf_desc[0]; 4027 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4028 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4029 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4030 ath_printtxbuf(bf, status == HAL_OK); 4031 if (status == HAL_EINPROGRESS) { 4032 ATH_TXQ_UNLOCK(txq); 4033 break; 4034 } 4035 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4036 ATH_TXQ_UNLOCK(txq); 4037 4038 ni = bf->bf_node; 4039 if (ni != NULL) { 4040 an = ATH_NODE(ni); 4041 if (ds->ds_txstat.ts_status == 0) { 4042 u_int8_t txant = ds->ds_txstat.ts_antenna; 4043 sc->sc_stats.ast_ant_tx[txant]++; 4044 sc->sc_ant_tx[txant]++; 4045 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4046 sc->sc_stats.ast_tx_altrate++; 4047 sc->sc_stats.ast_tx_rssi = 4048 ds->ds_txstat.ts_rssi; 4049 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4050 ds->ds_txstat.ts_rssi); 4051 pri = M_WME_GETAC(bf->bf_m); 4052 if (pri >= WME_AC_VO) 4053 ic->ic_wme.wme_hipri_traffic++; 4054 ni->ni_inact = ni->ni_inact_reload; 4055 } else { 4056 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4057 sc->sc_stats.ast_tx_xretries++; 4058 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4059 sc->sc_stats.ast_tx_fifoerr++; 4060 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4061 sc->sc_stats.ast_tx_filtered++; 4062 } 4063 sr = ds->ds_txstat.ts_shortretry; 4064 lr = ds->ds_txstat.ts_longretry; 4065 sc->sc_stats.ast_tx_shortretry += sr; 4066 sc->sc_stats.ast_tx_longretry += lr; 4067 /* 4068 * Hand the descriptor to the rate control algorithm. 4069 */ 4070 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4071 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4072 /* 4073 * If frame was ack'd update the last rx time 4074 * used to workaround phantom bmiss interrupts. 4075 */ 4076 if (ds->ds_txstat.ts_status == 0) 4077 nacked++; 4078 ath_rate_tx_complete(sc, an, ds, ds0); 4079 } 4080 /* 4081 * Reclaim reference to node. 4082 * 4083 * NB: the node may be reclaimed here if, for example 4084 * this is a DEAUTH message that was sent and the 4085 * node was timed out due to inactivity. 4086 */ 4087 ieee80211_free_node(ni); 4088 } 4089 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4090 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4091 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4092 m_freem(bf->bf_m); 4093 bf->bf_m = NULL; 4094 bf->bf_node = NULL; 4095 4096 ATH_TXBUF_LOCK(sc); 4097 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4098 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4099 ATH_TXBUF_UNLOCK(sc); 4100 } 4101 return nacked; 4102 } 4103 4104 static inline int 4105 txqactive(struct ath_hal *ah, int qnum) 4106 { 4107 u_int32_t txqs = 1<<qnum; 4108 ath_hal_gettxintrtxqs(ah, &txqs); 4109 return (txqs & (1<<qnum)); 4110 } 4111 4112 /* 4113 * Deferred processing of transmit interrupt; special-cased 4114 * for a single hardware transmit queue (e.g. 5210 and 5211). 4115 */ 4116 static void 4117 ath_tx_proc_q0(void *arg, int npending) 4118 { 4119 struct ath_softc *sc = arg; 4120 struct ifnet *ifp = &sc->sc_if; 4121 4122 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4123 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4124 } 4125 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4126 ath_tx_processq(sc, sc->sc_cabq); 4127 4128 if (sc->sc_softled) 4129 ath_led_event(sc, ATH_LED_TX); 4130 4131 ath_start(ifp); 4132 } 4133 4134 /* 4135 * Deferred processing of transmit interrupt; special-cased 4136 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4137 */ 4138 static void 4139 ath_tx_proc_q0123(void *arg, int npending) 4140 { 4141 struct ath_softc *sc = arg; 4142 struct ifnet *ifp = &sc->sc_if; 4143 int nacked; 4144 4145 /* 4146 * Process each active queue. 4147 */ 4148 nacked = 0; 4149 if (txqactive(sc->sc_ah, 0)) 4150 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4151 if (txqactive(sc->sc_ah, 1)) 4152 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4153 if (txqactive(sc->sc_ah, 2)) 4154 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4155 if (txqactive(sc->sc_ah, 3)) 4156 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4157 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4158 ath_tx_processq(sc, sc->sc_cabq); 4159 if (nacked) { 4160 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4161 } 4162 4163 if (sc->sc_softled) 4164 ath_led_event(sc, ATH_LED_TX); 4165 4166 ath_start(ifp); 4167 } 4168 4169 /* 4170 * Deferred processing of transmit interrupt. 4171 */ 4172 static void 4173 ath_tx_proc(void *arg, int npending) 4174 { 4175 struct ath_softc *sc = arg; 4176 struct ifnet *ifp = &sc->sc_if; 4177 int i, nacked; 4178 4179 /* 4180 * Process each active queue. 4181 */ 4182 nacked = 0; 4183 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4184 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4185 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4186 if (nacked) { 4187 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4188 } 4189 4190 if (sc->sc_softled) 4191 ath_led_event(sc, ATH_LED_TX); 4192 4193 ath_start(ifp); 4194 } 4195 4196 static void 4197 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4198 { 4199 struct ath_hal *ah = sc->sc_ah; 4200 struct ieee80211_node *ni; 4201 struct ath_buf *bf; 4202 struct ath_desc *ds; 4203 4204 /* 4205 * NB: this assumes output has been stopped and 4206 * we do not need to block ath_tx_tasklet 4207 */ 4208 for (;;) { 4209 ATH_TXQ_LOCK(txq); 4210 bf = STAILQ_FIRST(&txq->axq_q); 4211 if (bf == NULL) { 4212 txq->axq_link = NULL; 4213 ATH_TXQ_UNLOCK(txq); 4214 break; 4215 } 4216 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4217 ATH_TXQ_UNLOCK(txq); 4218 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4219 if (sc->sc_debug & ATH_DEBUG_RESET) 4220 ath_printtxbuf(bf, 4221 ath_hal_txprocdesc(ah, bf->bf_desc, 4222 &ds->ds_txstat) == HAL_OK); 4223 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4224 m_freem(bf->bf_m); 4225 bf->bf_m = NULL; 4226 ni = bf->bf_node; 4227 bf->bf_node = NULL; 4228 if (ni != NULL) { 4229 /* 4230 * Reclaim node reference. 4231 */ 4232 ieee80211_free_node(ni); 4233 } 4234 ATH_TXBUF_LOCK(sc); 4235 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4236 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4237 ATH_TXBUF_UNLOCK(sc); 4238 } 4239 } 4240 4241 static void 4242 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4243 { 4244 struct ath_hal *ah = sc->sc_ah; 4245 4246 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4247 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4248 __func__, txq->axq_qnum, 4249 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4250 txq->axq_link); 4251 } 4252 4253 /* 4254 * Drain the transmit queues and reclaim resources. 4255 */ 4256 static void 4257 ath_draintxq(struct ath_softc *sc) 4258 { 4259 struct ath_hal *ah = sc->sc_ah; 4260 int i; 4261 4262 /* XXX return value */ 4263 if (device_is_active(sc->sc_dev)) { 4264 /* don't touch the hardware if marked invalid */ 4265 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4266 DPRINTF(sc, ATH_DEBUG_RESET, 4267 "%s: beacon queue %p\n", __func__, 4268 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4269 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4270 if (ATH_TXQ_SETUP(sc, i)) 4271 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4272 } 4273 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4274 if (ATH_TXQ_SETUP(sc, i)) 4275 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4276 } 4277 4278 /* 4279 * Disable the receive h/w in preparation for a reset. 4280 */ 4281 static void 4282 ath_stoprecv(struct ath_softc *sc) 4283 { 4284 #define PA2DESC(_sc, _pa) \ 4285 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4286 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4287 struct ath_hal *ah = sc->sc_ah; 4288 u_int64_t tsf; 4289 4290 ath_hal_stoppcurecv(ah); /* disable PCU */ 4291 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4292 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4293 DELAY(3000); /* 3ms is long enough for 1 frame */ 4294 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4295 struct ath_buf *bf; 4296 4297 printf("%s: rx queue %p, link %p\n", __func__, 4298 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4299 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4300 struct ath_desc *ds = bf->bf_desc; 4301 tsf = ath_hal_gettsf64(sc->sc_ah); 4302 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4303 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4304 tsf, &ds->ds_rxstat); 4305 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4306 ath_printrxbuf(bf, status == HAL_OK); 4307 } 4308 } 4309 sc->sc_rxlink = NULL; /* just in case */ 4310 #undef PA2DESC 4311 } 4312 4313 /* 4314 * Enable the receive h/w following a reset. 4315 */ 4316 static int 4317 ath_startrecv(struct ath_softc *sc) 4318 { 4319 struct ath_hal *ah = sc->sc_ah; 4320 struct ath_buf *bf; 4321 4322 sc->sc_rxlink = NULL; 4323 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4324 int error = ath_rxbuf_init(sc, bf); 4325 if (error != 0) { 4326 DPRINTF(sc, ATH_DEBUG_RECV, 4327 "%s: ath_rxbuf_init failed %d\n", 4328 __func__, error); 4329 return error; 4330 } 4331 } 4332 4333 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4334 ath_hal_putrxbuf(ah, bf->bf_daddr); 4335 ath_hal_rxena(ah); /* enable recv descriptors */ 4336 ath_mode_init(sc); /* set filters, etc. */ 4337 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4338 return 0; 4339 } 4340 4341 /* 4342 * Update internal state after a channel change. 4343 */ 4344 static void 4345 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4346 { 4347 struct ieee80211com *ic = &sc->sc_ic; 4348 enum ieee80211_phymode mode; 4349 u_int16_t flags; 4350 4351 /* 4352 * Change channels and update the h/w rate map 4353 * if we're switching; e.g. 11a to 11b/g. 4354 */ 4355 mode = ieee80211_chan2mode(ic, chan); 4356 if (mode != sc->sc_curmode) 4357 ath_setcurmode(sc, mode); 4358 /* 4359 * Update BPF state. NB: ethereal et. al. don't handle 4360 * merged flags well so pick a unique mode for their use. 4361 */ 4362 if (IEEE80211_IS_CHAN_A(chan)) 4363 flags = IEEE80211_CHAN_A; 4364 /* XXX 11g schizophrenia */ 4365 else if (IEEE80211_IS_CHAN_G(chan) || 4366 IEEE80211_IS_CHAN_PUREG(chan)) 4367 flags = IEEE80211_CHAN_G; 4368 else 4369 flags = IEEE80211_CHAN_B; 4370 if (IEEE80211_IS_CHAN_T(chan)) 4371 flags |= IEEE80211_CHAN_TURBO; 4372 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4373 htole16(chan->ic_freq); 4374 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4375 htole16(flags); 4376 } 4377 4378 #if 0 4379 /* 4380 * Poll for a channel clear indication; this is required 4381 * for channels requiring DFS and not previously visited 4382 * and/or with a recent radar detection. 4383 */ 4384 static void 4385 ath_dfswait(void *arg) 4386 { 4387 struct ath_softc *sc = arg; 4388 struct ath_hal *ah = sc->sc_ah; 4389 HAL_CHANNEL hchan; 4390 4391 ath_hal_radar_wait(ah, &hchan); 4392 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4393 if_printf(&sc->sc_if, 4394 "channel %u/0x%x/0x%x has interference\n", 4395 hchan.channel, hchan.channelFlags, hchan.privFlags); 4396 return; 4397 } 4398 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4399 /* XXX should not happen */ 4400 return; 4401 } 4402 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4403 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4404 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4405 if_printf(&sc->sc_if, 4406 "channel %u/0x%x/0x%x marked clear\n", 4407 hchan.channel, hchan.channelFlags, hchan.privFlags); 4408 } else 4409 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4410 } 4411 #endif 4412 4413 /* 4414 * Set/change channels. If the channel is really being changed, 4415 * it's done by reseting the chip. To accomplish this we must 4416 * first cleanup any pending DMA, then restart stuff after a la 4417 * ath_init. 4418 */ 4419 static int 4420 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4421 { 4422 struct ath_hal *ah = sc->sc_ah; 4423 struct ieee80211com *ic = &sc->sc_ic; 4424 HAL_CHANNEL hchan; 4425 4426 /* 4427 * Convert to a HAL channel description with 4428 * the flags constrained to reflect the current 4429 * operating mode. 4430 */ 4431 hchan.channel = chan->ic_freq; 4432 hchan.channelFlags = ath_chan2flags(ic, chan); 4433 4434 DPRINTF(sc, ATH_DEBUG_RESET, 4435 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4436 __func__, 4437 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4438 sc->sc_curchan.channelFlags), 4439 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4440 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4441 hchan.channel, hchan.channelFlags); 4442 if (hchan.channel != sc->sc_curchan.channel || 4443 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4444 HAL_STATUS status; 4445 4446 /* 4447 * To switch channels clear any pending DMA operations; 4448 * wait long enough for the RX fifo to drain, reset the 4449 * hardware at the new frequency, and then re-enable 4450 * the relevant bits of the h/w. 4451 */ 4452 ath_hal_intrset(ah, 0); /* disable interrupts */ 4453 ath_draintxq(sc); /* clear pending tx frames */ 4454 ath_stoprecv(sc); /* turn off frame recv */ 4455 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4456 if_printf(ic->ic_ifp, "%s: unable to reset " 4457 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4458 __func__, ieee80211_chan2ieee(ic, chan), 4459 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4460 return EIO; 4461 } 4462 sc->sc_curchan = hchan; 4463 ath_update_txpow(sc); /* update tx power state */ 4464 ath_restore_diversity(sc); 4465 sc->sc_calinterval = 1; 4466 sc->sc_caltries = 0; 4467 4468 /* 4469 * Re-enable rx framework. 4470 */ 4471 if (ath_startrecv(sc) != 0) { 4472 if_printf(&sc->sc_if, 4473 "%s: unable to restart recv logic\n", __func__); 4474 return EIO; 4475 } 4476 4477 /* 4478 * Change channels and update the h/w rate map 4479 * if we're switching; e.g. 11a to 11b/g. 4480 */ 4481 ic->ic_ibss_chan = chan; 4482 ath_chan_change(sc, chan); 4483 4484 #if 0 4485 /* 4486 * Handle DFS required waiting period to determine 4487 * if channel is clear of radar traffic. 4488 */ 4489 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4490 #define DFS_AND_NOT_CLEAR(_c) \ 4491 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4492 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4493 if_printf(&sc->sc_if, 4494 "wait for DFS clear channel signal\n"); 4495 /* XXX stop sndq */ 4496 sc->sc_if.if_flags |= IFF_OACTIVE; 4497 callout_reset(&sc->sc_dfs_ch, 4498 2 * hz, ath_dfswait, sc); 4499 } else 4500 callout_stop(&sc->sc_dfs_ch); 4501 #undef DFS_NOT_CLEAR 4502 } 4503 #endif 4504 4505 /* 4506 * Re-enable interrupts. 4507 */ 4508 ath_hal_intrset(ah, sc->sc_imask); 4509 } 4510 return 0; 4511 } 4512 4513 static void 4514 ath_next_scan(void *arg) 4515 { 4516 struct ath_softc *sc = arg; 4517 struct ieee80211com *ic = &sc->sc_ic; 4518 int s; 4519 4520 /* don't call ath_start w/o network interrupts blocked */ 4521 s = splnet(); 4522 4523 if (ic->ic_state == IEEE80211_S_SCAN) 4524 ieee80211_next_scan(ic); 4525 splx(s); 4526 } 4527 4528 /* 4529 * Periodically recalibrate the PHY to account 4530 * for temperature/environment changes. 4531 */ 4532 static void 4533 ath_calibrate(void *arg) 4534 { 4535 struct ath_softc *sc = arg; 4536 struct ath_hal *ah = sc->sc_ah; 4537 HAL_BOOL iqCalDone; 4538 4539 sc->sc_stats.ast_per_cal++; 4540 4541 ATH_LOCK(sc); 4542 4543 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4544 /* 4545 * Rfgain is out of bounds, reset the chip 4546 * to load new gain values. 4547 */ 4548 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4549 "%s: rfgain change\n", __func__); 4550 sc->sc_stats.ast_per_rfgain++; 4551 ath_reset(&sc->sc_if); 4552 } 4553 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4554 DPRINTF(sc, ATH_DEBUG_ANY, 4555 "%s: calibration of channel %u failed\n", 4556 __func__, sc->sc_curchan.channel); 4557 sc->sc_stats.ast_per_calfail++; 4558 } 4559 /* 4560 * Calibrate noise floor data again in case of change. 4561 */ 4562 ath_hal_process_noisefloor(ah); 4563 /* 4564 * Poll more frequently when the IQ calibration is in 4565 * progress to speedup loading the final settings. 4566 * We temper this aggressive polling with an exponential 4567 * back off after 4 tries up to ath_calinterval. 4568 */ 4569 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4570 sc->sc_caltries = 0; 4571 sc->sc_calinterval = ath_calinterval; 4572 } else if (sc->sc_caltries > 4) { 4573 sc->sc_caltries = 0; 4574 sc->sc_calinterval <<= 1; 4575 if (sc->sc_calinterval > ath_calinterval) 4576 sc->sc_calinterval = ath_calinterval; 4577 } 4578 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4579 ("bad calibration interval %u", sc->sc_calinterval)); 4580 4581 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4582 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4583 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4584 sc->sc_caltries++; 4585 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4586 ath_calibrate, sc); 4587 ATH_UNLOCK(sc); 4588 } 4589 4590 static int 4591 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4592 { 4593 struct ifnet *ifp = ic->ic_ifp; 4594 struct ath_softc *sc = ifp->if_softc; 4595 struct ath_hal *ah = sc->sc_ah; 4596 struct ieee80211_node *ni; 4597 int i, error; 4598 const u_int8_t *bssid; 4599 u_int32_t rfilt; 4600 static const HAL_LED_STATE leds[] = { 4601 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4602 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4603 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4604 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4605 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4606 }; 4607 4608 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4609 ieee80211_state_name[ic->ic_state], 4610 ieee80211_state_name[nstate]); 4611 4612 callout_stop(&sc->sc_scan_ch); 4613 callout_stop(&sc->sc_cal_ch); 4614 #if 0 4615 callout_stop(&sc->sc_dfs_ch); 4616 #endif 4617 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4618 4619 if (nstate == IEEE80211_S_INIT) { 4620 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4621 /* 4622 * NB: disable interrupts so we don't rx frames. 4623 */ 4624 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4625 /* 4626 * Notify the rate control algorithm. 4627 */ 4628 ath_rate_newstate(sc, nstate); 4629 goto done; 4630 } 4631 ni = ic->ic_bss; 4632 error = ath_chan_set(sc, ic->ic_curchan); 4633 if (error != 0) 4634 goto bad; 4635 rfilt = ath_calcrxfilter(sc, nstate); 4636 if (nstate == IEEE80211_S_SCAN) 4637 bssid = ifp->if_broadcastaddr; 4638 else 4639 bssid = ni->ni_bssid; 4640 ath_hal_setrxfilter(ah, rfilt); 4641 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4642 __func__, rfilt, ether_sprintf(bssid)); 4643 4644 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4645 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4646 else 4647 ath_hal_setassocid(ah, bssid, 0); 4648 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4649 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4650 if (ath_hal_keyisvalid(ah, i)) 4651 ath_hal_keysetmac(ah, i, bssid); 4652 } 4653 4654 /* 4655 * Notify the rate control algorithm so rates 4656 * are setup should ath_beacon_alloc be called. 4657 */ 4658 ath_rate_newstate(sc, nstate); 4659 4660 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4661 /* nothing to do */; 4662 } else if (nstate == IEEE80211_S_RUN) { 4663 DPRINTF(sc, ATH_DEBUG_STATE, 4664 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4665 "capinfo=0x%04x chan=%d\n" 4666 , __func__ 4667 , ic->ic_flags 4668 , ni->ni_intval 4669 , ether_sprintf(ni->ni_bssid) 4670 , ni->ni_capinfo 4671 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4672 4673 switch (ic->ic_opmode) { 4674 case IEEE80211_M_HOSTAP: 4675 case IEEE80211_M_IBSS: 4676 /* 4677 * Allocate and setup the beacon frame. 4678 * 4679 * Stop any previous beacon DMA. This may be 4680 * necessary, for example, when an ibss merge 4681 * causes reconfiguration; there will be a state 4682 * transition from RUN->RUN that means we may 4683 * be called with beacon transmission active. 4684 */ 4685 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4686 ath_beacon_free(sc); 4687 error = ath_beacon_alloc(sc, ni); 4688 if (error != 0) 4689 goto bad; 4690 /* 4691 * If joining an adhoc network defer beacon timer 4692 * configuration to the next beacon frame so we 4693 * have a current TSF to use. Otherwise we're 4694 * starting an ibss/bss so there's no need to delay. 4695 */ 4696 if (ic->ic_opmode == IEEE80211_M_IBSS && 4697 ic->ic_bss->ni_tstamp.tsf != 0) 4698 sc->sc_syncbeacon = 1; 4699 else 4700 ath_beacon_config(sc); 4701 break; 4702 case IEEE80211_M_STA: 4703 /* 4704 * Allocate a key cache slot to the station. 4705 */ 4706 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4707 sc->sc_hasclrkey && 4708 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4709 ath_setup_stationkey(ni); 4710 /* 4711 * Defer beacon timer configuration to the next 4712 * beacon frame so we have a current TSF to use 4713 * (any TSF collected when scanning is likely old). 4714 */ 4715 sc->sc_syncbeacon = 1; 4716 break; 4717 default: 4718 break; 4719 } 4720 /* 4721 * Let the hal process statistics collected during a 4722 * scan so it can provide calibrated noise floor data. 4723 */ 4724 ath_hal_process_noisefloor(ah); 4725 /* 4726 * Reset rssi stats; maybe not the best place... 4727 */ 4728 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4729 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4730 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4731 } else { 4732 ath_hal_intrset(ah, 4733 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4734 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4735 } 4736 done: 4737 /* 4738 * Invoke the parent method to complete the work. 4739 */ 4740 error = sc->sc_newstate(ic, nstate, arg); 4741 /* 4742 * Finally, start any timers. 4743 */ 4744 if (nstate == IEEE80211_S_RUN) { 4745 /* start periodic recalibration timer */ 4746 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4747 ath_calibrate, sc); 4748 } else if (nstate == IEEE80211_S_SCAN) { 4749 /* start ap/neighbor scan timer */ 4750 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4751 ath_next_scan, sc); 4752 } 4753 bad: 4754 return error; 4755 } 4756 4757 /* 4758 * Allocate a key cache slot to the station so we can 4759 * setup a mapping from key index to node. The key cache 4760 * slot is needed for managing antenna state and for 4761 * compression when stations do not use crypto. We do 4762 * it uniliaterally here; if crypto is employed this slot 4763 * will be reassigned. 4764 */ 4765 static void 4766 ath_setup_stationkey(struct ieee80211_node *ni) 4767 { 4768 struct ieee80211com *ic = ni->ni_ic; 4769 struct ath_softc *sc = ic->ic_ifp->if_softc; 4770 ieee80211_keyix keyix, rxkeyix; 4771 4772 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4773 /* 4774 * Key cache is full; we'll fall back to doing 4775 * the more expensive lookup in software. Note 4776 * this also means no h/w compression. 4777 */ 4778 /* XXX msg+statistic */ 4779 } else { 4780 /* XXX locking? */ 4781 ni->ni_ucastkey.wk_keyix = keyix; 4782 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4783 /* NB: this will create a pass-thru key entry */ 4784 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4785 } 4786 } 4787 4788 /* 4789 * Setup driver-specific state for a newly associated node. 4790 * Note that we're called also on a re-associate, the isnew 4791 * param tells us if this is the first time or not. 4792 */ 4793 static void 4794 ath_newassoc(struct ieee80211_node *ni, int isnew) 4795 { 4796 struct ieee80211com *ic = ni->ni_ic; 4797 struct ath_softc *sc = ic->ic_ifp->if_softc; 4798 4799 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4800 if (isnew && 4801 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4802 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4803 ("new assoc with a unicast key already setup (keyix %u)", 4804 ni->ni_ucastkey.wk_keyix)); 4805 ath_setup_stationkey(ni); 4806 } 4807 } 4808 4809 static int 4810 ath_getchannels(struct ath_softc *sc, u_int cc, 4811 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4812 { 4813 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4814 struct ieee80211com *ic = &sc->sc_ic; 4815 struct ifnet *ifp = &sc->sc_if; 4816 struct ath_hal *ah = sc->sc_ah; 4817 HAL_CHANNEL *chans; 4818 int i, ix, nchan; 4819 4820 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4821 M_TEMP, M_NOWAIT); 4822 if (chans == NULL) { 4823 if_printf(ifp, "unable to allocate channel table\n"); 4824 return ENOMEM; 4825 } 4826 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4827 NULL, 0, NULL, 4828 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4829 u_int32_t rd; 4830 4831 (void)ath_hal_getregdomain(ah, &rd); 4832 if_printf(ifp, "unable to collect channel list from hal; " 4833 "regdomain likely %u country code %u\n", rd, cc); 4834 free(chans, M_TEMP); 4835 return EINVAL; 4836 } 4837 4838 /* 4839 * Convert HAL channels to ieee80211 ones and insert 4840 * them in the table according to their channel number. 4841 */ 4842 for (i = 0; i < nchan; i++) { 4843 HAL_CHANNEL *c = &chans[i]; 4844 u_int16_t flags; 4845 4846 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4847 if (ix > IEEE80211_CHAN_MAX) { 4848 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4849 ix, c->channel, c->channelFlags); 4850 continue; 4851 } 4852 if (ix < 0) { 4853 /* XXX can't handle stuff <2400 right now */ 4854 if (bootverbose) 4855 if_printf(ifp, "hal channel %d (%u/%x) " 4856 "cannot be handled; ignored\n", 4857 ix, c->channel, c->channelFlags); 4858 continue; 4859 } 4860 /* 4861 * Calculate net80211 flags; most are compatible 4862 * but some need massaging. Note the static turbo 4863 * conversion can be removed once net80211 is updated 4864 * to understand static vs. dynamic turbo. 4865 */ 4866 flags = c->channelFlags & COMPAT; 4867 if (c->channelFlags & CHANNEL_STURBO) 4868 flags |= IEEE80211_CHAN_TURBO; 4869 if (ic->ic_channels[ix].ic_freq == 0) { 4870 ic->ic_channels[ix].ic_freq = c->channel; 4871 ic->ic_channels[ix].ic_flags = flags; 4872 } else { 4873 /* channels overlap; e.g. 11g and 11b */ 4874 ic->ic_channels[ix].ic_flags |= flags; 4875 } 4876 } 4877 free(chans, M_TEMP); 4878 return 0; 4879 #undef COMPAT 4880 } 4881 4882 static void 4883 ath_led_done(void *arg) 4884 { 4885 struct ath_softc *sc = arg; 4886 4887 sc->sc_blinking = 0; 4888 } 4889 4890 /* 4891 * Turn the LED off: flip the pin and then set a timer so no 4892 * update will happen for the specified duration. 4893 */ 4894 static void 4895 ath_led_off(void *arg) 4896 { 4897 struct ath_softc *sc = arg; 4898 4899 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4900 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4901 } 4902 4903 /* 4904 * Blink the LED according to the specified on/off times. 4905 */ 4906 static void 4907 ath_led_blink(struct ath_softc *sc, int on, int off) 4908 { 4909 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4910 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4911 sc->sc_blinking = 1; 4912 sc->sc_ledoff = off; 4913 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4914 } 4915 4916 static void 4917 ath_led_event(struct ath_softc *sc, int event) 4918 { 4919 4920 sc->sc_ledevent = ticks; /* time of last event */ 4921 if (sc->sc_blinking) /* don't interrupt active blink */ 4922 return; 4923 switch (event) { 4924 case ATH_LED_POLL: 4925 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4926 sc->sc_hwmap[0].ledoff); 4927 break; 4928 case ATH_LED_TX: 4929 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4930 sc->sc_hwmap[sc->sc_txrate].ledoff); 4931 break; 4932 case ATH_LED_RX: 4933 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4934 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4935 break; 4936 } 4937 } 4938 4939 static void 4940 ath_update_txpow(struct ath_softc *sc) 4941 { 4942 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4943 struct ieee80211com *ic = &sc->sc_ic; 4944 struct ath_hal *ah = sc->sc_ah; 4945 u_int32_t txpow; 4946 4947 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4948 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4949 /* read back in case value is clamped */ 4950 (void)ath_hal_gettxpowlimit(ah, &txpow); 4951 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4952 } 4953 /* 4954 * Fetch max tx power level for status requests. 4955 */ 4956 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4957 ic->ic_bss->ni_txpower = txpow; 4958 } 4959 4960 static void 4961 rate_setup(struct ath_softc *sc, 4962 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4963 { 4964 int i, maxrates; 4965 4966 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4967 DPRINTF(sc, ATH_DEBUG_ANY, 4968 "%s: rate table too small (%u > %u)\n", 4969 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4970 maxrates = IEEE80211_RATE_MAXSIZE; 4971 } else 4972 maxrates = rt->rateCount; 4973 for (i = 0; i < maxrates; i++) 4974 rs->rs_rates[i] = rt->info[i].dot11Rate; 4975 rs->rs_nrates = maxrates; 4976 } 4977 4978 static int 4979 ath_rate_setup(struct ath_softc *sc, u_int mode) 4980 { 4981 struct ath_hal *ah = sc->sc_ah; 4982 struct ieee80211com *ic = &sc->sc_ic; 4983 const HAL_RATE_TABLE *rt; 4984 4985 switch (mode) { 4986 case IEEE80211_MODE_11A: 4987 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4988 break; 4989 case IEEE80211_MODE_11B: 4990 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4991 break; 4992 case IEEE80211_MODE_11G: 4993 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4994 break; 4995 case IEEE80211_MODE_TURBO_A: 4996 /* XXX until static/dynamic turbo is fixed */ 4997 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4998 break; 4999 case IEEE80211_MODE_TURBO_G: 5000 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5001 break; 5002 default: 5003 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5004 __func__, mode); 5005 return 0; 5006 } 5007 sc->sc_rates[mode] = rt; 5008 if (rt != NULL) { 5009 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5010 return 1; 5011 } else 5012 return 0; 5013 } 5014 5015 static void 5016 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5017 { 5018 #define N(a) (sizeof(a)/sizeof(a[0])) 5019 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5020 static const struct { 5021 u_int rate; /* tx/rx 802.11 rate */ 5022 u_int16_t timeOn; /* LED on time (ms) */ 5023 u_int16_t timeOff; /* LED off time (ms) */ 5024 } blinkrates[] = { 5025 { 108, 40, 10 }, 5026 { 96, 44, 11 }, 5027 { 72, 50, 13 }, 5028 { 48, 57, 14 }, 5029 { 36, 67, 16 }, 5030 { 24, 80, 20 }, 5031 { 22, 100, 25 }, 5032 { 18, 133, 34 }, 5033 { 12, 160, 40 }, 5034 { 10, 200, 50 }, 5035 { 6, 240, 58 }, 5036 { 4, 267, 66 }, 5037 { 2, 400, 100 }, 5038 { 0, 500, 130 }, 5039 }; 5040 const HAL_RATE_TABLE *rt; 5041 int i, j; 5042 5043 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5044 rt = sc->sc_rates[mode]; 5045 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5046 for (i = 0; i < rt->rateCount; i++) 5047 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5048 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5049 for (i = 0; i < 32; i++) { 5050 u_int8_t ix = rt->rateCodeToIndex[i]; 5051 if (ix == 0xff) { 5052 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5053 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5054 continue; 5055 } 5056 sc->sc_hwmap[i].ieeerate = 5057 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5058 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5059 if (rt->info[ix].shortPreamble || 5060 rt->info[ix].phy == IEEE80211_T_OFDM) 5061 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5062 /* NB: receive frames include FCS */ 5063 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5064 IEEE80211_RADIOTAP_F_FCS; 5065 /* setup blink rate table to avoid per-packet lookup */ 5066 for (j = 0; j < N(blinkrates)-1; j++) 5067 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5068 break; 5069 /* NB: this uses the last entry if the rate isn't found */ 5070 /* XXX beware of overlow */ 5071 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5072 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5073 } 5074 sc->sc_currates = rt; 5075 sc->sc_curmode = mode; 5076 /* 5077 * All protection frames are transmited at 2Mb/s for 5078 * 11g, otherwise at 1Mb/s. 5079 */ 5080 if (mode == IEEE80211_MODE_11G) 5081 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5082 else 5083 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5084 /* rate index used to send management frames */ 5085 sc->sc_minrateix = 0; 5086 /* 5087 * Setup multicast rate state. 5088 */ 5089 /* XXX layering violation */ 5090 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5091 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5092 /* NB: caller is responsible for reseting rate control state */ 5093 #undef N 5094 } 5095 5096 #ifdef AR_DEBUG 5097 static void 5098 ath_printrxbuf(struct ath_buf *bf, int done) 5099 { 5100 struct ath_desc *ds; 5101 int i; 5102 5103 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5104 printf("R%d (%p %" PRIx64 5105 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5106 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5107 ds->ds_link, ds->ds_data, 5108 ds->ds_ctl0, ds->ds_ctl1, 5109 ds->ds_hw[0], ds->ds_hw[1], 5110 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5111 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5112 } 5113 } 5114 5115 static void 5116 ath_printtxbuf(struct ath_buf *bf, int done) 5117 { 5118 struct ath_desc *ds; 5119 int i; 5120 5121 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5122 printf("T%d (%p %" PRIx64 5123 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5124 i, ds, 5125 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5126 ds->ds_link, ds->ds_data, 5127 ds->ds_ctl0, ds->ds_ctl1, 5128 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5129 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5130 } 5131 } 5132 #endif /* AR_DEBUG */ 5133 5134 static void 5135 ath_watchdog(struct ifnet *ifp) 5136 { 5137 struct ath_softc *sc = ifp->if_softc; 5138 struct ieee80211com *ic = &sc->sc_ic; 5139 struct ath_txq *axq; 5140 int i; 5141 5142 ifp->if_timer = 0; 5143 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5144 !device_is_active(sc->sc_dev)) 5145 return; 5146 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5147 if (!ATH_TXQ_SETUP(sc, i)) 5148 continue; 5149 axq = &sc->sc_txq[i]; 5150 ATH_TXQ_LOCK(axq); 5151 if (axq->axq_timer == 0) 5152 ; 5153 else if (--axq->axq_timer == 0) { 5154 ATH_TXQ_UNLOCK(axq); 5155 if_printf(ifp, "device timeout (txq %d, " 5156 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5157 if (sc->sc_txintrperiod > 1) 5158 sc->sc_txintrperiod--; 5159 ath_reset(ifp); 5160 ifp->if_oerrors++; 5161 sc->sc_stats.ast_watchdog++; 5162 break; 5163 } else 5164 ifp->if_timer = 1; 5165 ATH_TXQ_UNLOCK(axq); 5166 } 5167 ieee80211_watchdog(ic); 5168 } 5169 5170 /* 5171 * Diagnostic interface to the HAL. This is used by various 5172 * tools to do things like retrieve register contents for 5173 * debugging. The mechanism is intentionally opaque so that 5174 * it can change frequently w/o concern for compatiblity. 5175 */ 5176 static int 5177 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5178 { 5179 struct ath_hal *ah = sc->sc_ah; 5180 u_int id = ad->ad_id & ATH_DIAG_ID; 5181 void *indata = NULL; 5182 void *outdata = NULL; 5183 u_int32_t insize = ad->ad_in_size; 5184 u_int32_t outsize = ad->ad_out_size; 5185 int error = 0; 5186 5187 if (ad->ad_id & ATH_DIAG_IN) { 5188 /* 5189 * Copy in data. 5190 */ 5191 indata = malloc(insize, M_TEMP, M_NOWAIT); 5192 if (indata == NULL) { 5193 error = ENOMEM; 5194 goto bad; 5195 } 5196 error = copyin(ad->ad_in_data, indata, insize); 5197 if (error) 5198 goto bad; 5199 } 5200 if (ad->ad_id & ATH_DIAG_DYN) { 5201 /* 5202 * Allocate a buffer for the results (otherwise the HAL 5203 * returns a pointer to a buffer where we can read the 5204 * results). Note that we depend on the HAL leaving this 5205 * pointer for us to use below in reclaiming the buffer; 5206 * may want to be more defensive. 5207 */ 5208 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5209 if (outdata == NULL) { 5210 error = ENOMEM; 5211 goto bad; 5212 } 5213 } 5214 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5215 if (outsize < ad->ad_out_size) 5216 ad->ad_out_size = outsize; 5217 if (outdata != NULL) 5218 error = copyout(outdata, ad->ad_out_data, 5219 ad->ad_out_size); 5220 } else { 5221 error = EINVAL; 5222 } 5223 bad: 5224 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5225 free(indata, M_TEMP); 5226 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5227 free(outdata, M_TEMP); 5228 return error; 5229 } 5230 5231 static int 5232 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5233 { 5234 #define IS_RUNNING(ifp) \ 5235 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5236 struct ath_softc *sc = ifp->if_softc; 5237 struct ieee80211com *ic = &sc->sc_ic; 5238 struct ifreq *ifr = (struct ifreq *)data; 5239 int error = 0; 5240 5241 ATH_LOCK(sc); 5242 switch (cmd) { 5243 case SIOCSIFFLAGS: 5244 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5245 break; 5246 if (IS_RUNNING(ifp)) { 5247 /* 5248 * To avoid rescanning another access point, 5249 * do not call ath_init() here. Instead, 5250 * only reflect promisc mode settings. 5251 */ 5252 ath_mode_init(sc); 5253 } else if (ifp->if_flags & IFF_UP) { 5254 /* 5255 * Beware of being called during attach/detach 5256 * to reset promiscuous mode. In that case we 5257 * will still be marked UP but not RUNNING. 5258 * However trying to re-init the interface 5259 * is the wrong thing to do as we've already 5260 * torn down much of our state. There's 5261 * probably a better way to deal with this. 5262 */ 5263 error = ath_init(sc); 5264 } else if (device_is_active(sc->sc_dev)) 5265 ath_stop_locked(ifp, 1); 5266 break; 5267 case SIOCADDMULTI: 5268 case SIOCDELMULTI: 5269 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5270 if (ifp->if_flags & IFF_RUNNING) 5271 ath_mode_init(sc); 5272 error = 0; 5273 } 5274 break; 5275 case SIOCGATHSTATS: 5276 /* NB: embed these numbers to get a consistent view */ 5277 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5278 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5279 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5280 ATH_UNLOCK(sc); 5281 /* 5282 * NB: Drop the softc lock in case of a page fault; 5283 * we'll accept any potential inconsisentcy in the 5284 * statistics. The alternative is to copy the data 5285 * to a local structure. 5286 */ 5287 return copyout(&sc->sc_stats, 5288 ifr->ifr_data, sizeof (sc->sc_stats)); 5289 case SIOCGATHDIAG: 5290 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5291 break; 5292 default: 5293 error = ieee80211_ioctl(ic, cmd, data); 5294 if (error != ENETRESET) 5295 ; 5296 else if (IS_RUNNING(ifp) && 5297 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5298 error = ath_init(sc); 5299 else 5300 error = 0; 5301 break; 5302 } 5303 ATH_UNLOCK(sc); 5304 return error; 5305 #undef IS_RUNNING 5306 } 5307 5308 #if NBPFILTER > 0 5309 static void 5310 ath_bpfattach(struct ath_softc *sc) 5311 { 5312 struct ifnet *ifp = &sc->sc_if; 5313 5314 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5315 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5316 &sc->sc_drvbpf); 5317 /* 5318 * Initialize constant fields. 5319 * XXX make header lengths a multiple of 32-bits so subsequent 5320 * headers are properly aligned; this is a kludge to keep 5321 * certain applications happy. 5322 * 5323 * NB: the channel is setup each time we transition to the 5324 * RUN state to avoid filling it in for each frame. 5325 */ 5326 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5327 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5328 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5329 5330 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5331 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5332 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5333 } 5334 #endif 5335 5336 /* 5337 * Announce various information on device/driver attach. 5338 */ 5339 static void 5340 ath_announce(struct ath_softc *sc) 5341 { 5342 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5343 struct ifnet *ifp = &sc->sc_if; 5344 struct ath_hal *ah = sc->sc_ah; 5345 u_int modes, cc; 5346 5347 if_printf(ifp, "mac %d.%d phy %d.%d", 5348 ah->ah_macVersion, ah->ah_macRev, 5349 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5350 /* 5351 * Print radio revision(s). We check the wireless modes 5352 * to avoid falsely printing revs for inoperable parts. 5353 * Dual-band radio revs are returned in the 5 GHz rev number. 5354 */ 5355 ath_hal_getcountrycode(ah, &cc); 5356 modes = ath_hal_getwirelessmodes(ah, cc); 5357 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5358 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5359 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5360 ah->ah_analog5GhzRev >> 4, 5361 ah->ah_analog5GhzRev & 0xf, 5362 ah->ah_analog2GhzRev >> 4, 5363 ah->ah_analog2GhzRev & 0xf); 5364 else 5365 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5366 ah->ah_analog5GhzRev & 0xf); 5367 } else 5368 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5369 ah->ah_analog5GhzRev & 0xf); 5370 printf("\n"); 5371 if (bootverbose) { 5372 int i; 5373 for (i = 0; i <= WME_AC_VO; i++) { 5374 struct ath_txq *txq = sc->sc_ac2q[i]; 5375 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5376 txq->axq_qnum, ieee80211_wme_acnames[i]); 5377 } 5378 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5379 sc->sc_cabq->axq_qnum); 5380 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5381 } 5382 if (ath_rxbuf != ATH_RXBUF) 5383 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5384 if (ath_txbuf != ATH_TXBUF) 5385 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5386 #undef HAL_MODE_DUALBAND 5387 } 5388