xref: /netbsd-src/sys/dev/ic/arn9280.c (revision 13d4bb4cc874de96add7fc4227d38a1d656b03d1)
1*13d4bb4cSthorpej /*	$NetBSD: arn9280.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $	*/
264f89611Schristos /*	$OpenBSD: ar9280.c,v 1.18 2012/06/10 21:23:36 kettenis Exp $	*/
364f89611Schristos 
464f89611Schristos /*-
564f89611Schristos  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
664f89611Schristos  * Copyright (c) 2008-2009 Atheros Communications Inc.
764f89611Schristos  *
864f89611Schristos  * Permission to use, copy, modify, and/or distribute this software for any
964f89611Schristos  * purpose with or without fee is hereby granted, provided that the above
1064f89611Schristos  * copyright notice and this permission notice appear in all copies.
1164f89611Schristos  *
1264f89611Schristos  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1364f89611Schristos  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1464f89611Schristos  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1564f89611Schristos  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1664f89611Schristos  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
1764f89611Schristos  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1864f89611Schristos  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1964f89611Schristos  */
2064f89611Schristos 
2164f89611Schristos /*
2264f89611Schristos  * Driver for Atheros 802.11a/g/n chipsets.
2364f89611Schristos  * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets.
2464f89611Schristos  */
2564f89611Schristos 
2664f89611Schristos #include <sys/cdefs.h>
27*13d4bb4cSthorpej __KERNEL_RCSID(0, "$NetBSD: arn9280.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $");
2864f89611Schristos 
2964f89611Schristos #include <sys/param.h>
3064f89611Schristos #include <sys/sockio.h>
3164f89611Schristos #include <sys/mbuf.h>
3264f89611Schristos #include <sys/kernel.h>
3364f89611Schristos #include <sys/socket.h>
3464f89611Schristos #include <sys/systm.h>
3564f89611Schristos #include <sys/queue.h>
3664f89611Schristos #include <sys/callout.h>
3764f89611Schristos #include <sys/conf.h>
3864f89611Schristos #include <sys/device.h>
3964f89611Schristos 
4064f89611Schristos #include <sys/bus.h>
4164f89611Schristos #include <sys/endian.h>
4264f89611Schristos #include <sys/intr.h>
4364f89611Schristos 
4464f89611Schristos #include <net/bpf.h>
4564f89611Schristos #include <net/if.h>
4664f89611Schristos #include <net/if_arp.h>
4764f89611Schristos #include <net/if_dl.h>
4802421171Schristos #include <net/if_ether.h>
4964f89611Schristos #include <net/if_media.h>
5064f89611Schristos #include <net/if_types.h>
5164f89611Schristos 
5264f89611Schristos #include <netinet/in.h>
5364f89611Schristos #include <netinet/in_systm.h>
5464f89611Schristos #include <netinet/in_var.h>
5564f89611Schristos #include <netinet/ip.h>
5664f89611Schristos 
5764f89611Schristos #include <net80211/ieee80211_var.h>
5864f89611Schristos #include <net80211/ieee80211_amrr.h>
5964f89611Schristos #include <net80211/ieee80211_radiotap.h>
6064f89611Schristos 
6164f89611Schristos #include <dev/ic/athnreg.h>
6264f89611Schristos #include <dev/ic/athnvar.h>
6364f89611Schristos 
6464f89611Schristos #include <dev/ic/arn5008reg.h>
6564f89611Schristos #include <dev/ic/arn5008.h>
6664f89611Schristos #include <dev/ic/arn5416reg.h>	/* We share the ROM layout. */
6764f89611Schristos #include <dev/ic/arn5416.h>	/* We share the ROM layout. */
6864f89611Schristos #include <dev/ic/arn9280reg.h>
6964f89611Schristos #include <dev/ic/arn9280.h>
7064f89611Schristos 
7164f89611Schristos #define Static static
7264f89611Schristos 
7364f89611Schristos Static void	ar9280_init_from_rom(struct athn_softc *,
7464f89611Schristos 		    struct ieee80211_channel *, struct ieee80211_channel *);
7564f89611Schristos Static void	ar9280_olpc_init(struct athn_softc *);
7664f89611Schristos Static void	ar9280_olpc_temp_compensation(struct athn_softc *);
7764f89611Schristos Static void	ar9280_setup(struct athn_softc *);
7864f89611Schristos 
7964f89611Schristos PUBLIC int
ar9280_attach(struct athn_softc * sc)8064f89611Schristos ar9280_attach(struct athn_softc *sc)
8164f89611Schristos {
8264f89611Schristos 
8364f89611Schristos 	sc->sc_eep_base = AR5416_EEP_START_LOC;
8464f89611Schristos 	sc->sc_eep_size = sizeof(struct ar5416_eeprom);
8564f89611Schristos 	sc->sc_def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
8664f89611Schristos 	sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 10;
8764f89611Schristos 	sc->sc_led_pin = 1;
8864f89611Schristos 	sc->sc_workaround = AR9280_WA_DEFAULT;
8964f89611Schristos 	sc->sc_ops.setup = ar9280_setup;
9064f89611Schristos 	sc->sc_ops.swap_rom = ar5416_swap_rom;
9164f89611Schristos 	sc->sc_ops.init_from_rom = ar9280_init_from_rom;
9264f89611Schristos 	sc->sc_ops.set_txpower = ar5416_set_txpower;
9364f89611Schristos 	sc->sc_ops.set_synth = ar9280_set_synth;
9464f89611Schristos 	sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
9564f89611Schristos 	sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
9664f89611Schristos 	sc->sc_ops.olpc_init = ar9280_olpc_init;
9764f89611Schristos 	sc->sc_ops.olpc_temp_compensation = ar9280_olpc_temp_compensation;
9864f89611Schristos 	sc->sc_ini = &ar9280_2_0_ini;
9964f89611Schristos 	sc->sc_serdes = &ar9280_2_0_serdes;
10064f89611Schristos 
10164f89611Schristos 	return ar5008_attach(sc);
10264f89611Schristos }
10364f89611Schristos 
10464f89611Schristos Static void
ar9280_setup(struct athn_softc * sc)10564f89611Schristos ar9280_setup(struct athn_softc *sc)
10664f89611Schristos {
10764f89611Schristos 	const struct ar5416_eeprom *eep = sc->sc_eep;
10864f89611Schristos 	uint8_t type;
10964f89611Schristos 
11064f89611Schristos 	/* Determine if open loop power control should be used. */
11164f89611Schristos 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19 &&
11264f89611Schristos 	    eep->baseEepHeader.openLoopPwrCntl)
11364f89611Schristos 		sc->sc_flags |= ATHN_FLAG_OLPC;
11464f89611Schristos 
11564f89611Schristos 	/* Determine if fast PLL clock is supported. */
11664f89611Schristos 	if (AR_SREV_9280_20(sc) &&
11764f89611Schristos 	    (sc->sc_eep_rev <= AR_EEP_MINOR_VER_16 ||
11864f89611Schristos 	     eep->baseEepHeader.fastClk5g))
11964f89611Schristos 		sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK;
12064f89611Schristos 
12164f89611Schristos 	/*
12264f89611Schristos 	 * Determine if initialization value for AR_AN_TOP2 must be fixed.
12364f89611Schristos 	 * This is required for some AR9220 devices such as Ubiquiti SR71-12.
12464f89611Schristos 	 */
12564f89611Schristos 	if (AR_SREV_9280_20(sc) &&
12664f89611Schristos 	    sc->sc_eep_rev > AR_EEP_MINOR_VER_10 &&
12764f89611Schristos 	    !eep->baseEepHeader.pwdclkind) {
12864f89611Schristos 		DPRINTFN(DBG_INIT, sc, "AR_AN_TOP2 fixup required\n");
12964f89611Schristos 		sc->sc_flags |= ATHN_FLAG_AN_TOP2_FIXUP;
13064f89611Schristos 	}
13164f89611Schristos 
13264f89611Schristos 	if (AR_SREV_9280_20(sc)) {
13364f89611Schristos 		/* Check if we have a valid rxGainType field in ROM. */
13464f89611Schristos 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_17) {
13564f89611Schristos 			/* Select initialization values based on ROM. */
13664f89611Schristos 			type = eep->baseEepHeader.rxGainType;
13764f89611Schristos 			DPRINTFN(DBG_INIT, sc, "Rx gain type=0x%x\n", type);
13864f89611Schristos 			if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
13964f89611Schristos 				sc->sc_rx_gain = &ar9280_2_0_rx_gain_23db_backoff;
14064f89611Schristos 			else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
14164f89611Schristos 				sc->sc_rx_gain = &ar9280_2_0_rx_gain_13db_backoff;
14264f89611Schristos 			else
14364f89611Schristos 				sc->sc_rx_gain = &ar9280_2_0_rx_gain;
14464f89611Schristos 		}
14564f89611Schristos 		else
14664f89611Schristos 			sc->sc_rx_gain = &ar9280_2_0_rx_gain;
14764f89611Schristos 
14864f89611Schristos 		/* Check if we have a valid txGainType field in ROM. */
14964f89611Schristos 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
15064f89611Schristos 			/* Select initialization values based on ROM. */
15164f89611Schristos 			type = eep->baseEepHeader.txGainType;
15264f89611Schristos 			DPRINTFN(DBG_INIT, sc, "Tx gain type=0x%x\n", type);
15364f89611Schristos 			if (type == AR_EEP_TXGAIN_HIGH_POWER)
15464f89611Schristos 				sc->sc_tx_gain = &ar9280_2_0_tx_gain_high_power;
15564f89611Schristos 			else
15664f89611Schristos 				sc->sc_tx_gain = &ar9280_2_0_tx_gain;
15764f89611Schristos 		}
15864f89611Schristos 		else
15964f89611Schristos 			sc->sc_tx_gain = &ar9280_2_0_tx_gain;
16064f89611Schristos 	}
16164f89611Schristos }
16264f89611Schristos 
16364f89611Schristos PUBLIC int
ar9280_set_synth(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)16464f89611Schristos ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
16564f89611Schristos     struct ieee80211_channel *extc)
16664f89611Schristos {
16764f89611Schristos 	uint32_t phy, reg, ndiv = 0;
16864f89611Schristos 	uint32_t freq = c->ic_freq;
16964f89611Schristos 
17064f89611Schristos 	phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
17164f89611Schristos 
17264f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
17364f89611Schristos 		phy |= (freq << 16) / 15;
17464f89611Schristos 		phy |= AR9280_BMODE | AR9280_FRACMODE;
17564f89611Schristos 
17664f89611Schristos 		if (AR_SREV_9287_11_OR_LATER(sc)) {
17764f89611Schristos 			/* NB: Magic values from the Linux driver. */
17864f89611Schristos 			if (freq == 2484) {	/* Channel 14. */
17964f89611Schristos 				/* Japanese regulatory requirements. */
18064f89611Schristos 				AR_WRITE(sc, AR_PHY(637), 0x00000000);
18164f89611Schristos 				AR_WRITE(sc, AR_PHY(638), 0xefff0301);
18264f89611Schristos 				AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
18364f89611Schristos 			}
18464f89611Schristos 			else {
18564f89611Schristos 				AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
18664f89611Schristos 				AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
18764f89611Schristos 				AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
18864f89611Schristos 			}
18964f89611Schristos 		}
19064f89611Schristos 		else {
19164f89611Schristos 			reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
19264f89611Schristos 			if (freq == 2484)	/* Channel 14. */
19364f89611Schristos 				reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
19464f89611Schristos 			else
19564f89611Schristos 				reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
19664f89611Schristos 			AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
19764f89611Schristos 		}
19864f89611Schristos 	}
19964f89611Schristos 	else {
20064f89611Schristos 		if (AR_SREV_9285_10_OR_LATER(sc) ||
20164f89611Schristos 		    sc->sc_eep_rev < AR_EEP_MINOR_VER_22 ||
20264f89611Schristos 		    !((struct ar5416_base_eep_header *)sc->sc_eep)->frac_n_5g) {
20364f89611Schristos 			if ((freq % 20) == 0) {
20464f89611Schristos 				ndiv = (freq * 3) / 60;
20564f89611Schristos 				phy |= SM(AR9280_AMODE_REFSEL, 3);
20664f89611Schristos 			}
20764f89611Schristos 			else if ((freq % 10) == 0) {
20864f89611Schristos 				ndiv = (freq * 6) / 60;
20964f89611Schristos 				phy |= SM(AR9280_AMODE_REFSEL, 2);
21064f89611Schristos 			}
21164f89611Schristos 		}
21264f89611Schristos 		if (ndiv != 0) {
21364f89611Schristos 			phy |= (ndiv & 0x1ff) << 17;
21464f89611Schristos 			phy |= (ndiv & ~0x1ff) * 2;
21564f89611Schristos 		}
21664f89611Schristos 		else {
21764f89611Schristos 			phy |= (freq << 15) / 15;
21864f89611Schristos 			phy |= AR9280_FRACMODE;
21964f89611Schristos 
22064f89611Schristos 			reg = AR_READ(sc, AR_AN_SYNTH9);
22164f89611Schristos 			reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
22264f89611Schristos 			AR_WRITE(sc, AR_AN_SYNTH9, reg);
22364f89611Schristos 		}
22464f89611Schristos 	}
22564f89611Schristos 	AR_WRITE_BARRIER(sc);
22664f89611Schristos 	DPRINTFN(DBG_RF, sc, "AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy);
22764f89611Schristos 	AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
22864f89611Schristos 	AR_WRITE_BARRIER(sc);
22964f89611Schristos 	return 0;
23064f89611Schristos }
23164f89611Schristos 
23264f89611Schristos Static void
ar9280_init_from_rom(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)23364f89611Schristos ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
23464f89611Schristos     struct ieee80211_channel *extc)
23564f89611Schristos {
23664f89611Schristos 	static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
23764f89611Schristos 	const struct ar5416_eeprom *eep = sc->sc_eep;
23864f89611Schristos 	const struct ar5416_modal_eep_header *modal;
23964f89611Schristos 	uint32_t reg, offset;
24064f89611Schristos 	uint8_t txRxAtten;
24164f89611Schristos 	int i;
24264f89611Schristos 
24364f89611Schristos 	modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
24464f89611Schristos 
24564f89611Schristos 	AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
24664f89611Schristos 
24764f89611Schristos 	for (i = 0; i < AR9280_MAX_CHAINS; i++) {
24864f89611Schristos 		if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
24964f89611Schristos 			offset = chainoffset[i];
25064f89611Schristos 		else
25164f89611Schristos 			offset = i * 0x1000;
25264f89611Schristos 
25364f89611Schristos 		AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
25464f89611Schristos 		    modal->antCtrlChain[i]);
25564f89611Schristos 
25664f89611Schristos 		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
25764f89611Schristos 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
25864f89611Schristos 		    modal->iqCalICh[i]);
25964f89611Schristos 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
26064f89611Schristos 		    modal->iqCalQCh[i]);
26164f89611Schristos 		AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
26264f89611Schristos 
26364f89611Schristos 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
26464f89611Schristos 			reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
26564f89611Schristos 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
26664f89611Schristos 			    modal->bswMargin[i]);
26764f89611Schristos 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
26864f89611Schristos 			    modal->bswAtten[i]);
26964f89611Schristos 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
27064f89611Schristos 			    modal->xatten2Margin[i]);
27164f89611Schristos 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
27264f89611Schristos 			    modal->xatten2Db[i]);
27364f89611Schristos 			AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
27464f89611Schristos 		}
27564f89611Schristos 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
27664f89611Schristos 			txRxAtten = modal->txRxAttenCh[i];
27764f89611Schristos 		else	/* Workaround for ROM versions < 14.3. */
27864f89611Schristos 			txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
27964f89611Schristos 		reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
28064f89611Schristos 		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
28164f89611Schristos 		    txRxAtten);
28264f89611Schristos 		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
28364f89611Schristos 		    modal->rxTxMarginCh[i]);
28464f89611Schristos 		AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
28564f89611Schristos 	}
28664f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
28764f89611Schristos 		reg = AR_READ(sc, AR_AN_RF2G1_CH0);
28864f89611Schristos 		reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
28964f89611Schristos 		reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
29064f89611Schristos 		AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
29164f89611Schristos 		AR_WRITE_BARRIER(sc);
29264f89611Schristos 		DELAY(100);
29364f89611Schristos 
29464f89611Schristos 		reg = AR_READ(sc, AR_AN_RF2G1_CH1);
29564f89611Schristos 		reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
29664f89611Schristos 		reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
29764f89611Schristos 		AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
29864f89611Schristos 		AR_WRITE_BARRIER(sc);
29964f89611Schristos 		DELAY(100);
30064f89611Schristos 	}
30164f89611Schristos 	else {
30264f89611Schristos 		reg = AR_READ(sc, AR_AN_RF5G1_CH0);
30364f89611Schristos 		reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
30464f89611Schristos 		reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
30564f89611Schristos 		AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
30664f89611Schristos 		AR_WRITE_BARRIER(sc);
30764f89611Schristos 		DELAY(100);
30864f89611Schristos 
30964f89611Schristos 		reg = AR_READ(sc, AR_AN_RF5G1_CH1);
31064f89611Schristos 		reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
31164f89611Schristos 		reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
31264f89611Schristos 		AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
31364f89611Schristos 		AR_WRITE_BARRIER(sc);
31464f89611Schristos 		DELAY(100);
31564f89611Schristos 	}
31664f89611Schristos 	reg = AR_READ(sc, AR_AN_TOP2);
31764f89611Schristos 	if ((sc->sc_flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
31864f89611Schristos 		/*
31964f89611Schristos 		 * Hardcode the output voltage of x-PA bias LDO to the
32064f89611Schristos 		 * lowest value for UB94 such that the card doesn't get
32164f89611Schristos 		 * too hot.
32264f89611Schristos 		 */
32364f89611Schristos 		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
32464f89611Schristos 	}
32564f89611Schristos 	else
32664f89611Schristos 		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
32764f89611Schristos 	if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
32864f89611Schristos 		reg |= AR_AN_TOP2_LOCALBIAS;
32964f89611Schristos 	else
33064f89611Schristos 		reg &= ~AR_AN_TOP2_LOCALBIAS;
33164f89611Schristos 	AR_WRITE(sc, AR_AN_TOP2, reg);
33264f89611Schristos 	AR_WRITE_BARRIER(sc);
33364f89611Schristos 	DELAY(100);
33464f89611Schristos 
33564f89611Schristos 	reg = AR_READ(sc, AR_PHY_XPA_CFG);
33664f89611Schristos 	if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
33764f89611Schristos 		reg |= AR_PHY_FORCE_XPA_CFG;
33864f89611Schristos 	else
33964f89611Schristos 		reg &= ~AR_PHY_FORCE_XPA_CFG;
34064f89611Schristos 	AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
34164f89611Schristos 
34264f89611Schristos 	reg = AR_READ(sc, AR_PHY_SETTLING);
34364f89611Schristos 	reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
34464f89611Schristos 	AR_WRITE(sc, AR_PHY_SETTLING, reg);
34564f89611Schristos 
34664f89611Schristos 	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
34764f89611Schristos 	reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
34864f89611Schristos 	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
34964f89611Schristos 
35064f89611Schristos 	reg =  SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
35164f89611Schristos 	reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
35264f89611Schristos 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
35364f89611Schristos 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
35464f89611Schristos 	AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
35564f89611Schristos 
35664f89611Schristos 	reg = AR_READ(sc, AR_PHY_RF_CTL3);
35764f89611Schristos 	reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
35864f89611Schristos 	AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
35964f89611Schristos 
36064f89611Schristos 	reg = AR_READ(sc, AR_PHY_CCA(0));
36164f89611Schristos 	reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
36264f89611Schristos 	AR_WRITE(sc, AR_PHY_CCA(0), reg);
36364f89611Schristos 
36464f89611Schristos 	reg = AR_READ(sc, AR_PHY_EXT_CCA0);
36564f89611Schristos 	reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
36664f89611Schristos 	AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
36764f89611Schristos 
36864f89611Schristos 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
36964f89611Schristos 		reg = AR_READ(sc, AR_PHY_RF_CTL2);
37064f89611Schristos 		reg = RW(reg, AR_PHY_TX_END_DATA_START,
37164f89611Schristos 		    modal->txFrameToDataStart);
37264f89611Schristos 		reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
37364f89611Schristos 		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
37464f89611Schristos 	}
37564f89611Schristos #ifndef IEEE80211_NO_HT
37664f89611Schristos 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
37764f89611Schristos 		/* Overwrite switch settling with HT-40 value. */
37864f89611Schristos 		reg = AR_READ(sc, AR_PHY_SETTLING);
37964f89611Schristos 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
38064f89611Schristos 		AR_WRITE(sc, AR_PHY_SETTLING, reg);
38164f89611Schristos 	}
38264f89611Schristos #endif
38364f89611Schristos 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
38464f89611Schristos 		reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
38564f89611Schristos 		reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
38664f89611Schristos 		    MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
38764f89611Schristos 		AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
38864f89611Schristos 	}
38964f89611Schristos 	if (AR_SREV_9280_20(sc) &&
39064f89611Schristos 	    sc->sc_eep_rev >= AR_EEP_MINOR_VER_20) {
39164f89611Schristos 		reg = AR_READ(sc, AR_AN_TOP1);
39264f89611Schristos 		if (eep->baseEepHeader.dacLpMode &&
39364f89611Schristos 		    (IEEE80211_IS_CHAN_2GHZ(c) ||
39464f89611Schristos 		     !eep->baseEepHeader.dacHiPwrMode_5G))
39564f89611Schristos 			reg |= AR_AN_TOP1_DACLPMODE;
39664f89611Schristos 		else
39764f89611Schristos 			reg &= ~AR_AN_TOP1_DACLPMODE;
39864f89611Schristos 		AR_WRITE(sc, AR_AN_TOP1, reg);
39964f89611Schristos 		AR_WRITE_BARRIER(sc);
40064f89611Schristos 		DELAY(100);
40164f89611Schristos 
40264f89611Schristos 		reg = AR_READ(sc, AR_PHY_FRAME_CTL);
40364f89611Schristos 		reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
40464f89611Schristos 		    MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
40564f89611Schristos 		AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
40664f89611Schristos 
40764f89611Schristos 		reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
40864f89611Schristos 		reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
40964f89611Schristos 		    eep->baseEepHeader.desiredScaleCCK);
41064f89611Schristos 		AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
41164f89611Schristos 	}
41264f89611Schristos 	AR_WRITE_BARRIER(sc);
41364f89611Schristos }
41464f89611Schristos 
41564f89611Schristos PUBLIC void
ar9280_olpc_get_pdadcs(struct athn_softc * sc,struct ieee80211_channel * c,int chain,uint8_t * boundaries,uint8_t * pdadcs,uint8_t * txgain)41664f89611Schristos ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
41764f89611Schristos     int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain)
41864f89611Schristos {
41964f89611Schristos 	const struct ar5416_eeprom *eep = sc->sc_eep;
42064f89611Schristos 	const struct ar_cal_data_per_freq_olpc *pierdata;
42164f89611Schristos 	const uint8_t *pierfreq;
42264f89611Schristos 	uint8_t fbin, pcdac, pwr, idx;
42364f89611Schristos 	int i, lo, hi, npiers;
42464f89611Schristos 
42564f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
42664f89611Schristos 		pierfreq = eep->calFreqPier2G;
42764f89611Schristos 		pierdata = (const struct ar_cal_data_per_freq_olpc *)
42864f89611Schristos 		    eep->calPierData2G[chain];
42964f89611Schristos 		npiers = AR5416_NUM_2G_CAL_PIERS;
43064f89611Schristos 	}
43164f89611Schristos 	else {
43264f89611Schristos 		pierfreq = eep->calFreqPier5G;
43364f89611Schristos 		pierdata = (const struct ar_cal_data_per_freq_olpc *)
43464f89611Schristos 		    eep->calPierData5G[chain];
43564f89611Schristos 		npiers = AR5416_NUM_5G_CAL_PIERS;
43664f89611Schristos 	}
43764f89611Schristos 	/* Find channel in ROM pier table. */
43864f89611Schristos 	fbin = athn_chan2fbin(c);
43964f89611Schristos 	athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
44064f89611Schristos 
44164f89611Schristos 	/* Get average. */
44264f89611Schristos 	pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
44364f89611Schristos 	pwr /= 2;	/* Convert to dB. */
44464f89611Schristos 
44564f89611Schristos 	/* Find power control digital-to-analog converter (PCDAC) value. */
44664f89611Schristos 	pcdac = pierdata[hi].pcdac[0][0];
44764f89611Schristos 	for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)
44864f89611Schristos 		if (pcdac <= sc->sc_tx_gain_tbl[idx])
44964f89611Schristos 			break;
45064f89611Schristos 	*txgain = idx;
45164f89611Schristos 
45264f89611Schristos 	DPRINTFN(DBG_RF, sc,
45364f89611Schristos 	    "fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n",
45464f89611Schristos 	    fbin, lo, hi, pwr, pcdac, idx);
45564f89611Schristos 
45664f89611Schristos 	/* Fill phase domain analog-to-digital converter (PDADC) table. */
45764f89611Schristos 	for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
45864f89611Schristos 		pdadcs[i] = (i < pwr) ? 0x00 : 0xff;
45964f89611Schristos 
46064f89611Schristos 	for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)
46164f89611Schristos 		boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;
46264f89611Schristos }
46364f89611Schristos 
46464f89611Schristos PUBLIC void
ar9280_spur_mitigate(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)46564f89611Schristos ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
46664f89611Schristos     struct ieee80211_channel *extc)
46764f89611Schristos {
46864f89611Schristos 	const struct ar_spur_chan *spurchans;
46964f89611Schristos 	int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
47064f89611Schristos 	int spur_off, range, i;
47164f89611Schristos 
47264f89611Schristos 	/* NB: Always clear. */
47364f89611Schristos 	AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
47464f89611Schristos 
47564f89611Schristos 	range = (extc != NULL) ? 19 : 10;
47664f89611Schristos 
47764f89611Schristos 	spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
47864f89611Schristos 	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
47964f89611Schristos 		spur = spurchans[i].spurChan;
48064f89611Schristos 		if (spur == AR_NO_SPUR)
48164f89611Schristos 			return;	/* XXX disable if it was enabled! */
48264f89611Schristos 		spur /= 10;
48364f89611Schristos 		if (IEEE80211_IS_CHAN_2GHZ(c))
48464f89611Schristos 			spur += AR_BASE_FREQ_2GHZ;
48564f89611Schristos 		else
48664f89611Schristos 			spur += AR_BASE_FREQ_5GHZ;
48764f89611Schristos 		spur -= c->ic_freq;
48864f89611Schristos 		if (abs(spur) < range)
48964f89611Schristos 			break;
49064f89611Schristos 	}
49164f89611Schristos 	if (i == AR_EEPROM_MODAL_SPURS)
49264f89611Schristos 		return;	/* XXX disable if it was enabled! */
49364f89611Schristos 	DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
49464f89611Schristos 
49564f89611Schristos 	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
49664f89611Schristos 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
49764f89611Schristos 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
49864f89611Schristos 	    AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
49964f89611Schristos 	    AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
50064f89611Schristos 
50164f89611Schristos 	AR_WRITE(sc, AR_PHY_SPUR_REG,
50264f89611Schristos 	    AR_PHY_SPUR_REG_MASK_RATE_CNTL |
50364f89611Schristos 	    AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
50464f89611Schristos 	    AR_PHY_SPUR_REG_MASK_RATE_SELECT |
50564f89611Schristos 	    AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
50664f89611Schristos 	    SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
50764f89611Schristos 
50864f89611Schristos #ifndef IEEE80211_NO_HT
50964f89611Schristos 	if (extc != NULL) {
51064f89611Schristos 		spur_delta_phase = (spur * 262144) / 10;
51164f89611Schristos 		if (spur < 0) {
51264f89611Schristos 			spur_subchannel_sd = 1;
51364f89611Schristos 			spur_off = spur + 10;
51464f89611Schristos 		}
51564f89611Schristos 		else {
51664f89611Schristos 			spur_subchannel_sd = 0;
51764f89611Schristos 			spur_off = spur - 10;
51864f89611Schristos 		}
51964f89611Schristos 	}
52064f89611Schristos 	else
52164f89611Schristos #endif
52264f89611Schristos 	{
52364f89611Schristos 		spur_delta_phase = (spur * 524288) / 10;
52464f89611Schristos 		spur_subchannel_sd = 0;
52564f89611Schristos 		spur_off = spur;
52664f89611Schristos 	}
52764f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c))
52864f89611Schristos 		spur_freq_sd = (spur_off * 2048) / 44;
52964f89611Schristos 	else
53064f89611Schristos 		spur_freq_sd = (spur_off * 2048) / 40;
53164f89611Schristos 
53264f89611Schristos 	AR_WRITE(sc, AR_PHY_TIMING11,
53364f89611Schristos 	    AR_PHY_TIMING11_USE_SPUR_IN_AGC |
53464f89611Schristos 	    SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
53564f89611Schristos 	    SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
53664f89611Schristos 
53764f89611Schristos 	AR_WRITE(sc, AR_PHY_SFCORR_EXT,
53864f89611Schristos 	    SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
53964f89611Schristos 	AR_WRITE_BARRIER(sc);
54064f89611Schristos 
54164f89611Schristos 	bin = spur * 320;
54264f89611Schristos 	ar5008_set_viterbi_mask(sc, bin);
54364f89611Schristos }
54464f89611Schristos 
54564f89611Schristos PUBLIC void
ar9280_reset_rx_gain(struct athn_softc * sc,struct ieee80211_channel * c)54664f89611Schristos ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
54764f89611Schristos {
54864f89611Schristos 	const struct athn_gain *prog = sc->sc_rx_gain;
54964f89611Schristos 	const uint32_t *pvals;
55064f89611Schristos 	int i;
55164f89611Schristos 
55264f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c))
55364f89611Schristos 		pvals = prog->vals_2g;
55464f89611Schristos 	else
55564f89611Schristos 		pvals = prog->vals_5g;
55664f89611Schristos 	for (i = 0; i < prog->nregs; i++)
55764f89611Schristos 		AR_WRITE(sc, prog->regs[i], pvals[i]);
55864f89611Schristos }
55964f89611Schristos 
56064f89611Schristos PUBLIC void
ar9280_reset_tx_gain(struct athn_softc * sc,struct ieee80211_channel * c)56164f89611Schristos ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
56264f89611Schristos {
56364f89611Schristos 	const struct athn_gain *prog = sc->sc_tx_gain;
56464f89611Schristos 	const uint32_t *pvals;
56564f89611Schristos 	int i;
56664f89611Schristos 
56764f89611Schristos 	if (IEEE80211_IS_CHAN_2GHZ(c))
56864f89611Schristos 		pvals = prog->vals_2g;
56964f89611Schristos 	else
57064f89611Schristos 		pvals = prog->vals_5g;
57164f89611Schristos 	for (i = 0; i < prog->nregs; i++)
57264f89611Schristos 		AR_WRITE(sc, prog->regs[i], pvals[i]);
57364f89611Schristos }
57464f89611Schristos 
57564f89611Schristos Static void
ar9280_olpc_init(struct athn_softc * sc)57664f89611Schristos ar9280_olpc_init(struct athn_softc *sc)
57764f89611Schristos {
57864f89611Schristos 	uint32_t reg;
57964f89611Schristos 	int i;
58064f89611Schristos 
58164f89611Schristos 	/* Save original Tx gain values. */
58264f89611Schristos 	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
58364f89611Schristos 		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
58464f89611Schristos 		sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
58564f89611Schristos 	}
58664f89611Schristos 	/* Initial Tx gain temperature compensation. */
58764f89611Schristos 	sc->sc_tcomp = 0;
58864f89611Schristos }
58964f89611Schristos 
59064f89611Schristos Static void
ar9280_olpc_temp_compensation(struct athn_softc * sc)59164f89611Schristos ar9280_olpc_temp_compensation(struct athn_softc *sc)
59264f89611Schristos {
59364f89611Schristos 	const struct ar5416_eeprom *eep = sc->sc_eep;
59464f89611Schristos 	int8_t pdadc, txgain, tcomp;
59564f89611Schristos 	uint32_t reg;
59664f89611Schristos 	int i;
59764f89611Schristos 
59864f89611Schristos 	reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
59964f89611Schristos 	pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
60064f89611Schristos 	DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
60164f89611Schristos 
60264f89611Schristos 	if (sc->sc_pdadc == 0 || pdadc == 0)
60364f89611Schristos 		return;	/* No frames transmitted yet. */
60464f89611Schristos 
60564f89611Schristos 	/* Compute Tx gain temperature compensation. */
60664f89611Schristos 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_20 &&
60764f89611Schristos 	    eep->baseEepHeader.dacHiPwrMode_5G)
60864f89611Schristos 		tcomp = (pdadc - sc->sc_pdadc + 4) / 8;
60964f89611Schristos 	else
61064f89611Schristos 		tcomp = (pdadc - sc->sc_pdadc + 5) / 10;
61164f89611Schristos 	DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
61264f89611Schristos 
61364f89611Schristos 	if (tcomp == sc->sc_tcomp)
61464f89611Schristos 		return;	/* Don't rewrite the same values. */
61564f89611Schristos 	sc->sc_tcomp = tcomp;
61664f89611Schristos 
61764f89611Schristos 	/* Adjust Tx gain values. */
61864f89611Schristos 	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
61964f89611Schristos 		txgain = sc->sc_tx_gain_tbl[i] - tcomp;
62064f89611Schristos 		if (txgain < 0)
62164f89611Schristos 			txgain = 0;
62264f89611Schristos 		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
62364f89611Schristos 		reg = RW(reg, AR_PHY_TX_GAIN, txgain);
62464f89611Schristos 		AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
62564f89611Schristos 	}
62664f89611Schristos 	AR_WRITE_BARRIER(sc);
62764f89611Schristos }
628