1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: aic79xxvar.h,v 1.6 2003/07/26 06:15:57 thorpej Exp $ 41 * 42 * //depot/aic7xxx/aic7xxx/aic79xx.h#84 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.8 2003/02/27 23:23:16 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 48 */ 49 50 #ifndef _AIC79XXVAR_H_ 51 #define _AIC79XXVAR_H_ 52 53 /* Register Definitions */ 54 #include <dev/microcode/aic7xxx/aic79xx_reg.h> 55 56 /************************* Forward Declarations *******************************/ 57 struct ahd_platform_data; 58 struct scb_platform_data; 59 60 /****************************** Useful Macros *********************************/ 61 #ifndef MAX 62 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 63 #endif 64 65 #ifndef MIN 66 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 67 #endif 68 69 #ifndef TRUE 70 #define TRUE 1 71 #endif 72 #ifndef FALSE 73 #define FALSE 0 74 #endif 75 76 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 77 78 #define ALL_CHANNELS '\0' 79 #define ALL_TARGETS_MASK 0xFFFF 80 #define INITIATOR_WILDCARD (~0) 81 #define SCB_LIST_NULL 0xFF00 82 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 83 #define QOUTFIFO_ENTRY_VALID 0x8000 84 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 85 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 86 87 #define SCSIID_TARGET(ahd, scsiid) \ 88 (((scsiid) & TID) >> TID_SHIFT) 89 #define SCSIID_OUR_ID(scsiid) \ 90 ((scsiid) & OID) 91 #define SCSIID_CHANNEL(ahd, scsiid) ('A') 92 #define SCB_IS_SCSIBUS_B(ahd, scb) (0) 93 #define SCB_GET_OUR_ID(scb) \ 94 SCSIID_OUR_ID((scb)->hscb->scsiid) 95 #define SCB_GET_TARGET(ahd, scb) \ 96 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 97 #define SCB_GET_CHANNEL(ahd, scb) \ 98 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 99 #define SCB_GET_LUN(scb) \ 100 ((scb)->hscb->lun) 101 #define SCB_GET_TARGET_OFFSET(ahd, scb) \ 102 SCB_GET_TARGET(ahd, scb) 103 #define SCB_GET_TARGET_MASK(ahd, scb) \ 104 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 105 #ifdef AHD_DEBUG 106 #define SCB_IS_SILENT(scb) \ 107 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 108 && (((scb)->flags & SCB_SILENT) != 0)) 109 #else 110 #define SCB_IS_SILENT(scb) \ 111 (((scb)->flags & SCB_SILENT) != 0) 112 #endif 113 /* 114 * TCLs have the following format: TTTTLLLLLLLL 115 */ 116 #define TCL_TARGET_OFFSET(tcl) \ 117 ((((tcl) >> 4) & TID) >> 4) 118 #define TCL_LUN(tcl) \ 119 (tcl & (AHD_NUM_LUNS - 1)) 120 #define BUILD_TCL(scsiid, lun) \ 121 ((lun) | (((scsiid) & TID) << 4)) 122 #define BUILD_TCL_RAW(target, channel, lun) \ 123 ((lun) | ((target) << 8)) 124 125 #define SCB_GET_TAG(scb) \ 126 ahd_le16toh(scb->hscb->tag) 127 128 #ifndef AHD_TARGET_MODE 129 #undef AHD_TMODE_ENABLE 130 #define AHD_TMODE_ENABLE 0 131 #endif 132 133 #define AHD_BUILD_COL_IDX(target, lun) \ 134 (((lun) << 4) | target) 135 136 #define AHD_GET_SCB_COL_IDX(ahd, scb) \ 137 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 138 139 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 140 do { \ 141 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 142 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 143 } while (0) 144 145 #define AHD_COPY_SCB_COL_IDX(dst, src) \ 146 do { \ 147 dst->hscb->scsiid = src->hscb->scsiid; \ 148 dst->hscb->lun = src->hscb->lun; \ 149 } while (0) 150 151 #define AHD_NEVER_COL_IDX 0xFFFF 152 153 /**************************** Driver Constants ********************************/ 154 /* 155 * The maximum number of supported targets. 156 */ 157 #define AHD_NUM_TARGETS 16 158 159 /* 160 * The maximum number of supported luns. 161 * The identify message only supports 64 luns in non-packetized transfers. 162 * You can have 2^64 luns when information unit transfers are enabled, 163 * but until we see a need to support that many, we support 256. 164 */ 165 #define AHD_NUM_LUNS_NONPKT 64 166 #define AHD_NUM_LUNS 256 167 168 /* 169 * The maximum transfer per S/G segment. 170 */ 171 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 172 173 /* 174 * The maximum amount of SCB storage in hardware on a controller. 175 * This value represents an upper bound. Due to software design, 176 * we may not be able to use this number. 177 */ 178 #define AHD_SCB_MAX 512 179 180 /* 181 * The maximum number of concurrent transactions supported per driver instance. 182 * Sequencer Control Blocks (SCBs) store per-transaction information. 183 */ 184 #define AHD_MAX_QUEUE AHD_SCB_MAX 185 186 /* 187 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 188 * in size and accomodate as many transactions as can be queued concurrently. 189 */ 190 #define AHD_QIN_SIZE AHD_MAX_QUEUE 191 #define AHD_QOUT_SIZE AHD_MAX_QUEUE 192 193 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 194 /* 195 * The maximum amount of SCB storage we allocate in host memory. 196 */ 197 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 198 199 /* 200 * Ring Buffer of incoming target commands. 201 * We allocate 256 to simplify the logic in the sequencer 202 * by using the natural wrap point of an 8bit counter. 203 */ 204 #define AHD_TMODE_CMDS 256 205 206 /* Reset line assertion time in us */ 207 #define AHD_BUSRESET_DELAY 25 208 209 /******************* Chip Characteristics/Operating Settings *****************/ 210 /* 211 * Chip Type 212 * The chip order is from least sophisticated to most sophisticated. 213 */ 214 typedef enum { 215 AHD_NONE = 0x0000, 216 AHD_CHIPID_MASK = 0x00FF, 217 AHD_AIC7901 = 0x0001, 218 AHD_AIC7902 = 0x0002, 219 AHD_AIC7901A = 0x0003, 220 AHD_PCI = 0x0100, /* Bus type PCI */ 221 AHD_PCIX = 0x0200, /* Bus type PCIX */ 222 AHD_BUS_MASK = 0x0F00 223 } ahd_chip; 224 225 /* 226 * Features available in each chip type. 227 */ 228 typedef enum { 229 AHD_FENONE = 0x00000, 230 AHD_WIDE = 0x00001,/* Wide Channel */ 231 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 232 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 233 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 234 AHD_RTI = 0x04000,/* Retained Training Support */ 235 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 236 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 237 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 238 AHD_AIC7901_FE = AHD_FENONE, 239 AHD_AIC7902_FE = AHD_MULTI_FUNC 240 } ahd_feature; 241 242 /* 243 * Bugs in the silicon that we work around in software. 244 */ 245 typedef enum { 246 AHD_BUGNONE = 0x0000, 247 /* 248 * Rev A hardware fails to update LAST/CURR/NEXTSCB 249 * correctly in certain packetized selection cases. 250 */ 251 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 252 /* The wrong SCB is accessed to check the abort pending bit. */ 253 AHD_ABORT_LQI_BUG = 0x0002, 254 /* Packetized bitbucket crosses packet boundaries. */ 255 AHD_PKT_BITBUCKET_BUG = 0x0004, 256 /* The selection timer runs twice as long as its setting. */ 257 AHD_LONG_SETIMO_BUG = 0x0008, 258 /* The Non-LQ CRC error status is delayed until phase change. */ 259 AHD_NLQICRC_DELAYED_BUG = 0x0010, 260 /* The chip must be reset for all outgoing bus resets. */ 261 AHD_SCSIRST_BUG = 0x0020, 262 /* Some PCIX fields must be saved and restored across chip reset. */ 263 AHD_PCIX_CHIPRST_BUG = 0x0040, 264 /* MMAPIO is not functional in PCI-X mode. */ 265 AHD_PCIX_MMAPIO_BUG = 0x0080, 266 /* Reads to SCBRAM fail to reset the discard timer. */ 267 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 268 /* Bug workarounds that can be disabled on non-PCIX busses. */ 269 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 270 | AHD_PCIX_MMAPIO_BUG 271 | AHD_PCIX_SCBRAM_RD_BUG, 272 /* 273 * LQOSTOP0 status set even for forced selections with ATN 274 * to perform non-packetized message delivery. 275 */ 276 AHD_LQO_ATNO_BUG = 0x0200, 277 /* FIFO auto-flush does not always trigger. */ 278 AHD_AUTOFLUSH_BUG = 0x0400, 279 /* The CLRLQO registers are not self-clearing. */ 280 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 281 /* The PACKETIZED status bit refers to the previous connection. */ 282 AHD_PKTIZED_STATUS_BUG = 0x1000, 283 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 284 AHD_PKT_LUN_BUG = 0x2000, 285 /* 286 * Only the FIFO allocated to the non-packetized connection may 287 * be in use during a non-packetzied connection. 288 */ 289 AHD_NONPACKFIFO_BUG = 0x4000, 290 /* 291 * Writing to a DFF SCBPTR register may fail if concurent with 292 * a hardware write to the other DFF SCBPTR register. This is 293 * not currently a concern in our sequencer since all chips with 294 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 295 * occur in non-packetized connections. 296 */ 297 AHD_MDFF_WSCBPTR_BUG = 0x8000, 298 /* SGHADDR updates are slow. */ 299 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 300 /* 301 * Changing the MODE_PTR coincident with an interrupt that 302 * switches to a different mode will cause the interrupt to 303 * be in the mode written outside of interrupt context. 304 */ 305 AHD_SET_MODE_BUG = 0x20000, 306 /* Non-packetized busfree revision does not work. */ 307 AHD_BUSFREEREV_BUG = 0x40000, 308 /* 309 * Paced transfers are indicated with a non-standard PPR 310 * option bit in the neg table, 160MHz is indicated by 311 * sync factor 0x7, and the offset if off by a factor of 2. 312 */ 313 AHD_PACED_NEGTABLE_BUG = 0x80000, 314 /* LQOOVERRUN false positives. */ 315 AHD_LQOOVERRUN_BUG = 0x100000, 316 /* 317 * Controller write to INTSTAT will lose to a host 318 * write to CLRINT. 319 */ 320 AHD_INTCOLLISION_BUG = 0x200000, 321 /* 322 * The GEM318 violates the SCSI spec by not waiting 323 * the mandated bus settle delay between phase changes 324 * in some situations. Some aic79xx chip revs. are more 325 * strict in this regard and will treat REQ assertions 326 * that fall within the bus settle delay window as 327 * glitches. This flag tells the firmware to tolerate 328 * early REQ assertions. 329 */ 330 AHD_EARLY_REQ_BUG = 0x400000 331 } ahd_bug; 332 333 /* 334 * Configuration specific settings. 335 * The driver determines these settings by probing the 336 * chip/controller's configuration. 337 */ 338 typedef enum { 339 AHD_FNONE = 0x00000, 340 AHD_PRIMARY_CHANNEL = 0x00003,/* 341 * The channel that should 342 * be probed first. 343 */ 344 AHD_USEDEFAULTS = 0x00004,/* 345 * For cards without an seeprom 346 * or a BIOS to initialize the chip's 347 * SRAM, we use the default target 348 * settings. 349 */ 350 AHD_SEQUENCER_DEBUG = 0x00008, 351 AHD_RESET_BUS_A = 0x00010, 352 AHD_EXTENDED_TRANS_A = 0x00020, 353 AHD_TERM_ENB_A = 0x00040, 354 AHD_SPCHK_ENB_A = 0x00080, 355 AHD_STPWLEVEL_A = 0x00100, 356 AHD_INITIATORROLE = 0x00200,/* 357 * Allow initiator operations on 358 * this controller. 359 */ 360 AHD_TARGETROLE = 0x00400,/* 361 * Allow target operations on this 362 * controller. 363 */ 364 AHD_RESOURCE_SHORTAGE = 0x00800, 365 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 366 AHD_INT50_SPEEDFLEX = 0x02000,/* 367 * Internal 50pin connector 368 * sits behind an aic3860 369 */ 370 AHD_BIOS_ENABLED = 0x04000, 371 AHD_ALL_INTERRUPTS = 0x08000, 372 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 373 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 374 AHD_CURRENT_SENSING = 0x40000, 375 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 376 AHD_HP_BOARD = 0x100000, 377 AHD_RESET_POLL_ACTIVE = 0x200000, 378 AHD_UPDATE_PEND_CMDS = 0x400000, 379 AHD_RUNNING_QOUTFIFO = 0x800000 380 } ahd_flag; 381 382 /************************* Hardware SCB Definition ***************************/ 383 384 /* 385 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 386 * consists of a "hardware SCB" mirroring the fields available on the card 387 * and additional information the kernel stores for each transaction. 388 * 389 * To minimize space utilization, a portion of the hardware scb stores 390 * different data during different portions of a SCSI transaction. 391 * As initialized by the host driver for the initiator role, this area 392 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 393 * the cdb has been presented to the target, this area serves to store 394 * residual transfer information and the SCSI status byte. 395 * For the target role, the contents of this area do not change, but 396 * still serve a different purpose than for the initiator role. See 397 * struct target_data for details. 398 */ 399 400 /* 401 * Status information embedded in the shared portion of 402 * an SCB after passing the cdb to the target. The kernel 403 * driver will only read this data for transactions that 404 * complete abnormally. 405 */ 406 struct initiator_status { 407 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 408 uint32_t residual_sgptr; /* The next S/G for this transfer */ 409 uint8_t scsi_status; /* Standard SCSI status byte */ 410 }; 411 412 struct target_status { 413 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 414 uint32_t residual_sgptr; /* The next S/G for this transfer */ 415 uint8_t scsi_status; /* SCSI status to give to initiator */ 416 uint8_t target_phases; /* Bitmap of phases to execute */ 417 uint8_t data_phase; /* Data-In or Data-Out */ 418 uint8_t initiator_tag; /* Initiator's transaction tag */ 419 }; 420 421 /* 422 * Initiator mode SCB shared data area. 423 * If the embedded CDB is 12 bytes or less, we embed 424 * the sense buffer address in the SCB. This allows 425 * us to retrieve sense information without interrupting 426 * the host in packetized mode. 427 */ 428 typedef uint32_t sense_addr_t; 429 #define MAX_CDB_LEN 16 430 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 431 union initiator_data { 432 struct { 433 uint64_t cdbptr; 434 uint8_t cdblen; 435 } cdb_from_host; 436 uint8_t cdb[MAX_CDB_LEN]; 437 struct { 438 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 439 sense_addr_t sense_addr; 440 } cdb_plus_saddr; 441 }; 442 443 /* 444 * Target mode version of the shared data SCB segment. 445 */ 446 struct target_data { 447 uint32_t spare[2]; 448 uint8_t scsi_status; /* SCSI status to give to initiator */ 449 uint8_t target_phases; /* Bitmap of phases to execute */ 450 uint8_t data_phase; /* Data-In or Data-Out */ 451 uint8_t initiator_tag; /* Initiator's transaction tag */ 452 }; 453 454 struct hardware_scb { 455 /*0*/ union { 456 union initiator_data idata; 457 struct target_data tdata; 458 struct initiator_status istatus; 459 struct target_status tstatus; 460 } shared_data; 461 /* 462 * A word about residuals. 463 * The scb is presented to the sequencer with the dataptr and datacnt 464 * fields initialized to the contents of the first S/G element to 465 * transfer. The sgptr field is initialized to the bus address for 466 * the S/G element that follows the first in the in core S/G array 467 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 468 * S/G entry for this transfer (single S/G element transfer with the 469 * first elements address and length preloaded in the dataptr/datacnt 470 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 471 * The SG_FULL_RESID flag ensures that the residual will be correctly 472 * noted even if no data transfers occur. Once the data phase is entered, 473 * the residual sgptr and datacnt are loaded from the sgptr and the 474 * datacnt fields. After each S/G element's dataptr and length are 475 * loaded into the hardware, the residual sgptr is advanced. After 476 * each S/G element is expired, its datacnt field is checked to see 477 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 478 * residual sg ptr and the transfer is considered complete. If the 479 * sequencer determines that there is a residual in the tranfer, or 480 * there is non-zero status, it will set the SG_STATUS_VALID flag in 481 * sgptr and DMA the scb back into host memory. To summarize: 482 * 483 * Sequencer: 484 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 485 * or residual_sgptr does not have SG_LIST_NULL set. 486 * 487 * o We are transfering the last segment if residual_datacnt has 488 * the SG_LAST_SEG flag set. 489 * 490 * Host: 491 * o A residual can only have occurred if a completed scb has the 492 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 493 * the residual_datacnt, and the residual_sgptr field will tell 494 * for sure. 495 * 496 * o residual_sgptr and sgptr refer to the "next" sg entry 497 * and so may point beyond the last valid sg entry for the 498 * transfer. 499 */ 500 #define SG_PTR_MASK 0xFFFFFFF8 501 /*16*/ uint16_t tag; 502 /*18*/ uint8_t cdb_len; 503 /*19*/ uint8_t task_management; 504 /*20*/ uint32_t next_hscb_busaddr; 505 /*24*/ uint64_t dataptr; 506 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 507 /*36*/ uint32_t sgptr; 508 /*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 509 /*41*/ uint8_t scsiid; /* 510 * Selection out Id 511 * Our Id (bits 0-3) Their ID (bits 4-7) 512 */ 513 /*42*/ uint8_t lun; 514 /*43*/ uint8_t task_attribute; 515 /*44*/ uint32_t hscb_busaddr; 516 /******* Long lun field only downloaded for full 8 byte lun support *******/ 517 /*48*/ uint8_t pkt_long_lun[8]; 518 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 519 /*56*/ uint8_t spare[8]; 520 }; 521 522 /************************ Kernel SCB Definitions ******************************/ 523 /* 524 * Some fields of the SCB are OS dependent. Here we collect the 525 * definitions for elements that all OS platforms need to include 526 * in there SCB definition. 527 */ 528 529 /* 530 * Definition of a scatter/gather element as transfered to the controller. 531 * The aic7xxx chips only support a 24bit length. We use the top byte of 532 * the length to store additional address bits and a flag to indicate 533 * that a given segment terminates the transfer. This gives us an 534 * addressable range of 512GB on machines with 64bit PCI or with chips 535 * that can support dual address cycles on 32bit PCI busses. 536 */ 537 struct ahd_dma_seg { 538 uint32_t addr; 539 uint32_t len; 540 #define AHD_DMA_LAST_SEG 0x80000000 541 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000 542 #define AHD_SG_LEN_MASK 0x00FFFFFF 543 }; 544 545 struct ahd_dma64_seg { 546 uint64_t addr; 547 uint32_t len; 548 uint32_t pad; 549 }; 550 551 struct map_node { 552 bus_dmamap_t dmamap; 553 bus_addr_t physaddr; 554 uint8_t *vaddr; 555 bus_dma_segment_t dmasegs; 556 int nseg; 557 SLIST_ENTRY(map_node) links; 558 }; 559 560 struct ahd_pci_busdata { 561 pci_chipset_tag_t pc; 562 pcitag_t tag; 563 u_int dev; 564 u_int func; 565 int pcix_off; 566 }; 567 568 /* 569 * The current state of this SCB. 570 */ 571 typedef enum { 572 SCB_FLAG_NONE = 0x00000, 573 SCB_TRANSMISSION_ERROR = 0x00001,/* 574 * We detected a parity or CRC 575 * error that has effected the 576 * payload of the command. This 577 * flag is checked when normal 578 * status is returned to catch 579 * the case of a target not 580 * responding to our attempt 581 * to report the error. 582 */ 583 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 584 * Another device was active 585 * during the first timeout for 586 * this SCB so we gave ourselves 587 * an additional timeout period 588 * in case it was hogging the 589 * bus. 590 */ 591 SCB_DEVICE_RESET = 0x00004, 592 SCB_SENSE = 0x00008, 593 SCB_CDB32_PTR = 0x00010, 594 SCB_RECOVERY_SCB = 0x00020, 595 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 596 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 597 SCB_ABORT = 0x00100, 598 SCB_ACTIVE = 0x00200, 599 SCB_TARGET_IMMEDIATE = 0x00400, 600 SCB_PACKETIZED = 0x00800, 601 SCB_EXPECT_PPR_BUSFREE = 0x01000, 602 SCB_PKT_SENSE = 0x02000, 603 SCB_CMDPHASE_ABORT = 0x04000, 604 SCB_ON_COL_LIST = 0x08000, 605 SCB_SILENT = 0x10000,/* 606 * Be quiet about transmission type 607 * errors. They are expected and we 608 * don't want to upset the user. This 609 * flag is typically used during DV. 610 */ 611 SCB_FREEZE_QUEUE = 0x20000, 612 SCB_REQUEUE = 0x40000, 613 } scb_flag; 614 615 struct scb { 616 struct hardware_scb *hscb; 617 union { 618 SLIST_ENTRY(scb) sle; 619 LIST_ENTRY(scb) le; 620 TAILQ_ENTRY(scb) tqe; 621 } links; 622 union { 623 SLIST_ENTRY(scb) sle; 624 LIST_ENTRY(scb) le; 625 TAILQ_ENTRY(scb) tqe; 626 } links2; 627 #define pending_links links2.le 628 #define collision_links links2.le 629 struct scb *col_scb; 630 struct scsipi_xfer *xs; 631 632 struct ahd_softc *ahd_softc; 633 scb_flag flags; 634 bus_dmamap_t dmamap; 635 struct scb_platform_data *platform_data; 636 struct map_node *hscb_map; 637 struct map_node *sg_map; 638 struct map_node *sense_map; 639 void *sg_list; 640 uint8_t *sense_data; 641 bus_addr_t sg_list_busaddr; 642 bus_addr_t sense_busaddr; 643 u_int sg_count;/* How full ahd_dma_seg is */ 644 #define AHD_MAX_LQ_CRC_ERRORS 5 645 u_int crc_retry_count; 646 }; 647 648 TAILQ_HEAD(scb_tailq, scb); 649 LIST_HEAD(scb_list, scb); 650 651 struct scb_data { 652 /* 653 * TAILQ of lists of free SCBs grouped by device 654 * collision domains. 655 */ 656 struct scb_tailq free_scbs; 657 658 /* 659 * Per-device lists of SCBs whose tag ID would collide 660 * with an already active tag on the device. 661 */ 662 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 663 664 /* 665 * SCBs that will not collide with any active device. 666 */ 667 struct scb_list any_dev_free_scb_list; 668 669 /* 670 * Mapping from tag to SCB. 671 */ 672 struct scb *scbindex[AHD_SCB_MAX]; 673 674 SLIST_HEAD(, map_node) hscb_maps; 675 SLIST_HEAD(, map_node) sg_maps; 676 SLIST_HEAD(, map_node) sense_maps; 677 678 int scbs_left; /* unallocated scbs in head map_node */ 679 int sgs_left; /* unallocated sgs in head map_node */ 680 int sense_left; /* unallocated sense in head map_node */ 681 uint16_t numscbs; 682 uint16_t maxhscbs; /* Number of SCBs on the card */ 683 uint8_t init_level; /* 684 * How far we've initialized 685 * this structure. 686 */ 687 }; 688 689 /************************ Target Mode Definitions *****************************/ 690 691 /* 692 * Connection desciptor for select-in requests in target mode. 693 */ 694 struct target_cmd { 695 uint8_t scsiid; /* Our ID and the initiator's ID */ 696 uint8_t identify; /* Identify message */ 697 uint8_t bytes[22]; /* 698 * Bytes contains any additional message 699 * bytes terminated by 0xFF. The remainder 700 * is the cdb to execute. 701 */ 702 uint8_t cmd_valid; /* 703 * When a command is complete, the firmware 704 * will set cmd_valid to all bits set. 705 * After the host has seen the command, 706 * the bits are cleared. This allows us 707 * to just peek at host memory to determine 708 * if more work is complete. cmd_valid is on 709 * an 8 byte boundary to simplify setting 710 * it on aic7880 hardware which only has 711 * limited direct access to the DMA FIFO. 712 */ 713 uint8_t pad[7]; 714 }; 715 716 /* 717 * Number of events we can buffer up if we run out 718 * of immediate notify ccbs. 719 */ 720 #define AHD_TMODE_EVENT_BUFFER_SIZE 8 721 struct ahd_tmode_event { 722 uint8_t initiator_id; 723 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 724 #define EVENT_TYPE_BUS_RESET 0xFF 725 uint8_t event_arg; 726 }; 727 728 /* 729 * Per enabled lun target mode state. 730 * As this state is directly influenced by the host OS'es target mode 731 * environment, we let the OS module define it. Forward declare the 732 * structure here so we can store arrays of them, etc. in OS neutral 733 * data structures. 734 */ 735 #ifdef AHD_TARGET_MODE 736 struct ahd_tmode_lstate { 737 struct cam_path *path; 738 struct ccb_hdr_slist accept_tios; 739 struct ccb_hdr_slist immed_notifies; 740 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 741 uint8_t event_r_idx; 742 uint8_t event_w_idx; 743 }; 744 #else 745 struct ahd_tmode_lstate; 746 #endif 747 748 /******************** Transfer Negotiation Datastructures *********************/ 749 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 750 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 751 #define AHD_TRANS_GOAL 0x04 /* Modify negontiation goal */ 752 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 753 #define AHD_PERIOD_10MHz 0x19 754 755 #define AHD_WIDTH_UNKNOWN 0xFF 756 #define AHD_PERIOD_UNKNOWN 0xFF 757 #define AHD_OFFSET_UNKNOWN 0xFF 758 #define AHD_PPR_OPTS_UNKNOWN 0xFF 759 760 /* 761 * Transfer Negotiation Information. 762 */ 763 struct ahd_transinfo { 764 uint8_t protocol_version; /* SCSI Revision level */ 765 uint8_t transport_version; /* SPI Revision level */ 766 uint8_t width; /* Bus width */ 767 uint8_t period; /* Sync rate factor */ 768 uint8_t offset; /* Sync offset */ 769 uint8_t ppr_options; /* Parallel Protocol Request options */ 770 }; 771 772 /* 773 * Per-initiator current, goal and user transfer negotiation information. */ 774 struct ahd_initiator_tinfo { 775 struct ahd_transinfo curr; 776 struct ahd_transinfo goal; 777 struct ahd_transinfo user; 778 }; 779 780 /* 781 * Per enabled target ID state. 782 * Pointers to lun target state as well as sync/wide negotiation information 783 * for each initiator<->target mapping. For the initiator role we pretend 784 * that we are the target and the targets are the initiators since the 785 * negotiation is the same regardless of role. 786 */ 787 struct ahd_tmode_tstate { 788 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 789 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 790 791 /* 792 * Per initiator state bitmasks. 793 */ 794 uint16_t auto_negotiate;/* Auto Negotiation Required */ 795 uint16_t discenable; /* Disconnection allowed */ 796 uint16_t tagenable; /* Tagged Queuing allowed */ 797 }; 798 799 /* 800 * Points of interest along the negotiated transfer scale. 801 */ 802 #define AHD_SYNCRATE_160 0x8 803 #define AHD_SYNCRATE_PACED 0x8 804 #define AHD_SYNCRATE_DT 0x9 805 #define AHD_SYNCRATE_ULTRA2 0xa 806 #define AHD_SYNCRATE_ULTRA 0xc 807 #define AHD_SYNCRATE_FAST 0x19 808 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 809 #define AHD_SYNCRATE_SYNC 0x32 810 #define AHD_SYNCRATE_MIN 0x60 811 #define AHD_SYNCRATE_ASYNC 0xFF 812 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 813 814 /* Safe and valid period for async negotiations. */ 815 #define AHD_ASYNC_XFER_PERIOD 0x44 816 817 /* 818 * In RevA, the synctable uses a 120MHz rate for the period 819 * factor 8 and 160MHz for the period factor 7. The 120MHz 820 * rate never made it into the official SCSI spec, so we must 821 * compensate when setting the negotiation table for Rev A 822 * parts. 823 */ 824 #define AHD_SYNCRATE_REVA_120 0x8 825 #define AHD_SYNCRATE_REVA_160 0x7 826 827 /***************************** Lookup Tables **********************************/ 828 /* 829 * Phase -> name and message out response 830 * to parity errors in each phase table. 831 */ 832 struct ahd_phase_table_entry { 833 uint8_t phase; 834 uint8_t mesg_out; /* Message response to parity errors */ 835 char *phasemsg; 836 }; 837 838 /************************** Serial EEPROM Format ******************************/ 839 840 struct seeprom_config { 841 /* 842 * Per SCSI ID Configuration Flags 843 */ 844 uint16_t device_flags[16]; /* words 0-15 */ 845 #define CFXFER 0x003F /* synchronous transfer rate */ 846 #define CFXFER_ASYNC 0x3F 847 #define CFQAS 0x0040 /* Negotiate QAS */ 848 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 849 #define CFSTART 0x0100 /* send start unit SCSI command */ 850 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 851 #define CFDISC 0x0400 /* enable disconnection */ 852 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 853 #define CFWIDEB 0x1000 /* wide bus device */ 854 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 855 856 /* 857 * BIOS Control Bits 858 */ 859 uint16_t bios_control; /* word 16 */ 860 #define CFSUPREM 0x0001 /* support all removeable drives */ 861 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 862 #define CFBIOSSTATE 0x000C /* BIOS Action State */ 863 #define CFBS_DISABLED 0x00 864 #define CFBS_ENABLED 0x04 865 #define CFBS_DISABLED_SCAN 0x08 866 #define CFENABLEDV 0x0010 /* Perform Domain Validation */ 867 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 868 #define CFSPARITY 0x0040 /* SCSI parity */ 869 #define CFEXTEND 0x0080 /* extended translation enabled */ 870 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 871 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 872 #define CFMSG_VERBOSE 0x0000 873 #define CFMSG_SILENT 0x0200 874 #define CFMSG_DIAG 0x0400 875 #define CFRESETB 0x0800 /* reset SCSI bus at boot */ 876 /* UNUSED 0xf000 */ 877 878 /* 879 * Host Adapter Control Bits 880 */ 881 uint16_t adapter_control; /* word 17 */ 882 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 883 #define CFSTERM 0x0002 /* SCSI low byte termination */ 884 #define CFWSTERM 0x0004 /* SCSI high byte termination */ 885 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 886 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 887 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 888 #define CFSTPWLEVEL 0x0040 /* Termination level control */ 889 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 890 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 891 #define CFCLUSTERENB 0x8000 /* Cluster Enable */ 892 893 /* 894 * Bus Release Time, Host Adapter ID 895 */ 896 uint16_t brtime_id; /* word 18 */ 897 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 898 /* UNUSED 0x00f0 */ 899 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 900 901 /* 902 * Maximum targets 903 */ 904 uint16_t max_targets; /* word 19 */ 905 #define CFMAXTARG 0x00ff /* maximum targets */ 906 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 907 #define CFBOOTID 0xf000 /* Target to boot from */ 908 uint16_t res_1[10]; /* words 20-29 */ 909 uint16_t signature; /* BIOS Signature */ 910 #define CFSIGNATURE 0x400 911 uint16_t checksum; /* word 31 */ 912 }; 913 914 /****************************** Flexport Logic ********************************/ 915 #define FLXADDR_TERMCTL 0x0 916 #define FLX_TERMCTL_ENSECHIGH 0x8 917 #define FLX_TERMCTL_ENSECLOW 0x4 918 #define FLX_TERMCTL_ENPRIHIGH 0x2 919 #define FLX_TERMCTL_ENPRILOW 0x1 920 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1 921 #define FLX_ROMSTAT_SEECFG 0xF0 922 #define FLX_ROMSTAT_EECFG 0x0F 923 #define FLX_ROMSTAT_SEE_93C66 0x00 924 #define FLX_ROMSTAT_SEE_NONE 0xF0 925 #define FLX_ROMSTAT_EE_512x8 0x0 926 #define FLX_ROMSTAT_EE_1MBx8 0x1 927 #define FLX_ROMSTAT_EE_2MBx8 0x2 928 #define FLX_ROMSTAT_EE_4MBx8 0x3 929 #define FLX_ROMSTAT_EE_16MBx8 0x4 930 #define CURSENSE_ENB 0x1 931 #define FLXADDR_FLEXSTAT 0x2 932 #define FLX_FSTAT_BUSY 0x1 933 #define FLXADDR_CURRENT_STAT 0x4 934 #define FLX_CSTAT_SEC_HIGH 0xC0 935 #define FLX_CSTAT_SEC_LOW 0x30 936 #define FLX_CSTAT_PRI_HIGH 0x0C 937 #define FLX_CSTAT_PRI_LOW 0x03 938 #define FLX_CSTAT_MASK 0x03 939 #define FLX_CSTAT_SHIFT 2 940 #define FLX_CSTAT_OKAY 0x0 941 #define FLX_CSTAT_OVER 0x1 942 #define FLX_CSTAT_UNDER 0x2 943 #define FLX_CSTAT_INVALID 0x3 944 945 int ahd_read_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int); 946 947 int ahd_write_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int); 948 int ahd_wait_seeprom(struct ahd_softc *); 949 int ahd_verify_cksum(struct seeprom_config *); 950 int ahd_acquire_seeprom(struct ahd_softc *); 951 void ahd_release_seeprom(struct ahd_softc *); 952 953 /**************************** Message Buffer *********************************/ 954 typedef enum { 955 MSG_FLAG_NONE = 0x00, 956 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 957 MSG_FLAG_IU_REQ_CHANGED = 0x02, 958 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 959 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 960 MSG_FLAG_PACKETIZED = 0x10 961 } ahd_msg_flags; 962 963 typedef enum { 964 MSG_TYPE_NONE = 0x00, 965 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 966 MSG_TYPE_INITIATOR_MSGIN = 0x02, 967 MSG_TYPE_TARGET_MSGOUT = 0x03, 968 MSG_TYPE_TARGET_MSGIN = 0x04 969 } ahd_msg_type; 970 971 typedef enum { 972 MSGLOOP_IN_PROG, 973 MSGLOOP_MSGCOMPLETE, 974 MSGLOOP_TERMINATED 975 } msg_loop_stat; 976 977 /*********************** Software Configuration Structure *********************/ 978 struct ahd_suspend_channel_state { 979 uint8_t scsiseq; 980 uint8_t sxfrctl0; 981 uint8_t sxfrctl1; 982 uint8_t simode0; 983 uint8_t simode1; 984 uint8_t seltimer; 985 uint8_t seqctl; 986 }; 987 988 struct ahd_suspend_state { 989 struct ahd_suspend_channel_state channel[2]; 990 uint8_t optionmode; 991 uint8_t dscommand0; 992 uint8_t dspcistatus; 993 /* hsmailbox */ 994 uint8_t crccontrol1; 995 uint8_t scbbaddr; 996 /* Host and sequencer SCB counts */ 997 uint8_t dff_thrsh; 998 uint8_t *scratch_ram; 999 uint8_t *btt; 1000 }; 1001 1002 typedef int (*ahd_bus_intr_t)(struct ahd_softc *); 1003 1004 typedef enum { 1005 AHD_MODE_DFF0, 1006 AHD_MODE_DFF1, 1007 AHD_MODE_CCHAN, 1008 AHD_MODE_SCSI, 1009 AHD_MODE_CFG, 1010 AHD_MODE_UNKNOWN 1011 } ahd_mode; 1012 1013 #define AHD_MK_MSK(x) (0x01 << (x)) 1014 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1015 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1016 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1017 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1018 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1019 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1020 #define AHD_MODE_ANY_MSK (~0) 1021 1022 typedef uint8_t ahd_mode_state; 1023 1024 typedef void ahd_callback_t (void *); 1025 1026 struct ahd_softc { 1027 struct device sc_dev; 1028 1029 struct scsipi_channel sc_channel; 1030 struct device * sc_child; 1031 struct scsipi_adapter sc_adapter; 1032 1033 bus_space_tag_t tags[2]; 1034 bus_space_handle_t bshs[2]; 1035 1036 scsipi_adapter_req_t sc_req; 1037 1038 void *shutdown_hook; 1039 struct scb_data scb_data; 1040 1041 struct hardware_scb *next_queued_hscb; 1042 struct map_node *next_queued_hscb_map; 1043 1044 /* 1045 * SCBs that have been sent to the controller 1046 */ 1047 LIST_HEAD(, scb) pending_scbs; 1048 1049 /* 1050 * Current register window mode information. 1051 */ 1052 ahd_mode dst_mode; 1053 ahd_mode src_mode; 1054 1055 /* 1056 * Saved register window mode information 1057 * used for restore on next unpause. 1058 */ 1059 ahd_mode saved_dst_mode; 1060 ahd_mode saved_src_mode; 1061 1062 /* 1063 * Platform specific data. 1064 */ 1065 struct ahd_platform_data *platform_data; 1066 1067 /* 1068 * Bus specific device information. 1069 */ 1070 ahd_bus_intr_t bus_intr; 1071 1072 /* 1073 * Target mode related state kept on a per enabled lun basis. 1074 * Targets that are not enabled will have null entries. 1075 * As an initiator, we keep one target entry for our initiator 1076 * ID to store our sync/wide transfer settings. 1077 */ 1078 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1079 1080 char inited_target[AHD_NUM_TARGETS]; 1081 1082 /* 1083 * The black hole device responsible for handling requests for 1084 * disabled luns on enabled targets. 1085 */ 1086 struct ahd_tmode_lstate *black_hole; 1087 1088 /* 1089 * Device instance currently on the bus awaiting a continue TIO 1090 * for a command that was not given the disconnect priveledge. 1091 */ 1092 struct ahd_tmode_lstate *pending_device; 1093 1094 /* 1095 * Timer handles for timer driven callbacks. 1096 */ 1097 ahd_timer_t reset_timer; 1098 ahd_timer_t stat_timer; 1099 1100 /* 1101 * Statistics. 1102 */ 1103 #define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1104 #define AHD_STAT_BUCKETS 4 1105 u_int cmdcmplt_bucket; 1106 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1107 uint32_t cmdcmplt_total; 1108 1109 /* 1110 * Card characteristics 1111 */ 1112 ahd_chip chip; 1113 ahd_feature features; 1114 ahd_bug bugs; 1115 ahd_flag flags; 1116 struct seeprom_config *seep_config; 1117 1118 /* Values to store in the SEQCTL register for pause and unpause */ 1119 uint8_t unpause; 1120 uint8_t pause; 1121 1122 /* Command Queues */ 1123 uint16_t qoutfifonext; 1124 uint16_t qoutfifonext_valid_tag; 1125 uint16_t qinfifonext; 1126 uint16_t qinfifo[AHD_SCB_MAX]; 1127 uint16_t *qoutfifo; 1128 1129 /* Critical Section Data */ 1130 struct cs *critical_sections; 1131 u_int num_critical_sections; 1132 1133 /* Buffer for handling packetized bitbucket. */ 1134 uint8_t *overrun_buf; 1135 1136 /* Links for chaining softcs */ 1137 TAILQ_ENTRY(ahd_softc) links; 1138 1139 /* Channel Names ('A', 'B', etc.) */ 1140 char channel; 1141 1142 /* Initiator Bus ID */ 1143 uint8_t our_id; 1144 1145 /* 1146 * Target incoming command FIFO. 1147 */ 1148 struct target_cmd *targetcmds; 1149 uint8_t tqinfifonext; 1150 1151 /* 1152 * Cached verson of the hs_mailbox so we can avoid 1153 * pausing the sequencer during mailbox updates. 1154 */ 1155 uint8_t hs_mailbox; 1156 1157 /* 1158 * Incoming and outgoing message handling. 1159 */ 1160 uint8_t send_msg_perror; 1161 ahd_msg_flags msg_flags; 1162 ahd_msg_type msg_type; 1163 uint8_t msgout_buf[12];/* Message we are sending */ 1164 uint8_t msgin_buf[12];/* Message we are receiving */ 1165 u_int msgout_len; /* Length of message to send */ 1166 u_int msgout_index; /* Current index in msgout */ 1167 u_int msgin_index; /* Current index in msgin */ 1168 1169 /* 1170 * Mapping information for data structures shared 1171 * between the sequencer and kernel. 1172 */ 1173 bus_dma_tag_t parent_dmat; 1174 bus_dma_tag_t shared_data_dmat; 1175 struct map_node shared_data_map; 1176 int shared_data_size; 1177 int sc_dmaflags; 1178 1179 /* Information saved through suspend/resume cycles */ 1180 struct ahd_suspend_state suspend_state; 1181 1182 /* Number of enabled target mode device on this card */ 1183 u_int enabled_luns; 1184 1185 /* Initialization level of this data structure */ 1186 u_int init_level; 1187 1188 /* PCI cacheline size. */ 1189 u_int pci_cachesize; 1190 1191 /* IO Cell Parameters */ 1192 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1193 1194 u_int stack_size; 1195 uint16_t *saved_stack; 1196 1197 /* Per-Unit descriptive information */ 1198 const char *description; 1199 const char *bus_description; 1200 char *name; 1201 int unit; 1202 1203 /* Selection Timer settings */ 1204 int seltime; 1205 1206 /* 1207 * Interrupt coalescing settings. 1208 */ 1209 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1210 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1211 #define AHD_INT_COALESCING_MAXCMDS_MAX 127 1212 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1213 #define AHD_INT_COALESCING_MINCMDS_MAX 127 1214 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1215 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1216 u_int int_coalescing_timer; 1217 u_int int_coalescing_maxcmds; 1218 u_int int_coalescing_mincmds; 1219 u_int int_coalescing_threshold; 1220 u_int int_coalescing_stop_threshold; 1221 1222 uint16_t user_discenable;/* Disconnection allowed */ 1223 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1224 1225 /* Adapter interrupt routine */ 1226 void* ih; 1227 struct ahd_pci_busdata *bus_data; 1228 }; 1229 1230 TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1231 extern struct ahd_softc_tailq ahd_tailq; 1232 1233 /*************************** IO Cell Configuration ****************************/ 1234 #define AHD_PRECOMP_SLEW_INDEX \ 1235 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1236 1237 #define AHD_AMPLITUDE_INDEX \ 1238 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1239 1240 #define AHD_SET_SLEWRATE(ahd, new_slew) \ 1241 do { \ 1242 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1243 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1244 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1245 } while (0) 1246 1247 #define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1248 do { \ 1249 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1250 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1251 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1252 } while (0) 1253 1254 #define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1255 do { \ 1256 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1257 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1258 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1259 } while (0) 1260 1261 /************************ Active Device Information ***************************/ 1262 typedef enum { 1263 ROLE_UNKNOWN, 1264 ROLE_INITIATOR, 1265 ROLE_TARGET 1266 } role_t; 1267 1268 struct ahd_devinfo { 1269 int our_scsiid; 1270 int target_offset; 1271 uint16_t target_mask; 1272 u_int target; 1273 u_int lun; 1274 char channel; 1275 role_t role; /* 1276 * Only guaranteed to be correct if not 1277 * in the busfree state. 1278 */ 1279 }; 1280 1281 /****************************** PCI Structures ********************************/ 1282 #define AHD_PCI_IOADDR0 PCI_MAPREG_START /* I/O BAR*/ 1283 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */ 1284 #define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */ 1285 1286 typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *); 1287 1288 struct ahd_pci_identity { 1289 uint64_t full_id; 1290 uint64_t id_mask; 1291 char *name; 1292 ahd_device_setup_t *setup; 1293 }; 1294 extern struct ahd_pci_identity ahd_pci_ident_table []; 1295 extern const u_int ahd_num_pci_devs; 1296 1297 /***************************** VL/EISA Declarations ***************************/ 1298 struct aic7770_identity { 1299 uint32_t full_id; 1300 uint32_t id_mask; 1301 char *name; 1302 ahd_device_setup_t *setup; 1303 }; 1304 extern struct aic7770_identity aic7770_ident_table []; 1305 extern const int ahd_num_aic7770_devs; 1306 1307 #define AHD_EISA_SLOT_OFFSET 0xc00 1308 #define AHD_EISA_IOSIZE 0x100 1309 1310 /*************************** Function Declarations ****************************/ 1311 /******************************************************************************/ 1312 void ahd_reset_cmds_pending(struct ahd_softc *); 1313 u_int ahd_find_busy_tcl(struct ahd_softc *, u_int); 1314 void ahd_busy_tcl(struct ahd_softc *, u_int, u_int); 1315 static __inline void ahd_unbusy_tcl(struct ahd_softc *, u_int); 1316 static __inline void 1317 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1318 { 1319 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1320 } 1321 1322 /***************************** PCI Front End *********************************/ 1323 const struct ahd_pci_identity *ahd_find_pci_device(pcireg_t, pcireg_t); /*ahd_dev_softc_t);*/ 1324 int ahd_pci_config(struct ahd_softc *, 1325 struct ahd_pci_identity *); 1326 int ahd_pci_test_register_access(struct ahd_softc *); 1327 1328 /************************** SCB and SCB queue management **********************/ 1329 int ahd_probe_scbs(struct ahd_softc *); 1330 void ahd_qinfifo_requeue_tail(struct ahd_softc *, 1331 struct scb *); 1332 int ahd_match_scb(struct ahd_softc *, struct scb *, 1333 int, char, int, u_int, role_t); 1334 1335 /****************************** Initialization ********************************/ 1336 /*struct ahd_softc *ahd_alloc(void *, char *);*/ 1337 int ahd_softc_init(struct ahd_softc *); 1338 void ahd_controller_info(struct ahd_softc *, char *); 1339 int ahd_init(struct ahd_softc *); 1340 int ahd_default_config(struct ahd_softc *); 1341 int ahd_parse_cfgdata(struct ahd_softc *, 1342 struct seeprom_config *); 1343 void ahd_intr_enable(struct ahd_softc *, int); 1344 void ahd_update_coalescing_values(struct ahd_softc *, 1345 u_int, u_int, u_int); 1346 void ahd_enable_coalescing(struct ahd_softc *, int); 1347 void ahd_pause_and_flushwork(struct ahd_softc *); 1348 int ahd_suspend(struct ahd_softc *); 1349 int ahd_resume(struct ahd_softc *); 1350 void ahd_set_unit(struct ahd_softc *, int); 1351 void ahd_set_name(struct ahd_softc *, char *); 1352 struct scb *ahd_get_scb(struct ahd_softc *, u_int); 1353 void ahd_free_scb(struct ahd_softc *, struct scb *); 1354 void ahd_alloc_scbs(struct ahd_softc *); 1355 void ahd_free(struct ahd_softc *); 1356 int ahd_reset(struct ahd_softc *); 1357 void ahd_shutdown(void *); 1358 int ahd_write_flexport(struct ahd_softc *, u_int, u_int); 1359 int ahd_read_flexport(struct ahd_softc *, u_int, uint8_t *); 1360 int ahd_wait_flexport(struct ahd_softc *); 1361 1362 /*************************** Interrupt Services *******************************/ 1363 int ahd_pci_intr(struct ahd_softc *); 1364 void ahd_clear_intstat(struct ahd_softc *); 1365 void ahd_flush_qoutfifo(struct ahd_softc *); 1366 void ahd_run_qoutfifo(struct ahd_softc *); 1367 void ahd_run_post_qoutfifo(struct ahd_softc *); 1368 #ifdef AHD_TARGET_MODE 1369 void ahd_run_tqinfifo(struct ahd_softc *, int); 1370 #endif 1371 void ahd_handle_hwerrint(struct ahd_softc *); 1372 void ahd_handle_seqint(struct ahd_softc *, u_int); 1373 void ahd_handle_scsiint(struct ahd_softc *, u_int); 1374 void ahd_clear_critical_section(struct ahd_softc *); 1375 1376 /***************************** Error Recovery *********************************/ 1377 typedef enum { 1378 SEARCH_COMPLETE, 1379 SEARCH_COUNT, 1380 SEARCH_REMOVE, 1381 SEARCH_PRINT 1382 } ahd_search_action; 1383 int ahd_search_qinfifo(struct ahd_softc *, int, char, int, 1384 u_int, role_t, uint32_t, ahd_search_action); 1385 int ahd_search_disc_list(struct ahd_softc *, int, char, 1386 int, u_int, int, int, int); 1387 void ahd_freeze_devq(struct ahd_softc *, struct scb *); 1388 int ahd_reset_channel(struct ahd_softc *, char, int); 1389 int ahd_abort_scbs(struct ahd_softc *, int, char, int, 1390 u_int, role_t, uint32_t); 1391 void ahd_restart(struct ahd_softc *); 1392 void ahd_clear_fifo(struct ahd_softc *, u_int); 1393 void ahd_handle_scb_status(struct ahd_softc *, struct scb *); 1394 void ahd_handle_scsi_status(struct ahd_softc *, 1395 struct scb *); 1396 void ahd_calc_residual(struct ahd_softc *, struct scb *); 1397 /*************************** Utility Functions ********************************/ 1398 struct ahd_phase_table_entry* 1399 ahd_lookup_phase_entry(int); 1400 void ahd_compile_devinfo(struct ahd_devinfo *, u_int, u_int, 1401 u_int, char, role_t); 1402 /************************** Transfer Negotiation ******************************/ 1403 void ahd_find_syncrate(struct ahd_softc *, u_int *, 1404 u_int *, u_int); 1405 void ahd_validate_offset(struct ahd_softc *, 1406 struct ahd_initiator_tinfo *, u_int, u_int *, 1407 int, role_t); 1408 void ahd_validate_width(struct ahd_softc *, 1409 struct ahd_initiator_tinfo *, u_int *, role_t); 1410 /* 1411 * Negotiation types. These are used to qualify if we should renegotiate 1412 * even if our goal and current transport parameters are identical. 1413 */ 1414 typedef enum { 1415 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1416 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1417 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1418 } ahd_neg_type; 1419 int ahd_update_neg_request(struct ahd_softc *, 1420 struct ahd_devinfo *, struct ahd_tmode_tstate *, 1421 struct ahd_initiator_tinfo *, ahd_neg_type); 1422 void ahd_set_width(struct ahd_softc *, 1423 struct ahd_devinfo *, u_int, u_int, int); 1424 void ahd_set_syncrate(struct ahd_softc *, 1425 struct ahd_devinfo *, u_int, u_int, u_int, 1426 u_int, int); 1427 typedef enum { 1428 AHD_QUEUE_NONE, 1429 AHD_QUEUE_BASIC, 1430 AHD_QUEUE_TAGGED 1431 } ahd_queue_alg; 1432 1433 void ahd_set_tags(struct ahd_softc *, struct ahd_devinfo *, 1434 ahd_queue_alg); 1435 1436 /**************************** Target Mode *************************************/ 1437 #ifdef AHD_TARGET_MODE 1438 void ahd_send_lstate_events(struct ahd_softc *, 1439 struct ahd_tmode_lstate *); 1440 void ahd_handle_en_lun(struct ahd_softc *, 1441 struct cam_sim *, union ccb *); 1442 cam_status ahd_find_tmode_devs(struct ahd_softc *, struct cam_sim *, 1443 union ccb *, struct ahd_tmode_tstate **, 1444 struct ahd_tmode_lstate **, int); 1445 #ifndef AHD_TMODE_ENABLE 1446 #define AHD_TMODE_ENABLE 0 1447 #endif 1448 #endif 1449 /******************************* Debug ***************************************/ 1450 #ifdef AHD_DEBUG 1451 extern uint32_t ahd_debug; 1452 #define AHD_SHOW_MISC 0x00001 1453 #define AHD_SHOW_SENSE 0x00002 1454 #define AHD_SHOW_RECOVERY 0x00004 1455 #define AHD_DUMP_SEEPROM 0x00008 1456 #define AHD_SHOW_TERMCTL 0x00010 1457 #define AHD_SHOW_MEMORY 0x00020 1458 #define AHD_SHOW_MESSAGES 0x00040 1459 #define AHD_SHOW_MODEPTR 0x00080 1460 #define AHD_SHOW_SELTO 0x00100 1461 #define AHD_SHOW_FIFOS 0x00200 1462 #define AHD_SHOW_QFULL 0x00400 1463 #define AHD_SHOW_DV 0x00800 1464 #define AHD_SHOW_MASKED_ERRORS 0x01000 1465 #define AHD_SHOW_QUEUE 0x02000 1466 #define AHD_SHOW_TQIN 0x04000 1467 #define AHD_SHOW_SG 0x08000 1468 #define AHD_SHOW_INT_COALESCING 0x10000 1469 #define AHD_DEBUG_SEQUENCER 0x20000 1470 #endif 1471 void ahd_print_scb(struct scb *); 1472 void ahd_print_devinfo(struct ahd_softc *, 1473 struct ahd_devinfo *); 1474 void ahd_dump_sglist(struct scb *); 1475 void ahd_dump_all_cards_state(void); 1476 void ahd_dump_card_state(struct ahd_softc *); 1477 int ahd_print_register(ahd_reg_parse_entry_t *, u_int, 1478 const char *, u_int, u_int, u_int *, u_int); 1479 void ahd_dump_scbs(struct ahd_softc *); 1480 #endif /* _AIC79XXVAR_H_ */ 1481