1 /* $NetBSD: aic6360.c,v 1.52 1996/12/10 21:27:51 thorpej Exp $ */ 2 3 #ifdef DDB 4 #define integrate 5 #else 6 #define integrate static inline 7 #endif 8 9 /* 10 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Charles M. Hannum. 23 * 4. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * Copyright (c) 1994 Jarle Greipsland 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 1. Redistributions of source code must retain the above copyright 33 * notice, this list of conditions and the following disclaimer. 34 * 2. Redistributions in binary form must reproduce the above copyright 35 * notice, this list of conditions and the following disclaimer in the 36 * documentation and/or other materials provided with the distribution. 37 * 3. The name of the author may not be used to endorse or promote products 38 * derived from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 41 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 42 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 43 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 44 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 45 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 48 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 49 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 50 * POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * Acknowledgements: Many of the algorithms used in this driver are 55 * inspired by the work of Julian Elischer (julian@tfs.com) and 56 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 57 */ 58 59 /* TODO list: 60 * 1) Get the DMA stuff working. 61 * 2) Get the iov/uio stuff working. Is this a good thing ??? 62 * 3) Get the synch stuff working. 63 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 64 */ 65 66 /* 67 * A few customizable items: 68 */ 69 70 /* Use doubleword transfers to/from SCSI chip. Note: This requires 71 * motherboard support. Basicly, some motherboard chipsets are able to 72 * split a 32 bit I/O operation into two 16 bit I/O operations, 73 * transparently to the processor. This speeds up some things, notably long 74 * data transfers. 75 */ 76 #define AIC_USE_DWORDS 0 77 78 /* Synchronous data transfers? */ 79 #define AIC_USE_SYNCHRONOUS 0 80 #define AIC_SYNC_REQ_ACK_OFS 8 81 82 /* Wide data transfers? */ 83 #define AIC_USE_WIDE 0 84 #define AIC_MAX_WIDTH 0 85 86 /* Max attempts made to transmit a message */ 87 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 88 89 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 90 #define AIC_USE_EISA_DMA 0 91 #define AIC_USE_ISA_DMA 0 92 93 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 94 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 95 96 /* Some spin loop parameters (essentially how long to wait some places) 97 * The problem(?) is that sometimes we expect either to be able to transmit a 98 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 99 * returning from the interrupt just to get yanked back for the next byte we 100 * may spin in the interrupt routine waiting for this byte to come. How long? 101 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 102 */ 103 #define AIC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 104 #define AIC_MSGOUT_SPIN 1 105 106 /* Include debug functions? At the end of this file there are a bunch of 107 * functions that will print out various information regarding queued SCSI 108 * commands, driver state and chip contents. You can call them from the 109 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 110 * kernel uses less memory) but you lose the debugging facilities. 111 */ 112 #define AIC_DEBUG 1 113 114 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 115 116 /* End of customizable parameters */ 117 118 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 119 #error "I said not yet! Start paying attention... grumble" 120 #endif 121 122 #include <sys/types.h> 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/errno.h> 127 #include <sys/ioctl.h> 128 #include <sys/device.h> 129 #include <sys/buf.h> 130 #include <sys/proc.h> 131 #include <sys/user.h> 132 #include <sys/queue.h> 133 134 #include <machine/intr.h> 135 #include <machine/pio.h> 136 137 #include <scsi/scsi_all.h> 138 #include <scsi/scsi_message.h> 139 #include <scsi/scsiconf.h> 140 141 #include <dev/isa/isavar.h> 142 143 /* Definitions, most of them has turned out to be unneccesary, but here they 144 * are anyway. 145 */ 146 147 /* AIC6360 definitions */ 148 #define SCSISEQ 0x00 /* SCSI sequence control */ 149 #define SXFRCTL0 0x01 /* SCSI transfer control 0 */ 150 #define SXFRCTL1 0x02 /* SCSI transfer control 1 */ 151 #define SCSISIG 0x03 /* SCSI signal in/out */ 152 #define SCSIRATE 0x04 /* SCSI rate control */ 153 #define SCSIID 0x05 /* SCSI ID */ 154 #define SELID 0x05 /* Selection/Reselection ID */ 155 #define SCSIDAT 0x06 /* SCSI Latched Data */ 156 #define SCSIBUS 0x07 /* SCSI Data Bus*/ 157 #define STCNT0 0x08 /* SCSI transfer count */ 158 #define STCNT1 0x09 159 #define STCNT2 0x0a 160 #define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */ 161 #define SSTAT0 0x0b /* SCSI interrupt status 0 */ 162 #define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */ 163 #define SSTAT1 0x0c /* SCSI status 1 */ 164 #define SSTAT2 0x0d /* SCSI status 2 */ 165 #define SCSITEST 0x0e /* SCSI test control */ 166 #define SSTAT3 0x0e /* SCSI status 3 */ 167 #define CLRSERR 0x0f /* Clear SCSI errors */ 168 #define SSTAT4 0x0f /* SCSI status 4 */ 169 #define SIMODE0 0x10 /* SCSI interrupt mode 0 */ 170 #define SIMODE1 0x11 /* SCSI interrupt mode 1 */ 171 #define DMACNTRL0 0x12 /* DMA control 0 */ 172 #define DMACNTRL1 0x13 /* DMA control 1 */ 173 #define DMASTAT 0x14 /* DMA status */ 174 #define FIFOSTAT 0x15 /* FIFO status */ 175 #define DMADATA 0x16 /* DMA data */ 176 #define DMADATAL 0x16 /* DMA data low byte */ 177 #define DMADATAH 0x17 /* DMA data high byte */ 178 #define BRSTCNTRL 0x18 /* Burst Control */ 179 #define DMADATALONG 0x18 180 #define PORTA 0x1a /* Port A */ 181 #define PORTB 0x1b /* Port B */ 182 #define REV 0x1c /* Revision (001 for 6360) */ 183 #define STACK 0x1d /* Stack */ 184 #define TEST 0x1e /* Test register */ 185 #define ID 0x1f /* ID register */ 186 187 #define IDSTRING "(C)1991ADAPTECAIC6360 " 188 189 /* What all the bits do */ 190 191 /* SCSISEQ */ 192 #define TEMODEO 0x80 193 #define ENSELO 0x40 194 #define ENSELI 0x20 195 #define ENRESELI 0x10 196 #define ENAUTOATNO 0x08 197 #define ENAUTOATNI 0x04 198 #define ENAUTOATNP 0x02 199 #define SCSIRSTO 0x01 200 201 /* SXFRCTL0 */ 202 #define SCSIEN 0x80 203 #define DMAEN 0x40 204 #define CHEN 0x20 205 #define CLRSTCNT 0x10 206 #define SPIOEN 0x08 207 #define CLRCH 0x02 208 209 /* SXFRCTL1 */ 210 #define BITBUCKET 0x80 211 #define SWRAPEN 0x40 212 #define ENSPCHK 0x20 213 #define STIMESEL1 0x10 214 #define STIMESEL0 0x08 215 #define STIMO_256ms 0x00 216 #define STIMO_128ms 0x08 217 #define STIMO_64ms 0x10 218 #define STIMO_32ms 0x18 219 #define ENSTIMER 0x04 220 #define BYTEALIGN 0x02 221 222 /* SCSISIG (in) */ 223 #define CDI 0x80 224 #define IOI 0x40 225 #define MSGI 0x20 226 #define ATNI 0x10 227 #define SELI 0x08 228 #define BSYI 0x04 229 #define REQI 0x02 230 #define ACKI 0x01 231 232 /* Important! The 3 most significant bits of this register, in initiator mode, 233 * represents the "expected" SCSI bus phase and can be used to trigger phase 234 * mismatch and phase change interrupts. But more important: If there is a 235 * phase mismatch the chip will not transfer any data! This is actually a nice 236 * feature as it gives us a bit more control over what is happening when we are 237 * bursting data (in) through the FIFOs and the phase suddenly changes from 238 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 239 * proper phase to be set in this register instead of dumping the bits into the 240 * FIFOs. 241 */ 242 /* SCSISIG (out) */ 243 #define CDO 0x80 244 #define IOO 0x40 245 #define MSGO 0x20 246 #define ATNO 0x10 247 #define SELO 0x08 248 #define BSYO 0x04 249 #define REQO 0x02 250 #define ACKO 0x01 251 252 /* Information transfer phases */ 253 #define PH_DATAOUT (0) 254 #define PH_DATAIN (IOI) 255 #define PH_CMD (CDI) 256 #define PH_STAT (CDI | IOI) 257 #define PH_MSGOUT (MSGI | CDI) 258 #define PH_MSGIN (MSGI | CDI | IOI) 259 260 #define PH_MASK (MSGI | CDI | IOI) 261 262 #define PH_INVALID 0xff 263 264 /* SCSIRATE */ 265 #define SXFR2 0x40 266 #define SXFR1 0x20 267 #define SXFR0 0x10 268 #define SOFS3 0x08 269 #define SOFS2 0x04 270 #define SOFS1 0x02 271 #define SOFS0 0x01 272 273 /* SCSI ID */ 274 #define OID2 0x40 275 #define OID1 0x20 276 #define OID0 0x10 277 #define OID_S 4 /* shift value */ 278 #define TID2 0x04 279 #define TID1 0x02 280 #define TID0 0x01 281 #define SCSI_ID_MASK 0x7 282 283 /* SCSI selection/reselection ID (both target *and* initiator) */ 284 #define SELID7 0x80 285 #define SELID6 0x40 286 #define SELID5 0x20 287 #define SELID4 0x10 288 #define SELID3 0x08 289 #define SELID2 0x04 290 #define SELID1 0x02 291 #define SELID0 0x01 292 293 /* CLRSINT0 Clears what? (interrupt and/or status bit) */ 294 #define SETSDONE 0x80 295 #define CLRSELDO 0x40 /* I */ 296 #define CLRSELDI 0x20 /* I+ */ 297 #define CLRSELINGO 0x10 /* I */ 298 #define CLRSWRAP 0x08 /* I+S */ 299 #define CLRSDONE 0x04 /* I+S */ 300 #define CLRSPIORDY 0x02 /* I */ 301 #define CLRDMADONE 0x01 /* I */ 302 303 /* SSTAT0 Howto clear */ 304 #define TARGET 0x80 305 #define SELDO 0x40 /* Selfclearing */ 306 #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ 307 #define SELINGO 0x10 /* Selfclearing */ 308 #define SWRAP 0x08 /* CLRSWAP */ 309 #define SDONE 0x04 /* Not used in initiator mode */ 310 #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ 311 #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ 312 313 /* CLRSINT1 Clears what? */ 314 #define CLRSELTIMO 0x80 /* I+S */ 315 #define CLRATNO 0x40 316 #define CLRSCSIRSTI 0x20 /* I+S */ 317 #define CLRBUSFREE 0x08 /* I+S */ 318 #define CLRSCSIPERR 0x04 /* I+S */ 319 #define CLRPHASECHG 0x02 /* I+S */ 320 #define CLRREQINIT 0x01 /* I+S */ 321 322 /* SSTAT1 How to clear? When set?*/ 323 #define SELTO 0x80 /* C select out timeout */ 324 #define ATNTARG 0x40 /* Not used in initiator mode */ 325 #define SCSIRSTI 0x20 /* C RST asserted */ 326 #define PHASEMIS 0x10 /* Selfclearing */ 327 #define BUSFREE 0x08 /* C bus free condition */ 328 #define SCSIPERR 0x04 /* C parity error on inbound data */ 329 #define PHASECHG 0x02 /* C phase in SCSISIG doesn't match */ 330 #define REQINIT 0x01 /* C or ACK asserting edge of REQ */ 331 332 /* SSTAT2 */ 333 #define SOFFSET 0x20 334 #define SEMPTY 0x10 335 #define SFULL 0x08 336 #define SFCNT2 0x04 337 #define SFCNT1 0x02 338 #define SFCNT0 0x01 339 340 /* SCSITEST */ 341 #define SCTESTU 0x08 342 #define SCTESTD 0x04 343 #define STCTEST 0x01 344 345 /* SSTAT3 */ 346 #define SCSICNT3 0x80 347 #define SCSICNT2 0x40 348 #define SCSICNT1 0x20 349 #define SCSICNT0 0x10 350 #define OFFCNT3 0x08 351 #define OFFCNT2 0x04 352 #define OFFCNT1 0x02 353 #define OFFCNT0 0x01 354 355 /* CLRSERR */ 356 #define CLRSYNCERR 0x04 357 #define CLRFWERR 0x02 358 #define CLRFRERR 0x01 359 360 /* SSTAT4 */ 361 #define SYNCERR 0x04 362 #define FWERR 0x02 363 #define FRERR 0x01 364 365 /* SIMODE0 */ 366 #define ENSELDO 0x40 367 #define ENSELDI 0x20 368 #define ENSELINGO 0x10 369 #define ENSWRAP 0x08 370 #define ENSDONE 0x04 371 #define ENSPIORDY 0x02 372 #define ENDMADONE 0x01 373 374 /* SIMODE1 */ 375 #define ENSELTIMO 0x80 376 #define ENATNTARG 0x40 377 #define ENSCSIRST 0x20 378 #define ENPHASEMIS 0x10 379 #define ENBUSFREE 0x08 380 #define ENSCSIPERR 0x04 381 #define ENPHASECHG 0x02 382 #define ENREQINIT 0x01 383 384 /* DMACNTRL0 */ 385 #define ENDMA 0x80 386 #define B8MODE 0x40 387 #define DMA 0x20 388 #define DWORDPIO 0x10 389 #define WRITE 0x08 390 #define INTEN 0x04 391 #define RSTFIFO 0x02 392 #define SWINT 0x01 393 394 /* DMACNTRL1 */ 395 #define PWRDWN 0x80 396 #define ENSTK32 0x40 397 #define STK4 0x10 398 #define STK3 0x08 399 #define STK2 0x04 400 #define STK1 0x02 401 #define STK0 0x01 402 403 /* DMASTAT */ 404 #define ATDONE 0x80 405 #define WORDRDY 0x40 406 #define INTSTAT 0x20 407 #define DFIFOFULL 0x10 408 #define DFIFOEMP 0x08 409 #define DFIFOHF 0x04 410 #define DWORDRDY 0x02 411 412 /* BRSTCNTRL */ 413 #define BON3 0x80 414 #define BON2 0x40 415 #define BON1 0x20 416 #define BON0 0x10 417 #define BOFF3 0x08 418 #define BOFF2 0x04 419 #define BOFF1 0x02 420 #define BOFF0 0x01 421 422 /* TEST */ 423 #define BOFFTMR 0x40 424 #define BONTMR 0x20 425 #define STCNTH 0x10 426 #define STCNTM 0x08 427 #define STCNTL 0x04 428 #define SCSIBLK 0x02 429 #define DMABLK 0x01 430 431 #ifndef DDB 432 #define Debugger() panic("should call debugger here (aic6360.c)") 433 #endif /* ! DDB */ 434 435 typedef u_long physaddr; 436 typedef u_long physlen; 437 438 struct aic_dma_seg { 439 physaddr seg_addr; 440 physlen seg_len; 441 }; 442 443 #define AIC_NSEG 16 444 445 /* 446 * ACB. Holds additional information for each SCSI command Comments: We 447 * need a separate scsi command block because we may need to overwrite it 448 * with a request sense command. Basicly, we refrain from fiddling with 449 * the scsi_xfer struct (except do the expected updating of return values). 450 * We'll generally update: xs->{flags,resid,error,sense,status} and 451 * occasionally xs->retries. 452 */ 453 struct aic_acb { 454 struct scsi_generic scsi_cmd; 455 int scsi_cmd_length; 456 u_char *data_addr; /* Saved data pointer */ 457 int data_length; /* Residue */ 458 459 u_char target_stat; /* SCSI status byte */ 460 461 #ifdef notdef 462 struct aic_dma_seg dma[AIC_NSEG]; /* Physical addresses+len */ 463 #endif 464 465 TAILQ_ENTRY(aic_acb) chain; 466 struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */ 467 int flags; 468 #define ACB_ALLOC 0x01 469 #define ACB_NEXUS 0x02 470 #define ACB_SENSE 0x04 471 #define ACB_ABORT 0x40 472 #define ACB_RESET 0x80 473 int timeout; 474 }; 475 476 /* 477 * Some info about each (possible) target on the SCSI bus. This should 478 * probably have been a "per target+lunit" structure, but we'll leave it at 479 * this for now. 480 */ 481 struct aic_tinfo { 482 int cmds; /* #commands processed */ 483 int dconns; /* #disconnects */ 484 int touts; /* #timeouts */ 485 int perrs; /* #parity errors */ 486 int senses; /* #request sense commands sent */ 487 ushort lubusy; /* What local units/subr. are busy? */ 488 u_char flags; 489 #define DO_SYNC 0x01 /* (Re)Negotiate synchronous options */ 490 #define DO_WIDE 0x02 /* (Re)Negotiate wide options */ 491 u_char period; /* Period suggestion */ 492 u_char offset; /* Offset suggestion */ 493 u_char width; /* Width suggestion */ 494 } tinfo_t; 495 496 struct aic_softc { 497 struct device sc_dev; 498 struct isadev sc_id; 499 void *sc_ih; 500 501 int sc_iobase; 502 int sc_irq, sc_drq; 503 504 struct scsi_link sc_link; /* prototype for subdevs */ 505 506 TAILQ_HEAD(, aic_acb) free_list, ready_list, nexus_list; 507 struct aic_acb *sc_nexus; /* current command */ 508 struct aic_acb sc_acb[8]; 509 struct aic_tinfo sc_tinfo[8]; 510 511 /* Data about the current nexus (updated for every cmd switch) */ 512 u_char *sc_dp; /* Current data pointer */ 513 size_t sc_dleft; /* Data bytes left to transfer */ 514 u_char *sc_cp; /* Current command pointer */ 515 size_t sc_cleft; /* Command bytes left to transfer */ 516 517 /* Adapter state */ 518 u_char sc_phase; /* Current bus phase */ 519 u_char sc_prevphase; /* Previous bus phase */ 520 u_char sc_state; /* State applicable to the adapter */ 521 #define AIC_INIT 0 522 #define AIC_IDLE 1 523 #define AIC_SELECTING 2 /* SCSI command is arbiting */ 524 #define AIC_RESELECTED 3 /* Has been reselected */ 525 #define AIC_CONNECTED 4 /* Actively using the SCSI bus */ 526 #define AIC_DISCONNECT 5 /* MSG_DISCONNECT received */ 527 #define AIC_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */ 528 #define AIC_CLEANING 7 529 u_char sc_flags; 530 #define AIC_DROP_MSGIN 0x01 /* Discard all msgs (parity err detected) */ 531 #define AIC_ABORTING 0x02 /* Bailing out */ 532 #define AIC_DOINGDMA 0x04 /* The FIFO data path is active! */ 533 u_char sc_selid; /* Reselection ID */ 534 535 /* Message stuff */ 536 u_char sc_msgpriq; /* Messages we want to send */ 537 u_char sc_msgoutq; /* Messages sent during last MESSAGE OUT */ 538 u_char sc_lastmsg; /* Message last transmitted */ 539 u_char sc_currmsg; /* Message currently ready to transmit */ 540 #define SEND_DEV_RESET 0x01 541 #define SEND_PARITY_ERROR 0x02 542 #define SEND_INIT_DET_ERR 0x04 543 #define SEND_REJECT 0x08 544 #define SEND_IDENTIFY 0x10 545 #define SEND_ABORT 0x20 546 #define SEND_SDTR 0x40 547 #define SEND_WDTR 0x80 548 #define AIC_MAX_MSG_LEN 8 549 u_char sc_omess[AIC_MAX_MSG_LEN]; 550 u_char *sc_omp; /* Outgoing message pointer */ 551 u_char sc_imess[AIC_MAX_MSG_LEN]; 552 u_char *sc_imp; /* Incoming message pointer */ 553 554 /* Hardware stuff */ 555 int sc_initiator; /* Our scsi id */ 556 int sc_freq; /* Clock frequency in MHz */ 557 int sc_minsync; /* Minimum sync period / 4 */ 558 int sc_maxsync; /* Maximum sync period / 4 */ 559 }; 560 561 #if AIC_DEBUG 562 #define AIC_SHOWACBS 0x01 563 #define AIC_SHOWINTS 0x02 564 #define AIC_SHOWCMDS 0x04 565 #define AIC_SHOWMISC 0x08 566 #define AIC_SHOWTRACE 0x10 567 #define AIC_SHOWSTART 0x20 568 #define AIC_DOBREAK 0x40 569 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 570 #define AIC_PRINT(b, s) do {if ((aic_debug & (b)) != 0) printf s;} while (0) 571 #define AIC_BREAK() do {if ((aic_debug & AIC_DOBREAK) != 0) Debugger();} while (0) 572 #define AIC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 573 #else 574 #define AIC_PRINT(b, s) 575 #define AIC_BREAK() 576 #define AIC_ASSERT(x) 577 #endif 578 579 #define AIC_ACBS(s) AIC_PRINT(AIC_SHOWACBS, s) 580 #define AIC_INTS(s) AIC_PRINT(AIC_SHOWINTS, s) 581 #define AIC_CMDS(s) AIC_PRINT(AIC_SHOWCMDS, s) 582 #define AIC_MISC(s) AIC_PRINT(AIC_SHOWMISC, s) 583 #define AIC_TRACE(s) AIC_PRINT(AIC_SHOWTRACE, s) 584 #define AIC_START(s) AIC_PRINT(AIC_SHOWSTART, s) 585 586 int aicprobe __P((struct device *, void *, void *)); 587 void aicattach __P((struct device *, struct device *, void *)); 588 void aic_minphys __P((struct buf *)); 589 int aicintr __P((void *)); 590 void aic_init __P((struct aic_softc *)); 591 void aic_done __P((struct aic_softc *, struct aic_acb *)); 592 void aic_dequeue __P((struct aic_softc *, struct aic_acb *)); 593 int aic_scsi_cmd __P((struct scsi_xfer *)); 594 int aic_poll __P((struct aic_softc *, struct scsi_xfer *, int)); 595 integrate void aic_sched_msgout __P((struct aic_softc *, u_char)); 596 integrate void aic_setsync __P((struct aic_softc *, struct aic_tinfo *)); 597 void aic_select __P((struct aic_softc *, struct aic_acb *)); 598 void aic_timeout __P((void *)); 599 int aic_find __P((struct aic_softc *)); 600 void aic_sched __P((struct aic_softc *)); 601 void aic_scsi_reset __P((struct aic_softc *)); 602 void aic_reset __P((struct aic_softc *)); 603 void aic_free_acb __P((struct aic_softc *, struct aic_acb *, int)); 604 struct aic_acb* aic_get_acb __P((struct aic_softc *, int)); 605 int aic_reselect __P((struct aic_softc *, int)); 606 void aic_sense __P((struct aic_softc *, struct aic_acb *)); 607 void aic_msgin __P((struct aic_softc *)); 608 void aic_abort __P((struct aic_softc *, struct aic_acb *)); 609 void aic_msgout __P((struct aic_softc *)); 610 int aic_dataout_pio __P((struct aic_softc *, u_char *, int)); 611 int aic_datain_pio __P((struct aic_softc *, u_char *, int)); 612 #if AIC_DEBUG 613 void aic_print_acb __P((struct aic_acb *)); 614 void aic_dump_driver __P((struct aic_softc *)); 615 void aic_dump6360 __P((struct aic_softc *)); 616 void aic_show_scsi_cmd __P((struct aic_acb *)); 617 void aic_print_active_acb __P((void)); 618 #endif 619 620 struct cfattach aic_ca = { 621 sizeof(struct aic_softc), aicprobe, aicattach 622 }; 623 624 struct cfdriver aic_cd = { 625 NULL, "aic", DV_DULL 626 }; 627 628 struct scsi_adapter aic_switch = { 629 aic_scsi_cmd, 630 aic_minphys, 631 0, 632 0, 633 }; 634 635 struct scsi_device aic_dev = { 636 NULL, /* Use default error handler */ 637 NULL, /* have a queue, served by this */ 638 NULL, /* have no async handler */ 639 NULL, /* Use default 'done' routine */ 640 }; 641 642 /* 643 * INITIALIZATION ROUTINES (probe, attach ++) 644 */ 645 646 /* 647 * aicprobe: probe for AIC6360 SCSI-controller 648 * returns non-zero value if a controller is found. 649 */ 650 int 651 aicprobe(parent, match, aux) 652 struct device *parent; 653 void *match, *aux; 654 { 655 struct aic_softc *sc = match; 656 struct isa_attach_args *ia = aux; 657 658 #ifdef NEWCONFIG 659 if (ia->ia_iobase == IOBASEUNK) 660 return 0; 661 #endif 662 663 sc->sc_iobase = ia->ia_iobase; 664 if (aic_find(sc) != 0) 665 return 0; 666 667 #ifdef NEWCONFIG 668 if (ia->ia_irq != IRQUNK) { 669 if (ia->ia_irq != sc->sc_irq) { 670 printf("%s: irq mismatch; kernel configured %d != board configured %d\n", 671 sc->sc_dev.dv_xname, ia->ia_irq, sc->sc_irq); 672 return 0; 673 } 674 } else 675 ia->ia_irq = sc->sc_irq; 676 677 if (ia->ia_drq != DRQUNK) { 678 if (ia->ia_drq != sc->sc_drq) { 679 printf("%s: drq mismatch; kernel configured %d != board configured %d\n", 680 sc->sc_dev.dv_xname, ia->ia_drq, sc->sc_drq); 681 return 0; 682 } 683 } else 684 ia->ia_drq = sc->sc_drq; 685 #endif 686 687 ia->ia_msize = 0; 688 ia->ia_iosize = 0x20; 689 return 1; 690 } 691 692 /* Do the real search-for-device. 693 * Prerequisite: sc->sc_iobase should be set to the proper value 694 */ 695 int 696 aic_find(sc) 697 struct aic_softc *sc; 698 { 699 int iobase = sc->sc_iobase; 700 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 701 int i; 702 703 /* Remove aic6360 from possible powerdown mode */ 704 outb(iobase + DMACNTRL0, 0); 705 706 /* Thanks to mark@aggregate.com for the new method for detecting 707 * whether the chip is present or not. Bonus: may also work for 708 * the AIC-6260! 709 */ 710 AIC_TRACE(("aic: probing for aic-chip at port 0x%x\n", 711 sc->sc_iobase)); 712 /* 713 * Linux also init's the stack to 1-16 and then clears it, 714 * 6260's don't appear to have an ID reg - mpg 715 */ 716 /* Push the sequence 0,1,..,15 on the stack */ 717 #define STSIZE 16 718 outb(iobase + DMACNTRL1, 0); /* Reset stack pointer */ 719 for (i = 0; i < STSIZE; i++) 720 outb(iobase + STACK, i); 721 722 /* See if we can pull out the same sequence */ 723 outb(iobase + DMACNTRL1, 0); 724 for (i = 0; i < STSIZE && inb(iobase + STACK) == i; i++) 725 ; 726 if (i != STSIZE) { 727 AIC_START(("STACK futzed at %d.\n", i)); 728 return ENXIO; 729 } 730 731 /* See if we can pull the id string out of the ID register, 732 * now only used for informational purposes. 733 */ 734 bzero(chip_id, sizeof(chip_id)); 735 insb(iobase + ID, chip_id, sizeof(IDSTRING)-1); 736 AIC_START(("AIC found at 0x%x ", sc->sc_iobase)); 737 AIC_START(("ID: %s ",chip_id)); 738 AIC_START(("chip revision %d\n",(int)inb(iobase + REV))); 739 740 sc->sc_initiator = 7; 741 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 742 743 /* 744 * These are the bounds of the sync period, based on the frequency of 745 * the chip's clock input and the size and offset of the sync period 746 * register. 747 * 748 * For a 20Mhz clock, this gives us 25, or 100nS, or 10MB/s, as a 749 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 750 * minimum transfer rate. 751 */ 752 sc->sc_minsync = (2 * 250) / sc->sc_freq; 753 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 754 755 return 0; 756 } 757 758 /* 759 * Attach the AIC6360, fill out some high and low level data structures 760 */ 761 void 762 aicattach(parent, self, aux) 763 struct device *parent, *self; 764 void *aux; 765 { 766 struct isa_attach_args *ia = aux; 767 struct aic_softc *sc = (void *)self; 768 769 AIC_TRACE(("aicattach ")); 770 sc->sc_state = AIC_INIT; 771 aic_init(sc); /* Init chip and driver */ 772 773 /* 774 * Fill in the prototype scsi_link 775 */ 776 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 777 sc->sc_link.adapter_softc = sc; 778 sc->sc_link.adapter_target = sc->sc_initiator; 779 sc->sc_link.adapter = &aic_switch; 780 sc->sc_link.device = &aic_dev; 781 sc->sc_link.openings = 2; 782 sc->sc_link.max_target = 7; 783 784 printf("\n"); 785 786 #ifdef NEWCONFIG 787 isa_establish(&sc->sc_id, &sc->sc_dev); 788 #endif 789 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 790 IPL_BIO, aicintr, sc); 791 792 config_found(self, &sc->sc_link, scsiprint); 793 } 794 795 796 /* Initialize AIC6360 chip itself 797 * The following conditions should hold: 798 * aicprobe should have succeeded, i.e. the iobase address in aic_softc must 799 * be valid. 800 */ 801 void 802 aic_reset(sc) 803 struct aic_softc *sc; 804 { 805 int iobase = sc->sc_iobase; 806 807 outb(iobase + SCSITEST, 0); /* Doc. recommends to clear these two */ 808 outb(iobase + TEST, 0); /* registers before operations commence */ 809 810 /* Reset SCSI-FIFO and abort any transfers */ 811 outb(iobase + SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 812 813 /* Reset DMA-FIFO */ 814 outb(iobase + DMACNTRL0, RSTFIFO); 815 outb(iobase + DMACNTRL1, 0); 816 817 outb(iobase + SCSISEQ, 0); /* Disable all selection features */ 818 outb(iobase + SXFRCTL1, 0); 819 820 outb(iobase + SIMODE0, 0x00); /* Disable some interrupts */ 821 outb(iobase + CLRSINT0, 0x7f); /* Clear a slew of interrupts */ 822 823 outb(iobase + SIMODE1, 0x00); /* Disable some more interrupts */ 824 outb(iobase + CLRSINT1, 0xef); /* Clear another slew of interrupts */ 825 826 outb(iobase + SCSIRATE, 0); /* Disable synchronous transfers */ 827 828 outb(iobase + CLRSERR, 0x07); /* Haven't seen ant errors (yet) */ 829 830 outb(iobase + SCSIID, sc->sc_initiator << OID_S); /* Set our SCSI-ID */ 831 outb(iobase + BRSTCNTRL, EISA_BRST_TIM); 832 } 833 834 /* Pull the SCSI RST line for 500 us */ 835 void 836 aic_scsi_reset(sc) 837 struct aic_softc *sc; 838 { 839 int iobase = sc->sc_iobase; 840 841 outb(iobase + SCSISEQ, SCSIRSTO); 842 delay(500); 843 outb(iobase + SCSISEQ, 0); 844 delay(50); 845 } 846 847 /* 848 * Initialize aic SCSI driver. 849 */ 850 void 851 aic_init(sc) 852 struct aic_softc *sc; 853 { 854 int iobase = sc->sc_iobase; 855 struct aic_acb *acb; 856 int r; 857 858 aic_reset(sc); 859 aic_scsi_reset(sc); 860 aic_reset(sc); 861 862 if (sc->sc_state == AIC_INIT) { 863 /* First time through; initialize. */ 864 TAILQ_INIT(&sc->ready_list); 865 TAILQ_INIT(&sc->nexus_list); 866 TAILQ_INIT(&sc->free_list); 867 sc->sc_nexus = NULL; 868 acb = sc->sc_acb; 869 bzero(acb, sizeof(sc->sc_acb)); 870 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 871 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 872 acb++; 873 } 874 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 875 } else { 876 /* Cancel any active commands. */ 877 sc->sc_state = AIC_CLEANING; 878 if ((acb = sc->sc_nexus) != NULL) { 879 acb->xs->error = XS_DRIVER_STUFFUP; 880 untimeout(aic_timeout, acb); 881 aic_done(sc, acb); 882 } 883 while ((acb = sc->nexus_list.tqh_first) != NULL) { 884 acb->xs->error = XS_DRIVER_STUFFUP; 885 untimeout(aic_timeout, acb); 886 aic_done(sc, acb); 887 } 888 } 889 890 sc->sc_prevphase = PH_INVALID; 891 for (r = 0; r < 8; r++) { 892 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 893 894 ti->flags = 0; 895 #if AIC_USE_SYNCHRONOUS 896 ti->flags |= DO_SYNC; 897 ti->period = sc->sc_minsync; 898 ti->offset = AIC_SYNC_REQ_ACK_OFS; 899 #else 900 ti->period = ti->offset = 0; 901 #endif 902 #if AIC_USE_WIDE 903 ti->flags |= DO_WIDE; 904 ti->width = AIC_MAX_WIDTH; 905 #else 906 ti->width = 0; 907 #endif 908 } 909 910 sc->sc_state = AIC_IDLE; 911 outb(iobase + DMACNTRL0, INTEN); 912 } 913 914 void 915 aic_free_acb(sc, acb, flags) 916 struct aic_softc *sc; 917 struct aic_acb *acb; 918 int flags; 919 { 920 int s; 921 922 s = splbio(); 923 924 acb->flags = 0; 925 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 926 927 /* 928 * If there were none, wake anybody waiting for one to come free, 929 * starting with queued entries. 930 */ 931 if (acb->chain.tqe_next == 0) 932 wakeup(&sc->free_list); 933 934 splx(s); 935 } 936 937 struct aic_acb * 938 aic_get_acb(sc, flags) 939 struct aic_softc *sc; 940 int flags; 941 { 942 struct aic_acb *acb; 943 int s; 944 945 s = splbio(); 946 947 while ((acb = sc->free_list.tqh_first) == NULL && 948 (flags & SCSI_NOSLEEP) == 0) 949 tsleep(&sc->free_list, PRIBIO, "aicacb", 0); 950 if (acb) { 951 TAILQ_REMOVE(&sc->free_list, acb, chain); 952 acb->flags |= ACB_ALLOC; 953 } 954 955 splx(s); 956 return acb; 957 } 958 959 /* 960 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 961 */ 962 963 /* 964 * Expected sequence: 965 * 1) Command inserted into ready list 966 * 2) Command selected for execution 967 * 3) Command won arbitration and has selected target device 968 * 4) Send message out (identify message, eventually also sync.negotiations) 969 * 5) Send command 970 * 5a) Receive disconnect message, disconnect. 971 * 5b) Reselected by target 972 * 5c) Receive identify message from target. 973 * 6) Send or receive data 974 * 7) Receive status 975 * 8) Receive message (command complete etc.) 976 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 977 * Repeat 2-8 (no disconnects please...) 978 */ 979 980 /* 981 * Start a SCSI-command 982 * This function is called by the higher level SCSI-driver to queue/run 983 * SCSI-commands. 984 */ 985 int 986 aic_scsi_cmd(xs) 987 struct scsi_xfer *xs; 988 { 989 struct scsi_link *sc_link = xs->sc_link; 990 struct aic_softc *sc = sc_link->adapter_softc; 991 struct aic_acb *acb; 992 int s, flags; 993 994 AIC_TRACE(("aic_scsi_cmd ")); 995 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 996 sc_link->target)); 997 998 flags = xs->flags; 999 if ((acb = aic_get_acb(sc, flags)) == NULL) { 1000 xs->error = XS_DRIVER_STUFFUP; 1001 return TRY_AGAIN_LATER; 1002 } 1003 1004 /* Initialize acb */ 1005 acb->xs = xs; 1006 acb->timeout = xs->timeout; 1007 1008 if (xs->flags & SCSI_RESET) { 1009 acb->flags |= ACB_RESET; 1010 acb->scsi_cmd_length = 0; 1011 acb->data_length = 0; 1012 } else { 1013 bcopy(xs->cmd, &acb->scsi_cmd, xs->cmdlen); 1014 acb->scsi_cmd_length = xs->cmdlen; 1015 acb->data_addr = xs->data; 1016 acb->data_length = xs->datalen; 1017 } 1018 acb->target_stat = 0; 1019 1020 s = splbio(); 1021 1022 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 1023 if (sc->sc_state == AIC_IDLE) 1024 aic_sched(sc); 1025 1026 splx(s); 1027 1028 if ((flags & SCSI_POLL) == 0) 1029 return SUCCESSFULLY_QUEUED; 1030 1031 /* Not allowed to use interrupts, use polling instead */ 1032 if (aic_poll(sc, xs, acb->timeout)) { 1033 aic_timeout(acb); 1034 if (aic_poll(sc, xs, acb->timeout)) 1035 aic_timeout(acb); 1036 } 1037 return COMPLETE; 1038 } 1039 1040 /* 1041 * Adjust transfer size in buffer structure 1042 */ 1043 void 1044 aic_minphys(bp) 1045 struct buf *bp; 1046 { 1047 1048 AIC_TRACE(("aic_minphys ")); 1049 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 1050 bp->b_bcount = (AIC_NSEG << PGSHIFT); 1051 minphys(bp); 1052 } 1053 1054 /* 1055 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 1056 */ 1057 int 1058 aic_poll(sc, xs, count) 1059 struct aic_softc *sc; 1060 struct scsi_xfer *xs; 1061 int count; 1062 { 1063 int iobase = sc->sc_iobase; 1064 1065 AIC_TRACE(("aic_poll ")); 1066 while (count) { 1067 /* 1068 * If we had interrupts enabled, would we 1069 * have got an interrupt? 1070 */ 1071 if ((inb(iobase + DMASTAT) & INTSTAT) != 0) 1072 aicintr(sc); 1073 if ((xs->flags & ITSDONE) != 0) 1074 return 0; 1075 delay(1000); 1076 count--; 1077 } 1078 return 1; 1079 } 1080 1081 /* 1082 * LOW LEVEL SCSI UTILITIES 1083 */ 1084 1085 integrate void 1086 aic_sched_msgout(sc, m) 1087 struct aic_softc *sc; 1088 u_char m; 1089 { 1090 int iobase = sc->sc_iobase; 1091 1092 if (sc->sc_msgpriq == 0) 1093 outb(iobase + SCSISIG, sc->sc_phase | ATNO); 1094 sc->sc_msgpriq |= m; 1095 } 1096 1097 /* 1098 * Set synchronous transfer offset and period. 1099 */ 1100 integrate void 1101 aic_setsync(sc, ti) 1102 struct aic_softc *sc; 1103 struct aic_tinfo *ti; 1104 { 1105 #if AIC_USE_SYNCHRONOUS 1106 int iobase = sc->sc_iobase; 1107 1108 if (ti->offset != 0) 1109 outb(iobase + SCSIRATE, 1110 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 1111 else 1112 outb(iobase + SCSIRATE, 0); 1113 #endif 1114 } 1115 1116 /* 1117 * Start a selection. This is used by aic_sched() to select an idle target, 1118 * and by aic_done() to immediately reselect a target to get sense information. 1119 */ 1120 void 1121 aic_select(sc, acb) 1122 struct aic_softc *sc; 1123 struct aic_acb *acb; 1124 { 1125 struct scsi_link *sc_link = acb->xs->sc_link; 1126 int target = sc_link->target; 1127 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 1128 int iobase = sc->sc_iobase; 1129 1130 outb(iobase + SCSIID, sc->sc_initiator << OID_S | target); 1131 aic_setsync(sc, ti); 1132 outb(iobase + SXFRCTL1, STIMO_256ms | ENSTIMER); 1133 1134 /* Always enable reselections. */ 1135 outb(iobase + SIMODE0, ENSELDI | ENSELDO); 1136 outb(iobase + SIMODE1, ENSCSIRST | ENSELTIMO); 1137 outb(iobase + SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 1138 1139 sc->sc_state = AIC_SELECTING; 1140 } 1141 1142 int 1143 aic_reselect(sc, message) 1144 struct aic_softc *sc; 1145 int message; 1146 { 1147 u_char selid, target, lun; 1148 struct aic_acb *acb; 1149 struct scsi_link *sc_link; 1150 struct aic_tinfo *ti; 1151 1152 /* 1153 * The SCSI chip made a snapshot of the data bus while the reselection 1154 * was being negotiated. This enables us to determine which target did 1155 * the reselect. 1156 */ 1157 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 1158 if (selid & (selid - 1)) { 1159 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 1160 sc->sc_dev.dv_xname, selid); 1161 AIC_BREAK(); 1162 goto reset; 1163 } 1164 1165 /* Search wait queue for disconnected cmd 1166 * The list should be short, so I haven't bothered with 1167 * any more sophisticated structures than a simple 1168 * singly linked list. 1169 */ 1170 target = ffs(selid) - 1; 1171 lun = message & 0x07; 1172 for (acb = sc->nexus_list.tqh_first; acb != NULL; 1173 acb = acb->chain.tqe_next) { 1174 sc_link = acb->xs->sc_link; 1175 if (sc_link->target == target && sc_link->lun == lun) 1176 break; 1177 } 1178 if (acb == NULL) { 1179 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 1180 sc->sc_dev.dv_xname, target, lun); 1181 AIC_BREAK(); 1182 goto abort; 1183 } 1184 1185 /* Make this nexus active again. */ 1186 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1187 sc->sc_state = AIC_CONNECTED; 1188 sc->sc_nexus = acb; 1189 ti = &sc->sc_tinfo[target]; 1190 ti->lubusy |= (1 << lun); 1191 aic_setsync(sc, ti); 1192 1193 if (acb->flags & ACB_RESET) 1194 aic_sched_msgout(sc, SEND_DEV_RESET); 1195 else if (acb->flags & ACB_ABORT) 1196 aic_sched_msgout(sc, SEND_ABORT); 1197 1198 /* Do an implicit RESTORE POINTERS. */ 1199 sc->sc_dp = acb->data_addr; 1200 sc->sc_dleft = acb->data_length; 1201 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1202 sc->sc_cleft = acb->scsi_cmd_length; 1203 1204 return (0); 1205 1206 reset: 1207 aic_sched_msgout(sc, SEND_DEV_RESET); 1208 return (1); 1209 1210 abort: 1211 aic_sched_msgout(sc, SEND_ABORT); 1212 return (1); 1213 } 1214 1215 /* 1216 * Schedule a SCSI operation. This has now been pulled out of the interrupt 1217 * handler so that we may call it from aic_scsi_cmd and aic_done. This may 1218 * save us an unecessary interrupt just to get things going. Should only be 1219 * called when state == AIC_IDLE and at bio pl. 1220 */ 1221 void 1222 aic_sched(sc) 1223 register struct aic_softc *sc; 1224 { 1225 struct aic_acb *acb; 1226 struct scsi_link *sc_link; 1227 struct aic_tinfo *ti; 1228 int iobase = sc->sc_iobase; 1229 1230 /* 1231 * Find first acb in ready queue that is for a target/lunit pair that 1232 * is not busy. 1233 */ 1234 outb(iobase + CLRSINT1, CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 1235 for (acb = sc->ready_list.tqh_first; acb != NULL; 1236 acb = acb->chain.tqe_next) { 1237 sc_link = acb->xs->sc_link; 1238 ti = &sc->sc_tinfo[sc_link->target]; 1239 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 1240 AIC_MISC(("selecting %d:%d ", 1241 sc_link->target, sc_link->lun)); 1242 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1243 sc->sc_nexus = acb; 1244 aic_select(sc, acb); 1245 return; 1246 } else 1247 AIC_MISC(("%d:%d busy\n", 1248 sc_link->target, sc_link->lun)); 1249 } 1250 AIC_MISC(("idle ")); 1251 /* Nothing to start; just enable reselections and wait. */ 1252 outb(iobase + SIMODE0, ENSELDI); 1253 outb(iobase + SIMODE1, ENSCSIRST); 1254 outb(iobase + SCSISEQ, ENRESELI); 1255 } 1256 1257 void 1258 aic_sense(sc, acb) 1259 struct aic_softc *sc; 1260 struct aic_acb *acb; 1261 { 1262 struct scsi_xfer *xs = acb->xs; 1263 struct scsi_link *sc_link = xs->sc_link; 1264 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1265 struct scsi_sense *ss = (void *)&acb->scsi_cmd; 1266 1267 AIC_MISC(("requesting sense ")); 1268 /* Next, setup a request sense command block */ 1269 bzero(ss, sizeof(*ss)); 1270 ss->opcode = REQUEST_SENSE; 1271 ss->byte2 = sc_link->lun << 5; 1272 ss->length = sizeof(struct scsi_sense_data); 1273 acb->scsi_cmd_length = sizeof(*ss); 1274 acb->data_addr = (char *)&xs->sense; 1275 acb->data_length = sizeof(struct scsi_sense_data); 1276 acb->flags |= ACB_SENSE; 1277 ti->senses++; 1278 if (acb->flags & ACB_NEXUS) 1279 ti->lubusy &= ~(1 << sc_link->lun); 1280 if (acb == sc->sc_nexus) { 1281 aic_select(sc, acb); 1282 } else { 1283 aic_dequeue(sc, acb); 1284 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1285 if (sc->sc_state == AIC_IDLE) 1286 aic_sched(sc); 1287 } 1288 } 1289 1290 /* 1291 * POST PROCESSING OF SCSI_CMD (usually current) 1292 */ 1293 void 1294 aic_done(sc, acb) 1295 struct aic_softc *sc; 1296 struct aic_acb *acb; 1297 { 1298 struct scsi_xfer *xs = acb->xs; 1299 struct scsi_link *sc_link = xs->sc_link; 1300 struct aic_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 1301 1302 AIC_TRACE(("aic_done ")); 1303 1304 /* 1305 * Now, if we've come here with no error code, i.e. we've kept the 1306 * initial XS_NOERROR, and the status code signals that we should 1307 * check sense, we'll need to set up a request sense cmd block and 1308 * push the command back into the ready queue *before* any other 1309 * commands for this target/lunit, else we lose the sense info. 1310 * We don't support chk sense conditions for the request sense cmd. 1311 */ 1312 if (xs->error == XS_NOERROR) { 1313 if (acb->flags & ACB_ABORT) { 1314 xs->error = XS_DRIVER_STUFFUP; 1315 } else if (acb->flags & ACB_SENSE) { 1316 xs->error = XS_SENSE; 1317 } else if (acb->target_stat == SCSI_CHECK) { 1318 /* First, save the return values */ 1319 xs->resid = acb->data_length; 1320 xs->status = acb->target_stat; 1321 aic_sense(sc, acb); 1322 return; 1323 } else { 1324 xs->resid = acb->data_length; 1325 } 1326 } 1327 1328 xs->flags |= ITSDONE; 1329 1330 #if AIC_DEBUG 1331 if ((aic_debug & AIC_SHOWMISC) != 0) { 1332 if (xs->resid != 0) 1333 printf("resid=%d ", xs->resid); 1334 if (xs->error == XS_SENSE) 1335 printf("sense=0x%02x\n", xs->sense.error_code); 1336 else 1337 printf("error=%d\n", xs->error); 1338 } 1339 #endif 1340 1341 /* 1342 * Remove the ACB from whatever queue it happens to be on. 1343 */ 1344 if (acb->flags & ACB_NEXUS) 1345 ti->lubusy &= ~(1 << sc_link->lun); 1346 if (acb == sc->sc_nexus) { 1347 sc->sc_nexus = NULL; 1348 sc->sc_state = AIC_IDLE; 1349 aic_sched(sc); 1350 } else 1351 aic_dequeue(sc, acb); 1352 1353 aic_free_acb(sc, acb, xs->flags); 1354 ti->cmds++; 1355 scsi_done(xs); 1356 } 1357 1358 void 1359 aic_dequeue(sc, acb) 1360 struct aic_softc *sc; 1361 struct aic_acb *acb; 1362 { 1363 1364 if (acb->flags & ACB_NEXUS) { 1365 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1366 } else { 1367 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1368 } 1369 } 1370 1371 /* 1372 * INTERRUPT/PROTOCOL ENGINE 1373 */ 1374 1375 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1376 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1377 #define ISEXTMSG(m) ((m) == 0x01) 1378 1379 /* 1380 * Precondition: 1381 * The SCSI bus is already in the MSGI phase and there is a message byte 1382 * on the bus, along with an asserted REQ signal. 1383 */ 1384 void 1385 aic_msgin(sc) 1386 register struct aic_softc *sc; 1387 { 1388 int iobase = sc->sc_iobase; 1389 u_char sstat1; 1390 int n; 1391 1392 AIC_TRACE(("aic_msgin ")); 1393 1394 if (sc->sc_prevphase == PH_MSGIN) { 1395 /* This is a continuation of the previous message. */ 1396 n = sc->sc_imp - sc->sc_imess; 1397 goto nextbyte; 1398 } 1399 1400 /* This is a new MESSAGE IN phase. Clean up our state. */ 1401 sc->sc_flags &= ~AIC_DROP_MSGIN; 1402 1403 nextmsg: 1404 n = 0; 1405 sc->sc_imp = &sc->sc_imess[n]; 1406 1407 nextbyte: 1408 /* 1409 * Read a whole message, but don't ack the last byte. If we reject the 1410 * message, we have to assert ATN during the message transfer phase 1411 * itself. 1412 */ 1413 for (;;) { 1414 for (;;) { 1415 sstat1 = inb(iobase + SSTAT1); 1416 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1417 break; 1418 /* Wait for REQINIT. XXX Need timeout. */ 1419 } 1420 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1421 /* 1422 * Target left MESSAGE IN, probably because it 1423 * a) noticed our ATN signal, or 1424 * b) ran out of messages. 1425 */ 1426 goto out; 1427 } 1428 1429 /* If parity error, just dump everything on the floor. */ 1430 if ((sstat1 & SCSIPERR) != 0) { 1431 sc->sc_flags |= AIC_DROP_MSGIN; 1432 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1433 } 1434 1435 /* Gather incoming message bytes if needed. */ 1436 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 1437 if (n >= AIC_MAX_MSG_LEN) { 1438 (void) inb(iobase + SCSIDAT); 1439 sc->sc_flags |= AIC_DROP_MSGIN; 1440 aic_sched_msgout(sc, SEND_REJECT); 1441 } else { 1442 *sc->sc_imp++ = inb(iobase + SCSIDAT); 1443 n++; 1444 /* 1445 * This testing is suboptimal, but most 1446 * messages will be of the one byte variety, so 1447 * it should not affect performance 1448 * significantly. 1449 */ 1450 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1451 break; 1452 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1453 break; 1454 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1455 n == sc->sc_imess[1] + 2) 1456 break; 1457 } 1458 } else 1459 (void) inb(iobase + SCSIDAT); 1460 1461 /* 1462 * If we reach this spot we're either: 1463 * a) in the middle of a multi-byte message, or 1464 * b) dropping bytes. 1465 */ 1466 outb(iobase + SXFRCTL0, CHEN | SPIOEN); 1467 /* Ack the last byte read. */ 1468 (void) inb(iobase + SCSIDAT); 1469 outb(iobase + SXFRCTL0, CHEN); 1470 while ((inb(iobase + SCSISIG) & ACKI) != 0) 1471 ; 1472 } 1473 1474 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1475 1476 /* We now have a complete message. Parse it. */ 1477 switch (sc->sc_state) { 1478 struct aic_acb *acb; 1479 struct scsi_link *sc_link; 1480 struct aic_tinfo *ti; 1481 1482 case AIC_CONNECTED: 1483 AIC_ASSERT(sc->sc_nexus != NULL); 1484 acb = sc->sc_nexus; 1485 ti = &sc->sc_tinfo[acb->xs->sc_link->target]; 1486 1487 switch (sc->sc_imess[0]) { 1488 case MSG_CMDCOMPLETE: 1489 if (sc->sc_dleft < 0) { 1490 sc_link = acb->xs->sc_link; 1491 printf("%s: %d extra bytes from %d:%d\n", 1492 sc->sc_dev.dv_xname, -sc->sc_dleft, 1493 sc_link->target, sc_link->lun); 1494 acb->data_length = 0; 1495 } 1496 acb->xs->resid = acb->data_length = sc->sc_dleft; 1497 sc->sc_state = AIC_CMDCOMPLETE; 1498 break; 1499 1500 case MSG_PARITY_ERROR: 1501 /* Resend the last message. */ 1502 aic_sched_msgout(sc, sc->sc_lastmsg); 1503 break; 1504 1505 case MSG_MESSAGE_REJECT: 1506 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1507 switch (sc->sc_lastmsg) { 1508 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1509 case SEND_IDENTIFY: 1510 ti->flags &= ~(DO_SYNC | DO_WIDE); 1511 ti->period = ti->offset = 0; 1512 aic_setsync(sc, ti); 1513 ti->width = 0; 1514 break; 1515 #endif 1516 #if AIC_USE_SYNCHRONOUS 1517 case SEND_SDTR: 1518 ti->flags &= ~DO_SYNC; 1519 ti->period = ti->offset = 0; 1520 aic_setsync(sc, ti); 1521 break; 1522 #endif 1523 #if AIC_USE_WIDE 1524 case SEND_WDTR: 1525 ti->flags &= ~DO_WIDE; 1526 ti->width = 0; 1527 break; 1528 #endif 1529 case SEND_INIT_DET_ERR: 1530 aic_sched_msgout(sc, SEND_ABORT); 1531 break; 1532 } 1533 break; 1534 1535 case MSG_NOOP: 1536 break; 1537 1538 case MSG_DISCONNECT: 1539 ti->dconns++; 1540 sc->sc_state = AIC_DISCONNECT; 1541 break; 1542 1543 case MSG_SAVEDATAPOINTER: 1544 acb->data_addr = sc->sc_dp; 1545 acb->data_length = sc->sc_dleft; 1546 break; 1547 1548 case MSG_RESTOREPOINTERS: 1549 sc->sc_dp = acb->data_addr; 1550 sc->sc_dleft = acb->data_length; 1551 sc->sc_cp = (u_char *)&acb->scsi_cmd; 1552 sc->sc_cleft = acb->scsi_cmd_length; 1553 break; 1554 1555 case MSG_EXTENDED: 1556 switch (sc->sc_imess[2]) { 1557 #if AIC_USE_SYNCHRONOUS 1558 case MSG_EXT_SDTR: 1559 if (sc->sc_imess[1] != 3) 1560 goto reject; 1561 ti->period = sc->sc_imess[3]; 1562 ti->offset = sc->sc_imess[4]; 1563 ti->flags &= ~DO_SYNC; 1564 if (ti->offset == 0) { 1565 } else if (ti->period < sc->sc_minsync || 1566 ti->period > sc->sc_maxsync || 1567 ti->offset > 8) { 1568 ti->period = ti->offset = 0; 1569 aic_sched_msgout(sc, SEND_SDTR); 1570 } else { 1571 sc_print_addr(acb->xs->sc_link); 1572 printf("sync, offset %d, period %dnsec\n", 1573 ti->offset, ti->period * 4); 1574 } 1575 aic_setsync(sc, ti); 1576 break; 1577 #endif 1578 1579 #if AIC_USE_WIDE 1580 case MSG_EXT_WDTR: 1581 if (sc->sc_imess[1] != 2) 1582 goto reject; 1583 ti->width = sc->sc_imess[3]; 1584 ti->flags &= ~DO_WIDE; 1585 if (ti->width == 0) { 1586 } else if (ti->width > AIC_MAX_WIDTH) { 1587 ti->width = 0; 1588 aic_sched_msgout(sc, SEND_WDTR); 1589 } else { 1590 sc_print_addr(acb->xs->sc_link); 1591 printf("wide, width %d\n", 1592 1 << (3 + ti->width)); 1593 } 1594 break; 1595 #endif 1596 1597 default: 1598 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1599 sc->sc_dev.dv_xname); 1600 AIC_BREAK(); 1601 goto reject; 1602 } 1603 break; 1604 1605 default: 1606 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1607 sc->sc_dev.dv_xname); 1608 AIC_BREAK(); 1609 reject: 1610 aic_sched_msgout(sc, SEND_REJECT); 1611 break; 1612 } 1613 break; 1614 1615 case AIC_RESELECTED: 1616 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1617 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1618 sc->sc_dev.dv_xname); 1619 AIC_BREAK(); 1620 goto reset; 1621 } 1622 1623 (void) aic_reselect(sc, sc->sc_imess[0]); 1624 break; 1625 1626 default: 1627 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1628 sc->sc_dev.dv_xname); 1629 AIC_BREAK(); 1630 reset: 1631 aic_sched_msgout(sc, SEND_DEV_RESET); 1632 break; 1633 1634 #ifdef notdef 1635 abort: 1636 aic_sched_msgout(sc, SEND_ABORT); 1637 break; 1638 #endif 1639 } 1640 1641 outb(iobase + SXFRCTL0, CHEN | SPIOEN); 1642 /* Ack the last message byte. */ 1643 (void) inb(iobase + SCSIDAT); 1644 outb(iobase + SXFRCTL0, CHEN); 1645 while ((inb(iobase + SCSISIG) & ACKI) != 0) 1646 ; 1647 1648 /* Go get the next message, if any. */ 1649 goto nextmsg; 1650 1651 out: 1652 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1653 } 1654 1655 /* 1656 * Send the highest priority, scheduled message. 1657 */ 1658 void 1659 aic_msgout(sc) 1660 register struct aic_softc *sc; 1661 { 1662 int iobase = sc->sc_iobase; 1663 #if AIC_USE_SYNCHRONOUS 1664 struct aic_tinfo *ti; 1665 #endif 1666 u_char sstat1; 1667 int n; 1668 1669 AIC_TRACE(("aic_msgout ")); 1670 1671 /* Reset the FIFO. */ 1672 outb(iobase + DMACNTRL0, RSTFIFO); 1673 /* Enable REQ/ACK protocol. */ 1674 outb(iobase + SXFRCTL0, CHEN | SPIOEN); 1675 1676 if (sc->sc_prevphase == PH_MSGOUT) { 1677 if (sc->sc_omp == sc->sc_omess) { 1678 /* 1679 * This is a retransmission. 1680 * 1681 * We get here if the target stayed in MESSAGE OUT 1682 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1683 * that all of the previously transmitted messages must 1684 * be sent again, in the same order. Therefore, we 1685 * requeue all the previously transmitted messages, and 1686 * start again from the top. Our simple priority 1687 * scheme keeps the messages in the right order. 1688 */ 1689 AIC_MISC(("retransmitting ")); 1690 sc->sc_msgpriq |= sc->sc_msgoutq; 1691 /* 1692 * Set ATN. If we're just sending a trivial 1-byte 1693 * message, we'll clear ATN later on anyway. 1694 */ 1695 outb(iobase + SCSISIG, PH_MSGOUT | ATNO); 1696 } else { 1697 /* This is a continuation of the previous message. */ 1698 n = sc->sc_omp - sc->sc_omess; 1699 goto nextbyte; 1700 } 1701 } 1702 1703 /* No messages transmitted so far. */ 1704 sc->sc_msgoutq = 0; 1705 sc->sc_lastmsg = 0; 1706 1707 nextmsg: 1708 /* Pick up highest priority message. */ 1709 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1710 sc->sc_msgpriq &= ~sc->sc_currmsg; 1711 sc->sc_msgoutq |= sc->sc_currmsg; 1712 1713 /* Build the outgoing message data. */ 1714 switch (sc->sc_currmsg) { 1715 case SEND_IDENTIFY: 1716 AIC_ASSERT(sc->sc_nexus != NULL); 1717 sc->sc_omess[0] = 1718 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->lun, 1); 1719 n = 1; 1720 break; 1721 1722 #if AIC_USE_SYNCHRONOUS 1723 case SEND_SDTR: 1724 AIC_ASSERT(sc->sc_nexus != NULL); 1725 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1726 sc->sc_omess[4] = MSG_EXTENDED; 1727 sc->sc_omess[3] = 3; 1728 sc->sc_omess[2] = MSG_EXT_SDTR; 1729 sc->sc_omess[1] = ti->period >> 2; 1730 sc->sc_omess[0] = ti->offset; 1731 n = 5; 1732 break; 1733 #endif 1734 1735 #if AIC_USE_WIDE 1736 case SEND_WDTR: 1737 AIC_ASSERT(sc->sc_nexus != NULL); 1738 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target]; 1739 sc->sc_omess[3] = MSG_EXTENDED; 1740 sc->sc_omess[2] = 2; 1741 sc->sc_omess[1] = MSG_EXT_WDTR; 1742 sc->sc_omess[0] = ti->width; 1743 n = 4; 1744 break; 1745 #endif 1746 1747 case SEND_DEV_RESET: 1748 sc->sc_flags |= AIC_ABORTING; 1749 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1750 n = 1; 1751 break; 1752 1753 case SEND_REJECT: 1754 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1755 n = 1; 1756 break; 1757 1758 case SEND_PARITY_ERROR: 1759 sc->sc_omess[0] = MSG_PARITY_ERROR; 1760 n = 1; 1761 break; 1762 1763 case SEND_INIT_DET_ERR: 1764 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1765 n = 1; 1766 break; 1767 1768 case SEND_ABORT: 1769 sc->sc_flags |= AIC_ABORTING; 1770 sc->sc_omess[0] = MSG_ABORT; 1771 n = 1; 1772 break; 1773 1774 default: 1775 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1776 sc->sc_dev.dv_xname); 1777 AIC_BREAK(); 1778 sc->sc_omess[0] = MSG_NOOP; 1779 n = 1; 1780 break; 1781 } 1782 sc->sc_omp = &sc->sc_omess[n]; 1783 1784 nextbyte: 1785 /* Send message bytes. */ 1786 for (;;) { 1787 for (;;) { 1788 sstat1 = inb(iobase + SSTAT1); 1789 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1790 break; 1791 /* Wait for REQINIT. XXX Need timeout. */ 1792 } 1793 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1794 /* 1795 * Target left MESSAGE OUT, possibly to reject 1796 * our message. 1797 * 1798 * If this is the last message being sent, then we 1799 * deassert ATN, since either the target is going to 1800 * ignore this message, or it's going to ask for a 1801 * retransmission via MESSAGE PARITY ERROR (in which 1802 * case we reassert ATN anyway). 1803 */ 1804 if (sc->sc_msgpriq == 0) 1805 outb(iobase + CLRSINT1, CLRATNO); 1806 goto out; 1807 } 1808 1809 /* Clear ATN before last byte if this is the last message. */ 1810 if (n == 1 && sc->sc_msgpriq == 0) 1811 outb(iobase + CLRSINT1, CLRATNO); 1812 /* Send message byte. */ 1813 outb(iobase + SCSIDAT, *--sc->sc_omp); 1814 --n; 1815 /* Keep track of the last message we've sent any bytes of. */ 1816 sc->sc_lastmsg = sc->sc_currmsg; 1817 /* Wait for ACK to be negated. XXX Need timeout. */ 1818 while ((inb(iobase + SCSISIG) & ACKI) != 0) 1819 ; 1820 1821 if (n == 0) 1822 break; 1823 } 1824 1825 /* We get here only if the entire message has been transmitted. */ 1826 if (sc->sc_msgpriq != 0) { 1827 /* There are more outgoing messages. */ 1828 goto nextmsg; 1829 } 1830 1831 /* 1832 * The last message has been transmitted. We need to remember the last 1833 * message transmitted (in case the target switches to MESSAGE IN phase 1834 * and sends a MESSAGE REJECT), and the list of messages transmitted 1835 * this time around (in case the target stays in MESSAGE OUT phase to 1836 * request a retransmit). 1837 */ 1838 1839 out: 1840 /* Disable REQ/ACK protocol. */ 1841 outb(iobase + SXFRCTL0, CHEN); 1842 } 1843 1844 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the aic6360 1845 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1846 * and ACK deasserted (i.e. waiting for a data byte) 1847 * This new revision has been optimized (I tried) to make the common case fast, 1848 * and the rarer cases (as a result) somewhat more comlex 1849 */ 1850 int 1851 aic_dataout_pio(sc, p, n) 1852 register struct aic_softc *sc; 1853 u_char *p; 1854 int n; 1855 { 1856 int iobase = sc->sc_iobase; 1857 register u_char dmastat = 0; 1858 int out = 0; 1859 #define DOUTAMOUNT 128 /* Full FIFO */ 1860 1861 AIC_MISC(("%02x%02x ", inb(iobase + FIFOSTAT), inb(iobase + SSTAT2))); 1862 1863 /* Clear host FIFO and counter. */ 1864 outb(iobase + DMACNTRL0, RSTFIFO | WRITE); 1865 /* Enable FIFOs. */ 1866 outb(iobase + DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1867 outb(iobase + SXFRCTL0, SCSIEN | DMAEN | CHEN); 1868 1869 /* Turn off ENREQINIT for now. */ 1870 outb(iobase + SIMODE1, 1871 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1872 1873 /* I have tried to make the main loop as tight as possible. This 1874 * means that some of the code following the loop is a bit more 1875 * complex than otherwise. 1876 */ 1877 while (n > 0) { 1878 for (;;) { 1879 dmastat = inb(iobase + DMASTAT); 1880 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1881 break; 1882 } 1883 1884 if ((dmastat & INTSTAT) != 0) 1885 goto phasechange; 1886 1887 if (n >= DOUTAMOUNT) { 1888 n -= DOUTAMOUNT; 1889 out += DOUTAMOUNT; 1890 1891 #if AIC_USE_DWORDS 1892 outsl(iobase + DMADATALONG, p, DOUTAMOUNT >> 2); 1893 #else 1894 outsw(iobase + DMADATA, p, DOUTAMOUNT >> 1); 1895 #endif 1896 1897 p += DOUTAMOUNT; 1898 } else { 1899 register int xfer; 1900 1901 xfer = n; 1902 AIC_MISC(("%d> ", xfer)); 1903 1904 n -= xfer; 1905 out += xfer; 1906 1907 #if AIC_USE_DWORDS 1908 if (xfer >= 12) { 1909 outsl(iobase + DMADATALONG, p, xfer >> 2); 1910 p += xfer & ~3; 1911 xfer &= 3; 1912 } 1913 #else 1914 if (xfer >= 8) { 1915 outsw(iobase + DMADATA, p, xfer >> 1); 1916 p += xfer & ~1; 1917 xfer &= 1; 1918 } 1919 #endif 1920 1921 if (xfer > 0) { 1922 outb(iobase + DMACNTRL0, ENDMA | B8MODE | WRITE); 1923 outsb(iobase + DMADATA, p, xfer); 1924 p += xfer; 1925 outb(iobase + DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1926 } 1927 } 1928 } 1929 1930 if (out == 0) { 1931 outb(iobase + SXFRCTL1, BITBUCKET); 1932 for (;;) { 1933 if ((inb(iobase + DMASTAT) & INTSTAT) != 0) 1934 break; 1935 } 1936 outb(iobase + SXFRCTL1, 0); 1937 AIC_MISC(("extra data ")); 1938 } else { 1939 /* See the bytes off chip */ 1940 for (;;) { 1941 dmastat = inb(iobase + DMASTAT); 1942 if ((dmastat & INTSTAT) != 0) 1943 goto phasechange; 1944 if ((dmastat & DFIFOEMP) != 0 && 1945 (inb(iobase + SSTAT2) & SEMPTY) != 0) 1946 break; 1947 } 1948 } 1949 1950 phasechange: 1951 if ((dmastat & INTSTAT) != 0) { 1952 /* Some sort of phase change. */ 1953 int amount; 1954 1955 /* Stop transfers, do some accounting */ 1956 amount = inb(iobase + FIFOSTAT) + (inb(iobase + SSTAT2) & 15); 1957 if (amount > 0) { 1958 out -= amount; 1959 outb(iobase + DMACNTRL0, RSTFIFO | WRITE); 1960 outb(iobase + SXFRCTL0, CHEN | CLRCH); 1961 AIC_MISC(("+%d ", amount)); 1962 } 1963 } 1964 1965 /* Turn on ENREQINIT again. */ 1966 outb(iobase + SIMODE1, 1967 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1968 1969 /* Stop the FIFO data path. */ 1970 outb(iobase + SXFRCTL0, CHEN); 1971 outb(iobase + DMACNTRL0, 0); 1972 1973 return out; 1974 } 1975 1976 /* aic_datain_pio: perform data transfers using the FIFO datapath in the aic6360 1977 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1978 * and ACK deasserted (i.e. at least one byte is ready). 1979 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1980 * transferred. This, is OK for fast targets, but not so smart for slow 1981 * targets which don't disconnect or for huge transfers. 1982 */ 1983 int 1984 aic_datain_pio(sc, p, n) 1985 register struct aic_softc *sc; 1986 u_char *p; 1987 int n; 1988 { 1989 int iobase = sc->sc_iobase; 1990 register u_char dmastat; 1991 int in = 0; 1992 #define DINAMOUNT 128 /* Full FIFO */ 1993 1994 AIC_MISC(("%02x%02x ", inb(iobase + FIFOSTAT), inb(iobase + SSTAT2))); 1995 1996 /* Clear host FIFO and counter. */ 1997 outb(iobase + DMACNTRL0, RSTFIFO); 1998 /* Enable FIFOs. */ 1999 outb(iobase + DMACNTRL0, ENDMA | DWORDPIO); 2000 outb(iobase + SXFRCTL0, SCSIEN | DMAEN | CHEN); 2001 2002 /* Turn off ENREQINIT for now. */ 2003 outb(iobase + SIMODE1, 2004 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 2005 2006 /* We leave this loop if one or more of the following is true: 2007 * a) phase != PH_DATAIN && FIFOs are empty 2008 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 2009 */ 2010 while (n > 0) { 2011 /* Wait for fifo half full or phase mismatch */ 2012 for (;;) { 2013 dmastat = inb(iobase + DMASTAT); 2014 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 2015 break; 2016 } 2017 2018 if ((dmastat & DFIFOFULL) != 0) { 2019 n -= DINAMOUNT; 2020 in += DINAMOUNT; 2021 2022 #if AIC_USE_DWORDS 2023 insl(iobase + DMADATALONG, p, DINAMOUNT >> 2); 2024 #else 2025 insw(iobase + DMADATA, p, DINAMOUNT >> 1); 2026 #endif 2027 2028 p += DINAMOUNT; 2029 } else { 2030 register int xfer; 2031 2032 xfer = min(inb(iobase + FIFOSTAT), n); 2033 AIC_MISC((">%d ", xfer)); 2034 2035 n -= xfer; 2036 in += xfer; 2037 2038 #if AIC_USE_DWORDS 2039 if (xfer >= 12) { 2040 insl(iobase + DMADATALONG, p, xfer >> 2); 2041 p += xfer & ~3; 2042 xfer &= 3; 2043 } 2044 #else 2045 if (xfer >= 8) { 2046 insw(iobase + DMADATA, p, xfer >> 1); 2047 p += xfer & ~1; 2048 xfer &= 1; 2049 } 2050 #endif 2051 2052 if (xfer > 0) { 2053 outb(iobase + DMACNTRL0, ENDMA | B8MODE); 2054 insb(iobase + DMADATA, p, xfer); 2055 p += xfer; 2056 outb(iobase + DMACNTRL0, ENDMA | DWORDPIO); 2057 } 2058 } 2059 2060 if ((dmastat & INTSTAT) != 0) 2061 goto phasechange; 2062 } 2063 2064 /* Some SCSI-devices are rude enough to transfer more data than what 2065 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 2066 * requested 512. Test for progress, i.e. real transfers. If no real 2067 * transfers have been performed (n is probably already zero) and the 2068 * FIFO is not empty, waste some bytes.... 2069 */ 2070 if (in == 0) { 2071 outb(iobase + SXFRCTL1, BITBUCKET); 2072 for (;;) { 2073 if ((inb(iobase + DMASTAT) & INTSTAT) != 0) 2074 break; 2075 } 2076 outb(iobase + SXFRCTL1, 0); 2077 AIC_MISC(("extra data ")); 2078 } 2079 2080 phasechange: 2081 /* Turn on ENREQINIT again. */ 2082 outb(iobase + SIMODE1, 2083 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 2084 2085 /* Stop the FIFO data path. */ 2086 outb(iobase + SXFRCTL0, CHEN); 2087 outb(iobase + DMACNTRL0, 0); 2088 2089 return in; 2090 } 2091 2092 /* 2093 * This is the workhorse routine of the driver. 2094 * Deficiencies (for now): 2095 * 1) always uses programmed I/O 2096 */ 2097 int 2098 aicintr(arg) 2099 void *arg; 2100 { 2101 register struct aic_softc *sc = arg; 2102 int iobase = sc->sc_iobase; 2103 u_char sstat0, sstat1; 2104 register struct aic_acb *acb; 2105 register struct scsi_link *sc_link; 2106 struct aic_tinfo *ti; 2107 int n; 2108 2109 /* 2110 * Clear INTEN. We enable it again before returning. This makes the 2111 * interrupt esssentially level-triggered. 2112 */ 2113 outb(iobase + DMACNTRL0, 0); 2114 2115 AIC_TRACE(("aicintr ")); 2116 2117 loop: 2118 /* 2119 * First check for abnormal conditions, such as reset. 2120 */ 2121 sstat1 = inb(iobase + SSTAT1); 2122 AIC_MISC(("sstat1:0x%02x ", sstat1)); 2123 2124 if ((sstat1 & SCSIRSTI) != 0) { 2125 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 2126 goto reset; 2127 } 2128 2129 /* 2130 * Check for less serious errors. 2131 */ 2132 if ((sstat1 & SCSIPERR) != 0) { 2133 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 2134 outb(iobase + CLRSINT1, CLRSCSIPERR); 2135 if (sc->sc_prevphase == PH_MSGIN) { 2136 sc->sc_flags |= AIC_DROP_MSGIN; 2137 aic_sched_msgout(sc, SEND_PARITY_ERROR); 2138 } else 2139 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 2140 } 2141 2142 /* 2143 * If we're not already busy doing something test for the following 2144 * conditions: 2145 * 1) We have been reselected by something 2146 * 2) We have selected something successfully 2147 * 3) Our selection process has timed out 2148 * 4) This is really a bus free interrupt just to get a new command 2149 * going? 2150 * 5) Spurious interrupt? 2151 */ 2152 switch (sc->sc_state) { 2153 case AIC_IDLE: 2154 case AIC_SELECTING: 2155 sstat0 = inb(iobase + SSTAT0); 2156 AIC_MISC(("sstat0:0x%02x ", sstat0)); 2157 2158 if ((sstat0 & TARGET) != 0) { 2159 /* 2160 * We don't currently support target mode. 2161 */ 2162 printf("%s: target mode selected; going to BUS FREE\n", 2163 sc->sc_dev.dv_xname); 2164 outb(iobase + SCSISIG, 0); 2165 2166 goto sched; 2167 } else if ((sstat0 & SELDI) != 0) { 2168 AIC_MISC(("reselected ")); 2169 2170 /* 2171 * If we're trying to select a target ourselves, 2172 * push our command back into the ready list. 2173 */ 2174 if (sc->sc_state == AIC_SELECTING) { 2175 AIC_MISC(("backoff selector ")); 2176 AIC_ASSERT(sc->sc_nexus != NULL); 2177 acb = sc->sc_nexus; 2178 sc->sc_nexus = NULL; 2179 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2180 } 2181 2182 /* Save reselection ID. */ 2183 sc->sc_selid = inb(iobase + SELID); 2184 2185 sc->sc_state = AIC_RESELECTED; 2186 } else if ((sstat0 & SELDO) != 0) { 2187 AIC_MISC(("selected ")); 2188 2189 /* We have selected a target. Things to do: 2190 * a) Determine what message(s) to send. 2191 * b) Verify that we're still selecting the target. 2192 * c) Mark device as busy. 2193 */ 2194 if (sc->sc_state != AIC_SELECTING) { 2195 printf("%s: selection out while idle; resetting\n", 2196 sc->sc_dev.dv_xname); 2197 AIC_BREAK(); 2198 goto reset; 2199 } 2200 AIC_ASSERT(sc->sc_nexus != NULL); 2201 acb = sc->sc_nexus; 2202 sc_link = acb->xs->sc_link; 2203 ti = &sc->sc_tinfo[sc_link->target]; 2204 2205 sc->sc_msgpriq = SEND_IDENTIFY; 2206 if (acb->flags & ACB_RESET) 2207 sc->sc_msgpriq |= SEND_DEV_RESET; 2208 else if (acb->flags & ACB_ABORT) 2209 sc->sc_msgpriq |= SEND_ABORT; 2210 else { 2211 #if AIC_USE_SYNCHRONOUS 2212 if ((ti->flags & DO_SYNC) != 0) 2213 sc->sc_msgpriq |= SEND_SDTR; 2214 #endif 2215 #if AIC_USE_WIDE 2216 if ((ti->flags & DO_WIDE) != 0) 2217 sc->sc_msgpriq |= SEND_WDTR; 2218 #endif 2219 } 2220 2221 acb->flags |= ACB_NEXUS; 2222 ti->lubusy |= (1 << sc_link->lun); 2223 2224 /* Do an implicit RESTORE POINTERS. */ 2225 sc->sc_dp = acb->data_addr; 2226 sc->sc_dleft = acb->data_length; 2227 sc->sc_cp = (u_char *)&acb->scsi_cmd; 2228 sc->sc_cleft = acb->scsi_cmd_length; 2229 2230 /* On our first connection, schedule a timeout. */ 2231 if ((acb->xs->flags & SCSI_POLL) == 0) 2232 timeout(aic_timeout, acb, (acb->timeout * hz) / 1000); 2233 2234 sc->sc_state = AIC_CONNECTED; 2235 } else if ((sstat1 & SELTO) != 0) { 2236 AIC_MISC(("selection timeout ")); 2237 2238 if (sc->sc_state != AIC_SELECTING) { 2239 printf("%s: selection timeout while idle; resetting\n", 2240 sc->sc_dev.dv_xname); 2241 AIC_BREAK(); 2242 goto reset; 2243 } 2244 AIC_ASSERT(sc->sc_nexus != NULL); 2245 acb = sc->sc_nexus; 2246 2247 outb(iobase + SXFRCTL1, 0); 2248 outb(iobase + SCSISEQ, ENRESELI); 2249 outb(iobase + CLRSINT1, CLRSELTIMO); 2250 delay(250); 2251 2252 acb->xs->error = XS_SELTIMEOUT; 2253 goto finish; 2254 } else { 2255 if (sc->sc_state != AIC_IDLE) { 2256 printf("%s: BUS FREE while not idle; state=%d\n", 2257 sc->sc_dev.dv_xname, sc->sc_state); 2258 AIC_BREAK(); 2259 goto out; 2260 } 2261 2262 goto sched; 2263 } 2264 2265 /* 2266 * Turn off selection stuff, and prepare to catch bus free 2267 * interrupts, parity errors, and phase changes. 2268 */ 2269 outb(iobase + SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 2270 outb(iobase + SXFRCTL1, 0); 2271 outb(iobase + SCSISEQ, ENAUTOATNP); 2272 outb(iobase + CLRSINT0, CLRSELDI | CLRSELDO); 2273 outb(iobase + CLRSINT1, CLRBUSFREE | CLRPHASECHG); 2274 outb(iobase + SIMODE0, 0); 2275 outb(iobase + SIMODE1, 2276 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 2277 2278 sc->sc_flags = 0; 2279 sc->sc_prevphase = PH_INVALID; 2280 goto dophase; 2281 } 2282 2283 if ((sstat1 & BUSFREE) != 0) { 2284 /* We've gone to BUS FREE phase. */ 2285 outb(iobase + CLRSINT1, CLRBUSFREE | CLRPHASECHG); 2286 2287 switch (sc->sc_state) { 2288 case AIC_RESELECTED: 2289 goto sched; 2290 2291 case AIC_CONNECTED: 2292 AIC_ASSERT(sc->sc_nexus != NULL); 2293 acb = sc->sc_nexus; 2294 2295 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 2296 if (sc->sc_prevphase == PH_MSGOUT) { 2297 /* 2298 * If the target went to BUS FREE phase during 2299 * or immediately after sending a SDTR or WDTR 2300 * message, disable negotiation. 2301 */ 2302 sc_link = acb->xs->sc_link; 2303 ti = &sc->sc_tinfo[sc_link->target]; 2304 switch (sc->sc_lastmsg) { 2305 #if AIC_USE_SYNCHRONOUS 2306 case SEND_SDTR: 2307 ti->flags &= ~DO_SYNC; 2308 ti->period = ti->offset = 0; 2309 break; 2310 #endif 2311 #if AIC_USE_WIDE 2312 case SEND_WDTR: 2313 ti->flags &= ~DO_WIDE; 2314 ti->width = 0; 2315 break; 2316 #endif 2317 } 2318 } 2319 #endif 2320 2321 if ((sc->sc_flags & AIC_ABORTING) == 0) { 2322 /* 2323 * Section 5.1.1 of the SCSI 2 spec suggests 2324 * issuing a REQUEST SENSE following an 2325 * unexpected disconnect. Some devices go into 2326 * a contingent allegiance condition when 2327 * disconnecting, and this is necessary to 2328 * clean up their state. 2329 */ 2330 printf("%s: unexpected disconnect; sending REQUEST SENSE\n", 2331 sc->sc_dev.dv_xname); 2332 AIC_BREAK(); 2333 aic_sense(sc, acb); 2334 goto out; 2335 } 2336 2337 acb->xs->error = XS_DRIVER_STUFFUP; 2338 goto finish; 2339 2340 case AIC_DISCONNECT: 2341 AIC_ASSERT(sc->sc_nexus != NULL); 2342 acb = sc->sc_nexus; 2343 #if 1 /* XXXX */ 2344 acb->data_addr = sc->sc_dp; 2345 acb->data_length = sc->sc_dleft; 2346 #endif 2347 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 2348 sc->sc_nexus = NULL; 2349 goto sched; 2350 2351 case AIC_CMDCOMPLETE: 2352 AIC_ASSERT(sc->sc_nexus != NULL); 2353 acb = sc->sc_nexus; 2354 goto finish; 2355 } 2356 } 2357 2358 outb(iobase + CLRSINT1, CLRPHASECHG); 2359 2360 dophase: 2361 if ((sstat1 & REQINIT) == 0) { 2362 /* Wait for REQINIT. */ 2363 goto out; 2364 } 2365 2366 sc->sc_phase = inb(iobase + SCSISIG) & PH_MASK; 2367 outb(iobase + SCSISIG, sc->sc_phase); 2368 2369 switch (sc->sc_phase) { 2370 case PH_MSGOUT: 2371 if (sc->sc_state != AIC_CONNECTED && 2372 sc->sc_state != AIC_RESELECTED) 2373 break; 2374 aic_msgout(sc); 2375 sc->sc_prevphase = PH_MSGOUT; 2376 goto loop; 2377 2378 case PH_MSGIN: 2379 if (sc->sc_state != AIC_CONNECTED && 2380 sc->sc_state != AIC_RESELECTED) 2381 break; 2382 aic_msgin(sc); 2383 sc->sc_prevphase = PH_MSGIN; 2384 goto loop; 2385 2386 case PH_CMD: 2387 if (sc->sc_state != AIC_CONNECTED) 2388 break; 2389 #if AIC_DEBUG 2390 if ((aic_debug & AIC_SHOWMISC) != 0) { 2391 AIC_ASSERT(sc->sc_nexus != NULL); 2392 acb = sc->sc_nexus; 2393 printf("cmd=0x%02x+%d ", 2394 acb->scsi_cmd.opcode, acb->scsi_cmd_length-1); 2395 } 2396 #endif 2397 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 2398 sc->sc_cp += n; 2399 sc->sc_cleft -= n; 2400 sc->sc_prevphase = PH_CMD; 2401 goto loop; 2402 2403 case PH_DATAOUT: 2404 if (sc->sc_state != AIC_CONNECTED) 2405 break; 2406 AIC_MISC(("dataout %d ", sc->sc_dleft)); 2407 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 2408 sc->sc_dp += n; 2409 sc->sc_dleft -= n; 2410 sc->sc_prevphase = PH_DATAOUT; 2411 goto loop; 2412 2413 case PH_DATAIN: 2414 if (sc->sc_state != AIC_CONNECTED) 2415 break; 2416 AIC_MISC(("datain %d ", sc->sc_dleft)); 2417 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 2418 sc->sc_dp += n; 2419 sc->sc_dleft -= n; 2420 sc->sc_prevphase = PH_DATAIN; 2421 goto loop; 2422 2423 case PH_STAT: 2424 if (sc->sc_state != AIC_CONNECTED) 2425 break; 2426 AIC_ASSERT(sc->sc_nexus != NULL); 2427 acb = sc->sc_nexus; 2428 outb(iobase + SXFRCTL0, CHEN | SPIOEN); 2429 acb->target_stat = inb(iobase + SCSIDAT); 2430 outb(iobase + SXFRCTL0, CHEN); 2431 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2432 sc->sc_prevphase = PH_STAT; 2433 goto loop; 2434 } 2435 2436 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2437 AIC_BREAK(); 2438 reset: 2439 aic_init(sc); 2440 return 1; 2441 2442 finish: 2443 untimeout(aic_timeout, acb); 2444 aic_done(sc, acb); 2445 goto out; 2446 2447 sched: 2448 sc->sc_state = AIC_IDLE; 2449 aic_sched(sc); 2450 goto out; 2451 2452 out: 2453 outb(iobase + DMACNTRL0, INTEN); 2454 return 1; 2455 } 2456 2457 void 2458 aic_abort(sc, acb) 2459 struct aic_softc *sc; 2460 struct aic_acb *acb; 2461 { 2462 2463 /* 2 secs for the abort */ 2464 acb->timeout = AIC_ABORT_TIMEOUT; 2465 acb->flags |= ACB_ABORT; 2466 2467 if (acb == sc->sc_nexus) { 2468 /* 2469 * If we're still selecting, the message will be scheduled 2470 * after selection is complete. 2471 */ 2472 if (sc->sc_state == AIC_CONNECTED) 2473 aic_sched_msgout(sc, SEND_ABORT); 2474 } else { 2475 aic_dequeue(sc, acb); 2476 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2477 if (sc->sc_state == AIC_IDLE) 2478 aic_sched(sc); 2479 } 2480 } 2481 2482 void 2483 aic_timeout(arg) 2484 void *arg; 2485 { 2486 struct aic_acb *acb = arg; 2487 struct scsi_xfer *xs = acb->xs; 2488 struct scsi_link *sc_link = xs->sc_link; 2489 struct aic_softc *sc = sc_link->adapter_softc; 2490 int s; 2491 2492 sc_print_addr(sc_link); 2493 printf("timed out"); 2494 2495 s = splbio(); 2496 2497 if (acb->flags & ACB_ABORT) { 2498 /* abort timed out */ 2499 printf(" AGAIN\n"); 2500 /* XXX Must reset! */ 2501 } else { 2502 /* abort the operation that has timed out */ 2503 printf("\n"); 2504 acb->xs->error = XS_TIMEOUT; 2505 aic_abort(sc, acb); 2506 } 2507 2508 splx(s); 2509 } 2510 2511 #ifdef AIC_DEBUG 2512 /* 2513 * The following functions are mostly used for debugging purposes, either 2514 * directly called from the driver or from the kernel debugger. 2515 */ 2516 2517 void 2518 aic_show_scsi_cmd(acb) 2519 struct aic_acb *acb; 2520 { 2521 u_char *b = (u_char *)&acb->scsi_cmd; 2522 struct scsi_link *sc_link = acb->xs->sc_link; 2523 int i; 2524 2525 sc_print_addr(sc_link); 2526 if ((acb->xs->flags & SCSI_RESET) == 0) { 2527 for (i = 0; i < acb->scsi_cmd_length; i++) { 2528 if (i) 2529 printf(","); 2530 printf("%x", b[i]); 2531 } 2532 printf("\n"); 2533 } else 2534 printf("RESET\n"); 2535 } 2536 2537 void 2538 aic_print_acb(acb) 2539 struct aic_acb *acb; 2540 { 2541 2542 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2543 printf(" dp=%p dleft=%d target_stat=%x\n", 2544 acb->data_addr, acb->data_length, acb->target_stat); 2545 aic_show_scsi_cmd(acb); 2546 } 2547 2548 void 2549 aic_print_active_acb() 2550 { 2551 struct aic_acb *acb; 2552 struct aic_softc *sc = aic_cd.cd_devs[0]; 2553 2554 printf("ready list:\n"); 2555 for (acb = sc->ready_list.tqh_first; acb != NULL; 2556 acb = acb->chain.tqe_next) 2557 aic_print_acb(acb); 2558 printf("nexus:\n"); 2559 if (sc->sc_nexus != NULL) 2560 aic_print_acb(sc->sc_nexus); 2561 printf("nexus list:\n"); 2562 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2563 acb = acb->chain.tqe_next) 2564 aic_print_acb(acb); 2565 } 2566 2567 void 2568 aic_dump6360(sc) 2569 struct aic_softc *sc; 2570 { 2571 int iobase = sc->sc_iobase; 2572 2573 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2574 inb(iobase + SCSISEQ), inb(iobase + SXFRCTL0), 2575 inb(iobase + SXFRCTL1), inb(iobase + SCSISIG)); 2576 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2577 inb(iobase + SSTAT0), inb(iobase + SSTAT1), inb(iobase + SSTAT2), 2578 inb(iobase + SSTAT3), inb(iobase + SSTAT4)); 2579 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x DMASTAT=%x\n", 2580 inb(iobase + SIMODE0), inb(iobase + SIMODE1), 2581 inb(iobase + DMACNTRL0), inb(iobase + DMACNTRL1), 2582 inb(iobase + DMASTAT)); 2583 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2584 inb(iobase + FIFOSTAT), inb(iobase + SCSIBUS)); 2585 } 2586 2587 void 2588 aic_dump_driver(sc) 2589 struct aic_softc *sc; 2590 { 2591 struct aic_tinfo *ti; 2592 int i; 2593 2594 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2595 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2596 sc->sc_state, sc->sc_imess[0], 2597 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2598 for (i = 0; i < 7; i++) { 2599 ti = &sc->sc_tinfo[i]; 2600 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2601 i, ti->cmds, ti->dconns, ti->touts); 2602 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2603 } 2604 } 2605 #endif 2606