1 /* $NetBSD: ahcisatareg.h,v 1.4 2008/01/25 21:41:48 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SATA AHCI v1.0 register defines */ 34 35 /* misc defines */ 36 #define AHCI_MAX_PORTS 32 37 #define AHCI_MAX_CMDS 32 38 39 /* in-memory structures used by the controller */ 40 /* physical region descriptor: points to a region of data (max 4MB) */ 41 struct ahci_dma_prd { 42 u_int32_t prd_dba; /* data base address (64 bits) */ 43 u_int32_t prd_dbau; 44 u_int32_t prd_res; /* reserved */ 45 u_int32_t prd_dbc; /* data byte count */ 46 #define AHCI_PRD_DBC_MASK 0x003fffff 47 #define AHCI_PRD_DBC_IPC 0x80000000 /* interrupt on completion */ 48 } __packed; 49 50 #define AHCI_NPRD ((MAXPHYS/PAGE_SIZE) + 1) 51 52 /* command table: describe a command to send to drive */ 53 struct ahci_cmd_tbl { 54 u_int8_t cmdt_cfis[64]; /* command FIS */ 55 u_int8_t cmdt_acmd[16]; /* ATAPI command */ 56 u_int8_t cmdt_res[48]; /* reserved */ 57 struct ahci_dma_prd cmdt_prd[1]; /* extended to AHCI_NPRD */ 58 } __packed; 59 60 #define AHCI_CMDTBL_ALIGN 0x7f 61 62 #define AHCI_CMDTBL_SIZE ((sizeof(struct ahci_cmd_tbl) + \ 63 (sizeof(struct ahci_dma_prd) * (AHCI_NPRD - 1)) + (AHCI_CMDTBL_ALIGN)) \ 64 & ~AHCI_CMDTBL_ALIGN) 65 66 /* 67 * command header: points to a command table. The command list is an array 68 * of theses. 69 */ 70 struct ahci_cmd_header { 71 u_int16_t cmdh_flags; 72 #define AHCI_CMDH_F_PMP_MASK 0xf000 /* port multiplier port */ 73 #define AHCI_CMDH_F_PMP_SHIFT 12 74 #define AHCI_CMDH_F_CBSY 0x0400 /* clear BSY on R_OK */ 75 #define AHCI_CMDH_F_BIST 0x0200 /* BIST FIS */ 76 #define AHCI_CMDH_F_RST 0x0100 /* Reset FIS */ 77 #define AHCI_CMDH_F_PRF 0x0080 /* prefectchable */ 78 #define AHCI_CMDH_F_WR 0x0040 /* write */ 79 #define AHCI_CMDH_F_A 0x0020 /* ATAPI */ 80 #define AHCI_CMDH_F_CFL_MASK 0x001f /* command FIS length (in dw) */ 81 #define AHCI_CMDH_F_CFL_SHIFT 0 82 u_int16_t cmdh_prdtl; /* number of cmdt_prd */ 83 u_int32_t cmdh_prdbc; /* physical region descriptor byte count */ 84 u_int32_t cmdh_cmdtba; /* phys. addr. of cmd_tbl */ 85 u_int32_t cmdh_cmdtbau; /* (64bits, 128bytes aligned) */ 86 u_int32_t cmdh_res[4]; /* reserved */ 87 } __packed; 88 89 #define AHCI_CMDH_SIZE (sizeof(struct ahci_cmd_header) * AHCI_MAX_CMDS) 90 91 /* received FIS: where the HBA stores various type of FIS it receives */ 92 struct ahci_r_fis { 93 u_int8_t rfis_dsfis[32]; /* DMA setup FIS */ 94 u_int8_t rfis_psfis[32]; /* PIO setup FIS */ 95 u_int8_t rfis_rfis[24]; /* D2H register FIS */ 96 u_int8_t rfis_sdbfis[8]; /* set device bit FIS */ 97 u_int8_t rfis_ukfis[64]; /* unknown FIS */ 98 u_int8_t rfis_res[96]; 99 } __packed; 100 101 #define AHCI_RFIS_SIZE (sizeof(struct ahci_r_fis)) 102 103 /* PCI registers */ 104 /* class Mass storage, subclass SATA, interface AHCI */ 105 #define PCI_INTERFACE_SATA_AHCI 0x01 106 107 #define AHCI_PCI_ABAR 0x24 /* native ACHI registers (memory mapped) */ 108 109 /* ABAR registers */ 110 /* Global registers */ 111 #define AHCI_CAP 0x00 /* HBA capabilities */ 112 #define AHCI_CAP_NPMASK 0x0000001f /* Number of ports */ 113 #define AHCI_CAP_XS 0x00000020 /* External SATA */ 114 #define AHCI_CAP_EM 0x00000040 /* Enclosure Management */ 115 #define AHCI_CAP_CCC 0x00000080 /* command completion coalescing */ 116 #define AHCI_CAP_NCS 0x00001f00 /* number of command slots */ 117 #define AHCI_CAP_PS 0x00002000 /* Partial State */ 118 #define AHCI_CAP_SS 0x00004000 /* Slumber State */ 119 #define AHCI_CAP_PMD 0x00008000 /* PIO multiple DRQ blocks */ 120 #define AHCI_CAP_FBS 0x00010000 /* FIS-Based switching */ 121 #define AHCI_CAP_SPM 0x00020000 /* Port multipliers */ 122 #define AHCI_CAP_SAM 0x00040000 /* AHCI-only */ 123 #define AHCI_CAP_NZO 0x00080000 /* Non-zero DMA offset (reserved) */ 124 #define AHCI_CAP_IS 0x00f00000 /* Interface speed */ 125 #define AHCI_CAP_IS_GEN1 0x00100000 /* 1.5 GB/s */ 126 #define AHCI_CAP_IS_GEN2 0x00200000 /* 1.5 and 3 GB/s */ 127 #define AHCI_CAP_CLO 0x01000000 /* Command list override */ 128 #define AHCI_CAP_AL 0x02000000 /* Single Activitly LED */ 129 #define AHCI_CAP_ALP 0x04000000 /* Agressive link power management */ 130 #define AHCI_CAP_SSU 0x08000000 /* Staggered spin-up */ 131 #define AHCI_CAP_MPS 0x10000000 /* Mechanical swicth */ 132 #define AHCI_CAP_NTF 0x20000000 /* Snotification */ 133 #define AHCI_CAP_NCQ 0x40000000 /* Native command queuing */ 134 #define AHCI_CAP_64BIT 0x80000000 /* 64bit addresses */ 135 136 #define AHCI_GHC 0x04 /* HBA control */ 137 #define AHCI_GHC_HR 0x00000001 /* HBA reset */ 138 #define AHCI_GHC_IE 0x00000002 /* Interrupt enable */ 139 #define AHCI_GHC_MRSM 0x00000004 /* MSI revert to single message */ 140 #define AHCI_GHC_AE 0x80000000 /* AHCI enable */ 141 142 #define AHCI_IS 0x08 /* Interrupt status register: one bit per port */ 143 144 #define AHCI_PI 0x0c /* Port implemented: one bit per port */ 145 146 #define AHCI_VS 0x10 /* AHCI version */ 147 #define AHCI_VS_10 0x00010000 /* AHCI spec 1.0 */ 148 #define AHCI_VS_11 0x00010100 /* AHCI spec 1.1 */ 149 #define AHCI_VS_12 0x00010200 /* AHCI spec 1.2 */ 150 151 #define AHCI_CC_CTL 0x14 /* command completion coalescing control */ 152 #define AHCI_CC_TV_MASK 0xffff0000 /* timeout value */ 153 #define AHCI_CC_TV_SHIFT 16 154 #define AHCI_CC_CC_MASK 0x0000ff00 /* command completion */ 155 #define AHCI_CC_CC_SHIFT 8 156 #define AHCI_CC_INT_MASK 0x000000f8 /* interrupt */ 157 #define AHCI_CC_INT_SHIFT 3 158 #define AHCI_CC_EN 0x000000001 /* enable */ 159 160 #define AHCI_CC_PORTS 0x18 /* command completion coalescing ports (1b/port */ 161 162 #define AHCI_EM_LOC 0x1c /* enclosure managemement location */ 163 #define AHCI_EML_OFF_MASK 0xffff0000 /* offset in ABAR */ 164 #define AHCI_EML_OFF_SHIFT 16 165 #define AHCI_EML_SZ_MASK 0x0000ffff /* offset in ABAR */ 166 #define AHCI_EML_SZ_SHIFT 0 167 168 #define AHCI_EM_CTL 0x20 /* enclosure management control */ 169 #define AHCI_EMC_PM 0x08000000 /* port multiplier support */ 170 #define AHCI_EMC_ALHD 0x04000000 /* activity LED hardware driven */ 171 #define AHCI_EMC_XMIT 0x02000000 /* tramsit messages only */ 172 #define AHCI_EMC_SMB 0x01000000 /* single message buffer */ 173 #define AHCI_EMC_SGPIO 0x00080000 /* enclosure management messages */ 174 #define AHCI_EMC_SES2 0x00040000 /* SeS-2 messages */ 175 #define AHCI_EMC_SAF 0x00020000 /* SAF_TE messages */ 176 #define AHCI_EMC_LED 0x00010000 /* LED messages */ 177 #define AHCI_EMC_RST 0x00000200 /* Reset */ 178 #define AHCI_EMC_TM 0x00000100 /* Transmit message */ 179 #define AHCI_EMC_MR 0x00000001 /* Message received */ 180 181 /* Per-port registers */ 182 #define AHCI_P_OFFSET(port) (0x80 * (port)) 183 184 #define AHCI_P_CLB(p) (0x100 + AHCI_P_OFFSET(p)) /* command list addr */ 185 #define AHCI_P_CLBU(p) (0x104 + AHCI_P_OFFSET(p)) /* command list addr */ 186 #define AHCI_P_FB(p) (0x108 + AHCI_P_OFFSET(p)) /* FIS addr */ 187 #define AHCI_P_FBU(p) (0x10c + AHCI_P_OFFSET(p)) /* FIS addr */ 188 #define AHCI_P_IS(p) (0x110 + AHCI_P_OFFSET(p)) /* Interrupt status */ 189 #define AHCI_P_IE(p) (0x114 + AHCI_P_OFFSET(p)) /* Interrupt enable */ 190 #define AHCI_P_IX_CPDS 0x80000000 /* Cold port detect */ 191 #define AHCI_P_IX_TFES 0x40000000 /* Task file error */ 192 #define AHCI_P_IX_HBFS 0x20000000 /* Host bus fatal error */ 193 #define AHCI_P_IX_HBDS 0x10000000 /* Host bus data error */ 194 #define AHCI_P_IX_IFS 0x08000000 /* Interface fatal error */ 195 #define AHCI_P_IX_INFS 0x04000000 /* Interface non-fatal error */ 196 #define AHCI_P_IX_OFS 0x01000000 /* Overflow */ 197 #define AHCI_P_IX_IPMS 0x00800000 /* Incorrect port multiplier */ 198 #define AHCI_P_IX_PRCS 0x00400000 /* Phy Ready change */ 199 #define AHCI_P_IX_DMPS 0x00000080 /* Device Mechanical Presence */ 200 #define AHCI_P_IX_PCS 0x00000040 /* port Connect change */ 201 #define AHCI_P_IX_DPS 0x00000020 /* dexcriptor processed */ 202 #define AHCI_P_IX_UFS 0x00000010 /* Unknown FIS */ 203 #define AHCI_P_IX_SDBS 0x00000008 /* Set device bit */ 204 #define AHCI_P_IX_DSS 0x00000004 /* DMA setup FIS */ 205 #define AHCI_P_IX_PSS 0x00000002 /* PIO setup FIS */ 206 #define AHCI_P_IX_DHRS 0x00000001 /* Device to Host FIS */ 207 208 #define AHCI_P_CMD(p) (0x118 + AHCI_P_OFFSET(p)) /* Port command/status */ 209 #define AHCI_P_CMD_ICC_MASK 0xf0000000 /* Interface Comm. Control */ 210 #define AHCI_P_CMD_ICC_SL 0x60000000 /* State slumber */ 211 #define AHCI_P_CMD_ICC_PA 0x20000000 /* State partial */ 212 #define AHCI_P_CMD_ICC_AC 0x10000000 /* State active */ 213 #define AHCI_P_CMD_ICC_NO 0x00000000 /* State idle/NOP */ 214 #define AHCI_P_CMD_ASP 0x08000000 /* Agressive Slumber/Partial */ 215 #define AHCI_P_CMD_ALPE 0x04000000 /* Agressive link power management */ 216 #define AHCI_P_CMD_DLAE 0x02000000 /* drive LED on ATAPI */ 217 #define AHCI_P_CMD_ATAP 0x01000000 /* Device is ATAPI */ 218 #define AHCI_P_CMD_ESP 0x00200000 /* external SATA port */ 219 #define AHCI_P_CMD_CPD 0x00100000 /* Cold presence detection */ 220 #define AHCI_P_CMD_MPSP 0x00080000 /* Mechanical switch attached */ 221 #define AHCI_P_CMD_HPCP 0x00040000 /* hot-plug capable */ 222 #define AHCI_P_CMD_PMA 0x00020000 /* port multiplier attached */ 223 #define AHCI_P_CMD_CPS 0x00010000 /* cold presence state */ 224 #define AHCI_P_CMD_CR 0x00008000 /* command list running */ 225 #define AHCI_P_CMD_FR 0x00004000 /* FIS receive running */ 226 #define AHCI_P_CMD_MPSS 0x00002000 /* mechanical switch state */ 227 #define AHCI_P_CMD_CCS_MASK 0x00001f00 /* current command slot */ 228 #define AHCI_P_CMD_CCS_SHIFT 12 229 #define AHCI_P_CMD_FRE 0x00000010 /* FIS receive enable */ 230 #define AHCI_P_CMD_CLO 0x00000008 /* command list override */ 231 #define AHCI_P_CMD_POD 0x00000004 /* power on device */ 232 #define AHCI_P_CMD_SUD 0x00000002 /* spin up device */ 233 #define AHCI_P_CMD_ST 0x00000001 /* start */ 234 235 #define AHCI_P_TFD(p) (0x120 + AHCI_P_OFFSET(p)) /* Port task file data */ 236 #define AHCI_P_TFD_ERR_MASK 0x0000ff00 /* error register */ 237 #define AHCI_P_TFD_ERR_SHIFT 8 238 #define AHCI_P_TFD_ST 0x000000ff /* status register */ 239 #define AHCI_P_TFD_ST_SHIFT 0 240 241 #define AHCI_P_SIG(p) (0x124 + AHCI_P_OFFSET(p)) /* device signature */ 242 #define AHCI_P_SIG_LBAH_MASK 0xff000000 243 #define AHCI_P_SIG_LBAH_SHIFT 24 244 #define AHCI_P_SIG_LBAM_MASK 0x00ff0000 245 #define AHCI_P_SIG_LBAM_SHIFT 16 246 #define AHCI_P_SIG_LBAL_MASK 0x0000ff00 247 #define AHCI_P_SIG_LBAL_SHIFT 8 248 #define AHCI_P_SIG_SC_MASK 0x000000ff 249 #define AHCI_P_SIG_SC_SHIFT 8 250 251 #define AHCI_P_SSTS(p) (0x128 + AHCI_P_OFFSET(p)) /* Serial ATA status */ 252 253 #define AHCI_P_SCTL(p) (0x12c + AHCI_P_OFFSET(p)) /* Serial ATA control */ 254 255 #define AHCI_P_SERR(p) (0x130 + AHCI_P_OFFSET(p)) /* Serial ATA error */ 256 257 #define AHCI_P_SACT(p) (0x134 + AHCI_P_OFFSET(p)) /* Serial ATA active */ 258 /* one bit per tag/command slot */ 259 260 #define AHCI_P_CI(p) (0x138 + AHCI_P_OFFSET(p)) /* Command issued */ 261 /* one bit per tag/command slot */ 262 263 #define AHCI_P_FNTF(p) (0x13c + AHCI_P_OFFSET(p)) /* SNotification */ 264 /* one bit per port */ 265