1 /* $NetBSD: ahcisata_core.c,v 1.31 2011/01/10 11:18:14 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.31 2011/01/10 11:18:14 tsutsui Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/proc.h> 38 #include <sys/buf.h> 39 40 #include <dev/ata/atareg.h> 41 #include <dev/ata/satavar.h> 42 #include <dev/ata/satareg.h> 43 #include <dev/ata/satafisvar.h> 44 #include <dev/ata/satafisreg.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 48 49 #include "atapibus.h" 50 51 #ifdef AHCI_DEBUG 52 int ahcidebug_mask = 0x0; 53 #endif 54 55 static void ahci_probe_drive(struct ata_channel *); 56 static void ahci_setup_channel(struct ata_channel *); 57 58 static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 59 static void ahci_reset_drive(struct ata_drive_datas *, int); 60 static void ahci_reset_channel(struct ata_channel *, int); 61 static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 62 static int ahci_ata_addref(struct ata_drive_datas *); 63 static void ahci_ata_delref(struct ata_drive_datas *); 64 static void ahci_killpending(struct ata_drive_datas *); 65 66 static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 67 static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 68 static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 69 static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 70 static void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 71 static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 72 static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 73 static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 74 static void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 75 static void ahci_timeout(void *); 76 static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 77 78 #if NATAPIBUS > 0 79 static void ahci_atapibus_attach(struct atabus_softc *); 80 static void ahci_atapi_kill_pending(struct scsipi_periph *); 81 static void ahci_atapi_minphys(struct buf *); 82 static void ahci_atapi_scsipi_request(struct scsipi_channel *, 83 scsipi_adapter_req_t, void *); 84 static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 85 static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 86 static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 87 static void ahci_atapi_probe_device(struct atapibus_softc *, int); 88 89 static const struct scsipi_bustype ahci_atapi_bustype = { 90 SCSIPI_BUSTYPE_ATAPI, 91 atapi_scsipi_cmd, 92 atapi_interpret_sense, 93 atapi_print_addr, 94 ahci_atapi_kill_pending, 95 }; 96 #endif /* NATAPIBUS */ 97 98 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 99 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 100 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 101 102 const struct ata_bustype ahci_ata_bustype = { 103 SCSIPI_BUSTYPE_ATA, 104 ahci_ata_bio, 105 ahci_reset_drive, 106 ahci_reset_channel, 107 ahci_exec_command, 108 ata_get_params, 109 ahci_ata_addref, 110 ahci_ata_delref, 111 ahci_killpending 112 }; 113 114 static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 115 static void ahci_setup_port(struct ahci_softc *sc, int i); 116 117 static int 118 ahci_reset(struct ahci_softc *sc) 119 { 120 int i; 121 122 /* reset controller */ 123 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 124 /* wait up to 1s for reset to complete */ 125 for (i = 0; i < 1000; i++) { 126 delay(1000); 127 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 128 break; 129 } 130 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 131 aprint_error("%s: reset failed\n", AHCINAME(sc)); 132 return -1; 133 } 134 /* enable ahci mode */ 135 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 136 return 0; 137 } 138 139 static void 140 ahci_setup_ports(struct ahci_softc *sc) 141 { 142 uint32_t ahci_ports; 143 int i, port; 144 145 ahci_ports = AHCI_READ(sc, AHCI_PI); 146 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 147 if ((ahci_ports & (1 << i)) == 0) 148 continue; 149 if (port >= sc->sc_atac.atac_nchannels) { 150 aprint_error("%s: more ports than announced\n", 151 AHCINAME(sc)); 152 break; 153 } 154 ahci_setup_port(sc, i); 155 } 156 } 157 158 static void 159 ahci_reprobe_drives(struct ahci_softc *sc) 160 { 161 uint32_t ahci_ports; 162 int i, port; 163 struct ahci_channel *achp; 164 struct ata_channel *chp; 165 166 ahci_ports = AHCI_READ(sc, AHCI_PI); 167 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 168 if ((ahci_ports & (1 << i)) == 0) 169 continue; 170 if (port >= sc->sc_atac.atac_nchannels) { 171 aprint_error("%s: more ports than announced\n", 172 AHCINAME(sc)); 173 break; 174 } 175 achp = &sc->sc_channels[i]; 176 chp = &achp->ata_channel; 177 178 ahci_probe_drive(chp); 179 } 180 } 181 182 static void 183 ahci_setup_port(struct ahci_softc *sc, int i) 184 { 185 struct ahci_channel *achp; 186 187 achp = &sc->sc_channels[i]; 188 189 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 190 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32); 191 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 192 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32); 193 } 194 195 static void 196 ahci_enable_intrs(struct ahci_softc *sc) 197 { 198 199 /* clear interrupts */ 200 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 201 /* enable interrupts */ 202 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 203 } 204 205 void 206 ahci_attach(struct ahci_softc *sc) 207 { 208 uint32_t ahci_cap, ahci_rev, ahci_ports; 209 int i, j, port; 210 struct ahci_channel *achp; 211 struct ata_channel *chp; 212 int error; 213 int dmasize; 214 void *cmdhp; 215 void *cmdtblp; 216 217 if (ahci_reset(sc) != 0) 218 return; 219 220 ahci_cap = AHCI_READ(sc, AHCI_CAP); 221 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 222 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 223 ahci_rev = AHCI_READ(sc, AHCI_VS); 224 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 225 switch(ahci_rev) { 226 case AHCI_VS_10: 227 aprint_normal("1.0"); 228 break; 229 case AHCI_VS_11: 230 aprint_normal("1.1"); 231 break; 232 case AHCI_VS_12: 233 aprint_normal("1.2"); 234 break; 235 default: 236 aprint_normal("0x%x", ahci_rev); 237 break; 238 } 239 240 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 241 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 242 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 243 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 244 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 245 sc->sc_atac.atac_pio_cap = 4; 246 sc->sc_atac.atac_dma_cap = 2; 247 sc->sc_atac.atac_udma_cap = 6; 248 sc->sc_atac.atac_channels = sc->sc_chanarray; 249 sc->sc_atac.atac_probe = ahci_probe_drive; 250 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 251 sc->sc_atac.atac_set_modes = ahci_setup_channel; 252 #if NATAPIBUS > 0 253 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 254 #endif 255 256 dmasize = 257 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 258 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 259 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT); 260 if (error) { 261 aprint_error("%s: unable to allocate command header memory" 262 ", error=%d\n", AHCINAME(sc), error); 263 return; 264 } 265 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg, 266 sc->sc_cmd_hdr_nseg, dmasize, 267 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 268 if (error) { 269 aprint_error("%s: unable to map command header memory" 270 ", error=%d\n", AHCINAME(sc), error); 271 return; 272 } 273 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 274 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 275 if (error) { 276 aprint_error("%s: unable to create command header map" 277 ", error=%d\n", AHCINAME(sc), error); 278 return; 279 } 280 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 281 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 282 if (error) { 283 aprint_error("%s: unable to load command header map" 284 ", error=%d\n", AHCINAME(sc), error); 285 return; 286 } 287 sc->sc_cmd_hdr = cmdhp; 288 289 ahci_enable_intrs(sc); 290 291 ahci_ports = AHCI_READ(sc, AHCI_PI); 292 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 293 if ((ahci_ports & (1 << i)) == 0) 294 continue; 295 if (port >= sc->sc_atac.atac_nchannels) { 296 aprint_error("%s: more ports than announced\n", 297 AHCINAME(sc)); 298 break; 299 } 300 achp = &sc->sc_channels[i]; 301 chp = &achp->ata_channel; 302 sc->sc_chanarray[i] = chp; 303 chp->ch_channel = i; 304 chp->ch_atac = &sc->sc_atac; 305 chp->ch_queue = malloc(sizeof(struct ata_queue), 306 M_DEVBUF, M_NOWAIT); 307 if (chp->ch_queue == NULL) { 308 aprint_error("%s port %d: can't allocate memory for " 309 "command queue", AHCINAME(sc), i); 310 break; 311 } 312 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 313 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 314 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg, 315 BUS_DMA_NOWAIT); 316 if (error) { 317 aprint_error("%s: unable to allocate command table " 318 "memory, error=%d\n", AHCINAME(sc), error); 319 break; 320 } 321 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 322 achp->ahcic_cmd_tbl_nseg, dmasize, 323 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 324 if (error) { 325 aprint_error("%s: unable to map command table memory" 326 ", error=%d\n", AHCINAME(sc), error); 327 break; 328 } 329 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 330 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 331 if (error) { 332 aprint_error("%s: unable to create command table map" 333 ", error=%d\n", AHCINAME(sc), error); 334 break; 335 } 336 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 337 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 338 if (error) { 339 aprint_error("%s: unable to load command table map" 340 ", error=%d\n", AHCINAME(sc), error); 341 break; 342 } 343 achp->ahcic_cmdh = (struct ahci_cmd_header *) 344 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 345 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 346 AHCI_CMDH_SIZE * port; 347 achp->ahcic_rfis = (struct ahci_r_fis *) 348 ((char *)cmdhp + 349 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 350 AHCI_RFIS_SIZE * port); 351 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 352 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 353 AHCI_RFIS_SIZE * port; 354 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") " 355 "rfis %p (0x%" PRIx64 ")\n", i, 356 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh, 357 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis), 358 DEBUG_PROBE); 359 360 for (j = 0; j < sc->sc_ncmds; j++) { 361 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 362 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 363 achp->ahcic_bus_cmd_tbl[j] = 364 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 365 AHCI_CMDTBL_SIZE * j; 366 achp->ahcic_cmdh[j].cmdh_cmdtba = 367 htole64(achp->ahcic_bus_cmd_tbl[j]); 368 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j, 369 achp->ahcic_cmd_tbl[j], 370 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 371 /* The xfer DMA map */ 372 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 373 AHCI_NPRD, 0x400000 /* 4MB */, 0, 374 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 375 &achp->ahcic_datad[j]); 376 if (error) { 377 aprint_error("%s: couldn't alloc xfer DMA map, " 378 "error=%d\n", AHCINAME(sc), error); 379 goto end; 380 } 381 } 382 ahci_setup_port(sc, i); 383 chp->ch_ndrive = 1; 384 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 385 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) { 386 aprint_error("%s: couldn't map channel %d " 387 "sata_status regs\n", AHCINAME(sc), i); 388 break; 389 } 390 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 391 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) { 392 aprint_error("%s: couldn't map channel %d " 393 "sata_control regs\n", AHCINAME(sc), i); 394 break; 395 } 396 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 397 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) { 398 aprint_error("%s: couldn't map channel %d " 399 "sata_error regs\n", AHCINAME(sc), i); 400 break; 401 } 402 ata_channel_attach(chp); 403 port++; 404 end: 405 continue; 406 } 407 } 408 409 int 410 ahci_detach(struct ahci_softc *sc, int flags) 411 { 412 struct atac_softc *atac; 413 struct ahci_channel *achp; 414 struct ata_channel *chp; 415 struct scsipi_adapter *adapt; 416 uint32_t ahci_ports; 417 int i, j; 418 int error; 419 420 atac = &sc->sc_atac; 421 adapt = &atac->atac_atapi_adapter._generic; 422 423 ahci_ports = AHCI_READ(sc, AHCI_PI); 424 for (i = 0; i < AHCI_MAX_PORTS; i++) { 425 achp = &sc->sc_channels[i]; 426 chp = &achp->ata_channel; 427 428 if ((ahci_ports & (1 << i)) == 0) 429 continue; 430 if (i >= sc->sc_atac.atac_nchannels) { 431 aprint_error("%s: more ports than announced\n", 432 AHCINAME(sc)); 433 break; 434 } 435 436 if (chp->atabus == NULL) 437 continue; 438 if ((error = config_detach(chp->atabus, flags)) != 0) 439 return error; 440 441 for (j = 0; j < sc->sc_ncmds; j++) 442 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]); 443 444 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld); 445 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld); 446 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0], 447 AHCI_CMDTBL_SIZE * sc->sc_ncmds); 448 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg, 449 achp->ahcic_cmd_tbl_nseg); 450 451 free(chp->ch_queue, M_DEVBUF); 452 chp->atabus = NULL; 453 } 454 455 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd); 456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd); 457 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr, 458 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels); 459 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg); 460 461 if (adapt->adapt_refcnt != 0) 462 return EBUSY; 463 464 return 0; 465 } 466 467 void 468 ahci_resume(struct ahci_softc *sc) 469 { 470 ahci_reset(sc); 471 ahci_setup_ports(sc); 472 ahci_reprobe_drives(sc); 473 ahci_enable_intrs(sc); 474 } 475 476 int 477 ahci_intr(void *v) 478 { 479 struct ahci_softc *sc = v; 480 uint32_t is; 481 int i, r = 0; 482 483 while ((is = AHCI_READ(sc, AHCI_IS))) { 484 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 485 DEBUG_INTR); 486 r = 1; 487 AHCI_WRITE(sc, AHCI_IS, is); 488 for (i = 0; i < AHCI_MAX_PORTS; i++) 489 if (is & (1 << i)) 490 ahci_intr_port(sc, &sc->sc_channels[i]); 491 } 492 return r; 493 } 494 495 static void 496 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 497 { 498 uint32_t is, tfd; 499 struct ata_channel *chp = &achp->ata_channel; 500 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 501 int slot; 502 503 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 504 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 505 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 506 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 507 DEBUG_INTR); 508 509 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 510 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 511 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 512 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 513 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 514 return; 515 /* stop channel */ 516 ahci_channel_stop(sc, chp, 0); 517 if (slot != 0) { 518 printf("ahci_intr_port: slot %d\n", slot); 519 panic("ahci_intr_port"); 520 } 521 if (is & AHCI_P_IX_TFES) { 522 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 523 chp->ch_error = 524 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 525 chp->ch_status = (tfd & 0xff); 526 } else { 527 /* emulate a CRC error */ 528 chp->ch_error = WDCE_CRC; 529 chp->ch_status = WDCS_ERR; 530 } 531 xfer->c_intr(chp, xfer, is); 532 /* if channel has not been restarted, do it now */ 533 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 534 == 0) 535 ahci_channel_start(sc, chp); 536 } else { 537 slot = 0; /* XXX */ 538 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 539 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 540 chp->ch_channel, is, achp->ahcic_cmds_active, 541 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 542 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 543 return; 544 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 545 == 0) { 546 xfer->c_intr(chp, xfer, 0); 547 } 548 } 549 } 550 551 static void 552 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 553 { 554 struct ata_channel *chp = drvp->chnl_softc; 555 ata_reset_channel(chp, flags); 556 return; 557 } 558 559 static void 560 ahci_reset_channel(struct ata_channel *chp, int flags) 561 { 562 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 563 struct ahci_channel *achp = (struct ahci_channel *)chp; 564 int i, tfd; 565 566 ahci_channel_stop(sc, chp, flags); 567 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 568 achp->ahcic_sstatus) != SStatus_DET_DEV) { 569 printf("%s: port reset failed\n", AHCINAME(sc)); 570 /* XXX and then ? */ 571 } 572 if (chp->ch_queue->active_xfer) { 573 chp->ch_queue->active_xfer->c_kill_xfer(chp, 574 chp->ch_queue->active_xfer, KILL_RESET); 575 } 576 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 577 /* clear port interrupt register */ 578 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 579 /* clear SErrors and start operations */ 580 ahci_channel_start(sc, chp); 581 /* wait 31s for BSY to clear */ 582 for (i = 0; i <AHCI_RST_WAIT; i++) { 583 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 584 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 585 & WDCS_BSY) == 0) 586 break; 587 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 588 } 589 if (i == AHCI_RST_WAIT) 590 aprint_error("%s: BSY never cleared, TD 0x%x\n", 591 AHCINAME(sc), tfd); 592 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 593 DEBUG_PROBE); 594 /* clear port interrupt register */ 595 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 596 597 return; 598 } 599 600 static int 601 ahci_ata_addref(struct ata_drive_datas *drvp) 602 { 603 return 0; 604 } 605 606 static void 607 ahci_ata_delref(struct ata_drive_datas *drvp) 608 { 609 return; 610 } 611 612 static void 613 ahci_killpending(struct ata_drive_datas *drvp) 614 { 615 return; 616 } 617 618 static void 619 ahci_probe_drive(struct ata_channel *chp) 620 { 621 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 622 struct ahci_channel *achp = (struct ahci_channel *)chp; 623 int i, s; 624 uint32_t sig; 625 626 /* XXX This should be done by other code. */ 627 for (i = 0; i < chp->ch_ndrive; i++) { 628 chp->ch_drive[i].chnl_softc = chp; 629 chp->ch_drive[i].drive = i; 630 } 631 632 /* bring interface up, accept FISs, power up and spin up device */ 633 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 634 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 635 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 636 /* reset the PHY and bring online */ 637 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 638 achp->ahcic_sstatus)) { 639 case SStatus_DET_DEV: 640 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 641 /* clear port interrupt register */ 642 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 643 /* clear SErrors and start operations */ 644 ahci_channel_start(sc, chp); 645 /* wait 31s for BSY to clear */ 646 for (i = 0; i <AHCI_RST_WAIT; i++) { 647 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 648 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 649 & WDCS_BSY) == 0) 650 break; 651 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 652 } 653 if (i == AHCI_RST_WAIT) { 654 aprint_error("%s: BSY never cleared, TD 0x%x\n", 655 AHCINAME(sc), sig); 656 return; 657 } 658 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 659 DEBUG_PROBE); 660 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 661 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 662 AHCINAME(sc), chp->ch_channel, sig, 663 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 664 /* 665 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 666 * cases we get wrong values here, so ignore it. 667 */ 668 s = splbio(); 669 if ((sig & 0xffff0000) == 0xeb140000) { 670 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 671 } else 672 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 673 splx(s); 674 /* clear port interrupt register */ 675 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 676 /* and enable interrupts */ 677 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 678 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 679 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 680 AHCI_P_IX_DHRS); 681 /* wait 500ms before actually starting operations */ 682 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 683 break; 684 685 default: 686 break; 687 } 688 } 689 690 static void 691 ahci_setup_channel(struct ata_channel *chp) 692 { 693 return; 694 } 695 696 static int 697 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 698 { 699 struct ata_channel *chp = drvp->chnl_softc; 700 struct ata_xfer *xfer; 701 int ret; 702 int s; 703 704 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 705 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 706 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 707 DEBUG_XFERS); 708 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 709 ATAXF_NOSLEEP); 710 if (xfer == NULL) { 711 return ATACMD_TRY_AGAIN; 712 } 713 if (ata_c->flags & AT_POLL) 714 xfer->c_flags |= C_POLL; 715 if (ata_c->flags & AT_WAIT) 716 xfer->c_flags |= C_WAIT; 717 xfer->c_drive = drvp->drive; 718 xfer->c_databuf = ata_c->data; 719 xfer->c_bcount = ata_c->bcount; 720 xfer->c_cmd = ata_c; 721 xfer->c_start = ahci_cmd_start; 722 xfer->c_intr = ahci_cmd_complete; 723 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 724 s = splbio(); 725 ata_exec_xfer(chp, xfer); 726 #ifdef DIAGNOSTIC 727 if ((ata_c->flags & AT_POLL) != 0 && 728 (ata_c->flags & AT_DONE) == 0) 729 panic("ahci_exec_command: polled command not done"); 730 #endif 731 if (ata_c->flags & AT_DONE) { 732 ret = ATACMD_COMPLETE; 733 } else { 734 if (ata_c->flags & AT_WAIT) { 735 while ((ata_c->flags & AT_DONE) == 0) { 736 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 737 } 738 ret = ATACMD_COMPLETE; 739 } else { 740 ret = ATACMD_QUEUED; 741 } 742 } 743 splx(s); 744 return ret; 745 } 746 747 static void 748 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 749 { 750 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 751 struct ahci_channel *achp = (struct ahci_channel *)chp; 752 struct ata_command *ata_c = xfer->c_cmd; 753 int slot = 0 /* XXX slot */; 754 struct ahci_cmd_tbl *cmd_tbl; 755 struct ahci_cmd_header *cmd_h; 756 int i; 757 int channel = chp->ch_channel; 758 759 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 760 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 761 762 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 763 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 764 cmd_tbl), DEBUG_XFERS); 765 766 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis); 767 768 cmd_h = &achp->ahcic_cmdh[slot]; 769 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 770 chp->ch_channel, cmd_h), DEBUG_XFERS); 771 if (ahci_dma_setup(chp, slot, 772 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 773 ata_c->data : NULL, 774 ata_c->bcount, 775 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 776 ata_c->flags |= AT_DF; 777 ahci_cmd_complete(chp, xfer, slot); 778 return; 779 } 780 cmd_h->cmdh_flags = htole16( 781 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 782 RHD_FISLEN / 4); 783 cmd_h->cmdh_prdbc = 0; 784 AHCI_CMDH_SYNC(sc, achp, slot, 785 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 786 787 if (ata_c->flags & AT_POLL) { 788 /* polled command, disable interrupts */ 789 AHCI_WRITE(sc, AHCI_GHC, 790 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 791 } 792 chp->ch_flags |= ATACH_IRQ_WAIT; 793 chp->ch_status = 0; 794 /* start command */ 795 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 796 /* and says we started this command */ 797 achp->ahcic_cmds_active |= 1 << slot; 798 799 if ((ata_c->flags & AT_POLL) == 0) { 800 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 801 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 802 ahci_timeout, chp); 803 return; 804 } 805 /* 806 * Polled command. 807 */ 808 for (i = 0; i < ata_c->timeout / 10; i++) { 809 if (ata_c->flags & AT_DONE) 810 break; 811 ahci_intr_port(sc, achp); 812 if (ata_c->flags & AT_WAIT) 813 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 814 else 815 delay(10000); 816 } 817 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 818 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 819 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 820 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 821 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 822 DEBUG_XFERS); 823 if ((ata_c->flags & AT_DONE) == 0) { 824 ata_c->flags |= AT_TIMEOU; 825 ahci_cmd_complete(chp, xfer, slot); 826 } 827 /* reenable interrupts */ 828 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 829 } 830 831 static void 832 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 833 { 834 struct ata_command *ata_c = xfer->c_cmd; 835 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 836 DEBUG_FUNCS); 837 838 switch (reason) { 839 case KILL_GONE: 840 ata_c->flags |= AT_GONE; 841 break; 842 case KILL_RESET: 843 ata_c->flags |= AT_RESET; 844 break; 845 default: 846 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 847 panic("ahci_cmd_kill_xfer"); 848 } 849 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 850 } 851 852 static int 853 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 854 { 855 int slot = 0; /* XXX slot */ 856 struct ata_command *ata_c = xfer->c_cmd; 857 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 858 struct ahci_channel *achp = (struct ahci_channel *)chp; 859 860 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 861 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 862 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 863 DEBUG_FUNCS); 864 chp->ch_flags &= ~ATACH_IRQ_WAIT; 865 if (xfer->c_flags & C_TIMEOU) { 866 ata_c->flags |= AT_TIMEOU; 867 } else 868 callout_stop(&chp->ch_callout); 869 870 chp->ch_queue->active_xfer = NULL; 871 872 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 873 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 874 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 875 wakeup(&chp->ch_queue->active_xfer); 876 return 0; 877 } 878 879 if (chp->ch_status & WDCS_BSY) { 880 ata_c->flags |= AT_TIMEOU; 881 } else if (chp->ch_status & WDCS_ERR) { 882 ata_c->r_error = chp->ch_error; 883 ata_c->flags |= AT_ERROR; 884 } 885 886 if (ata_c->flags & AT_READREG) 887 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis); 888 889 ahci_cmd_done(chp, xfer, slot); 890 return 0; 891 } 892 893 static void 894 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 895 { 896 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 897 struct ahci_channel *achp = (struct ahci_channel *)chp; 898 struct ata_command *ata_c = xfer->c_cmd; 899 uint16_t *idwordbuf; 900 int i; 901 902 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 903 DEBUG_FUNCS); 904 905 /* this comamnd is not active any more */ 906 achp->ahcic_cmds_active &= ~(1 << slot); 907 908 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 909 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 910 achp->ahcic_datad[slot]->dm_mapsize, 911 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 912 BUS_DMASYNC_POSTWRITE); 913 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 914 } 915 916 AHCI_CMDH_SYNC(sc, achp, slot, 917 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 918 919 /* ata(4) expects IDENTIFY data to be in host endianess */ 920 if (ata_c->r_command == WDCC_IDENTIFY || 921 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 922 idwordbuf = xfer->c_databuf; 923 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 924 idwordbuf[i] = le16toh(idwordbuf[i]); 925 } 926 } 927 928 ata_c->flags |= AT_DONE; 929 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 930 ata_c->flags |= AT_XFDONE; 931 932 ata_free_xfer(chp, xfer); 933 if (ata_c->flags & AT_WAIT) 934 wakeup(ata_c); 935 else if (ata_c->callback) 936 ata_c->callback(ata_c->callback_arg); 937 atastart(chp); 938 return; 939 } 940 941 static int 942 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 943 { 944 struct ata_channel *chp = drvp->chnl_softc; 945 struct ata_xfer *xfer; 946 947 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 948 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 949 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 950 DEBUG_XFERS); 951 xfer = ata_get_xfer(ATAXF_NOSLEEP); 952 if (xfer == NULL) { 953 return ATACMD_TRY_AGAIN; 954 } 955 if (ata_bio->flags & ATA_POLL) 956 xfer->c_flags |= C_POLL; 957 xfer->c_drive = drvp->drive; 958 xfer->c_cmd = ata_bio; 959 xfer->c_databuf = ata_bio->databuf; 960 xfer->c_bcount = ata_bio->bcount; 961 xfer->c_start = ahci_bio_start; 962 xfer->c_intr = ahci_bio_complete; 963 xfer->c_kill_xfer = ahci_bio_kill_xfer; 964 ata_exec_xfer(chp, xfer); 965 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 966 } 967 968 static void 969 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 970 { 971 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 972 struct ahci_channel *achp = (struct ahci_channel *)chp; 973 struct ata_bio *ata_bio = xfer->c_cmd; 974 int slot = 0 /* XXX slot */; 975 struct ahci_cmd_tbl *cmd_tbl; 976 struct ahci_cmd_header *cmd_h; 977 int i; 978 int channel = chp->ch_channel; 979 980 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 981 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 982 983 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 984 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 985 cmd_tbl), DEBUG_XFERS); 986 987 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis); 988 989 cmd_h = &achp->ahcic_cmdh[slot]; 990 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 991 chp->ch_channel, cmd_h), DEBUG_XFERS); 992 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 993 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 994 ata_bio->error = ERR_DMA; 995 ata_bio->r_error = 0; 996 ahci_bio_complete(chp, xfer, slot); 997 return; 998 } 999 cmd_h->cmdh_flags = htole16( 1000 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 1001 RHD_FISLEN / 4); 1002 cmd_h->cmdh_prdbc = 0; 1003 AHCI_CMDH_SYNC(sc, achp, slot, 1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1005 1006 if (xfer->c_flags & C_POLL) { 1007 /* polled command, disable interrupts */ 1008 AHCI_WRITE(sc, AHCI_GHC, 1009 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1010 } 1011 chp->ch_flags |= ATACH_IRQ_WAIT; 1012 chp->ch_status = 0; 1013 /* start command */ 1014 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1015 /* and says we started this command */ 1016 achp->ahcic_cmds_active |= 1 << slot; 1017 1018 if ((xfer->c_flags & C_POLL) == 0) { 1019 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1020 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1021 ahci_timeout, chp); 1022 return; 1023 } 1024 /* 1025 * Polled command. 1026 */ 1027 for (i = 0; i < ATA_DELAY / 10; i++) { 1028 if (ata_bio->flags & ATA_ITSDONE) 1029 break; 1030 ahci_intr_port(sc, achp); 1031 if (ata_bio->flags & ATA_NOSLEEP) 1032 delay(10000); 1033 else 1034 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1035 } 1036 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1037 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1038 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1039 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1040 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1041 DEBUG_XFERS); 1042 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1043 ata_bio->error = TIMEOUT; 1044 ahci_bio_complete(chp, xfer, slot); 1045 } 1046 /* reenable interrupts */ 1047 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1048 } 1049 1050 static void 1051 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1052 { 1053 int slot = 0; /* XXX slot */ 1054 int drive = xfer->c_drive; 1055 struct ata_bio *ata_bio = xfer->c_cmd; 1056 struct ahci_channel *achp = (struct ahci_channel *)chp; 1057 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1058 DEBUG_FUNCS); 1059 1060 achp->ahcic_cmds_active &= ~(1 << slot); 1061 ata_free_xfer(chp, xfer); 1062 ata_bio->flags |= ATA_ITSDONE; 1063 switch (reason) { 1064 case KILL_GONE: 1065 ata_bio->error = ERR_NODEV; 1066 break; 1067 case KILL_RESET: 1068 ata_bio->error = ERR_RESET; 1069 break; 1070 default: 1071 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1072 panic("ahci_bio_kill_xfer"); 1073 } 1074 ata_bio->r_error = WDCE_ABRT; 1075 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1076 } 1077 1078 static int 1079 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1080 { 1081 int slot = 0; /* XXX slot */ 1082 struct ata_bio *ata_bio = xfer->c_cmd; 1083 int drive = xfer->c_drive; 1084 struct ahci_channel *achp = (struct ahci_channel *)chp; 1085 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1086 1087 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1088 DEBUG_FUNCS); 1089 1090 achp->ahcic_cmds_active &= ~(1 << slot); 1091 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1092 if (xfer->c_flags & C_TIMEOU) { 1093 ata_bio->error = TIMEOUT; 1094 } else { 1095 callout_stop(&chp->ch_callout); 1096 ata_bio->error = NOERROR; 1097 } 1098 1099 chp->ch_queue->active_xfer = NULL; 1100 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1101 achp->ahcic_datad[slot]->dm_mapsize, 1102 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1103 BUS_DMASYNC_POSTWRITE); 1104 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1105 1106 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1107 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1108 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1109 wakeup(&chp->ch_queue->active_xfer); 1110 return 0; 1111 } 1112 ata_free_xfer(chp, xfer); 1113 ata_bio->flags |= ATA_ITSDONE; 1114 if (chp->ch_status & WDCS_DWF) { 1115 ata_bio->error = ERR_DF; 1116 } else if (chp->ch_status & WDCS_ERR) { 1117 ata_bio->error = ERROR; 1118 ata_bio->r_error = chp->ch_error; 1119 } else if (chp->ch_status & WDCS_CORR) 1120 ata_bio->flags |= ATA_CORR; 1121 1122 AHCI_CMDH_SYNC(sc, achp, slot, 1123 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1124 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1125 ata_bio->bcount), DEBUG_XFERS); 1126 /* 1127 * if it was a write, complete data buffer may have been transfered 1128 * before error detection; in this case don't use cmdh_prdbc 1129 * as it won't reflect what was written to media. Assume nothing 1130 * was transfered and leave bcount as-is. 1131 */ 1132 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1133 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1134 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1135 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1136 atastart(chp); 1137 return 0; 1138 } 1139 1140 static void 1141 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1142 { 1143 int i; 1144 /* stop channel */ 1145 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1146 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1147 /* wait 1s for channel to stop */ 1148 for (i = 0; i <100; i++) { 1149 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1150 == 0) 1151 break; 1152 if (flags & AT_WAIT) 1153 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1154 else 1155 delay(10000); 1156 } 1157 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1158 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1159 /* XXX controller reset ? */ 1160 return; 1161 } 1162 } 1163 1164 static void 1165 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1166 { 1167 /* clear error */ 1168 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1169 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1170 1171 /* and start controller */ 1172 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1173 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1174 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1175 } 1176 1177 static void 1178 ahci_timeout(void *v) 1179 { 1180 struct ata_channel *chp = (struct ata_channel *)v; 1181 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1182 int s = splbio(); 1183 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1184 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1185 xfer->c_flags |= C_TIMEOU; 1186 xfer->c_intr(chp, xfer, 0); 1187 } 1188 splx(s); 1189 } 1190 1191 static int 1192 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1193 size_t count, int op) 1194 { 1195 int error, seg; 1196 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1197 struct ahci_channel *achp = (struct ahci_channel *)chp; 1198 struct ahci_cmd_tbl *cmd_tbl; 1199 struct ahci_cmd_header *cmd_h; 1200 1201 cmd_h = &achp->ahcic_cmdh[slot]; 1202 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1203 1204 if (data == NULL) { 1205 cmd_h->cmdh_prdtl = 0; 1206 goto end; 1207 } 1208 1209 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1210 data, count, NULL, 1211 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1212 if (error) { 1213 printf("%s port %d: failed to load xfer: %d\n", 1214 AHCINAME(sc), chp->ch_channel, error); 1215 return error; 1216 } 1217 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1218 achp->ahcic_datad[slot]->dm_mapsize, 1219 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1220 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1221 cmd_tbl->cmdt_prd[seg].prd_dba = htole64( 1222 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1223 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1224 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1225 } 1226 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1227 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1228 end: 1229 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1230 return 0; 1231 } 1232 1233 #if NATAPIBUS > 0 1234 static void 1235 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1236 { 1237 struct ata_channel *chp = ata_sc->sc_chan; 1238 struct atac_softc *atac = chp->ch_atac; 1239 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1240 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1241 /* 1242 * Fill in the scsipi_adapter. 1243 */ 1244 adapt->adapt_dev = atac->atac_dev; 1245 adapt->adapt_nchannels = atac->atac_nchannels; 1246 adapt->adapt_request = ahci_atapi_scsipi_request; 1247 adapt->adapt_minphys = ahci_atapi_minphys; 1248 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1249 1250 /* 1251 * Fill in the scsipi_channel. 1252 */ 1253 memset(chan, 0, sizeof(*chan)); 1254 chan->chan_adapter = adapt; 1255 chan->chan_bustype = &ahci_atapi_bustype; 1256 chan->chan_channel = chp->ch_channel; 1257 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1258 chan->chan_openings = 1; 1259 chan->chan_max_periph = 1; 1260 chan->chan_ntargets = 1; 1261 chan->chan_nluns = 1; 1262 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1263 atapiprint); 1264 } 1265 1266 static void 1267 ahci_atapi_minphys(struct buf *bp) 1268 { 1269 if (bp->b_bcount > MAXPHYS) 1270 bp->b_bcount = MAXPHYS; 1271 minphys(bp); 1272 } 1273 1274 /* 1275 * Kill off all pending xfers for a periph. 1276 * 1277 * Must be called at splbio(). 1278 */ 1279 static void 1280 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1281 { 1282 struct atac_softc *atac = 1283 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1284 struct ata_channel *chp = 1285 atac->atac_channels[periph->periph_channel->chan_channel]; 1286 1287 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1288 } 1289 1290 static void 1291 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1292 scsipi_adapter_req_t req, void *arg) 1293 { 1294 struct scsipi_adapter *adapt = chan->chan_adapter; 1295 struct scsipi_periph *periph; 1296 struct scsipi_xfer *sc_xfer; 1297 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1298 struct atac_softc *atac = &sc->sc_atac; 1299 struct ata_xfer *xfer; 1300 int channel = chan->chan_channel; 1301 int drive, s; 1302 1303 switch (req) { 1304 case ADAPTER_REQ_RUN_XFER: 1305 sc_xfer = arg; 1306 periph = sc_xfer->xs_periph; 1307 drive = periph->periph_target; 1308 if (!device_is_active(atac->atac_dev)) { 1309 sc_xfer->error = XS_DRIVER_STUFFUP; 1310 scsipi_done(sc_xfer); 1311 return; 1312 } 1313 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1314 if (xfer == NULL) { 1315 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1316 scsipi_done(sc_xfer); 1317 return; 1318 } 1319 1320 if (sc_xfer->xs_control & XS_CTL_POLL) 1321 xfer->c_flags |= C_POLL; 1322 xfer->c_drive = drive; 1323 xfer->c_flags |= C_ATAPI; 1324 xfer->c_cmd = sc_xfer; 1325 xfer->c_databuf = sc_xfer->data; 1326 xfer->c_bcount = sc_xfer->datalen; 1327 xfer->c_start = ahci_atapi_start; 1328 xfer->c_intr = ahci_atapi_complete; 1329 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1330 xfer->c_dscpoll = 0; 1331 s = splbio(); 1332 ata_exec_xfer(atac->atac_channels[channel], xfer); 1333 #ifdef DIAGNOSTIC 1334 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1335 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1336 panic("ahci_atapi_scsipi_request: polled command " 1337 "not done"); 1338 #endif 1339 splx(s); 1340 return; 1341 default: 1342 /* Not supported, nothing to do. */ 1343 ; 1344 } 1345 } 1346 1347 static void 1348 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1349 { 1350 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1351 struct ahci_channel *achp = (struct ahci_channel *)chp; 1352 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1353 int slot = 0 /* XXX slot */; 1354 struct ahci_cmd_tbl *cmd_tbl; 1355 struct ahci_cmd_header *cmd_h; 1356 int i; 1357 int channel = chp->ch_channel; 1358 1359 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1360 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1361 1362 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1363 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1364 cmd_tbl), DEBUG_XFERS); 1365 1366 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis); 1367 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1368 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1369 1370 cmd_h = &achp->ahcic_cmdh[slot]; 1371 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1372 chp->ch_channel, cmd_h), DEBUG_XFERS); 1373 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1374 sc_xfer->datalen, 1375 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1376 BUS_DMA_READ : BUS_DMA_WRITE)) { 1377 sc_xfer->error = XS_DRIVER_STUFFUP; 1378 ahci_atapi_complete(chp, xfer, slot); 1379 return; 1380 } 1381 cmd_h->cmdh_flags = htole16( 1382 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1383 RHD_FISLEN / 4 | AHCI_CMDH_F_A); 1384 cmd_h->cmdh_prdbc = 0; 1385 AHCI_CMDH_SYNC(sc, achp, slot, 1386 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1387 1388 if (xfer->c_flags & C_POLL) { 1389 /* polled command, disable interrupts */ 1390 AHCI_WRITE(sc, AHCI_GHC, 1391 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1392 } 1393 chp->ch_flags |= ATACH_IRQ_WAIT; 1394 chp->ch_status = 0; 1395 /* start command */ 1396 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1397 /* and says we started this command */ 1398 achp->ahcic_cmds_active |= 1 << slot; 1399 1400 if ((xfer->c_flags & C_POLL) == 0) { 1401 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1402 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1403 ahci_timeout, chp); 1404 return; 1405 } 1406 /* 1407 * Polled command. 1408 */ 1409 for (i = 0; i < ATA_DELAY / 10; i++) { 1410 if (sc_xfer->xs_status & XS_STS_DONE) 1411 break; 1412 ahci_intr_port(sc, achp); 1413 delay(10000); 1414 } 1415 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1416 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1417 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1418 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1419 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1420 DEBUG_XFERS); 1421 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1422 sc_xfer->error = XS_TIMEOUT; 1423 ahci_atapi_complete(chp, xfer, slot); 1424 } 1425 /* reenable interrupts */ 1426 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1427 } 1428 1429 static int 1430 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1431 { 1432 int slot = 0; /* XXX slot */ 1433 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1434 int drive = xfer->c_drive; 1435 struct ahci_channel *achp = (struct ahci_channel *)chp; 1436 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1437 1438 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1439 DEBUG_FUNCS); 1440 1441 achp->ahcic_cmds_active &= ~(1 << slot); 1442 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1443 if (xfer->c_flags & C_TIMEOU) { 1444 sc_xfer->error = XS_TIMEOUT; 1445 } else { 1446 callout_stop(&chp->ch_callout); 1447 sc_xfer->error = 0; 1448 } 1449 1450 chp->ch_queue->active_xfer = NULL; 1451 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1452 achp->ahcic_datad[slot]->dm_mapsize, 1453 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1454 BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1456 1457 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1458 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1459 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1460 wakeup(&chp->ch_queue->active_xfer); 1461 return 0; 1462 } 1463 ata_free_xfer(chp, xfer); 1464 1465 AHCI_CMDH_SYNC(sc, achp, slot, 1466 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1467 sc_xfer->resid = sc_xfer->datalen; 1468 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1469 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1470 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1471 if (chp->ch_status & WDCS_ERR && 1472 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1473 sc_xfer->resid == sc_xfer->datalen)) { 1474 sc_xfer->error = XS_SHORTSENSE; 1475 sc_xfer->sense.atapi_sense = chp->ch_error; 1476 if ((sc_xfer->xs_periph->periph_quirks & 1477 PQUIRK_NOSENSE) == 0) { 1478 /* ask scsipi to send a REQUEST_SENSE */ 1479 sc_xfer->error = XS_BUSY; 1480 sc_xfer->status = SCSI_CHECK; 1481 } 1482 } 1483 scsipi_done(sc_xfer); 1484 atastart(chp); 1485 return 0; 1486 } 1487 1488 static void 1489 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1490 { 1491 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1492 struct ahci_channel *achp = (struct ahci_channel *)chp; 1493 int slot = 0; /* XXX slot */ 1494 1495 achp->ahcic_cmds_active &= ~(1 << slot); 1496 1497 /* remove this command from xfer queue */ 1498 switch (reason) { 1499 case KILL_GONE: 1500 sc_xfer->error = XS_DRIVER_STUFFUP; 1501 break; 1502 case KILL_RESET: 1503 sc_xfer->error = XS_RESET; 1504 break; 1505 default: 1506 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1507 panic("ahci_ata_atapi_kill_xfer"); 1508 } 1509 ata_free_xfer(chp, xfer); 1510 scsipi_done(sc_xfer); 1511 } 1512 1513 static void 1514 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1515 { 1516 struct scsipi_channel *chan = sc->sc_channel; 1517 struct scsipi_periph *periph; 1518 struct ataparams ids; 1519 struct ataparams *id = &ids; 1520 struct ahci_softc *ahcic = 1521 device_private(chan->chan_adapter->adapt_dev); 1522 struct atac_softc *atac = &ahcic->sc_atac; 1523 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1524 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1525 struct scsipibus_attach_args sa; 1526 char serial_number[21], model[41], firmware_revision[9]; 1527 int s; 1528 1529 /* skip if already attached */ 1530 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1531 return; 1532 1533 /* if no ATAPI device detected at attach time, skip */ 1534 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1535 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1536 "not present\n", target), DEBUG_PROBE); 1537 return; 1538 } 1539 1540 /* Some ATAPI devices need a bit more time after software reset. */ 1541 delay(5000); 1542 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1543 #ifdef ATAPI_DEBUG_PROBE 1544 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1545 AHCINAME(ahcic), target, 1546 id->atap_config & ATAPI_CFG_CMD_MASK, 1547 id->atap_config & ATAPI_CFG_DRQ_MASK); 1548 #endif 1549 periph = scsipi_alloc_periph(M_NOWAIT); 1550 if (periph == NULL) { 1551 aprint_error_dev(sc->sc_dev, 1552 "unable to allocate periph for drive %d\n", 1553 target); 1554 return; 1555 } 1556 periph->periph_dev = NULL; 1557 periph->periph_channel = chan; 1558 periph->periph_switch = &atapi_probe_periphsw; 1559 periph->periph_target = target; 1560 periph->periph_lun = 0; 1561 periph->periph_quirks = PQUIRK_ONLYBIG; 1562 1563 #ifdef SCSIPI_DEBUG 1564 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1565 SCSIPI_DEBUG_TARGET == target) 1566 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1567 #endif 1568 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1569 if (id->atap_config & ATAPI_CFG_REMOV) 1570 periph->periph_flags |= PERIPH_REMOVABLE; 1571 if (periph->periph_type == T_SEQUENTIAL) { 1572 s = splbio(); 1573 drvp->drive_flags |= DRIVE_ATAPIST; 1574 splx(s); 1575 } 1576 1577 sa.sa_periph = periph; 1578 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1579 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1580 T_REMOV : T_FIXED; 1581 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1582 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1583 20); 1584 scsipi_strvis((u_char *)firmware_revision, 8, 1585 id->atap_revision, 8); 1586 sa.sa_inqbuf.vendor = model; 1587 sa.sa_inqbuf.product = serial_number; 1588 sa.sa_inqbuf.revision = firmware_revision; 1589 1590 /* 1591 * Determine the operating mode capabilities of the device. 1592 */ 1593 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1594 periph->periph_cap |= PERIPH_CAP_CMD16; 1595 /* XXX This is gross. */ 1596 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1597 1598 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1599 1600 if (drvp->drv_softc) 1601 ata_probe_caps(drvp); 1602 else { 1603 s = splbio(); 1604 drvp->drive_flags &= ~DRIVE_ATAPI; 1605 splx(s); 1606 } 1607 } else { 1608 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1609 "failed for drive %s:%d:%d: error 0x%x\n", 1610 AHCINAME(ahcic), chp->ch_channel, target, 1611 chp->ch_error), DEBUG_PROBE); 1612 s = splbio(); 1613 drvp->drive_flags &= ~DRIVE_ATAPI; 1614 splx(s); 1615 } 1616 } 1617 #endif /* NATAPIBUS */ 1618