1 /* $NetBSD: ahcisata_core.c,v 1.15 2008/05/07 13:52:12 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.15 2008/05/07 13:52:12 bouyer Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include "atapibus.h" 54 55 #ifdef AHCI_DEBUG 56 int ahcidebug_mask = 0x0; 57 #endif 58 59 void ahci_probe_drive(struct ata_channel *); 60 void ahci_setup_channel(struct ata_channel *); 61 62 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 63 void ahci_reset_drive(struct ata_drive_datas *, int); 64 void ahci_reset_channel(struct ata_channel *, int); 65 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 66 int ahci_ata_addref(struct ata_drive_datas *); 67 void ahci_ata_delref(struct ata_drive_datas *); 68 void ahci_killpending(struct ata_drive_datas *); 69 70 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 71 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 72 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 73 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 74 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 75 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 76 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 77 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 78 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 79 void ahci_timeout(void *); 80 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 81 82 #if NATAPIBUS > 0 83 void ahci_atapibus_attach(struct atabus_softc *); 84 void ahci_atapi_kill_pending(struct scsipi_periph *); 85 void ahci_atapi_minphys(struct buf *); 86 void ahci_atapi_scsipi_request(struct scsipi_channel *, 87 scsipi_adapter_req_t, void *); 88 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 89 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 90 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 91 void ahci_atapi_probe_device(struct atapibus_softc *, int); 92 93 static const struct scsipi_bustype ahci_atapi_bustype = { 94 SCSIPI_BUSTYPE_ATAPI, 95 atapi_scsipi_cmd, 96 atapi_interpret_sense, 97 atapi_print_addr, 98 ahci_atapi_kill_pending, 99 }; 100 #endif /* NATAPIBUS */ 101 102 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 103 104 const struct ata_bustype ahci_ata_bustype = { 105 SCSIPI_BUSTYPE_ATA, 106 ahci_ata_bio, 107 ahci_reset_drive, 108 ahci_reset_channel, 109 ahci_exec_command, 110 ata_get_params, 111 ahci_ata_addref, 112 ahci_ata_delref, 113 ahci_killpending 114 }; 115 116 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 117 118 static void ahci_setup_port(struct ahci_softc *sc, int i); 119 120 int 121 ahci_reset(struct ahci_softc *sc) 122 { 123 int i; 124 125 /* reset controller */ 126 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 127 /* wait up to 1s for reset to complete */ 128 for (i = 0; i < 1000; i++) { 129 delay(1000); 130 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 131 break; 132 } 133 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 134 aprint_error("%s: reset failed\n", AHCINAME(sc)); 135 return -1; 136 } 137 /* enable ahci mode */ 138 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 139 return 0; 140 } 141 142 void 143 ahci_setup_ports(struct ahci_softc *sc) 144 { 145 u_int32_t ahci_ports; 146 int i, port; 147 148 ahci_ports = AHCI_READ(sc, AHCI_PI); 149 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 150 if ((ahci_ports & (1 << i)) == 0) 151 continue; 152 if (port >= sc->sc_atac.atac_nchannels) { 153 aprint_error("%s: more ports than announced\n", 154 AHCINAME(sc)); 155 break; 156 } 157 ahci_setup_port(sc, i); 158 } 159 } 160 161 void 162 ahci_reprobe_drives(struct ahci_softc *sc) 163 { 164 u_int32_t ahci_ports; 165 int i, port; 166 struct ahci_channel *achp; 167 struct ata_channel *chp; 168 169 ahci_ports = AHCI_READ(sc, AHCI_PI); 170 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 171 if ((ahci_ports & (1 << i)) == 0) 172 continue; 173 if (port >= sc->sc_atac.atac_nchannels) { 174 aprint_error("%s: more ports than announced\n", 175 AHCINAME(sc)); 176 break; 177 } 178 achp = &sc->sc_channels[i]; 179 chp = &achp->ata_channel; 180 181 ahci_probe_drive(chp); 182 } 183 } 184 185 static void 186 ahci_setup_port(struct ahci_softc *sc, int i) 187 { 188 struct ahci_channel *achp; 189 190 achp = &sc->sc_channels[i]; 191 192 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 193 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 194 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 195 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 196 } 197 198 void 199 ahci_enable_intrs(struct ahci_softc *sc) 200 { 201 202 /* clear interrupts */ 203 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 204 /* enable interrupts */ 205 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 206 } 207 208 void 209 ahci_attach(struct ahci_softc *sc) 210 { 211 u_int32_t ahci_cap, ahci_rev, ahci_ports; 212 int i, j, port; 213 struct ahci_channel *achp; 214 struct ata_channel *chp; 215 int error; 216 bus_dma_segment_t seg; 217 int rseg; 218 int dmasize; 219 void *cmdhp; 220 void *cmdtblp; 221 222 if (ahci_reset(sc) != 0) 223 return; 224 225 ahci_cap = AHCI_READ(sc, AHCI_CAP); 226 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 227 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 228 ahci_rev = AHCI_READ(sc, AHCI_VS); 229 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 230 switch(ahci_rev) { 231 case AHCI_VS_10: 232 aprint_normal("1.0"); 233 break; 234 case AHCI_VS_11: 235 aprint_normal("1.1"); 236 break; 237 case AHCI_VS_12: 238 aprint_normal("1.2"); 239 break; 240 default: 241 aprint_normal("0x%x", ahci_rev); 242 break; 243 } 244 245 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 246 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 247 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 248 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 249 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 250 sc->sc_atac.atac_pio_cap = 4; 251 sc->sc_atac.atac_dma_cap = 2; 252 sc->sc_atac.atac_udma_cap = 6; 253 sc->sc_atac.atac_channels = sc->sc_chanarray; 254 sc->sc_atac.atac_probe = ahci_probe_drive; 255 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 256 sc->sc_atac.atac_set_modes = ahci_setup_channel; 257 #if NATAPIBUS > 0 258 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 259 #endif 260 261 dmasize = 262 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 263 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 264 &seg, 1, &rseg, BUS_DMA_NOWAIT); 265 if (error) { 266 aprint_error("%s: unable to allocate command header memory" 267 ", error=%d\n", AHCINAME(sc), error); 268 return; 269 } 270 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 271 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 272 if (error) { 273 aprint_error("%s: unable to map command header memory" 274 ", error=%d\n", AHCINAME(sc), error); 275 return; 276 } 277 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 278 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 279 if (error) { 280 aprint_error("%s: unable to create command header map" 281 ", error=%d\n", AHCINAME(sc), error); 282 return; 283 } 284 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 285 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 286 if (error) { 287 aprint_error("%s: unable to load command header map" 288 ", error=%d\n", AHCINAME(sc), error); 289 return; 290 } 291 sc->sc_cmd_hdr = cmdhp; 292 293 ahci_enable_intrs(sc); 294 295 ahci_ports = AHCI_READ(sc, AHCI_PI); 296 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 297 if ((ahci_ports & (1 << i)) == 0) 298 continue; 299 if (port >= sc->sc_atac.atac_nchannels) { 300 aprint_error("%s: more ports than announced\n", 301 AHCINAME(sc)); 302 break; 303 } 304 achp = &sc->sc_channels[i]; 305 chp = (struct ata_channel *)achp; 306 sc->sc_chanarray[i] = chp; 307 chp->ch_channel = i; 308 chp->ch_atac = &sc->sc_atac; 309 chp->ch_queue = malloc(sizeof(struct ata_queue), 310 M_DEVBUF, M_NOWAIT); 311 if (chp->ch_queue == NULL) { 312 aprint_error("%s port %d: can't allocate memory for " 313 "command queue", AHCINAME(sc), i); 314 break; 315 } 316 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 318 &seg, 1, &rseg, BUS_DMA_NOWAIT); 319 if (error) { 320 aprint_error("%s: unable to allocate command table " 321 "memory, error=%d\n", AHCINAME(sc), error); 322 break; 323 } 324 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 325 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error("%s: unable to map command table memory" 328 ", error=%d\n", AHCINAME(sc), error); 329 break; 330 } 331 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 332 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 333 if (error) { 334 aprint_error("%s: unable to create command table map" 335 ", error=%d\n", AHCINAME(sc), error); 336 break; 337 } 338 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 339 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error("%s: unable to load command table map" 342 ", error=%d\n", AHCINAME(sc), error); 343 break; 344 } 345 achp->ahcic_cmdh = (struct ahci_cmd_header *) 346 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 347 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 348 AHCI_CMDH_SIZE * port; 349 achp->ahcic_rfis = (struct ahci_r_fis *) 350 ((char *)cmdhp + 351 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 352 AHCI_RFIS_SIZE * port); 353 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 354 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 355 AHCI_RFIS_SIZE * port; 356 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 357 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 358 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 359 DEBUG_PROBE); 360 361 for (j = 0; j < sc->sc_ncmds; j++) { 362 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 363 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 364 achp->ahcic_bus_cmd_tbl[j] = 365 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 366 AHCI_CMDTBL_SIZE * j; 367 achp->ahcic_cmdh[j].cmdh_cmdtba = 368 htole32(achp->ahcic_bus_cmd_tbl[j]); 369 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 370 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 371 achp->ahcic_cmd_tbl[j], 372 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 373 /* The xfer DMA map */ 374 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 375 AHCI_NPRD, 0x400000 /* 4MB */, 0, 376 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 377 &achp->ahcic_datad[j]); 378 if (error) { 379 aprint_error("%s: couldn't alloc xfer DMA map, " 380 "error=%d\n", AHCINAME(sc), error); 381 goto end; 382 } 383 } 384 ahci_setup_port(sc, i); 385 chp->ch_ndrive = 1; 386 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 387 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 388 aprint_error("%s: couldn't map channel %d " 389 "sata_status regs\n", AHCINAME(sc), i); 390 break; 391 } 392 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 393 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 394 aprint_error("%s: couldn't map channel %d " 395 "sata_control regs\n", AHCINAME(sc), i); 396 break; 397 } 398 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 399 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 400 aprint_error("%s: couldn't map channel %d " 401 "sata_error regs\n", AHCINAME(sc), i); 402 break; 403 } 404 ata_channel_attach(chp); 405 port++; 406 end: 407 continue; 408 } 409 } 410 411 int 412 ahci_intr(void *v) 413 { 414 struct ahci_softc *sc = v; 415 u_int32_t is; 416 int i, r = 0; 417 418 while ((is = AHCI_READ(sc, AHCI_IS))) { 419 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 420 DEBUG_INTR); 421 r = 1; 422 AHCI_WRITE(sc, AHCI_IS, is); 423 for (i = 0; i < AHCI_MAX_PORTS; i++) 424 if (is & (1 << i)) 425 ahci_intr_port(sc, &sc->sc_channels[i]); 426 } 427 return r; 428 } 429 430 void 431 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 432 { 433 u_int32_t is, tfd; 434 struct ata_channel *chp = &achp->ata_channel; 435 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 436 int slot; 437 438 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 439 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 440 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 441 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 442 DEBUG_INTR); 443 444 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 445 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 446 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 447 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 448 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 449 return; 450 /* stop channel */ 451 ahci_channel_stop(sc, chp, 0); 452 if (slot != 0) { 453 printf("ahci_intr_port: slot %d\n", slot); 454 panic("ahci_intr_port"); 455 } 456 if (is & AHCI_P_IX_TFES) { 457 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 458 chp->ch_error = 459 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 460 chp->ch_status = (tfd & 0xff); 461 } else { 462 /* emulate a CRC error */ 463 chp->ch_error = WDCE_CRC; 464 chp->ch_status = WDCS_ERR; 465 } 466 xfer->c_intr(chp, xfer, is); 467 /* if channel has not been restarted, do it now */ 468 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 469 == 0) 470 ahci_channel_start(sc, chp); 471 } else { 472 slot = 0; /* XXX */ 473 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 474 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 475 chp->ch_channel, is, achp->ahcic_cmds_active, 476 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 477 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 478 return; 479 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 480 == 0) { 481 xfer->c_intr(chp, xfer, 0); 482 } 483 } 484 } 485 486 void 487 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 488 { 489 struct ata_channel *chp = drvp->chnl_softc; 490 ata_reset_channel(chp, flags); 491 return; 492 } 493 494 void 495 ahci_reset_channel(struct ata_channel *chp, int flags) 496 { 497 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 498 struct ahci_channel *achp = (struct ahci_channel *)chp; 499 500 ahci_channel_stop(sc, chp, flags); 501 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 502 achp->ahcic_sstatus) != SStatus_DET_DEV) { 503 printf("%s: port reset failed\n", AHCINAME(sc)); 504 /* XXX and then ? */ 505 } 506 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 507 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 508 if (chp->ch_queue->active_xfer) { 509 chp->ch_queue->active_xfer->c_kill_xfer(chp, 510 chp->ch_queue->active_xfer, KILL_RESET); 511 } 512 ahci_channel_start(sc, chp); 513 #if 0 514 /* Wait 15s for device to host FIS to arrive. */ 515 for (i = 0; i <1500; i++) { 516 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) & AHCI_P_IX_DHRS) 517 break; 518 if (flags & AT_WAIT) 519 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 520 else 521 delay (10000); 522 } 523 if (i == 1500) 524 aprint_error("%s port %d: D2H FIS never arrived\n", AHCINAME(sc)); 525 #endif 526 /* clear port interrupt register */ 527 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 528 529 return; 530 } 531 532 int 533 ahci_ata_addref(struct ata_drive_datas *drvp) 534 { 535 return 0; 536 } 537 538 void 539 ahci_ata_delref(struct ata_drive_datas *drvp) 540 { 541 return; 542 } 543 544 void 545 ahci_killpending(struct ata_drive_datas *drvp) 546 { 547 return; 548 } 549 550 void 551 ahci_probe_drive(struct ata_channel *chp) 552 { 553 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 554 struct ahci_channel *achp = (struct ahci_channel *)chp; 555 int i, s; 556 u_int32_t sig; 557 558 /* XXX This should be done by other code. */ 559 for (i = 0; i < chp->ch_ndrive; i++) { 560 chp->ch_drive[i].chnl_softc = chp; 561 chp->ch_drive[i].drive = i; 562 } 563 564 /* bring interface up, power up and spin up device */ 565 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 566 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 567 /* reset the PHY and bring online */ 568 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 569 achp->ahcic_sstatus)) { 570 case SStatus_DET_DEV: 571 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 572 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 573 #if 0 574 /* wait 15s for d2h FIS */ 575 for (i = 0; i <1500; i++) { 576 if (AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)) 577 & AHCI_P_IX_DHRS) 578 break; 579 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 580 } 581 if (i == 1500) 582 aprint_error("%s: D2H FIS never arrived\n", 583 AHCINAME(sc)); 584 #endif 585 586 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 587 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 588 AHCINAME(sc), chp->ch_channel, sig, 589 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 590 /* 591 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 592 * cases we get wrong values here, so ignore it. 593 */ 594 s = splbio(); 595 if ((sig & 0xffff0000) == 0xeb140000) { 596 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 597 } else 598 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 599 splx(s); 600 /* enable interrupts */ 601 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 602 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 603 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 604 AHCI_P_IX_DHRS); 605 /* and start operations */ 606 ahci_channel_start(sc, chp); 607 /* wait 100ms before actually starting operations */ 608 tsleep(&sc, PRIBIO, "ahciprb", mstohz(100)); 609 break; 610 611 default: 612 break; 613 } 614 } 615 616 void 617 ahci_setup_channel(struct ata_channel *chp) 618 { 619 return; 620 } 621 622 int 623 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 624 { 625 struct ata_channel *chp = drvp->chnl_softc; 626 struct ata_xfer *xfer; 627 int ret; 628 int s; 629 630 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 631 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 632 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 633 DEBUG_XFERS); 634 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 635 ATAXF_NOSLEEP); 636 if (xfer == NULL) { 637 return ATACMD_TRY_AGAIN; 638 } 639 if (ata_c->flags & AT_POLL) 640 xfer->c_flags |= C_POLL; 641 if (ata_c->flags & AT_WAIT) 642 xfer->c_flags |= C_WAIT; 643 xfer->c_drive = drvp->drive; 644 xfer->c_databuf = ata_c->data; 645 xfer->c_bcount = ata_c->bcount; 646 xfer->c_cmd = ata_c; 647 xfer->c_start = ahci_cmd_start; 648 xfer->c_intr = ahci_cmd_complete; 649 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 650 s = splbio(); 651 ata_exec_xfer(chp, xfer); 652 #ifdef DIAGNOSTIC 653 if ((ata_c->flags & AT_POLL) != 0 && 654 (ata_c->flags & AT_DONE) == 0) 655 panic("ahci_exec_command: polled command not done"); 656 #endif 657 if (ata_c->flags & AT_DONE) { 658 ret = ATACMD_COMPLETE; 659 } else { 660 if (ata_c->flags & AT_WAIT) { 661 while ((ata_c->flags & AT_DONE) == 0) { 662 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 663 } 664 ret = ATACMD_COMPLETE; 665 } else { 666 ret = ATACMD_QUEUED; 667 } 668 } 669 splx(s); 670 return ret; 671 } 672 673 void 674 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 675 { 676 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 677 struct ahci_channel *achp = (struct ahci_channel *)chp; 678 struct ata_command *ata_c = xfer->c_cmd; 679 int slot = 0 /* XXX slot */; 680 struct ahci_cmd_tbl *cmd_tbl; 681 struct ahci_cmd_header *cmd_h; 682 u_int8_t *fis; 683 int i; 684 int channel = chp->ch_channel; 685 686 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 687 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 688 689 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 690 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 691 cmd_tbl), DEBUG_XFERS); 692 fis = cmd_tbl->cmdt_cfis; 693 694 fis[0] = 0x27; /* host to device */ 695 fis[1] = 0x80; /* command FIS */ 696 fis[2] = ata_c->r_command; 697 fis[3] = ata_c->r_features; 698 fis[4] = ata_c->r_sector; 699 fis[5] = ata_c->r_cyl & 0xff; 700 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 701 fis[7] = ata_c->r_head & 0x0f; 702 fis[8] = 0; 703 fis[9] = 0; 704 fis[10] = 0; 705 fis[11] = 0; 706 fis[12] = ata_c->r_count; 707 fis[13] = 0; 708 fis[14] = 0; 709 fis[15] = WDCTL_4BIT; 710 fis[16] = 0; 711 fis[17] = 0; 712 fis[18] = 0; 713 fis[19] = 0; 714 715 cmd_h = &achp->ahcic_cmdh[slot]; 716 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 717 chp->ch_channel, cmd_h), DEBUG_XFERS); 718 if (ahci_dma_setup(chp, slot, 719 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL, 720 ata_c->bcount, 721 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 722 ata_c->flags |= AT_DF; 723 ahci_cmd_complete(chp, xfer, slot); 724 return; 725 } 726 cmd_h->cmdh_flags = htole16( 727 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 728 20 /* fis lenght */ / 4); 729 cmd_h->cmdh_prdbc = 0; 730 AHCI_CMDH_SYNC(sc, achp, slot, 731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732 733 if (ata_c->flags & AT_POLL) { 734 /* polled command, disable interrupts */ 735 AHCI_WRITE(sc, AHCI_GHC, 736 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 737 } 738 chp->ch_flags |= ATACH_IRQ_WAIT; 739 chp->ch_status = 0; 740 /* start command */ 741 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 742 /* and says we started this command */ 743 achp->ahcic_cmds_active |= 1 << slot; 744 745 if ((ata_c->flags & AT_POLL) == 0) { 746 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 747 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 748 ahci_timeout, chp); 749 return; 750 } 751 /* 752 * Polled command. 753 */ 754 for (i = 0; i < ata_c->timeout / 10; i++) { 755 if (ata_c->flags & AT_DONE) 756 break; 757 ahci_intr_port(sc, achp); 758 if (ata_c->flags & AT_WAIT) 759 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 760 else 761 delay(10000); 762 } 763 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 764 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 765 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 766 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 767 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 768 DEBUG_XFERS); 769 if ((ata_c->flags & AT_DONE) == 0) { 770 ata_c->flags |= AT_TIMEOU; 771 ahci_cmd_complete(chp, xfer, slot); 772 } 773 /* reenable interrupts */ 774 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 775 } 776 777 void 778 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 779 { 780 struct ata_command *ata_c = xfer->c_cmd; 781 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 782 DEBUG_FUNCS); 783 784 switch (reason) { 785 case KILL_GONE: 786 ata_c->flags |= AT_GONE; 787 break; 788 case KILL_RESET: 789 ata_c->flags |= AT_RESET; 790 break; 791 default: 792 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 793 panic("ahci_cmd_kill_xfer"); 794 } 795 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 796 } 797 798 int 799 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 800 { 801 int slot = 0; /* XXX slot */ 802 struct ata_command *ata_c = xfer->c_cmd; 803 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 804 805 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 806 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 807 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 808 DEBUG_FUNCS); 809 chp->ch_flags &= ~ATACH_IRQ_WAIT; 810 if (xfer->c_flags & C_TIMEOU) { 811 ata_c->flags |= AT_TIMEOU; 812 } else 813 callout_stop(&chp->ch_callout); 814 815 chp->ch_queue->active_xfer = NULL; 816 817 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 818 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 819 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 820 wakeup(&chp->ch_queue->active_xfer); 821 return 0; 822 } 823 if (is) { 824 ata_c->r_head = 0; 825 ata_c->r_count = 0; 826 ata_c->r_sector = 0; 827 ata_c->r_cyl = 0; 828 if (chp->ch_status & WDCS_BSY) { 829 ata_c->flags |= AT_TIMEOU; 830 } else if (chp->ch_status & WDCS_ERR) { 831 ata_c->r_error = chp->ch_error; 832 ata_c->flags |= AT_ERROR; 833 } 834 } 835 ahci_cmd_done(chp, xfer, slot); 836 return 0; 837 } 838 839 void 840 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 841 { 842 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 843 struct ahci_channel *achp = (struct ahci_channel *)chp; 844 struct ata_command *ata_c = xfer->c_cmd; 845 846 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 847 DEBUG_FUNCS); 848 849 /* this comamnd is not active any more */ 850 achp->ahcic_cmds_active &= ~(1 << slot); 851 852 if (ata_c->flags & (AT_READ|AT_WRITE)) { 853 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 854 achp->ahcic_datad[slot]->dm_mapsize, 855 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 856 BUS_DMASYNC_POSTWRITE); 857 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 858 } 859 860 AHCI_CMDH_SYNC(sc, achp, slot, 861 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 862 863 ata_c->flags |= AT_DONE; 864 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 865 ata_c->flags |= AT_XFDONE; 866 867 ata_free_xfer(chp, xfer); 868 if (ata_c->flags & AT_WAIT) 869 wakeup(ata_c); 870 else if (ata_c->callback) 871 ata_c->callback(ata_c->callback_arg); 872 atastart(chp); 873 return; 874 } 875 876 int 877 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 878 { 879 struct ata_channel *chp = drvp->chnl_softc; 880 struct ata_xfer *xfer; 881 882 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 883 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 884 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 885 DEBUG_XFERS); 886 xfer = ata_get_xfer(ATAXF_NOSLEEP); 887 if (xfer == NULL) { 888 return ATACMD_TRY_AGAIN; 889 } 890 if (ata_bio->flags & ATA_POLL) 891 xfer->c_flags |= C_POLL; 892 xfer->c_drive = drvp->drive; 893 xfer->c_cmd = ata_bio; 894 xfer->c_databuf = ata_bio->databuf; 895 xfer->c_bcount = ata_bio->bcount; 896 xfer->c_start = ahci_bio_start; 897 xfer->c_intr = ahci_bio_complete; 898 xfer->c_kill_xfer = ahci_bio_kill_xfer; 899 ata_exec_xfer(chp, xfer); 900 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 901 } 902 903 void 904 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 905 { 906 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 907 struct ahci_channel *achp = (struct ahci_channel *)chp; 908 struct ata_bio *ata_bio = xfer->c_cmd; 909 int slot = 0 /* XXX slot */; 910 struct ahci_cmd_tbl *cmd_tbl; 911 struct ahci_cmd_header *cmd_h; 912 u_int8_t *fis; 913 int i, nblks; 914 int channel = chp->ch_channel; 915 916 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 917 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 918 919 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 920 921 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 922 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 923 cmd_tbl), DEBUG_XFERS); 924 fis = cmd_tbl->cmdt_cfis; 925 926 fis[0] = 0x27; /* host to device */ 927 fis[1] = 0x80; /* command FIS */ 928 if (ata_bio->flags & ATA_LBA48) { 929 fis[2] = (ata_bio->flags & ATA_READ) ? 930 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 931 } else { 932 fis[2] = 933 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 934 } 935 fis[3] = 0; /* features */ 936 fis[4] = ata_bio->blkno & 0xff; 937 fis[5] = (ata_bio->blkno >> 8) & 0xff; 938 fis[6] = (ata_bio->blkno >> 16) & 0xff; 939 if (ata_bio->flags & ATA_LBA48) { 940 fis[7] = WDSD_LBA; 941 fis[8] = (ata_bio->blkno >> 24) & 0xff; 942 fis[9] = (ata_bio->blkno >> 32) & 0xff; 943 fis[10] = (ata_bio->blkno >> 40) & 0xff; 944 } else { 945 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 946 fis[8] = 0; 947 fis[9] = 0; 948 fis[10] = 0; 949 } 950 fis[11] = 0; /* ext features */ 951 fis[12] = nblks & 0xff; 952 fis[13] = (ata_bio->flags & ATA_LBA48) ? 953 ((nblks >> 8) & 0xff) : 0; 954 fis[14] = 0; 955 fis[15] = WDCTL_4BIT; 956 fis[16] = 0; 957 fis[17] = 0; 958 fis[18] = 0; 959 fis[19] = 0; 960 961 cmd_h = &achp->ahcic_cmdh[slot]; 962 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 963 chp->ch_channel, cmd_h), DEBUG_XFERS); 964 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 965 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 966 ata_bio->error = ERR_DMA; 967 ata_bio->r_error = 0; 968 ahci_bio_complete(chp, xfer, slot); 969 return; 970 } 971 cmd_h->cmdh_flags = htole16( 972 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 973 20 /* fis lenght */ / 4); 974 cmd_h->cmdh_prdbc = 0; 975 AHCI_CMDH_SYNC(sc, achp, slot, 976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 977 978 if (xfer->c_flags & C_POLL) { 979 /* polled command, disable interrupts */ 980 AHCI_WRITE(sc, AHCI_GHC, 981 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 982 } 983 chp->ch_flags |= ATACH_IRQ_WAIT; 984 chp->ch_status = 0; 985 /* start command */ 986 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 987 /* and says we started this command */ 988 achp->ahcic_cmds_active |= 1 << slot; 989 990 if ((xfer->c_flags & C_POLL) == 0) { 991 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 992 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 993 ahci_timeout, chp); 994 return; 995 } 996 /* 997 * Polled command. 998 */ 999 for (i = 0; i < ATA_DELAY / 10; i++) { 1000 if (ata_bio->flags & ATA_ITSDONE) 1001 break; 1002 ahci_intr_port(sc, achp); 1003 if (ata_bio->flags & ATA_NOSLEEP) 1004 delay(10000); 1005 else 1006 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1007 } 1008 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1009 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1010 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1011 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1012 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1013 DEBUG_XFERS); 1014 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1015 ata_bio->error = TIMEOUT; 1016 ahci_bio_complete(chp, xfer, slot); 1017 } 1018 /* reenable interrupts */ 1019 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1020 } 1021 1022 void 1023 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1024 { 1025 int slot = 0; /* XXX slot */ 1026 int drive = xfer->c_drive; 1027 struct ata_bio *ata_bio = xfer->c_cmd; 1028 struct ahci_channel *achp = (struct ahci_channel *)chp; 1029 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1030 DEBUG_FUNCS); 1031 1032 achp->ahcic_cmds_active &= ~(1 << slot); 1033 ata_free_xfer(chp, xfer); 1034 ata_bio->flags |= ATA_ITSDONE; 1035 switch (reason) { 1036 case KILL_GONE: 1037 ata_bio->error = ERR_NODEV; 1038 break; 1039 case KILL_RESET: 1040 ata_bio->error = ERR_RESET; 1041 break; 1042 default: 1043 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1044 panic("ahci_bio_kill_xfer"); 1045 } 1046 ata_bio->r_error = WDCE_ABRT; 1047 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1048 } 1049 1050 int 1051 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1052 { 1053 int slot = 0; /* XXX slot */ 1054 struct ata_bio *ata_bio = xfer->c_cmd; 1055 int drive = xfer->c_drive; 1056 struct ahci_channel *achp = (struct ahci_channel *)chp; 1057 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1058 1059 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1060 DEBUG_FUNCS); 1061 1062 achp->ahcic_cmds_active &= ~(1 << slot); 1063 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1064 if (xfer->c_flags & C_TIMEOU) { 1065 ata_bio->error = TIMEOUT; 1066 } else { 1067 callout_stop(&chp->ch_callout); 1068 ata_bio->error = 0; 1069 } 1070 1071 chp->ch_queue->active_xfer = NULL; 1072 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1073 achp->ahcic_datad[slot]->dm_mapsize, 1074 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1075 BUS_DMASYNC_POSTWRITE); 1076 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1077 1078 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1079 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1080 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1081 wakeup(&chp->ch_queue->active_xfer); 1082 return 0; 1083 } 1084 ata_free_xfer(chp, xfer); 1085 ata_bio->flags |= ATA_ITSDONE; 1086 if (chp->ch_status & WDCS_DWF) { 1087 ata_bio->error = ERR_DF; 1088 } else if (chp->ch_status & WDCS_ERR) { 1089 ata_bio->error = ERROR; 1090 ata_bio->r_error = chp->ch_error; 1091 } else if (chp->ch_status & WDCS_CORR) 1092 ata_bio->flags |= ATA_CORR; 1093 1094 AHCI_CMDH_SYNC(sc, achp, slot, 1095 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1096 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1097 ata_bio->bcount), DEBUG_XFERS); 1098 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1099 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1100 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1101 atastart(chp); 1102 return 0; 1103 } 1104 1105 void 1106 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1107 { 1108 int i; 1109 /* stop channel */ 1110 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1111 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1112 /* wait 1s for channel to stop */ 1113 for (i = 0; i <100; i++) { 1114 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1115 == 0) 1116 break; 1117 if (flags & AT_WAIT) 1118 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1119 else 1120 delay(10000); 1121 } 1122 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1123 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1124 /* XXX controller reset ? */ 1125 return; 1126 } 1127 } 1128 1129 void 1130 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1131 { 1132 /* clear error */ 1133 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 0); 1134 1135 /* and start controller */ 1136 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1137 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1138 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1139 } 1140 1141 void 1142 ahci_timeout(void *v) 1143 { 1144 struct ata_channel *chp = (struct ata_channel *)v; 1145 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1146 int s = splbio(); 1147 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1148 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1149 xfer->c_flags |= C_TIMEOU; 1150 xfer->c_intr(chp, xfer, 0); 1151 } 1152 splx(s); 1153 } 1154 1155 int 1156 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1157 size_t count, int op) 1158 { 1159 int error, seg; 1160 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1161 struct ahci_channel *achp = (struct ahci_channel *)chp; 1162 struct ahci_cmd_tbl *cmd_tbl; 1163 struct ahci_cmd_header *cmd_h; 1164 1165 cmd_h = &achp->ahcic_cmdh[slot]; 1166 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1167 1168 if (data == NULL) { 1169 cmd_h->cmdh_prdtl = 0; 1170 goto end; 1171 } 1172 1173 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1174 data, count, NULL, 1175 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1176 if (error) { 1177 printf("%s port %d: failed to load xfer: %d\n", 1178 AHCINAME(sc), chp->ch_channel, error); 1179 return error; 1180 } 1181 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1182 achp->ahcic_datad[slot]->dm_mapsize, 1183 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1184 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1185 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1186 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1187 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1188 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1189 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1190 } 1191 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1192 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1193 end: 1194 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1195 return 0; 1196 } 1197 1198 #if NATAPIBUS > 0 1199 void 1200 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1201 { 1202 struct ata_channel *chp = ata_sc->sc_chan; 1203 struct atac_softc *atac = chp->ch_atac; 1204 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1205 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1206 /* 1207 * Fill in the scsipi_adapter. 1208 */ 1209 adapt->adapt_dev = atac->atac_dev; 1210 adapt->adapt_nchannels = atac->atac_nchannels; 1211 adapt->adapt_request = ahci_atapi_scsipi_request; 1212 adapt->adapt_minphys = ahci_atapi_minphys; 1213 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1214 1215 /* 1216 * Fill in the scsipi_channel. 1217 */ 1218 memset(chan, 0, sizeof(*chan)); 1219 chan->chan_adapter = adapt; 1220 chan->chan_bustype = &ahci_atapi_bustype; 1221 chan->chan_channel = chp->ch_channel; 1222 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1223 chan->chan_openings = 1; 1224 chan->chan_max_periph = 1; 1225 chan->chan_ntargets = 1; 1226 chan->chan_nluns = 1; 1227 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1228 atapiprint); 1229 } 1230 1231 void 1232 ahci_atapi_minphys(struct buf *bp) 1233 { 1234 if (bp->b_bcount > MAXPHYS) 1235 bp->b_bcount = MAXPHYS; 1236 minphys(bp); 1237 } 1238 1239 /* 1240 * Kill off all pending xfers for a periph. 1241 * 1242 * Must be called at splbio(). 1243 */ 1244 void 1245 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1246 { 1247 struct atac_softc *atac = 1248 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1249 struct ata_channel *chp = 1250 atac->atac_channels[periph->periph_channel->chan_channel]; 1251 1252 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1253 } 1254 1255 void 1256 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1257 scsipi_adapter_req_t req, void *arg) 1258 { 1259 struct scsipi_adapter *adapt = chan->chan_adapter; 1260 struct scsipi_periph *periph; 1261 struct scsipi_xfer *sc_xfer; 1262 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1263 struct atac_softc *atac = &sc->sc_atac; 1264 struct ata_xfer *xfer; 1265 int channel = chan->chan_channel; 1266 int drive, s; 1267 1268 switch (req) { 1269 case ADAPTER_REQ_RUN_XFER: 1270 sc_xfer = arg; 1271 periph = sc_xfer->xs_periph; 1272 drive = periph->periph_target; 1273 if (!device_is_active(atac->atac_dev)) { 1274 sc_xfer->error = XS_DRIVER_STUFFUP; 1275 scsipi_done(sc_xfer); 1276 return; 1277 } 1278 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1279 if (xfer == NULL) { 1280 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1281 scsipi_done(sc_xfer); 1282 return; 1283 } 1284 1285 if (sc_xfer->xs_control & XS_CTL_POLL) 1286 xfer->c_flags |= C_POLL; 1287 xfer->c_drive = drive; 1288 xfer->c_flags |= C_ATAPI; 1289 xfer->c_cmd = sc_xfer; 1290 xfer->c_databuf = sc_xfer->data; 1291 xfer->c_bcount = sc_xfer->datalen; 1292 xfer->c_start = ahci_atapi_start; 1293 xfer->c_intr = ahci_atapi_complete; 1294 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1295 xfer->c_dscpoll = 0; 1296 s = splbio(); 1297 ata_exec_xfer(atac->atac_channels[channel], xfer); 1298 #ifdef DIAGNOSTIC 1299 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1300 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1301 panic("ahci_atapi_scsipi_request: polled command " 1302 "not done"); 1303 #endif 1304 splx(s); 1305 return; 1306 default: 1307 /* Not supported, nothing to do. */ 1308 ; 1309 } 1310 } 1311 1312 void 1313 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1314 { 1315 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1316 struct ahci_channel *achp = (struct ahci_channel *)chp; 1317 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1318 int slot = 0 /* XXX slot */; 1319 struct ahci_cmd_tbl *cmd_tbl; 1320 struct ahci_cmd_header *cmd_h; 1321 u_int8_t *fis; 1322 int i; 1323 int channel = chp->ch_channel; 1324 1325 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1326 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1327 1328 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1329 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1330 cmd_tbl), DEBUG_XFERS); 1331 fis = cmd_tbl->cmdt_cfis; 1332 1333 fis[0] = 0x27; /* host to device */ 1334 fis[1] = 0x80; /* command FIS */ 1335 fis[2] = ATAPI_PKT_CMD; 1336 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1337 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1338 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1339 fis[4] = 0; 1340 fis[5] = 0; 1341 fis[6] = 0; 1342 fis[7] = WDSD_LBA; 1343 fis[8] = 0; 1344 fis[9] = 0; 1345 fis[10] = 0; 1346 fis[11] = 0; /* ext features */ 1347 fis[12] = 0; 1348 fis[13] = 0; 1349 fis[14] = 0; 1350 fis[15] = WDCTL_4BIT; 1351 fis[16] = 0; 1352 fis[17] = 0; 1353 fis[18] = 0; 1354 fis[19] = 0; 1355 1356 cmd_h = &achp->ahcic_cmdh[slot]; 1357 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1358 chp->ch_channel, cmd_h), DEBUG_XFERS); 1359 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1360 sc_xfer->datalen, 1361 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1362 BUS_DMA_READ : BUS_DMA_WRITE)) { 1363 sc_xfer->error = XS_DRIVER_STUFFUP; 1364 ahci_atapi_complete(chp, xfer, slot); 1365 return; 1366 } 1367 cmd_h->cmdh_flags = htole16( 1368 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1369 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1370 cmd_h->cmdh_prdbc = 0; 1371 AHCI_CMDH_SYNC(sc, achp, slot, 1372 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1373 1374 if (xfer->c_flags & C_POLL) { 1375 /* polled command, disable interrupts */ 1376 AHCI_WRITE(sc, AHCI_GHC, 1377 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1378 } 1379 chp->ch_flags |= ATACH_IRQ_WAIT; 1380 chp->ch_status = 0; 1381 /* start command */ 1382 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1383 /* and says we started this command */ 1384 achp->ahcic_cmds_active |= 1 << slot; 1385 1386 if ((xfer->c_flags & C_POLL) == 0) { 1387 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1388 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1389 ahci_timeout, chp); 1390 return; 1391 } 1392 /* 1393 * Polled command. 1394 */ 1395 for (i = 0; i < ATA_DELAY / 10; i++) { 1396 if (sc_xfer->xs_status & XS_STS_DONE) 1397 break; 1398 ahci_intr_port(sc, achp); 1399 delay(10000); 1400 } 1401 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1402 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1403 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1404 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1405 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1406 DEBUG_XFERS); 1407 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1408 sc_xfer->error = XS_TIMEOUT; 1409 ahci_atapi_complete(chp, xfer, slot); 1410 } 1411 /* reenable interrupts */ 1412 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1413 } 1414 1415 int 1416 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1417 { 1418 int slot = 0; /* XXX slot */ 1419 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1420 int drive = xfer->c_drive; 1421 struct ahci_channel *achp = (struct ahci_channel *)chp; 1422 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1423 1424 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1425 DEBUG_FUNCS); 1426 1427 achp->ahcic_cmds_active &= ~(1 << slot); 1428 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1429 if (xfer->c_flags & C_TIMEOU) { 1430 sc_xfer->error = XS_TIMEOUT; 1431 } else { 1432 callout_stop(&chp->ch_callout); 1433 sc_xfer->error = 0; 1434 } 1435 1436 chp->ch_queue->active_xfer = NULL; 1437 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1438 achp->ahcic_datad[slot]->dm_mapsize, 1439 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1440 BUS_DMASYNC_POSTWRITE); 1441 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1442 1443 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1444 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1445 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1446 wakeup(&chp->ch_queue->active_xfer); 1447 return 0; 1448 } 1449 ata_free_xfer(chp, xfer); 1450 1451 if (chp->ch_status & WDCS_ERR) { 1452 sc_xfer->error = XS_SHORTSENSE; 1453 sc_xfer->sense.atapi_sense = chp->ch_error; 1454 } 1455 1456 AHCI_CMDH_SYNC(sc, achp, slot, 1457 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1458 sc_xfer->resid = sc_xfer->datalen; 1459 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1460 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1461 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1462 scsipi_done(sc_xfer); 1463 atastart(chp); 1464 return 0; 1465 } 1466 1467 void 1468 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1469 { 1470 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1471 struct ahci_channel *achp = (struct ahci_channel *)chp; 1472 int slot = 0; /* XXX slot */ 1473 1474 achp->ahcic_cmds_active &= ~(1 << slot); 1475 1476 /* remove this command from xfer queue */ 1477 switch (reason) { 1478 case KILL_GONE: 1479 sc_xfer->error = XS_DRIVER_STUFFUP; 1480 break; 1481 case KILL_RESET: 1482 sc_xfer->error = XS_RESET; 1483 break; 1484 default: 1485 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1486 panic("ahci_ata_atapi_kill_xfer"); 1487 } 1488 ata_free_xfer(chp, xfer); 1489 scsipi_done(sc_xfer); 1490 } 1491 1492 void 1493 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1494 { 1495 struct scsipi_channel *chan = sc->sc_channel; 1496 struct scsipi_periph *periph; 1497 struct ataparams ids; 1498 struct ataparams *id = &ids; 1499 struct ahci_softc *ahcic = 1500 device_private(chan->chan_adapter->adapt_dev); 1501 struct atac_softc *atac = &ahcic->sc_atac; 1502 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1503 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1504 struct scsipibus_attach_args sa; 1505 char serial_number[21], model[41], firmware_revision[9]; 1506 int s; 1507 1508 /* skip if already attached */ 1509 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1510 return; 1511 1512 /* if no ATAPI device detected at attach time, skip */ 1513 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1514 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1515 "not present\n", target), DEBUG_PROBE); 1516 return; 1517 } 1518 1519 /* Some ATAPI devices need a bit more time after software reset. */ 1520 delay(5000); 1521 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1522 #ifdef ATAPI_DEBUG_PROBE 1523 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1524 AHCINAME(ahcic), target, 1525 id->atap_config & ATAPI_CFG_CMD_MASK, 1526 id->atap_config & ATAPI_CFG_DRQ_MASK); 1527 #endif 1528 periph = scsipi_alloc_periph(M_NOWAIT); 1529 if (periph == NULL) { 1530 aprint_error_dev(sc->sc_dev, 1531 "unable to allocate periph for drive %d\n", 1532 target); 1533 return; 1534 } 1535 periph->periph_dev = NULL; 1536 periph->periph_channel = chan; 1537 periph->periph_switch = &atapi_probe_periphsw; 1538 periph->periph_target = target; 1539 periph->periph_lun = 0; 1540 periph->periph_quirks = PQUIRK_ONLYBIG; 1541 1542 #ifdef SCSIPI_DEBUG 1543 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1544 SCSIPI_DEBUG_TARGET == target) 1545 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1546 #endif 1547 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1548 if (id->atap_config & ATAPI_CFG_REMOV) 1549 periph->periph_flags |= PERIPH_REMOVABLE; 1550 if (periph->periph_type == T_SEQUENTIAL) { 1551 s = splbio(); 1552 drvp->drive_flags |= DRIVE_ATAPIST; 1553 splx(s); 1554 } 1555 1556 sa.sa_periph = periph; 1557 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1558 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1559 T_REMOV : T_FIXED; 1560 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1561 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1562 20); 1563 scsipi_strvis((u_char *)firmware_revision, 8, 1564 id->atap_revision, 8); 1565 sa.sa_inqbuf.vendor = model; 1566 sa.sa_inqbuf.product = serial_number; 1567 sa.sa_inqbuf.revision = firmware_revision; 1568 1569 /* 1570 * Determine the operating mode capabilities of the device. 1571 */ 1572 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1573 periph->periph_cap |= PERIPH_CAP_CMD16; 1574 /* XXX This is gross. */ 1575 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1576 1577 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1578 1579 if (drvp->drv_softc) 1580 ata_probe_caps(drvp); 1581 else { 1582 s = splbio(); 1583 drvp->drive_flags &= ~DRIVE_ATAPI; 1584 splx(s); 1585 } 1586 } else { 1587 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1588 "failed for drive %s:%d:%d: error 0x%x\n", 1589 AHCINAME(ahcic), chp->ch_channel, target, 1590 chp->ch_error), DEBUG_PROBE); 1591 s = splbio(); 1592 drvp->drive_flags &= ~DRIVE_ATAPI; 1593 splx(s); 1594 } 1595 } 1596 #endif /* NATAPIBUS */ 1597