xref: /netbsd-src/sys/dev/ic/adw.h (revision 1e72df6a037fdd3c6d3014a2679ffff7daab84ca)
1*1e72df6aStsutsui /*      $NetBSD: adw.h,v 1.15 2019/12/15 16:48:27 tsutsui Exp $        */
2da0a3e61Sdante 
3da0a3e61Sdante /*
4da0a3e61Sdante  * Generic driver definitions and exported functions for the Advanced
5da0a3e61Sdante  * Systems Inc. SCSI controllers
6da0a3e61Sdante  *
7cbacaf54Sdante  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
8da0a3e61Sdante  * All rights reserved.
9da0a3e61Sdante  *
10da0a3e61Sdante  * Author: Baldassare Dante Profeta <dante@mclink.it>
11da0a3e61Sdante  *
12da0a3e61Sdante  * Redistribution and use in source and binary forms, with or without
13da0a3e61Sdante  * modification, are permitted provided that the following conditions
14da0a3e61Sdante  * are met:
15da0a3e61Sdante  * 1. Redistributions of source code must retain the above copyright
16da0a3e61Sdante  *    notice, this list of conditions and the following disclaimer.
17da0a3e61Sdante  * 2. Redistributions in binary form must reproduce the above copyright
18da0a3e61Sdante  *    notice, this list of conditions and the following disclaimer in the
19da0a3e61Sdante  *    documentation and/or other materials provided with the distribution.
20da0a3e61Sdante  *
21da0a3e61Sdante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22da0a3e61Sdante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23da0a3e61Sdante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24da0a3e61Sdante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25da0a3e61Sdante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26da0a3e61Sdante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27da0a3e61Sdante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28da0a3e61Sdante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29da0a3e61Sdante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30da0a3e61Sdante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31da0a3e61Sdante  * POSSIBILITY OF SUCH DAMAGE.
32da0a3e61Sdante  */
33da0a3e61Sdante 
34da0a3e61Sdante #ifndef _ADVANSYS_WIDE_H_
35da0a3e61Sdante #define _ADVANSYS_WIDE_H_
36da0a3e61Sdante 
37da0a3e61Sdante /******************************************************************************/
38da0a3e61Sdante 
39da0a3e61Sdante typedef int (* ADW_ISR_CALLBACK) (ADW_SOFTC *, ADW_SCSI_REQ_Q *);
40cbacaf54Sdante typedef void (* ADW_ASYNC_CALLBACK) (ADW_SOFTC *, u_int8_t);
41cbacaf54Sdante 
42cbacaf54Sdante 
43cbacaf54Sdante /*
44eab52d94Sdante  * per request scatter-gather element limit
45eab52d94Sdante  * We could have up to 256 SG lists.
46eab52d94Sdante  */
47cbacaf54Sdante #define ADW_MAX_SG_LIST		255
48da0a3e61Sdante 
49da0a3e61Sdante /*
50da0a3e61Sdante  * Scatter-Gather Definitions per request.
51da0a3e61Sdante  */
52da0a3e61Sdante 
53da0a3e61Sdante #define NO_OF_SG_PER_BLOCK	15
54da0a3e61Sdante 
55da0a3e61Sdante /* Number of SG blocks needed. */
56da0a3e61Sdante #define ADW_NUM_SG_BLOCK \
57da0a3e61Sdante 	((ADW_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
58da0a3e61Sdante 
59da0a3e61Sdante 
60cbacaf54Sdante struct adw_ccb {
61da0a3e61Sdante 	ADW_SCSI_REQ_Q		scsiq;
62cbacaf54Sdante 	ADW_SG_BLOCK		sg_block[ADW_NUM_SG_BLOCK];
63cbacaf54Sdante 
64df9803ceSthorpej 	struct scsi_sense_data scsi_sense;
65da0a3e61Sdante 
66da0a3e61Sdante 	TAILQ_ENTRY(adw_ccb)	chain;
67eab52d94Sdante 	struct adw_ccb		*nexthash;
68a01d72e8Sthorpej 	u_int32_t		hashkey;
69cbacaf54Sdante 
70da0a3e61Sdante 	struct scsipi_xfer	*xs;	/* the scsipi_xfer for this cmd */
71da0a3e61Sdante 	int			flags;	/* see below */
72da0a3e61Sdante 
73da0a3e61Sdante 	int			timeout;
74da0a3e61Sdante 	/*
75da0a3e61Sdante 	 * This DMA map maps the buffer involved in the transfer.
76da0a3e61Sdante 	 */
77da0a3e61Sdante 	bus_dmamap_t		dmamap_xfer;
78da0a3e61Sdante };
79da0a3e61Sdante 
80da0a3e61Sdante typedef struct adw_ccb ADW_CCB;
81da0a3e61Sdante 
82da0a3e61Sdante /* flags for ADW_CCB */
83da0a3e61Sdante #define CCB_ALLOC	0x01
84afa103cfSdante #define CCB_ABORTING	0x02
85afa103cfSdante #define CCB_ABORTED	0x04
86da0a3e61Sdante 
87da0a3e61Sdante 
886644e670Sdante #define ADW_MAX_CCB	63	/* Max. number commands per device (63) */
89da0a3e61Sdante 
90cbacaf54Sdante struct adw_control {
91da0a3e61Sdante 	ADW_CCB		ccbs[ADW_MAX_CCB];	/* all our control blocks */
92cbacaf54Sdante 	ADW_CARRIER	*carriers;		/* all our carriers */
93da0a3e61Sdante };
94da0a3e61Sdante 
95da0a3e61Sdante /*
96da0a3e61Sdante  * Offset of a CCB from the beginning of the control DMA mapping.
97da0a3e61Sdante  */
98da0a3e61Sdante #define	ADW_CCB_OFF(c)	(offsetof(struct adw_control, ccbs[0]) +	\
99da0a3e61Sdante 		    (((u_long)(c)) - ((u_long)&sc->sc_control->ccbs[0])))
100da0a3e61Sdante 
101da0a3e61Sdante /******************************************************************************/
102da0a3e61Sdante 
10318db93c7Sperry int adw_init(ADW_SOFTC *);
10418db93c7Sperry void adw_attach(ADW_SOFTC *);
10518db93c7Sperry int adw_intr(void *);
10618db93c7Sperry ADW_CCB *adw_ccb_phys_kv(ADW_SOFTC *, u_int32_t);
107da0a3e61Sdante 
108da0a3e61Sdante /******************************************************************************/
109da0a3e61Sdante 
110da0a3e61Sdante #endif /* _ADVANSYS_ADW_H_ */
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