1 /* $NetBSD: adw.c,v 1.25 2000/06/28 17:12:50 mrg Exp $ */ 2 3 /* 4 * Generic driver for the Advanced Systems Inc. SCSI controllers 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante@mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/buf.h> 50 #include <sys/proc.h> 51 #include <sys/user.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/ic/adwlib.h> 63 #include <dev/ic/adwmcode.h> 64 #include <dev/ic/adw.h> 65 66 #ifndef DDB 67 #define Debugger() panic("should call debugger here (adw.c)") 68 #endif /* ! DDB */ 69 70 /******************************************************************************/ 71 72 73 static int adw_alloc_controls __P((ADW_SOFTC *)); 74 static int adw_alloc_carriers __P((ADW_SOFTC *)); 75 static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int)); 76 static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *)); 77 static void adw_reset_ccb __P((ADW_CCB *)); 78 static int adw_init_ccb __P((ADW_SOFTC *, ADW_CCB *)); 79 static ADW_CCB *adw_get_ccb __P((ADW_SOFTC *, int)); 80 static int adw_queue_ccb __P((ADW_SOFTC *, ADW_CCB *, int)); 81 82 static int adw_scsi_cmd __P((struct scsipi_xfer *)); 83 static int adw_build_req __P((struct scsipi_xfer *, ADW_CCB *, int)); 84 static void adw_build_sglist __P((ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *)); 85 static void adwminphys __P((struct buf *)); 86 static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 87 static void adw_async_callback __P((ADW_SOFTC *, u_int8_t)); 88 89 static void adw_print_info __P((ADW_SOFTC *, int)); 90 91 static int adw_poll __P((ADW_SOFTC *, struct scsipi_xfer *, int)); 92 static void adw_timeout __P((void *)); 93 static void adw_reset_bus __P((ADW_SOFTC *)); 94 95 96 /******************************************************************************/ 97 98 99 /* the below structure is so we have a default dev struct for our link struct */ 100 struct scsipi_device adw_dev = 101 { 102 NULL, /* Use default error handler */ 103 NULL, /* have a queue, served by this */ 104 NULL, /* have no async handler */ 105 NULL, /* Use default 'done' routine */ 106 }; 107 108 109 /******************************************************************************/ 110 /* DMA Mapping for Control Blocks */ 111 /******************************************************************************/ 112 113 114 static int 115 adw_alloc_controls(sc) 116 ADW_SOFTC *sc; 117 { 118 bus_dma_segment_t seg; 119 int error, rseg; 120 121 /* 122 * Allocate the control structure. 123 */ 124 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control), 125 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 126 printf("%s: unable to allocate control structures," 127 " error = %d\n", sc->sc_dev.dv_xname, error); 128 return (error); 129 } 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct adw_control), (caddr_t *) & sc->sc_control, 132 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 133 printf("%s: unable to map control structures, error = %d\n", 134 sc->sc_dev.dv_xname, error); 135 return (error); 136 } 137 138 /* 139 * Create and load the DMA map used for the control blocks. 140 */ 141 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control), 142 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT, 143 &sc->sc_dmamap_control)) != 0) { 144 printf("%s: unable to create control DMA map, error = %d\n", 145 sc->sc_dev.dv_xname, error); 146 return (error); 147 } 148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control, 149 sc->sc_control, sizeof(struct adw_control), NULL, 150 BUS_DMA_NOWAIT)) != 0) { 151 printf("%s: unable to load control DMA map, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 return (error); 154 } 155 156 return (0); 157 } 158 159 160 static int 161 adw_alloc_carriers(sc) 162 ADW_SOFTC *sc; 163 { 164 bus_dma_segment_t seg; 165 int error, rseg; 166 167 /* 168 * Allocate the control structure. 169 */ 170 sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 171 M_DEVBUF, M_WAITOK); 172 if(!sc->sc_control->carriers) { 173 printf("%s: malloc() failed in allocating carrier structures\n", 174 sc->sc_dev.dv_xname); 175 return (ENOMEM); 176 } 177 178 if ((error = bus_dmamem_alloc(sc->sc_dmat, 179 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 180 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 181 printf("%s: unable to allocate carrier structures," 182 " error = %d\n", sc->sc_dev.dv_xname, error); 183 return (error); 184 } 185 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 186 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 187 (caddr_t *) &sc->sc_control->carriers, 188 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 189 printf("%s: unable to map carrier structures," 190 " error = %d\n", sc->sc_dev.dv_xname, error); 191 return (error); 192 } 193 194 /* 195 * Create and load the DMA map used for the control blocks. 196 */ 197 if ((error = bus_dmamap_create(sc->sc_dmat, 198 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, 199 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, 200 &sc->sc_dmamap_carrier)) != 0) { 201 printf("%s: unable to create carriers DMA map," 202 " error = %d\n", sc->sc_dev.dv_xname, error); 203 return (error); 204 } 205 if ((error = bus_dmamap_load(sc->sc_dmat, 206 sc->sc_dmamap_carrier, sc->sc_control->carriers, 207 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, 208 BUS_DMA_NOWAIT)) != 0) { 209 printf("%s: unable to load carriers DMA map," 210 " error = %d\n", sc->sc_dev.dv_xname, error); 211 return (error); 212 } 213 214 return (0); 215 } 216 217 218 /******************************************************************************/ 219 /* Control Blocks routines */ 220 /******************************************************************************/ 221 222 223 /* 224 * Create a set of ccbs and add them to the free list. Called once 225 * by adw_init(). We return the number of CCBs successfully created. 226 */ 227 static int 228 adw_create_ccbs(sc, ccbstore, count) 229 ADW_SOFTC *sc; 230 ADW_CCB *ccbstore; 231 int count; 232 { 233 ADW_CCB *ccb; 234 int i, error; 235 236 for (i = 0; i < count; i++) { 237 ccb = &ccbstore[i]; 238 if ((error = adw_init_ccb(sc, ccb)) != 0) { 239 printf("%s: unable to initialize ccb, error = %d\n", 240 sc->sc_dev.dv_xname, error); 241 return (i); 242 } 243 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain); 244 } 245 246 return (i); 247 } 248 249 250 /* 251 * A ccb is put onto the free list. 252 */ 253 static void 254 adw_free_ccb(sc, ccb) 255 ADW_SOFTC *sc; 256 ADW_CCB *ccb; 257 { 258 int s; 259 260 s = splbio(); 261 262 adw_reset_ccb(ccb); 263 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain); 264 265 /* 266 * If there were none, wake anybody waiting for one to come free, 267 * starting with queued entries. 268 */ 269 if (ccb->chain.tqe_next == 0) 270 wakeup(&sc->sc_free_ccb); 271 272 splx(s); 273 } 274 275 276 static void 277 adw_reset_ccb(ccb) 278 ADW_CCB *ccb; 279 { 280 281 ccb->flags = 0; 282 } 283 284 285 static int 286 adw_init_ccb(sc, ccb) 287 ADW_SOFTC *sc; 288 ADW_CCB *ccb; 289 { 290 int hashnum, error; 291 292 /* 293 * Create the DMA map for this CCB. 294 */ 295 error = bus_dmamap_create(sc->sc_dmat, 296 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 297 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE, 298 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer); 299 if (error) { 300 printf("%s: unable to create CCB DMA map, error = %d\n", 301 sc->sc_dev.dv_xname, error); 302 return (error); 303 } 304 305 /* 306 * put in the phystokv hash table 307 * Never gets taken out. 308 */ 309 ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr + 310 ADW_CCB_OFF(ccb); 311 hashnum = CCB_HASH(ccb->hashkey); 312 ccb->nexthash = sc->sc_ccbhash[hashnum]; 313 sc->sc_ccbhash[hashnum] = ccb; 314 adw_reset_ccb(ccb); 315 return (0); 316 } 317 318 319 /* 320 * Get a free ccb 321 * 322 * If there are none, see if we can allocate a new one 323 */ 324 static ADW_CCB * 325 adw_get_ccb(sc, flags) 326 ADW_SOFTC *sc; 327 int flags; 328 { 329 ADW_CCB *ccb = 0; 330 int s; 331 332 s = splbio(); 333 334 /* 335 * If we can and have to, sleep waiting for one to come free 336 * but only if we can't allocate a new one. 337 */ 338 for (;;) { 339 ccb = sc->sc_free_ccb.tqh_first; 340 if (ccb) { 341 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain); 342 break; 343 } 344 if ((flags & XS_CTL_NOSLEEP) != 0) 345 goto out; 346 347 tsleep(&sc->sc_free_ccb, PRIBIO, "adwccb", 0); 348 } 349 350 ccb->flags |= CCB_ALLOC; 351 352 out: 353 splx(s); 354 return (ccb); 355 } 356 357 358 /* 359 * Given a physical address, find the ccb that it corresponds to. 360 */ 361 ADW_CCB * 362 adw_ccb_phys_kv(sc, ccb_phys) 363 ADW_SOFTC *sc; 364 u_int32_t ccb_phys; 365 { 366 int hashnum = CCB_HASH(ccb_phys); 367 ADW_CCB *ccb = sc->sc_ccbhash[hashnum]; 368 369 while (ccb) { 370 if (ccb->hashkey == ccb_phys) 371 break; 372 ccb = ccb->nexthash; 373 } 374 return (ccb); 375 } 376 377 378 /* 379 * Queue a CCB to be sent to the controller, and send it if possible. 380 */ 381 static int 382 adw_queue_ccb(sc, ccb, retry) 383 ADW_SOFTC *sc; 384 ADW_CCB *ccb; 385 int retry; 386 { 387 int errcode = ADW_SUCCESS; 388 389 if(!retry) { 390 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); 391 } 392 393 while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) { 394 395 errcode = AdwExeScsiQueue(sc, &ccb->scsiq); 396 switch(errcode) { 397 case ADW_SUCCESS: 398 break; 399 400 case ADW_BUSY: 401 printf("ADW_BUSY\n"); 402 return(ADW_BUSY); 403 404 case ADW_ERROR: 405 printf("ADW_ERROR\n"); 406 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 407 return(ADW_ERROR); 408 } 409 410 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); 411 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); 412 413 if ((ccb->xs->xs_control & XS_CTL_POLL) == 0) 414 callout_reset(&ccb->xs->xs_callout, 415 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 416 } 417 418 return(errcode); 419 } 420 421 422 /******************************************************************************/ 423 /* SCSI layer interfacing routines */ 424 /******************************************************************************/ 425 426 427 int 428 adw_init(sc) 429 ADW_SOFTC *sc; 430 { 431 u_int16_t warn_code; 432 433 434 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) | 435 ADW_LIB_VERSION_MINOR; 436 sc->cfg.chip_version = 437 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type); 438 439 /* 440 * Reset the chip to start and allow register writes. 441 */ 442 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { 443 panic("adw_init: adw_find_signature failed"); 444 } else { 445 AdwResetChip(sc->sc_iot, sc->sc_ioh); 446 447 warn_code = AdwInitFromEEPROM(sc); 448 449 if (warn_code & ADW_WARN_EEPROM_CHKSUM) 450 printf("%s: Bad checksum found. " 451 "Setting default values\n", 452 sc->sc_dev.dv_xname); 453 if (warn_code & ADW_WARN_EEPROM_TERMINATION) 454 printf("%s: Bad bus termination setting." 455 "Using automatic termination.\n", 456 sc->sc_dev.dv_xname); 457 } 458 459 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; 460 sc->async_callback = (ADW_CALLBACK) adw_async_callback; 461 462 return 0; 463 } 464 465 466 void 467 adw_attach(sc) 468 ADW_SOFTC *sc; 469 { 470 int i, error; 471 472 473 TAILQ_INIT(&sc->sc_free_ccb); 474 TAILQ_INIT(&sc->sc_waiting_ccb); 475 TAILQ_INIT(&sc->sc_pending_ccb); 476 TAILQ_INIT(&sc->sc_queue); 477 478 479 /* 480 * Allocate the Control Blocks. 481 */ 482 error = adw_alloc_controls(sc); 483 if (error) 484 return; /* (error) */ ; 485 486 bzero(sc->sc_control, sizeof(struct adw_control)); 487 488 /* 489 * Create and initialize the Control Blocks. 490 */ 491 i = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB); 492 if (i == 0) { 493 printf("%s: unable to create Control Blocks\n", 494 sc->sc_dev.dv_xname); 495 return; /* (ENOMEM) */ ; 496 } else if (i != ADW_MAX_CCB) { 497 printf("%s: WARNING: only %d of %d Control Blocks" 498 " created\n", 499 sc->sc_dev.dv_xname, i, ADW_MAX_CCB); 500 } 501 502 /* 503 * Create and initialize the Carriers. 504 */ 505 error = adw_alloc_carriers(sc); 506 if (error) 507 return; /* (error) */ ; 508 509 /* 510 * Zero's the freeze_device status 511 */ 512 bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); 513 514 /* 515 * Initialize the adapter 516 */ 517 switch (AdwInitDriver(sc)) { 518 case ADW_IERR_BIST_PRE_TEST: 519 panic("%s: BIST pre-test error", 520 sc->sc_dev.dv_xname); 521 break; 522 523 case ADW_IERR_BIST_RAM_TEST: 524 panic("%s: BIST RAM test error", 525 sc->sc_dev.dv_xname); 526 break; 527 528 case ADW_IERR_MCODE_CHKSUM: 529 panic("%s: Microcode checksum error", 530 sc->sc_dev.dv_xname); 531 break; 532 533 case ADW_IERR_ILLEGAL_CONNECTION: 534 panic("%s: All three connectors are in use", 535 sc->sc_dev.dv_xname); 536 break; 537 538 case ADW_IERR_REVERSED_CABLE: 539 panic("%s: Cable is reversed", 540 sc->sc_dev.dv_xname); 541 break; 542 543 case ADW_IERR_HVD_DEVICE: 544 panic("%s: HVD attached to LVD connector", 545 sc->sc_dev.dv_xname); 546 break; 547 548 case ADW_IERR_SINGLE_END_DEVICE: 549 panic("%s: single-ended device is attached to" 550 " one of the connectors", 551 sc->sc_dev.dv_xname); 552 break; 553 554 case ADW_IERR_NO_CARRIER: 555 panic("%s: unable to create Carriers", 556 sc->sc_dev.dv_xname); 557 break; 558 559 case ADW_WARN_BUSRESET_ERROR: 560 printf("%s: WARNING: Bus Reset Error\n", 561 sc->sc_dev.dv_xname); 562 break; 563 } 564 565 /* 566 * Fill in the adapter. 567 */ 568 sc->sc_adapter.scsipi_cmd = adw_scsi_cmd; 569 sc->sc_adapter.scsipi_minphys = adwminphys; 570 571 /* 572 * fill in the prototype scsipi_link. 573 */ 574 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 575 sc->sc_link.adapter_softc = sc; 576 sc->sc_link.scsipi_scsi.adapter_target = sc->chip_scsi_id; 577 sc->sc_link.adapter = &sc->sc_adapter; 578 sc->sc_link.device = &adw_dev; 579 sc->sc_link.openings = 4; 580 sc->sc_link.scsipi_scsi.max_target = ADW_MAX_TID; 581 sc->sc_link.scsipi_scsi.max_lun = 7; 582 sc->sc_link.type = BUS_SCSI; 583 584 585 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 586 } 587 588 589 static void 590 adwminphys(bp) 591 struct buf *bp; 592 { 593 594 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE)) 595 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE); 596 minphys(bp); 597 } 598 599 600 /* 601 * start a scsi operation given the command and the data address. 602 * Also needs the unit, target and lu. 603 */ 604 static int 605 adw_scsi_cmd(xs) 606 struct scsipi_xfer *xs; 607 { 608 struct scsipi_link *sc_link = xs->sc_link; 609 ADW_SOFTC *sc = sc_link->adapter_softc; 610 ADW_CCB *ccb; 611 int s, fromqueue = 1, dontqueue = 0, nowait = 0, retry = 0; 612 int flags; 613 614 s = splbio(); /* protect the queue */ 615 616 /* 617 * If we're running the queue from adw_done(), we've been 618 * called with the first queue entry as our argument. 619 */ 620 if (xs == TAILQ_FIRST(&sc->sc_queue)) { 621 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 622 splx(s); 623 return (TRY_AGAIN_LATER); 624 } 625 626 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 627 fromqueue = 1; 628 nowait = 1; 629 } else { 630 if(sc->sc_freeze_dev[xs->sc_link->scsipi_scsi.target]) { 631 splx(s); 632 xs->error = XS_DRIVER_STUFFUP; 633 return (TRY_AGAIN_LATER); 634 } 635 636 /* Polled requests can't be queued for later. */ 637 dontqueue = xs->xs_control & XS_CTL_POLL; 638 639 /* 640 * If there are jobs in the queue, run them first. 641 */ 642 if (TAILQ_FIRST(&sc->sc_queue) != NULL) { 643 /* 644 * If we can't queue, we have to abort, since 645 * we have to preserve order. 646 */ 647 if (dontqueue) { 648 splx(s); 649 xs->error = XS_DRIVER_STUFFUP; 650 return (TRY_AGAIN_LATER); 651 } 652 /* 653 * Swap with the first queue entry. 654 */ 655 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 656 xs = TAILQ_FIRST(&sc->sc_queue); 657 TAILQ_REMOVE(&sc->sc_queue, xs, adapter_q); 658 fromqueue = 1; 659 } 660 } 661 662 663 /* 664 * get a ccb to use. If the transfer 665 * is from a buf (possibly from interrupt time) 666 * then we can't allow it to sleep 667 */ 668 669 flags = xs->xs_control; 670 if (nowait) 671 flags |= XS_CTL_NOSLEEP; 672 if ((ccb = adw_get_ccb(sc, flags)) == NULL) { 673 /* 674 * If we can't queue, we lose. 675 */ 676 if (dontqueue) { 677 splx(s); 678 xs->error = XS_DRIVER_STUFFUP; 679 return (TRY_AGAIN_LATER); 680 } 681 /* 682 * Stuff ourselves into the queue, in front 683 * if we came off in the first place. 684 */ 685 if (fromqueue) 686 TAILQ_INSERT_HEAD(&sc->sc_queue, xs, adapter_q); 687 else 688 TAILQ_INSERT_TAIL(&sc->sc_queue, xs, adapter_q); 689 splx(s); 690 return (SUCCESSFULLY_QUEUED); 691 } 692 splx(s); /* done playing with the queue */ 693 694 ccb->xs = xs; 695 ccb->timeout = xs->timeout; 696 697 if (adw_build_req(xs, ccb, flags)) { 698 retryagain: 699 s = splbio(); 700 retry = adw_queue_ccb(sc, ccb, retry); 701 splx(s); 702 703 switch(retry) { 704 case ADW_BUSY: 705 goto retryagain; 706 707 case ADW_ERROR: 708 xs->error = XS_DRIVER_STUFFUP; 709 return (COMPLETE); 710 } 711 712 /* 713 * Usually return SUCCESSFULLY QUEUED 714 */ 715 if ((xs->xs_control & XS_CTL_POLL) == 0) 716 return (SUCCESSFULLY_QUEUED); 717 718 /* 719 * If we can't use interrupts, poll on completion 720 */ 721 if (adw_poll(sc, xs, ccb->timeout)) { 722 adw_timeout(ccb); 723 if (adw_poll(sc, xs, ccb->timeout)) 724 adw_timeout(ccb); 725 } 726 } 727 return (COMPLETE); 728 } 729 730 731 /* 732 * Build a request structure for the Wide Boards. 733 */ 734 static int 735 adw_build_req(xs, ccb, flags) 736 struct scsipi_xfer *xs; 737 ADW_CCB *ccb; 738 int flags; 739 { 740 struct scsipi_link *sc_link = xs->sc_link; 741 ADW_SOFTC *sc = sc_link->adapter_softc; 742 bus_dma_tag_t dmat = sc->sc_dmat; 743 ADW_SCSI_REQ_Q *scsiqp; 744 int error; 745 746 scsiqp = &ccb->scsiq; 747 bzero(scsiqp, sizeof(ADW_SCSI_REQ_Q)); 748 749 /* 750 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the 751 * physical CCB structure. 752 */ 753 scsiqp->ccb_ptr = ccb->hashkey; 754 755 /* 756 * Build the ADW_SCSI_REQ_Q request. 757 */ 758 759 /* 760 * Set CDB length and copy it to the request structure. 761 * For wide boards a CDB length maximum of 16 bytes 762 * is supported. 763 */ 764 bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)? 765 xs->cmdlen : 12 ); 766 if(xs->cmdlen > 12) 767 bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12); 768 769 scsiqp->target_id = sc_link->scsipi_scsi.target; 770 scsiqp->target_lun = sc_link->scsipi_scsi.lun; 771 772 scsiqp->vsense_addr = &ccb->scsi_sense; 773 scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 774 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); 775 scsiqp->sense_len = sizeof(struct scsipi_sense_data); 776 777 /* 778 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. 779 */ 780 if (xs->datalen) { 781 /* 782 * Map the DMA transfer. 783 */ 784 #ifdef TFS 785 if (xs->xs_control & SCSI_DATA_UIO) { 786 error = bus_dmamap_load_uio(dmat, 787 ccb->dmamap_xfer, (struct uio *) xs->data, 788 (flags & XS_CTL_NOSLEEP) ? 789 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 790 } else 791 #endif /* TFS */ 792 { 793 error = bus_dmamap_load(dmat, 794 ccb->dmamap_xfer, xs->data, xs->datalen, NULL, 795 (flags & XS_CTL_NOSLEEP) ? 796 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 797 } 798 799 if (error) { 800 if (error == EFBIG) { 801 printf("%s: adw_scsi_cmd, more than %d dma" 802 " segments\n", 803 sc->sc_dev.dv_xname, ADW_MAX_SG_LIST); 804 } else { 805 printf("%s: adw_scsi_cmd, error %d loading" 806 " dma map\n", 807 sc->sc_dev.dv_xname, error); 808 } 809 810 xs->error = XS_DRIVER_STUFFUP; 811 adw_free_ccb(sc, ccb); 812 return (0); 813 } 814 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 815 ccb->dmamap_xfer->dm_mapsize, 816 (xs->xs_control & XS_CTL_DATA_IN) ? 817 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 818 819 /* 820 * Build scatter-gather list. 821 */ 822 scsiqp->data_cnt = xs->datalen; 823 scsiqp->vdata_addr = xs->data; 824 scsiqp->data_addr = ccb->dmamap_xfer->dm_segs[0].ds_addr; 825 bzero(ccb->sg_block, sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK); 826 adw_build_sglist(ccb, scsiqp, ccb->sg_block); 827 } else { 828 /* 829 * No data xfer, use non S/G values. 830 */ 831 scsiqp->data_cnt = 0; 832 scsiqp->vdata_addr = 0; 833 scsiqp->data_addr = 0; 834 } 835 836 return (1); 837 } 838 839 840 /* 841 * Build scatter-gather list for Wide Boards. 842 */ 843 static void 844 adw_build_sglist(ccb, scsiqp, sg_block) 845 ADW_CCB *ccb; 846 ADW_SCSI_REQ_Q *scsiqp; 847 ADW_SG_BLOCK *sg_block; 848 { 849 u_long sg_block_next_addr; /* block and its next */ 850 u_int32_t sg_block_physical_addr; 851 int i; /* how many SG entries */ 852 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0]; 853 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs; 854 855 856 sg_block_next_addr = (u_long) sg_block; /* allow math operation */ 857 sg_block_physical_addr = ccb->hashkey + 858 offsetof(struct adw_ccb, sg_block[0]); 859 scsiqp->sg_real_addr = sg_block_physical_addr; 860 861 /* 862 * If there are more than NO_OF_SG_PER_BLOCK dma segments (hw sg-list) 863 * then split the request into multiple sg-list blocks. 864 */ 865 866 do { 867 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 868 sg_block->sg_list[i].sg_addr = sg_list->ds_addr; 869 sg_block->sg_list[i].sg_count = sg_list->ds_len; 870 871 if (--sg_elem_cnt == 0) { 872 /* last entry, get out */ 873 sg_block->sg_cnt = i + i; 874 sg_block->sg_ptr = NULL; /* next link = NULL */ 875 return; 876 } 877 sg_list++; 878 } 879 sg_block_next_addr += sizeof(ADW_SG_BLOCK); 880 sg_block_physical_addr += sizeof(ADW_SG_BLOCK); 881 882 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 883 sg_block->sg_ptr = sg_block_physical_addr; 884 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */ 885 } while (1); 886 } 887 888 889 /******************************************************************************/ 890 /* Interrupts and TimeOut routines */ 891 /******************************************************************************/ 892 893 894 int 895 adw_intr(arg) 896 void *arg; 897 { 898 ADW_SOFTC *sc = arg; 899 struct scsipi_xfer *xs; 900 901 902 if(AdwISR(sc) != ADW_FALSE) { 903 /* 904 * If there are queue entries in the software queue, try to 905 * run the first one. We should be more or less guaranteed 906 * to succeed, since we just freed a CCB. 907 * 908 * NOTE: adw_scsi_cmd() relies on our calling it with 909 * the first entry in the queue. 910 */ 911 if ((xs = TAILQ_FIRST(&sc->sc_queue)) != NULL) 912 (void) adw_scsi_cmd(xs); 913 914 return (1); 915 } 916 917 return (0); 918 } 919 920 921 /* 922 * Poll a particular unit, looking for a particular xs 923 */ 924 static int 925 adw_poll(sc, xs, count) 926 ADW_SOFTC *sc; 927 struct scsipi_xfer *xs; 928 int count; 929 { 930 931 /* timeouts are in msec, so we loop in 1000 usec cycles */ 932 while (count) { 933 adw_intr(sc); 934 if (xs->xs_status & XS_STS_DONE) 935 return (0); 936 delay(1000); /* only happens in boot so ok */ 937 count--; 938 } 939 return (1); 940 } 941 942 943 static void 944 adw_timeout(arg) 945 void *arg; 946 { 947 ADW_CCB *ccb = arg; 948 struct scsipi_xfer *xs = ccb->xs; 949 struct scsipi_link *sc_link = xs->sc_link; 950 ADW_SOFTC *sc = sc_link->adapter_softc; 951 int s; 952 953 scsi_print_addr(sc_link); 954 printf("timed out"); 955 956 s = splbio(); 957 958 if (ccb->flags & CCB_ABORTED) { 959 /* 960 * Abort Timed Out 961 * 962 * No more opportunities. Lets try resetting the bus and 963 * reinitialize the host adapter. 964 */ 965 callout_stop(&xs->xs_callout); 966 printf(" AGAIN. Resetting SCSI Bus\n"); 967 adw_reset_bus(sc); 968 splx(s); 969 return; 970 } else if (ccb->flags & CCB_ABORTING) { 971 /* 972 * Abort the operation that has timed out. 973 * 974 * Second opportunity. 975 */ 976 printf("\n"); 977 xs->error = XS_TIMEOUT; 978 ccb->flags |= CCB_ABORTED; 979 #if 0 980 /* 981 * - XXX - 3.3a microcode is BROKEN!!! 982 * 983 * We cannot abort a CCB, so we can only hope the command 984 * get completed before the next timeout, otherwise a 985 * Bus Reset will arrive inexorably. 986 */ 987 /* 988 * ADW_ABORT_CCB() makes the board to generate an interrupt 989 * 990 * - XXX - The above assertion MUST be verified (and this 991 * code changed as well [callout_*()]), when the 992 * ADW_ABORT_CCB will be working again 993 */ 994 ADW_ABORT_CCB(sc, ccb); 995 #endif 996 /* 997 * waiting for multishot callout_reset() let's restart it 998 * by hand so the next time a timeout event will occour 999 * we will reset the bus. 1000 */ 1001 callout_reset(&xs->xs_callout, 1002 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1003 } else { 1004 /* 1005 * Abort the operation that has timed out. 1006 * 1007 * First opportunity. 1008 */ 1009 printf("\n"); 1010 xs->error = XS_TIMEOUT; 1011 ccb->flags |= CCB_ABORTING; 1012 #if 0 1013 /* 1014 * - XXX - 3.3a microcode is BROKEN!!! 1015 * 1016 * We cannot abort a CCB, so we can only hope the command 1017 * get completed before the next 2 timeout, otherwise a 1018 * Bus Reset will arrive inexorably. 1019 */ 1020 /* 1021 * ADW_ABORT_CCB() makes the board to generate an interrupt 1022 * 1023 * - XXX - The above assertion MUST be verified (and this 1024 * code changed as well [callout_*()]), when the 1025 * ADW_ABORT_CCB will be working again 1026 */ 1027 ADW_ABORT_CCB(sc, ccb); 1028 #endif 1029 /* 1030 * waiting for multishot callout_reset() let's restart it 1031 * by hand so to give a second opportunity to the command 1032 * which timed-out. 1033 */ 1034 callout_reset(&xs->xs_callout, 1035 (ccb->timeout * hz) / 1000, adw_timeout, ccb); 1036 } 1037 1038 splx(s); 1039 } 1040 1041 1042 static void 1043 adw_reset_bus(sc) 1044 ADW_SOFTC *sc; 1045 { 1046 ADW_CCB *ccb; 1047 int s; 1048 1049 s = splbio(); 1050 AdwResetSCSIBus(sc); 1051 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, 1052 adw_pending_ccb)) != NULL) { 1053 callout_stop(&ccb->xs->xs_callout); 1054 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1055 TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); 1056 } 1057 adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); 1058 splx(s); 1059 } 1060 1061 1062 /******************************************************************************/ 1063 /* Host Adapter and Peripherals Information Routines */ 1064 /******************************************************************************/ 1065 1066 1067 static void 1068 adw_print_info(sc, tid) 1069 ADW_SOFTC *sc; 1070 int tid; 1071 { 1072 bus_space_tag_t iot = sc->sc_iot; 1073 bus_space_handle_t ioh = sc->sc_ioh; 1074 u_int16_t wdtr_able, wdtr_done, wdtr; 1075 u_int16_t sdtr_able, sdtr_done, sdtr, period; 1076 static int wdtr_reneg = 0, sdtr_reneg = 0; 1077 1078 if (tid == 0){ 1079 wdtr_reneg = sdtr_reneg = 0; 1080 } 1081 1082 printf("%s: target %d ", sc->sc_dev.dv_xname, tid); 1083 1084 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able); 1085 if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1086 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done); 1087 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1088 (2 * tid), wdtr); 1089 printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8); 1090 if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1091 wdtr_reneg = 1; 1092 } else { 1093 printf("wide transfers disabled, "); 1094 } 1095 1096 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1097 if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) { 1098 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done); 1099 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + 1100 (2 * tid), sdtr); 1101 sdtr &= ~0x8000; 1102 if((sdtr & 0x1F) != 0) { 1103 if((sdtr & 0x1F00) == 0x1100){ 1104 printf("80.0 MHz"); 1105 } else if((sdtr & 0x1F00) == 0x1000){ 1106 printf("40.0 MHz"); 1107 } else { 1108 /* <= 20.0 MHz */ 1109 period = (((sdtr >> 8) * 25) + 50)/4; 1110 if(period == 0) { 1111 /* Should never happen. */ 1112 printf("? MHz"); 1113 } else { 1114 printf("%d.%d MHz", 250/period, 1115 ADW_TENTHS(250, period)); 1116 } 1117 } 1118 printf(" synchronous transfers\n"); 1119 } else { 1120 printf("asynchronous transfers\n"); 1121 } 1122 if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) 1123 sdtr_reneg = 1; 1124 } else { 1125 printf("synchronous transfers disabled\n"); 1126 } 1127 1128 if(wdtr_reneg || sdtr_reneg) { 1129 printf("%s: target %d %s", sc->sc_dev.dv_xname, tid, 1130 (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") : 1131 ((sdtr_reneg)? "sync" : "") ); 1132 printf(" renegotiation pending before next command.\n"); 1133 } 1134 } 1135 1136 1137 /******************************************************************************/ 1138 /* WIDE boards Interrupt callbacks */ 1139 /******************************************************************************/ 1140 1141 1142 /* 1143 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() 1144 * 1145 * Interrupt callback function for the Wide SCSI Adv Library. 1146 * 1147 * Notice: 1148 * Interrupts are disabled by the caller (AdwISR() function), and will be 1149 * enabled at the end of the caller. 1150 */ 1151 static void 1152 adw_isr_callback(sc, scsiq) 1153 ADW_SOFTC *sc; 1154 ADW_SCSI_REQ_Q *scsiq; 1155 { 1156 bus_dma_tag_t dmat = sc->sc_dmat; 1157 ADW_CCB *ccb; 1158 struct scsipi_xfer *xs; 1159 struct scsipi_sense_data *s1, *s2; 1160 1161 1162 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1163 1164 callout_stop(&ccb->xs->xs_callout); 1165 1166 xs = ccb->xs; 1167 1168 /* 1169 * If we were a data transfer, unload the map that described 1170 * the data buffer. 1171 */ 1172 if (xs->datalen) { 1173 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0, 1174 ccb->dmamap_xfer->dm_mapsize, 1175 (xs->xs_control & XS_CTL_DATA_IN) ? 1176 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1177 bus_dmamap_unload(dmat, ccb->dmamap_xfer); 1178 } 1179 1180 if ((ccb->flags & CCB_ALLOC) == 0) { 1181 printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname); 1182 Debugger(); 1183 return; 1184 } 1185 1186 /* 1187 * 'done_status' contains the command's ending status. 1188 * 'host_status' conatins the host adapter status. 1189 * 'scsi_status' contains the scsi peripheral status. 1190 */ 1191 if ((scsiq->host_status == QHSTA_NO_ERROR) && 1192 ((scsiq->done_status == QD_NO_ERROR) || 1193 (scsiq->done_status == QD_WITH_ERROR))) { 1194 switch (scsiq->host_status) { 1195 case SCSI_STATUS_GOOD: 1196 if ((scsiq->cdb[0] == INQUIRY) && 1197 (scsiq->target_lun == 0)) { 1198 adw_print_info(sc, scsiq->target_id); 1199 } 1200 xs->error = XS_NOERROR; 1201 xs->resid = scsiq->data_cnt; 1202 sc->sc_freeze_dev[scsiq->target_id] = 0; 1203 break; 1204 1205 case SCSI_STATUS_CHECK_CONDITION: 1206 case SCSI_STATUS_CMD_TERMINATED: 1207 s1 = &ccb->scsi_sense; 1208 s2 = &xs->sense.scsi_sense; 1209 *s2 = *s1; 1210 xs->error = XS_SENSE; 1211 sc->sc_freeze_dev[scsiq->target_id] = 1; 1212 break; 1213 1214 default: 1215 xs->error = XS_BUSY; 1216 sc->sc_freeze_dev[scsiq->target_id] = 1; 1217 break; 1218 } 1219 } else if (scsiq->done_status == QD_ABORTED_BY_HOST) { 1220 xs->error = XS_DRIVER_STUFFUP; 1221 } else { 1222 switch (scsiq->host_status) { 1223 case QHSTA_M_SEL_TIMEOUT: 1224 xs->error = XS_SELTIMEOUT; 1225 break; 1226 1227 case QHSTA_M_SXFR_OFF_UFLW: 1228 case QHSTA_M_SXFR_OFF_OFLW: 1229 case QHSTA_M_DATA_OVER_RUN: 1230 printf("%s: Overrun/Overflow/Underflow condition\n", 1231 sc->sc_dev.dv_xname); 1232 xs->error = XS_DRIVER_STUFFUP; 1233 break; 1234 1235 case QHSTA_M_SXFR_DESELECTED: 1236 case QHSTA_M_UNEXPECTED_BUS_FREE: 1237 printf("%s: Unexpected BUS free\n",sc->sc_dev.dv_xname); 1238 xs->error = XS_DRIVER_STUFFUP; 1239 break; 1240 1241 case QHSTA_M_SCSI_BUS_RESET: 1242 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1243 printf("%s: BUS Reset\n", sc->sc_dev.dv_xname); 1244 xs->error = XS_DRIVER_STUFFUP; 1245 break; 1246 1247 case QHSTA_M_BUS_DEVICE_RESET: 1248 printf("%s: Device Reset\n", sc->sc_dev.dv_xname); 1249 xs->error = XS_DRIVER_STUFFUP; 1250 break; 1251 1252 case QHSTA_M_QUEUE_ABORTED: 1253 printf("%s: Queue Aborted\n", sc->sc_dev.dv_xname); 1254 xs->error = XS_DRIVER_STUFFUP; 1255 break; 1256 1257 case QHSTA_M_SXFR_SDMA_ERR: 1258 case QHSTA_M_SXFR_SXFR_PERR: 1259 case QHSTA_M_RDMA_PERR: 1260 /* 1261 * DMA Error. This should *NEVER* happen! 1262 * 1263 * Lets try resetting the bus and reinitialize 1264 * the host adapter. 1265 */ 1266 printf("%s: DMA Error. Reseting bus\n", 1267 sc->sc_dev.dv_xname); 1268 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1269 adw_reset_bus(sc); 1270 xs->error = XS_BUSY; 1271 goto done; 1272 1273 case QHSTA_M_WTM_TIMEOUT: 1274 case QHSTA_M_SXFR_WD_TMO: 1275 /* The SCSI bus hung in a phase */ 1276 printf("%s: Watch Dog timer expired. Reseting bus\n", 1277 sc->sc_dev.dv_xname); 1278 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1279 adw_reset_bus(sc); 1280 xs->error = XS_BUSY; 1281 goto done; 1282 1283 case QHSTA_M_SXFR_XFR_PH_ERR: 1284 printf("%s: Transfer Error\n", sc->sc_dev.dv_xname); 1285 xs->error = XS_DRIVER_STUFFUP; 1286 break; 1287 1288 case QHSTA_M_BAD_CMPL_STATUS_IN: 1289 /* No command complete after a status message */ 1290 printf("%s: Bad Completion Status\n", 1291 sc->sc_dev.dv_xname); 1292 xs->error = XS_DRIVER_STUFFUP; 1293 break; 1294 1295 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1296 printf("%s: Auto Sense Failed\n", sc->sc_dev.dv_xname); 1297 xs->error = XS_DRIVER_STUFFUP; 1298 break; 1299 1300 case QHSTA_M_INVALID_DEVICE: 1301 printf("%s: Invalid Device\n", sc->sc_dev.dv_xname); 1302 xs->error = XS_DRIVER_STUFFUP; 1303 break; 1304 1305 case QHSTA_M_NO_AUTO_REQ_SENSE: 1306 /* 1307 * User didn't request sense, but we got a 1308 * check condition. 1309 */ 1310 printf("%s: Unexpected Check Condition\n", 1311 sc->sc_dev.dv_xname); 1312 xs->error = XS_DRIVER_STUFFUP; 1313 break; 1314 1315 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1316 printf("%s: Unknown Error\n", sc->sc_dev.dv_xname); 1317 xs->error = XS_DRIVER_STUFFUP; 1318 break; 1319 1320 default: 1321 panic("%s: Unhandled Host Status Error %x", 1322 sc->sc_dev.dv_xname, scsiq->host_status); 1323 } 1324 } 1325 1326 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); 1327 done: adw_free_ccb(sc, ccb); 1328 xs->xs_status |= XS_STS_DONE; 1329 scsipi_done(xs); 1330 } 1331 1332 1333 /* 1334 * adw_async_callback() - Adv Library asynchronous event callback function. 1335 */ 1336 static void 1337 adw_async_callback(sc, code) 1338 ADW_SOFTC *sc; 1339 u_int8_t code; 1340 { 1341 switch (code) { 1342 case ADV_ASYNC_SCSI_BUS_RESET_DET: 1343 /* The firmware detected a SCSI Bus reset. */ 1344 printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); 1345 break; 1346 1347 case ADV_ASYNC_RDMA_FAILURE: 1348 /* 1349 * Handle RDMA failure by resetting the SCSI Bus and 1350 * possibly the chip if it is unresponsive. 1351 */ 1352 printf("%s: RDMA failure. Resetting the SCSI Bus and" 1353 " the adapter\n", sc->sc_dev.dv_xname); 1354 AdwResetSCSIBus(sc); 1355 break; 1356 1357 case ADV_HOST_SCSI_BUS_RESET: 1358 /* Host generated SCSI bus reset occurred. */ 1359 printf("%s: Host generated SCSI bus reset occurred\n", 1360 sc->sc_dev.dv_xname); 1361 break; 1362 1363 case ADV_ASYNC_CARRIER_READY_FAILURE: 1364 /* Carrier Ready failure. */ 1365 printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); 1366 break; 1367 1368 default: 1369 break; 1370 } 1371 } 1372