1 /* $NetBSD: x1226.c,v 1.23 2020/01/02 19:00:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.23 2020/01/02 19:00:34 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/x1226reg.h> 54 55 #include "ioconf.h" 56 57 struct xrtc_softc { 58 device_t sc_dev; 59 i2c_tag_t sc_tag; 60 int sc_address; 61 int sc_open; 62 struct todr_chip_handle sc_todr; 63 }; 64 65 static void xrtc_attach(device_t, device_t, void *); 66 static int xrtc_match(device_t, cfdata_t, void *); 67 68 CFATTACH_DECL_NEW(xrtc, sizeof(struct xrtc_softc), 69 xrtc_match, xrtc_attach, NULL, NULL); 70 71 dev_type_open(xrtc_open); 72 dev_type_close(xrtc_close); 73 dev_type_read(xrtc_read); 74 dev_type_write(xrtc_write); 75 76 const struct cdevsw xrtc_cdevsw = { 77 .d_open = xrtc_open, 78 .d_close = xrtc_close, 79 .d_read = xrtc_read, 80 .d_write = xrtc_write, 81 .d_ioctl = noioctl, 82 .d_stop = nostop, 83 .d_tty = notty, 84 .d_poll = nopoll, 85 .d_mmap = nommap, 86 .d_kqfilter = nokqfilter, 87 .d_discard = nodiscard, 88 .d_flag = D_OTHER 89 }; 90 91 static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *); 92 static int xrtc_gettime_ymdhms(struct todr_chip_handle *, 93 struct clock_ymdhms *); 94 static int xrtc_settime_ymdhms(struct todr_chip_handle *, 95 struct clock_ymdhms *); 96 97 /* 98 * xrtc_match() 99 */ 100 static int 101 xrtc_match(device_t parent, cfdata_t cf, void *arg) 102 { 103 struct i2c_attach_args *ia = arg; 104 105 /* match only this RTC devices */ 106 if (ia->ia_addr == X1226_ADDR) 107 return (I2C_MATCH_ADDRESS_ONLY); 108 109 return (0); 110 } 111 112 /* 113 * xrtc_attach() 114 */ 115 static void 116 xrtc_attach(device_t parent, device_t self, void *arg) 117 { 118 struct xrtc_softc *sc = device_private(self); 119 struct i2c_attach_args *ia = arg; 120 121 aprint_naive(": Real-time Clock/NVRAM\n"); 122 aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n"); 123 124 sc->sc_tag = ia->ia_tag; 125 sc->sc_address = ia->ia_addr; 126 sc->sc_dev = self; 127 sc->sc_open = 0; 128 sc->sc_todr.cookie = sc; 129 sc->sc_todr.todr_gettime = NULL; 130 sc->sc_todr.todr_settime = NULL; 131 sc->sc_todr.todr_gettime_ymdhms = xrtc_gettime_ymdhms; 132 sc->sc_todr.todr_settime_ymdhms = xrtc_settime_ymdhms; 133 sc->sc_todr.todr_setwen = NULL; 134 135 todr_attach(&sc->sc_todr); 136 } 137 138 139 /*ARGSUSED*/ 140 int 141 xrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 142 { 143 struct xrtc_softc *sc; 144 145 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 146 return (ENXIO); 147 148 /* XXX: Locking */ 149 150 if (sc->sc_open) 151 return (EBUSY); 152 153 sc->sc_open = 1; 154 return (0); 155 } 156 157 /*ARGSUSED*/ 158 int 159 xrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 160 { 161 struct xrtc_softc *sc; 162 163 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 164 return (ENXIO); 165 166 sc->sc_open = 0; 167 return (0); 168 } 169 170 /*ARGSUSED*/ 171 int 172 xrtc_read(dev_t dev, struct uio *uio, int flags) 173 { 174 struct xrtc_softc *sc; 175 u_int8_t ch, cmdbuf[2]; 176 int addr, error; 177 178 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 179 return (ENXIO); 180 181 if (uio->uio_offset >= X1226_NVRAM_SIZE) 182 return (EINVAL); 183 184 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 185 return (error); 186 187 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 188 addr = (int)uio->uio_offset + X1226_NVRAM_START; 189 cmdbuf[0] = (addr >> 8) & 0xff; 190 cmdbuf[1] = addr & 0xff; 191 if ((error = iic_exec(sc->sc_tag, 192 I2C_OP_READ_WITH_STOP, 193 sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) { 194 iic_release_bus(sc->sc_tag, 0); 195 aprint_error_dev(sc->sc_dev, 196 "xrtc_read: read failed at 0x%x\n", 197 (int)uio->uio_offset); 198 return (error); 199 } 200 if ((error = uiomove(&ch, 1, uio)) != 0) { 201 iic_release_bus(sc->sc_tag, 0); 202 return (error); 203 } 204 } 205 206 iic_release_bus(sc->sc_tag, 0); 207 208 return (0); 209 } 210 211 /*ARGSUSED*/ 212 int 213 xrtc_write(dev_t dev, struct uio *uio, int flags) 214 { 215 struct xrtc_softc *sc; 216 u_int8_t cmdbuf[3]; 217 int addr, error; 218 219 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 220 return (ENXIO); 221 222 if (uio->uio_offset >= X1226_NVRAM_SIZE) 223 return (EINVAL); 224 225 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 226 return (error); 227 228 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 229 addr = (int)uio->uio_offset + X1226_NVRAM_START; 230 cmdbuf[0] = (addr >> 8) & 0xff; 231 cmdbuf[1] = addr & 0xff; 232 if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) { 233 break; 234 } 235 if ((error = iic_exec(sc->sc_tag, 236 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 237 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 238 iic_release_bus(sc->sc_tag, 0); 239 aprint_error_dev(sc->sc_dev, 240 "xrtc_write: write failed at 0x%x\n", 241 (int)uio->uio_offset); 242 return (error); 243 } 244 } 245 246 iic_release_bus(sc->sc_tag, 0); 247 248 return (0); 249 } 250 251 252 static int 253 xrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 254 { 255 struct xrtc_softc *sc = ch->cookie; 256 struct clock_ymdhms check; 257 int retries; 258 int error; 259 260 memset(dt, 0, sizeof(*dt)); 261 memset(&check, 0, sizeof(check)); 262 263 retries = 5; 264 do { 265 if ((error = xrtc_clock_read(sc, dt)) == 0) 266 error = xrtc_clock_read(sc, &check); 267 if (error) 268 return error; 269 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 270 271 return (0); 272 } 273 274 static int 275 xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt) 276 { 277 int i = 0; 278 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2]; 279 int error; 280 281 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 282 aprint_error_dev(sc->sc_dev, 283 "xrtc_clock_read: failed to acquire I2C bus\n"); 284 return (error); 285 } 286 287 /* Read each RTC register in order */ 288 for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) { 289 int addr = i + X1226_REG_RTC_BASE; 290 cmdbuf[0] = (addr >> 8) & 0xff; 291 cmdbuf[1] = addr & 0xff; 292 293 if ((error = iic_exec(sc->sc_tag, 294 I2C_OP_READ_WITH_STOP, 295 sc->sc_address, cmdbuf, 2, 296 &bcd[i], 1, 0)) != 0) { 297 iic_release_bus(sc->sc_tag, 0); 298 aprint_error_dev(sc->sc_dev, 299 "xrtc_clock_read: failed to read rtc " 300 "at 0x%x\n", i); 301 return (error); 302 } 303 } 304 305 /* Done with I2C */ 306 iic_release_bus(sc->sc_tag, 0); 307 308 /* 309 * Convert the X1226's register bcd values 310 */ 311 dt->dt_sec = bcdtobin(bcd[X1226_REG_SC - X1226_REG_RTC_BASE] 312 & X1226_REG_SC_MASK); 313 dt->dt_min = bcdtobin(bcd[X1226_REG_MN - X1226_REG_RTC_BASE] 314 & X1226_REG_MN_MASK); 315 if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) { 316 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 317 & X1226_REG_HR12_MASK); 318 if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) { 319 dt->dt_hour += 12; 320 } 321 } else { 322 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 323 & X1226_REG_HR24_MASK); 324 } 325 dt->dt_wday = bcdtobin(bcd[X1226_REG_DW - X1226_REG_RTC_BASE] 326 & X1226_REG_DT_MASK); 327 dt->dt_day = bcdtobin(bcd[X1226_REG_DT - X1226_REG_RTC_BASE] 328 & X1226_REG_DT_MASK); 329 dt->dt_mon = bcdtobin(bcd[X1226_REG_MO - X1226_REG_RTC_BASE] 330 & X1226_REG_MO_MASK); 331 dt->dt_year = bcdtobin(bcd[X1226_REG_YR - X1226_REG_RTC_BASE] 332 & X1226_REG_YR_MASK); 333 dt->dt_year += bcdtobin(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] 334 & X1226_REG_Y2K_MASK) * 100; 335 336 return (0); 337 } 338 339 static int 340 xrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 341 { 342 struct xrtc_softc *sc = ch->cookie; 343 int i = 0, addr; 344 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3]; 345 int error, error2; 346 347 /* 348 * Convert our time to bcd values 349 */ 350 bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = bintobcd(dt->dt_sec); 351 bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = bintobcd(dt->dt_min); 352 bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_hour) 353 | X1226_FLAG_HR_24H; 354 bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = bintobcd(dt->dt_wday); 355 bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = bintobcd(dt->dt_day); 356 bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = bintobcd(dt->dt_mon); 357 bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year % 100); 358 bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year / 100); 359 360 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "xrtc_clock_write: failed to acquire I2C bus\n"); 363 return (error); 364 } 365 366 /* Unlock register: Write Enable Latch */ 367 addr = X1226_REG_SR; 368 cmdbuf[0] = ((addr >> 8) & 0xff); 369 cmdbuf[1] = (addr & 0xff); 370 cmdbuf[2] = X1226_FLAG_SR_WEL; 371 if ((error = iic_exec(sc->sc_tag, 372 I2C_OP_WRITE_WITH_STOP, 373 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 374 iic_release_bus(sc->sc_tag, 0); 375 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 376 "failed to write-unlock status register(WEL=1)\n"); 377 return (error); 378 } 379 380 /* Unlock register: Register Write Enable Latch */ 381 addr = X1226_REG_SR; 382 cmdbuf[0] = ((addr >> 8) & 0xff); 383 cmdbuf[1] = (addr & 0xff); 384 cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL; 385 if ((error = iic_exec(sc->sc_tag, 386 I2C_OP_WRITE_WITH_STOP, 387 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 388 iic_release_bus(sc->sc_tag, 0); 389 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 390 "failed to write-unlock status register(RWEL=1)\n"); 391 return (error); 392 } 393 394 /* Write each RTC register in reverse order */ 395 for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) { 396 addr = i + X1226_REG_RTC_BASE; 397 cmdbuf[0] = ((addr >> 8) & 0xff); 398 cmdbuf[1] = (addr & 0xff); 399 if ((error = iic_exec(sc->sc_tag, 400 I2C_OP_WRITE_WITH_STOP, 401 sc->sc_address, cmdbuf, 2, 402 &bcd[i], 1, 0)) != 0) { 403 404 aprint_error_dev(sc->sc_dev, 405 "xrtc_clock_write: failed to write rtc at 0x%x\n", 406 i); 407 408 goto write_lock_rtc; 409 } 410 } 411 412 write_lock_rtc: 413 /* Lock register: WEL/RWEL off */ 414 addr = X1226_REG_SR; 415 cmdbuf[0] = ((addr >> 8) & 0xff); 416 cmdbuf[1] = (addr & 0xff); 417 cmdbuf[2] = 0; 418 if ((error2 = iic_exec(sc->sc_tag, 419 I2C_OP_WRITE_WITH_STOP, 420 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 421 iic_release_bus(sc->sc_tag, 0); 422 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 423 "failed to write-lock status register\n"); 424 return (error ? error : error2); 425 } 426 427 iic_release_bus(sc->sc_tag, 0); 428 return (error); 429 } 430