1 /* $NetBSD: rkpmic.c,v 1.2 2018/09/20 09:02:46 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rkpmic.c,v 1.2 2018/09/20 09:02:46 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 40 #include <dev/i2c/i2cvar.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #define CHIP_NAME_REG 0x17 45 #define CHIP_VER_REG 0x18 46 47 struct rkpmic_ctrl { 48 const char * name; 49 uint8_t enable_reg; 50 uint8_t enable_mask; 51 uint8_t vsel_reg; 52 uint8_t vsel_mask; 53 u_int base; 54 u_int step; 55 u_int flags; 56 #define F_ENABLE_WRITE_MASK 0x00 57 }; 58 59 struct rkpmic_config { 60 const char * name; 61 const struct rkpmic_ctrl *ctrl; 62 u_int nctrl; 63 }; 64 65 static const struct rkpmic_ctrl rk805_ctrls[] = { 66 /* DCDC */ 67 { .name = "DCDC_REG1", .flags = F_ENABLE_WRITE_MASK, 68 .enable_reg = 0x23, .enable_mask = __BIT(0), 69 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0), 70 .base = 712500, .step = 12500 }, 71 { .name = "DCDC_REG2", .flags = F_ENABLE_WRITE_MASK, 72 .enable_reg = 0x23, .enable_mask = __BIT(1), 73 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0), 74 .base = 712500, .step = 12500 }, 75 { .name = "DCDC_REG3", .flags = F_ENABLE_WRITE_MASK, 76 .enable_reg = 0x23, .enable_mask = __BIT(2) }, 77 { .name = "DCDC_REG4", .flags = F_ENABLE_WRITE_MASK, 78 .enable_reg = 0x23, .enable_mask = __BIT(3), 79 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0), 80 .base = 800000, .step = 100000 }, 81 82 /* LDO */ 83 { .name = "LDO_REG1", .flags = F_ENABLE_WRITE_MASK, 84 .enable_reg = 0x27, .enable_mask = __BIT(0), 85 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0), 86 .base = 800000, .step = 100000 }, 87 { .name = "LDO_REG2", .flags = F_ENABLE_WRITE_MASK, 88 .enable_reg = 0x27, .enable_mask = __BIT(1), 89 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0), 90 .base = 800000, .step = 100000 }, 91 { .name = "LDO_REG3", .flags = F_ENABLE_WRITE_MASK, 92 .enable_reg = 0x27, .enable_mask = __BIT(2), 93 .vsel_reg = 0x3f, .vsel_mask = __BITS(4,0), 94 .base = 800000, .step = 100000 }, 95 }; 96 97 static const struct rkpmic_config rk805_config = { 98 .name = "RK805", 99 .ctrl = rk805_ctrls, 100 .nctrl = __arraycount(rk805_ctrls), 101 }; 102 103 static const struct rkpmic_ctrl rk808_ctrls[] = { 104 /* DCDC */ 105 { .name = "DCDC_REG1", 106 .enable_reg = 0x23, .enable_mask = __BIT(0), 107 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0), 108 .base = 712500, .step = 12500 }, 109 { .name = "DCDC_REG2", 110 .enable_reg = 0x23, .enable_mask = __BIT(1), 111 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0), 112 .base = 712500, .step = 12500 }, 113 { .name = "DCDC_REG3", 114 .enable_reg = 0x23, .enable_mask = __BIT(2) }, 115 { .name = "DCDC_REG4", 116 .enable_reg = 0x23, .enable_mask = __BIT(3), 117 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0), 118 .base = 1800000, .step = 100000 }, 119 120 /* LDO */ 121 { .name = "LDO_REG1", 122 .enable_reg = 0x24, .enable_mask = __BIT(0), 123 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0), 124 .base = 1800000, .step = 100000 }, 125 { .name = "LDO_REG2", 126 .enable_reg = 0x24, .enable_mask = __BIT(0), 127 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0), 128 .base = 1800000, .step = 100000 }, 129 { .name = "LDO_REG3", 130 .enable_reg = 0x24, .enable_mask = __BIT(0), 131 .vsel_reg = 0x3f, .vsel_mask = __BITS(3,0), 132 .base = 800000, .step = 100000 }, 133 { .name = "LDO_REG4", 134 .enable_reg = 0x24, .enable_mask = __BIT(0), 135 .vsel_reg = 0x41, .vsel_mask = __BITS(4,0), 136 .base = 1800000, .step = 100000 }, 137 { .name = "LDO_REG5", 138 .enable_reg = 0x24, .enable_mask = __BIT(0), 139 .vsel_reg = 0x43, .vsel_mask = __BITS(4,0), 140 .base = 1800000, .step = 100000 }, 141 { .name = "LDO_REG6", 142 .enable_reg = 0x24, .enable_mask = __BIT(0), 143 .vsel_reg = 0x45, .vsel_mask = __BITS(4,0), 144 .base = 800000, .step = 100000 }, 145 { .name = "LDO_REG7", 146 .enable_reg = 0x24, .enable_mask = __BIT(0), 147 .vsel_reg = 0x47, .vsel_mask = __BITS(4,0), 148 .base = 800000, .step = 100000 }, 149 { .name = "LDO_REG8", 150 .enable_reg = 0x24, .enable_mask = __BIT(0), 151 .vsel_reg = 0x49, .vsel_mask = __BITS(4,0), 152 .base = 1800000, .step = 100000 }, 153 154 /* SWITCH */ 155 { .name = "SWITCH_REG1", 156 .enable_reg = 0x23, .enable_mask = __BIT(5) }, 157 { .name = "SWITCH_REG2", 158 .enable_reg = 0x23, .enable_mask = __BIT(6) }, 159 }; 160 161 static const struct rkpmic_config rk808_config = { 162 .name = "RK808", 163 .ctrl = rk808_ctrls, 164 .nctrl = __arraycount(rk808_ctrls), 165 }; 166 167 struct rkpmic_softc { 168 device_t sc_dev; 169 i2c_tag_t sc_i2c; 170 i2c_addr_t sc_addr; 171 int sc_phandle; 172 173 struct rkpmic_config *sc_conf; 174 }; 175 176 struct rkreg_softc { 177 device_t sc_dev; 178 struct rkpmic_softc *sc_pmic; 179 const struct rkpmic_ctrl *sc_ctrl; 180 }; 181 182 struct rkreg_attach_args { 183 const struct rkpmic_ctrl *reg_ctrl; 184 int reg_phandle; 185 }; 186 187 static const struct device_compatible_entry compat_data[] = { 188 { "rockchip,rk805", (uintptr_t)&rk805_config }, 189 { "rockchip,rk808", (uintptr_t)&rk808_config }, 190 { NULL } 191 }; 192 193 static uint8_t 194 rkpmic_read(struct rkpmic_softc *sc, uint8_t reg, int flags) 195 { 196 uint8_t val = 0; 197 int error; 198 199 error = iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, &val, flags); 200 if (error != 0) 201 aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error); 202 203 return val; 204 } 205 206 static void 207 rkpmic_write(struct rkpmic_softc *sc, uint8_t reg, uint8_t val, int flags) 208 { 209 int error; 210 211 error = iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, flags); 212 if (error != 0) 213 aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error); 214 } 215 216 #define I2C_READ(sc, reg) rkpmic_read((sc), (reg), I2C_F_POLL) 217 #define I2C_WRITE(sc, reg, val) rkpmic_write((sc), (reg), (val), I2C_F_POLL) 218 #define I2C_LOCK(sc) iic_acquire_bus((sc)->sc_i2c, I2C_F_POLL) 219 #define I2C_UNLOCK(sc) iic_release_bus((sc)->sc_i2c, I2C_F_POLL) 220 221 static int 222 rkpmic_match(device_t parent, cfdata_t match, void *aux) 223 { 224 struct i2c_attach_args *ia = aux; 225 int match_result; 226 227 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 228 return match_result; 229 230 return 0; 231 } 232 233 static void 234 rkpmic_attach(device_t parent, device_t self, void *aux) 235 { 236 struct rkpmic_softc * const sc = device_private(self); 237 struct i2c_attach_args *ia = aux; 238 struct rkreg_attach_args raa; 239 const struct device_compatible_entry *entry; 240 int child, regulators; 241 u_int chipid, n; 242 243 iic_compatible_match(ia, compat_data, &entry); 244 245 sc->sc_dev = self; 246 sc->sc_i2c = ia->ia_tag; 247 sc->sc_addr = ia->ia_addr; 248 sc->sc_phandle = ia->ia_cookie; 249 sc->sc_conf = (void *)entry->data; 250 251 aprint_naive("\n"); 252 aprint_normal(": %s Power Management IC\n", sc->sc_conf->name); 253 254 I2C_LOCK(sc); 255 chipid = I2C_READ(sc, CHIP_NAME_REG) << 8; 256 chipid |= I2C_READ(sc, CHIP_VER_REG); 257 aprint_debug_dev(self, "Chip ID 0x%04x\n", chipid); 258 I2C_UNLOCK(sc); 259 260 regulators = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 261 if (regulators < 0) 262 return; 263 264 for (n = 0; n < sc->sc_conf->nctrl; n++) { 265 child = of_find_firstchild_byname(regulators, sc->sc_conf->ctrl[n].name); 266 if (child < 0) 267 continue; 268 raa.reg_ctrl = &sc->sc_conf->ctrl[n]; 269 raa.reg_phandle = child; 270 config_found(self, &raa, NULL); 271 } 272 } 273 274 static int 275 rkreg_acquire(device_t dev) 276 { 277 return 0; 278 } 279 280 static void 281 rkreg_release(device_t dev) 282 { 283 } 284 285 static int 286 rkreg_enable(device_t dev, bool enable) 287 { 288 struct rkreg_softc * const sc = device_private(dev); 289 const struct rkpmic_ctrl *c = sc->sc_ctrl; 290 uint8_t val; 291 292 if (!c->enable_mask) 293 return EINVAL; 294 295 I2C_LOCK(sc->sc_pmic); 296 if (c->flags & F_ENABLE_WRITE_MASK) 297 val |= c->enable_mask << 4; 298 else 299 val = I2C_READ(sc->sc_pmic, c->enable_reg); 300 if (enable) 301 val |= c->enable_mask; 302 else 303 val &= ~c->enable_mask; 304 I2C_WRITE(sc->sc_pmic, c->enable_reg, val); 305 I2C_UNLOCK(sc->sc_pmic); 306 307 return 0; 308 } 309 310 static int 311 rkreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 312 { 313 struct rkreg_softc * const sc = device_private(dev); 314 const struct rkpmic_ctrl *c = sc->sc_ctrl; 315 uint8_t val; 316 u_int vsel; 317 318 if (!c->vsel_mask) 319 return EINVAL; 320 321 if (min_uvol < c->base) 322 return ERANGE; 323 324 vsel = (min_uvol - c->base) / c->step; 325 if (vsel > __SHIFTOUT_MASK(c->vsel_mask)) 326 return ERANGE; 327 328 I2C_LOCK(sc->sc_pmic); 329 val = I2C_READ(sc->sc_pmic, c->vsel_reg); 330 val &= ~c->vsel_mask; 331 val |= __SHIFTIN(vsel, c->vsel_mask); 332 I2C_WRITE(sc->sc_pmic, c->vsel_reg, val); 333 I2C_UNLOCK(sc->sc_pmic); 334 335 return 0; 336 } 337 338 static int 339 rkreg_get_voltage(device_t dev, u_int *puvol) 340 { 341 struct rkreg_softc * const sc = device_private(dev); 342 const struct rkpmic_ctrl *c = sc->sc_ctrl; 343 uint8_t val; 344 345 if (!c->vsel_mask) 346 return EINVAL; 347 348 I2C_LOCK(sc->sc_pmic); 349 val = I2C_READ(sc->sc_pmic, c->vsel_reg); 350 I2C_UNLOCK(sc->sc_pmic); 351 352 *puvol = __SHIFTOUT(val, c->vsel_mask) * c->step + c->base; 353 354 return 0; 355 } 356 357 static struct fdtbus_regulator_controller_func rkreg_funcs = { 358 .acquire = rkreg_acquire, 359 .release = rkreg_release, 360 .enable = rkreg_enable, 361 .set_voltage = rkreg_set_voltage, 362 .get_voltage = rkreg_get_voltage, 363 }; 364 365 static int 366 rkreg_match(device_t parent, cfdata_t match, void *aux) 367 { 368 return 1; 369 } 370 371 static void 372 rkreg_attach(device_t parent, device_t self, void *aux) 373 { 374 struct rkreg_softc * const sc = device_private(self); 375 struct rkreg_attach_args *raa = aux; 376 const int phandle = raa->reg_phandle; 377 const char *name; 378 379 sc->sc_dev = self; 380 sc->sc_pmic = device_private(parent); 381 sc->sc_ctrl = raa->reg_ctrl; 382 383 fdtbus_register_regulator_controller(self, phandle, 384 &rkreg_funcs); 385 386 aprint_naive("\n"); 387 name = fdtbus_get_string(phandle, "regulator-name"); 388 if (!name) 389 name = fdtbus_get_string(phandle, "name"); 390 aprint_normal(": %s\n", name); 391 } 392 393 CFATTACH_DECL_NEW(rkpmic, sizeof(struct rkpmic_softc), 394 rkpmic_match, rkpmic_attach, NULL, NULL); 395 396 CFATTACH_DECL_NEW(rkreg, sizeof(struct rkreg_softc), 397 rkreg_match, rkreg_attach, NULL, NULL); 398