1 /* $NetBSD: motoi2c.c,v 1.13 2022/07/22 23:43:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.13 2022/07/22 23:43:23 thorpej Exp $"); 34 35 #if defined(__arm__) || defined(__aarch64__) 36 #include "opt_fdt.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 #include <sys/mutex.h> 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/motoi2creg.h> 48 #include <dev/i2c/motoi2cvar.h> 49 50 #ifdef FDT 51 #include <dev/fdt/fdtvar.h> 52 #endif 53 54 #ifdef DEBUG 55 int motoi2c_debug = 0; 56 #define DPRINTF(x) if (motoi2c_debug) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 static int motoi2c_acquire_bus(void *, int); 62 static void motoi2c_release_bus(void *, int); 63 static int motoi2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 64 void *, size_t, int); 65 static void motoi2c_clear_status(struct motoi2c_softc *, uint8_t); 66 static int motoi2c_busy_wait(struct motoi2c_softc *, uint8_t); 67 68 static const struct motoi2c_settings motoi2c_default_settings = { 69 .i2c_adr = MOTOI2C_ADR_DEFAULT, 70 .i2c_fdr = MOTOI2C_FDR_DEFAULT, 71 .i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT, 72 }; 73 74 #define I2C_READ(r) ((*sc->sc_iord)(sc, (r))) 75 #define I2C_WRITE(r,v) ((*sc->sc_iowr)(sc, (r), (v))) 76 #define I2C_SETCLR(r, s, c) \ 77 ((*sc->sc_iowr)(sc, (r), ((*sc->sc_iord)(sc, (r)) | (s)) & ~(c))) 78 79 static uint8_t 80 motoi2c_iord1(struct motoi2c_softc *sc, bus_size_t off) 81 { 82 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 83 } 84 85 static void 86 motoi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data) 87 { 88 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, data); 89 } 90 91 void 92 motoi2c_attach(struct motoi2c_softc *sc, 93 const struct motoi2c_settings *settings) 94 { 95 struct i2cbus_attach_args iba; 96 97 if (settings == NULL) { 98 sc->sc_settings = motoi2c_default_settings; 99 } else { 100 sc->sc_settings = *settings; 101 } 102 if (sc->sc_iord == NULL) 103 sc->sc_iord = motoi2c_iord1; 104 if (sc->sc_iowr == NULL) 105 sc->sc_iowr = motoi2c_iowr1; 106 107 iic_tag_init(&sc->sc_i2c); 108 sc->sc_i2c.ic_cookie = sc; 109 sc->sc_i2c.ic_acquire_bus = motoi2c_acquire_bus; 110 sc->sc_i2c.ic_release_bus = motoi2c_release_bus; 111 sc->sc_i2c.ic_exec = motoi2c_exec; 112 memset(&iba, 0, sizeof(iba)); 113 iba.iba_tag = &sc->sc_i2c; 114 iba.iba_child_devices = sc->sc_child_devices; 115 116 if ((sc->sc_flags & MOTOI2C_F_ENABLE_INV) != 0) { 117 sc->sc_enable_mask = 0; 118 sc->sc_disable_mask = CR_MEN; 119 } else { 120 sc->sc_enable_mask = CR_MEN; 121 sc->sc_disable_mask = 0; 122 } 123 124 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* reset before config */ 125 I2C_WRITE(I2CDFSRR, sc->sc_settings.i2c_dfsrr); /* sampling units */ 126 I2C_WRITE(I2CFDR, sc->sc_settings.i2c_fdr); /* divider 3072 */ 127 I2C_WRITE(I2CADR, sc->sc_settings.i2c_adr); /* our slave address */ 128 motoi2c_clear_status(sc, I2C_READ(I2CSR)); 129 130 #ifdef FDT 131 if (sc->sc_phandle != 0) { 132 fdtbus_register_i2c_controller(&sc->sc_i2c, sc->sc_phandle); 133 fdtbus_attach_i2cbus(sc->sc_dev, sc->sc_phandle, &sc->sc_i2c, 134 iicbus_print); 135 } else 136 #endif 137 config_found(sc->sc_dev, &iba, iicbus_print, 138 CFARGS(.iattr = "i2cbus")); 139 } 140 141 static int 142 motoi2c_acquire_bus(void *v, int flags) 143 { 144 struct motoi2c_softc * const sc = v; 145 146 I2C_WRITE(I2CCR, sc->sc_enable_mask); /* enable the I2C module */ 147 148 return 0; 149 } 150 151 static void 152 motoi2c_release_bus(void *v, int flags) 153 { 154 struct motoi2c_softc * const sc = v; 155 156 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* disable the I2C module */ 157 } 158 159 static int 160 motoi2c_stop_wait(struct motoi2c_softc *sc) 161 { 162 u_int timo; 163 int error = 0; 164 165 timo = 1000; 166 while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo) 167 DELAY(1); 168 169 if (timo == 0) { 170 DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR))); 171 error = ETIMEDOUT; 172 } 173 174 return error; 175 } 176 177 static void 178 motoi2c_clear_status(struct motoi2c_softc *sc, uint8_t sr) 179 { 180 if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) { 181 I2C_WRITE(I2CSR, sr); 182 } else { 183 I2C_WRITE(I2CSR, 0); 184 } 185 } 186 187 /* busy waiting for byte data transfer completion */ 188 static int 189 motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr) 190 { 191 uint8_t sr; 192 u_int timo; 193 int error = 0; 194 195 timo = 1000; 196 while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo) 197 DELAY(10); 198 199 if (timo == 0) { 200 DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n", 201 __func__, sr, I2C_READ(I2CCR))); 202 error = ETIMEDOUT; 203 } 204 /* 205 * RXAK is only valid when transmitting. 206 */ 207 if ((cr & CR_MTX) && (sr & SR_RXAK)) { 208 DPRINTF(("%s: missing rx ack (%#x): spin=%u\n", 209 __func__, sr, 1000 - timo)); 210 error = EIO; 211 } 212 motoi2c_clear_status(sc, sr); 213 return error; 214 } 215 216 int 217 motoi2c_intr(void *v) 218 { 219 struct motoi2c_softc * const sc = v; 220 221 panic("%s(%p)", __func__, sc); 222 223 return 0; 224 } 225 226 int 227 motoi2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, 228 const void *cmdbuf, size_t cmdlen, 229 void *databuf, size_t datalen, 230 int flags) 231 { 232 struct motoi2c_softc * const sc = v; 233 uint8_t sr; 234 uint8_t cr; 235 int error; 236 237 sr = I2C_READ(I2CSR); 238 cr = I2C_READ(I2CCR); 239 240 #if 0 241 DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n", 242 __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags, 243 sr, cr)); 244 #endif 245 246 if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) { 247 /* wait for bus becoming available */ 248 error = motoi2c_stop_wait(sc); 249 if (error) 250 return ETIMEDOUT; 251 } 252 253 /* reset interrupt and arbitration-lost flags (all others are RO) */ 254 motoi2c_clear_status(sc, sr); 255 sr = I2C_READ(I2CSR); 256 257 /* 258 * Generate start condition 259 */ 260 cr = sc->sc_enable_mask | CR_MTX | CR_MSTA; 261 I2C_WRITE(I2CCR, cr); 262 263 DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n", 264 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 265 266 sr = I2C_READ(I2CSR); 267 if (sr & SR_MAL) { 268 DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n", 269 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 270 I2C_WRITE(I2CCR, sc->sc_disable_mask); 271 DELAY(10); 272 I2C_WRITE(I2CCR, sc->sc_enable_mask | CR_MTX | CR_MSTA); 273 DELAY(10); 274 sr = I2C_READ(I2CSR); 275 if (sr & SR_MAL) { 276 error = EBUSY; 277 goto out; 278 } 279 DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n", 280 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 281 } 282 283 /* send target address and transfer direction */ 284 uint8_t addr_byte = (addr << 1) 285 | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0); 286 I2C_WRITE(I2CDR, addr_byte); 287 288 error = motoi2c_busy_wait(sc, cr); 289 if (error) { 290 DPRINTF(("%s: error sending address: %d\n", __func__, error)); 291 if (error == EIO) 292 error = ENXIO; 293 goto out; 294 } 295 296 const uint8_t *cmdptr = cmdbuf; 297 for (size_t i = 0; i < cmdlen; i++) { 298 I2C_WRITE(I2CDR, *cmdptr++); 299 300 error = motoi2c_busy_wait(sc, cr); 301 if (error) { 302 DPRINTF(("%s: error sending cmd byte %zu (cr=%#x/%#x):" 303 " %d\n", __func__, i, I2C_READ(I2CCR), cr, error)); 304 goto out; 305 } 306 } 307 308 if (cmdlen > 0 && I2C_OP_READ_P(op)) { 309 KASSERT(cr & CR_MTX); 310 KASSERT((cr & CR_TXAK) == 0); 311 I2C_WRITE(I2CCR, cr | CR_RSTA); 312 #if 0 313 DPRINTF(("%s: restarted(read): sr=%#x cr=%#x(%#x)\n", 314 __func__, I2C_READ(I2CSR), cr | CR_RSTA, I2C_READ(I2CCR))); 315 #endif 316 317 /* send target address and read transfer direction */ 318 addr_byte |= 1; 319 I2C_WRITE(I2CDR, addr_byte); 320 321 error = motoi2c_busy_wait(sc, cr); 322 if (error) { 323 if (error == EIO) 324 error = ENXIO; 325 goto out; 326 } 327 } 328 329 if (I2C_OP_READ_P(op)) { 330 uint8_t *dataptr = databuf; 331 cr &= ~CR_MTX; /* clear transmit flags */ 332 if (datalen <= 1) 333 cr |= CR_TXAK; 334 I2C_WRITE(I2CCR, cr); 335 DELAY(10); 336 (void)I2C_READ(I2CDR); /* dummy read */ 337 for (size_t i = 0; i < datalen; i++) { 338 /* 339 * If a master receiver wants to terminate a data 340 * transfer, it must inform the slave transmitter by 341 * not acknowledging the last byte of data (by setting 342 * the transmit acknowledge bit (I2CCR[TXAK])) before 343 * reading the next-to-last byte of data. 344 */ 345 error = motoi2c_busy_wait(sc, cr); 346 if (error) { 347 DPRINTF(("%s: error reading byte %zu: %d\n", 348 __func__, i, error)); 349 goto out; 350 } 351 if (i == datalen - 2) { 352 cr |= CR_TXAK; 353 I2C_WRITE(I2CCR, cr); 354 } else if (i == datalen - 1 && I2C_OP_STOP_P(op)) { 355 cr = sc->sc_enable_mask | CR_TXAK; 356 I2C_WRITE(I2CCR, cr); 357 } 358 *dataptr++ = I2C_READ(I2CDR); 359 } 360 if (datalen == 0) { 361 if (I2C_OP_STOP_P(op)) { 362 cr = sc->sc_enable_mask | CR_TXAK; 363 I2C_WRITE(I2CCR, cr); 364 } 365 (void)I2C_READ(I2CDR); /* dummy read */ 366 error = motoi2c_busy_wait(sc, cr); 367 if (error) { 368 DPRINTF(("%s: error reading dummy last byte:" 369 "%d\n", __func__, error)); 370 goto out; 371 } 372 } 373 } else { 374 const uint8_t *dataptr = databuf; 375 for (size_t i = 0; i < datalen; i++) { 376 I2C_WRITE(I2CDR, *dataptr++); 377 error = motoi2c_busy_wait(sc, cr); 378 if (error) { 379 DPRINTF(("%s: error sending data byte %zu:" 380 " %d\n", __func__, i, error)); 381 goto out; 382 } 383 } 384 } 385 386 out: 387 /* 388 * If we encountered an error condition or caller wants a STOP, 389 * send a STOP. 390 */ 391 if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) { 392 cr = sc->sc_enable_mask; 393 I2C_WRITE(I2CCR, cr); 394 motoi2c_stop_wait(sc); 395 DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__, 396 cr, I2C_READ(I2CCR))); 397 } 398 399 DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__, 400 I2C_READ(I2CSR), I2C_READ(I2CCR), error)); 401 402 return error; 403 } 404