1 /* $NetBSD: m41t00.c,v 1.19 2014/11/20 16:34:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41t00.c,v 1.19 2014/11/20 16:34:26 christos Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <dev/i2c/i2cvar.h> 56 #include <dev/i2c/m41t00reg.h> 57 58 struct m41t00_softc { 59 device_t sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static int m41t00_match(device_t, cfdata_t, void *); 67 static void m41t00_attach(device_t, device_t, void *); 68 69 CFATTACH_DECL_NEW(m41trtc, sizeof(struct m41t00_softc), 70 m41t00_match, m41t00_attach, NULL, NULL); 71 extern struct cfdriver m41trtc_cd; 72 73 dev_type_open(m41t00_open); 74 dev_type_close(m41t00_close); 75 dev_type_read(m41t00_read); 76 dev_type_write(m41t00_write); 77 78 const struct cdevsw m41t00_cdevsw = { 79 .d_open = m41t00_open, 80 .d_close = m41t00_close, 81 .d_read = m41t00_read, 82 .d_write = m41t00_write, 83 .d_ioctl = noioctl, 84 .d_stop = nostop, 85 .d_tty = notty, 86 .d_poll = nopoll, 87 .d_mmap = nommap, 88 .d_kqfilter = nokqfilter, 89 .d_discard = nodiscard, 90 .d_flag = D_OTHER 91 }; 92 93 static int m41t00_clock_read(struct m41t00_softc *, struct clock_ymdhms *); 94 static int m41t00_clock_write(struct m41t00_softc *, struct clock_ymdhms *); 95 static int m41t00_gettime(struct todr_chip_handle *, struct timeval *); 96 static int m41t00_settime(struct todr_chip_handle *, struct timeval *); 97 98 int 99 m41t00_match(device_t parent, cfdata_t cf, void *aux) 100 { 101 struct i2c_attach_args *ia = aux; 102 103 if (ia->ia_addr == M41T00_ADDR) { 104 return 1; 105 } 106 107 return 0; 108 } 109 110 void 111 m41t00_attach(device_t parent, device_t self, void *aux) 112 { 113 struct m41t00_softc *sc = device_private(self); 114 struct i2c_attach_args *ia = aux; 115 116 sc->sc_tag = ia->ia_tag; 117 sc->sc_address = ia->ia_addr; 118 sc->sc_dev = self; 119 120 aprint_naive(": Real-time Clock\n"); 121 aprint_normal(": M41T00 Real-time Clock\n"); 122 123 sc->sc_open = 0; 124 sc->sc_todr.cookie = sc; 125 sc->sc_todr.todr_gettime = m41t00_gettime; 126 sc->sc_todr.todr_settime = m41t00_settime; 127 sc->sc_todr.todr_setwen = NULL; 128 129 todr_attach(&sc->sc_todr); 130 } 131 132 /*ARGSUSED*/ 133 int 134 m41t00_open(dev_t dev, int flag, int fmt, struct lwp *l) 135 { 136 struct m41t00_softc *sc; 137 138 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 139 return ENXIO; 140 141 /* XXX: Locking */ 142 143 if (sc->sc_open) 144 return EBUSY; 145 146 sc->sc_open = 1; 147 return 0; 148 } 149 150 /*ARGSUSED*/ 151 int 152 m41t00_close(dev_t dev, int flag, int fmt, struct lwp *l) 153 { 154 struct m41t00_softc *sc; 155 156 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 157 return ENXIO; 158 159 sc->sc_open = 0; 160 return 0; 161 } 162 163 /*ARGSUSED*/ 164 int 165 m41t00_read(dev_t dev, struct uio *uio, int flags) 166 { 167 struct m41t00_softc *sc; 168 u_int8_t ch, cmdbuf[1]; 169 int a, error; 170 171 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 172 return ENXIO; 173 174 if (uio->uio_offset >= M41T00_NBYTES) 175 return EINVAL; 176 177 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 178 return error; 179 180 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 181 a = (int)uio->uio_offset; 182 cmdbuf[0] = a; 183 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 184 sc->sc_address, cmdbuf, 1, 185 &ch, 1, 0)) != 0) { 186 iic_release_bus(sc->sc_tag, 0); 187 aprint_error_dev(sc->sc_dev, 188 "m41t00_read: read failed at 0x%x\n", a); 189 return error; 190 } 191 if ((error = uiomove(&ch, 1, uio)) != 0) { 192 iic_release_bus(sc->sc_tag, 0); 193 return error; 194 } 195 } 196 197 iic_release_bus(sc->sc_tag, 0); 198 199 return 0; 200 } 201 202 /*ARGSUSED*/ 203 int 204 m41t00_write(dev_t dev, struct uio *uio, int flags) 205 { 206 struct m41t00_softc *sc; 207 u_int8_t cmdbuf[2]; 208 int a, error; 209 210 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 211 return ENXIO; 212 213 if (uio->uio_offset >= M41T00_NBYTES) 214 return EINVAL; 215 216 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 217 return error; 218 219 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 220 a = (int)uio->uio_offset; 221 222 cmdbuf[0] = a; 223 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 224 break; 225 226 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 227 sc->sc_address, 228 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 229 aprint_error_dev(sc->sc_dev, 230 "m41t00_write: write failed at 0x%x\n", a); 231 break; 232 } 233 } 234 235 iic_release_bus(sc->sc_tag, 0); 236 237 return error; 238 } 239 240 static int 241 m41t00_gettime(struct todr_chip_handle *ch, struct timeval *tv) 242 { 243 struct m41t00_softc *sc = ch->cookie; 244 struct clock_ymdhms dt; 245 246 if (m41t00_clock_read(sc, &dt) == 0) 247 return -1; 248 249 tv->tv_sec = clock_ymdhms_to_secs(&dt); 250 tv->tv_usec = 0; 251 252 return 0; 253 } 254 255 static int 256 m41t00_settime(struct todr_chip_handle *ch, struct timeval *tv) 257 { 258 struct m41t00_softc *sc = ch->cookie; 259 struct clock_ymdhms dt; 260 261 clock_secs_to_ymdhms(tv->tv_sec, &dt); 262 263 if (m41t00_clock_write(sc, &dt) == 0) 264 return -1; 265 266 return 0; 267 } 268 269 static int m41t00_rtc_offset[] = { 270 M41T00_SEC, 271 M41T00_MIN, 272 M41T00_CENHR, 273 M41T00_DAY, 274 M41T00_DATE, 275 M41T00_MONTH, 276 M41T00_YEAR, 277 }; 278 279 static int 280 m41t00_clock_read(struct m41t00_softc *sc, struct clock_ymdhms *dt) 281 { 282 u_int8_t bcd[M41T00_NBYTES], cmdbuf[1]; 283 int i, n; 284 285 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 286 aprint_error_dev(sc->sc_dev, 287 "m41t00_clock_read: failed to acquire I2C bus\n"); 288 return 0; 289 } 290 291 /* Read each timekeeping register in order. */ 292 n = sizeof(m41t00_rtc_offset) / sizeof(m41t00_rtc_offset[0]); 293 for (i = 0; i < n ; i++) { 294 cmdbuf[0] = m41t00_rtc_offset[i]; 295 296 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 297 sc->sc_address, cmdbuf, 1, 298 &bcd[i], 1, I2C_F_POLL)) { 299 iic_release_bus(sc->sc_tag, I2C_F_POLL); 300 aprint_error_dev(sc->sc_dev, 301 "m41t00_clock_read: failed to read rtc " 302 "at 0x%x\n", 303 m41t00_rtc_offset[i]); 304 return 0; 305 } 306 } 307 308 /* Done with I2C */ 309 iic_release_bus(sc->sc_tag, I2C_F_POLL); 310 311 /* 312 * Convert the M41T00's register values into something useable 313 */ 314 dt->dt_sec = bcdtobin(bcd[M41T00_SEC] & M41T00_SEC_MASK); 315 dt->dt_min = bcdtobin(bcd[M41T00_MIN] & M41T00_MIN_MASK); 316 dt->dt_hour = bcdtobin(bcd[M41T00_CENHR] & M41T00_HOUR_MASK); 317 dt->dt_day = bcdtobin(bcd[M41T00_DATE] & M41T00_DATE_MASK); 318 dt->dt_wday = bcdtobin(bcd[M41T00_DAY] & M41T00_DAY_MASK); 319 dt->dt_mon = bcdtobin(bcd[M41T00_MONTH] & M41T00_MONTH_MASK); 320 dt->dt_year = bcdtobin(bcd[M41T00_YEAR] & M41T00_YEAR_MASK); 321 322 /* 323 * Since the m41t00 just stores 00-99, and this is 2003 as I write 324 * this comment, use 2000 as a base year 325 */ 326 dt->dt_year += 2000; 327 328 return 1; 329 } 330 331 static int 332 m41t00_clock_write(struct m41t00_softc *sc, struct clock_ymdhms *dt) 333 { 334 uint8_t bcd[M41T00_DATE_BYTES], cmdbuf[2]; 335 uint8_t init_seconds, final_seconds; 336 int i; 337 338 /* 339 * Convert our time representation into something the MAX6900 340 * can understand. 341 */ 342 bcd[M41T00_SEC] = bintobcd(dt->dt_sec); 343 bcd[M41T00_MIN] = bintobcd(dt->dt_min); 344 bcd[M41T00_CENHR] = bintobcd(dt->dt_hour); 345 bcd[M41T00_DATE] = bintobcd(dt->dt_day); 346 bcd[M41T00_DAY] = bintobcd(dt->dt_wday); 347 bcd[M41T00_MONTH] = bintobcd(dt->dt_mon); 348 bcd[M41T00_YEAR] = bintobcd(dt->dt_year % 100); 349 350 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 351 aprint_error_dev(sc->sc_dev, 352 "m41t00_clock_write: failed to acquire I2C bus\n"); 353 return 0; 354 } 355 356 /* 357 * The MAX6900 RTC manual recommends ensuring "atomicity" of 358 * a non-burst write by: 359 * 360 * - writing SECONDS 361 * - reading back SECONDS, remembering it as "initial seconds" 362 * - write the remaing RTC registers 363 * - read back SECONDS as "final seconds" 364 * - if "initial seconds" == 59, ensure "final seconds" == 59 365 * - else, ensure "final seconds" is no more than one second 366 * beyond "initial seconds". 367 * 368 * This sounds reasonable for the M41T00, too. 369 */ 370 again: 371 cmdbuf[0] = M41T00_SEC; 372 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 373 cmdbuf, 1, &bcd[M41T00_SEC], 1, I2C_F_POLL)) { 374 iic_release_bus(sc->sc_tag, I2C_F_POLL); 375 aprint_error_dev(sc->sc_dev, 376 "m41t00_clock_write: failed to write SECONDS\n"); 377 return 0; 378 } 379 380 cmdbuf[0] = M41T00_SEC; 381 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 382 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 383 iic_release_bus(sc->sc_tag, I2C_F_POLL); 384 aprint_error_dev(sc->sc_dev, 385 "m41t00_clock_write: failed to read " 386 "INITIAL SECONDS\n"); 387 return 0; 388 } 389 init_seconds = bcdtobin(init_seconds & M41T00_SEC_MASK); 390 391 for (i = 1; i < M41T00_DATE_BYTES; i++) { 392 cmdbuf[0] = m41t00_rtc_offset[i]; 393 if (iic_exec(sc->sc_tag, 394 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 395 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 396 iic_release_bus(sc->sc_tag, I2C_F_POLL); 397 aprint_error_dev(sc->sc_dev, 398 "m41t00_clock_write: failed to write rtc " 399 " at 0x%x\n", 400 m41t00_rtc_offset[i]); 401 return 0; 402 } 403 } 404 405 cmdbuf[0] = M41T00_SEC; 406 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 407 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 408 iic_release_bus(sc->sc_tag, I2C_F_POLL); 409 aprint_error_dev(sc->sc_dev, 410 "m41t00_clock_write: failed to read " 411 "FINAL SECONDS\n"); 412 return 0; 413 } 414 final_seconds = bcdtobin(final_seconds & M41T00_SEC_MASK); 415 416 if ((init_seconds != final_seconds) && 417 (((init_seconds + 1) % 60) != final_seconds)) { 418 #if 1 419 printf("%s: m41t00_clock_write: init %d, final %d, try again\n", 420 device_xname(sc->sc_dev), init_seconds, final_seconds); 421 #endif 422 goto again; 423 } 424 425 iic_release_bus(sc->sc_tag, I2C_F_POLL); 426 427 return 1; 428 } 429