1 /* $NetBSD: i2c_bitbang.c,v 1.13 2010/04/25 00:35:58 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Common module for bit-bang'ing an I2C bus. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i2c_bitbang.c,v 1.13 2010/04/25 00:35:58 tsutsui Exp $"); 44 45 #include <sys/param.h> 46 47 #include <dev/i2c/i2cvar.h> 48 #include <dev/i2c/i2c_bitbang.h> 49 50 #define SETBITS(x) ops->ibo_set_bits(v, (x)) 51 #define DIR(x) ops->ibo_set_dir(v, (x)) 52 #define READ ops->ibo_read_bits(v) 53 54 #define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */ 55 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */ 56 #define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */ 57 #define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */ 58 59 #ifndef SCL_BAIL_COUNT 60 #define SCL_BAIL_COUNT 1000 61 #endif 62 63 static inline int i2c_wait_for_scl(void *, i2c_bitbang_ops_t); 64 65 static inline int 66 i2c_wait_for_scl(void *v, i2c_bitbang_ops_t ops) 67 { 68 int bail = 0; 69 70 while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) { 71 delay(1); 72 bail++; 73 } 74 if (bail == SCL_BAIL_COUNT) { 75 i2c_bitbang_send_stop(v, 0, ops); 76 return EIO; 77 } 78 return 0; 79 } 80 81 /*ARGSUSED*/ 82 int 83 i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops) 84 { 85 86 /* start condition: put SDA H->L edge during SCL=H */ 87 88 DIR(OUTPUT); 89 SETBITS(SDA | SCL); 90 delay(5); /* bus free time (4.7 us) */ 91 SETBITS( 0 | SCL); 92 if (i2c_wait_for_scl(v, ops) != 0) 93 return EIO; 94 delay(4); /* start hold time (4.0 us) */ 95 96 /* leave SCL=L and SDA=L to avoid unexpected start/stop condition */ 97 SETBITS( 0 | 0); 98 99 return 0; 100 } 101 102 /*ARGSUSED*/ 103 int 104 i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops) 105 { 106 107 /* stop condition: put SDA L->H edge during SCL=H */ 108 109 /* assume SCL=L, SDA=L here */ 110 DIR(OUTPUT); 111 SETBITS( 0 | SCL); 112 delay(4); /* stop setup time (4.0 us) */ 113 SETBITS(SDA | SCL); 114 115 return 0; 116 } 117 118 int 119 i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags, 120 i2c_bitbang_ops_t ops) 121 { 122 123 if (addr < 0x80) { 124 uint8_t i2caddr; 125 126 /* disallow the 10-bit address prefix */ 127 if ((addr & 0x78) == 0x78) 128 return EINVAL; 129 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0); 130 (void) i2c_bitbang_send_start(v, flags, ops); 131 132 return (i2c_bitbang_write_byte(v, i2caddr, 133 flags & ~I2C_F_STOP, ops)); 134 135 } else if (addr < 0x400) { 136 uint16_t i2caddr; 137 int rv; 138 139 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0) | 140 0xf000; 141 142 (void) i2c_bitbang_send_start(v, flags, ops); 143 rv = i2c_bitbang_write_byte(v, i2caddr >> 8, 144 flags & ~I2C_F_STOP, ops); 145 /* did a slave ack the 10-bit prefix? */ 146 if (rv != 0) 147 return rv; 148 149 /* send the lower 7-bits (+ read/write mode) */ 150 return (i2c_bitbang_write_byte(v, i2caddr & 0xff, 151 flags & ~I2C_F_STOP, ops)); 152 153 } else 154 return EINVAL; 155 } 156 157 int 158 i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags, i2c_bitbang_ops_t ops) 159 { 160 int i; 161 uint8_t val = 0; 162 uint32_t bit; 163 164 /* assume SCL=L, SDA=L here */ 165 166 DIR(INPUT); 167 168 for (i = 0; i < 8; i++) { 169 val <<= 1; 170 171 /* data is set at SCL H->L edge */ 172 /* SDA is set here because DIR() is INPUT */ 173 SETBITS(SDA | 0); 174 delay(5); /* clock low time (4.7 us) */ 175 176 /* read data at SCL L->H edge */ 177 SETBITS(SDA | SCL); 178 if (i2c_wait_for_scl(v, ops) != 0) 179 return EIO; 180 if (READ & SDA) 181 val |= 1; 182 delay(4); /* clock high time (4.0 us) */ 183 } 184 /* set SCL H->L before set SDA direction OUTPUT */ 185 SETBITS(SDA | 0); 186 187 /* set ack after SCL H->L edge */ 188 bit = (flags & I2C_F_LAST) ? SDA : 0; 189 DIR(OUTPUT); 190 SETBITS(bit | 0); 191 delay(5); /* clock low time (4.7 us) */ 192 193 /* ack is checked at SCL L->H edge */ 194 SETBITS(bit | SCL); 195 if (i2c_wait_for_scl(v, ops) != 0) 196 return EIO; 197 delay(4); /* clock high time (4.0 us) */ 198 199 /* set SCL H->L for next data; don't change SDA here */ 200 SETBITS(bit | 0); 201 202 /* leave SCL=L and SDA=L to avoid unexpected start/stop condition */ 203 SETBITS( 0 | 0); 204 205 206 if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST)) 207 (void) i2c_bitbang_send_stop(v, flags, ops); 208 209 *valp = val; 210 return 0; 211 } 212 213 int 214 i2c_bitbang_write_byte(void *v, uint8_t val, int flags, i2c_bitbang_ops_t ops) 215 { 216 uint32_t bit; 217 uint8_t mask; 218 int error; 219 220 /* assume at SCL=L, SDA=L here */ 221 222 DIR(OUTPUT); 223 224 for (mask = 0x80; mask != 0; mask >>= 1) { 225 bit = (val & mask) ? SDA : 0; 226 227 /* set data after SCL H->L edge */ 228 SETBITS(bit | 0); 229 delay(5); /* clock low time (4.7 us) */ 230 231 /* data is fetched at SCL L->H edge */ 232 SETBITS(bit | SCL); 233 if (i2c_wait_for_scl(v, ops)) 234 return EIO; 235 delay(4); /* clock high time (4.0 us) */ 236 237 /* put SCL H->L edge; don't change SDA here */ 238 SETBITS(bit | 0); 239 } 240 241 /* ack is set at H->L edge */ 242 DIR(INPUT); 243 delay(5); /* clock low time (4.7 us) */ 244 245 /* read ack at L->H edge */ 246 /* SDA is set here because DIR() is INPUT */ 247 SETBITS(SDA | SCL); 248 if (i2c_wait_for_scl(v, ops) != 0) 249 return EIO; 250 error = (READ & SDA) ? EIO : 0; 251 delay(4); /* clock high time (4.0 us) */ 252 253 /* set SCL H->L before set SDA direction OUTPUT */ 254 SETBITS(SDA | 0); 255 DIR(OUTPUT); 256 /* leave SCL=L and SDA=L to avoid unexpected start/stop condition */ 257 SETBITS( 0 | 0); 258 259 if (flags & I2C_F_STOP) 260 (void) i2c_bitbang_send_stop(v, flags, ops); 261 262 return error; 263 } 264