1 /* $NetBSD: i2c_bitbang.c,v 1.7 2007/04/30 00:07:54 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Common module for bit-bang'ing an I2C bus. 40 */ 41 42 #include <sys/param.h> 43 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #define SETBITS(x) ops->ibo_set_bits(v, (x)) 48 #define DIR(x) ops->ibo_set_dir(v, (x)) 49 #define READ ops->ibo_read_bits(v) 50 51 #define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */ 52 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */ 53 #define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */ 54 #define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */ 55 56 #ifndef SCL_BAIL_COUNT 57 #define SCL_BAIL_COUNT 1000 58 #endif 59 60 static inline int i2c_wait_for_scl(void *, i2c_bitbang_ops_t); 61 62 static inline int 63 i2c_wait_for_scl(void *v, i2c_bitbang_ops_t ops) 64 { 65 int bail = 0; 66 67 while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) { 68 69 delay(1); 70 bail++; 71 } 72 if (bail == SCL_BAIL_COUNT) { 73 74 i2c_bitbang_send_stop(v, 0, ops); 75 return EIO; 76 } 77 return 0; 78 } 79 80 /*ARGSUSED*/ 81 int 82 i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops) 83 { 84 85 DIR(OUTPUT); 86 87 SETBITS(SDA | SCL); 88 delay(5); /* bus free time (4.7 uS) */ 89 SETBITS( SCL); 90 if (i2c_wait_for_scl(v, ops) != 0) 91 return EIO; 92 delay(4); /* start hold time (4.0 uS) */ 93 SETBITS( 0); 94 delay(5); /* clock low time (4.7 uS) */ 95 96 return (0); 97 } 98 99 /*ARGSUSED*/ 100 int 101 i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops) 102 { 103 104 DIR(OUTPUT); 105 106 SETBITS( SCL); 107 delay(4); /* stop setup time (4.0 uS) */ 108 SETBITS(SDA | SCL); 109 110 return (0); 111 } 112 113 int 114 i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags, 115 i2c_bitbang_ops_t ops) 116 { 117 118 if (addr < 0x80) { 119 uint8_t i2caddr; 120 121 /* disallow the 10-bit address prefix */ 122 if ((addr & 0x78) == 0x78) 123 return EINVAL; 124 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0); 125 (void) i2c_bitbang_send_start(v, flags, ops); 126 127 return (i2c_bitbang_write_byte(v, i2caddr, 128 flags & ~I2C_F_STOP, ops)); 129 130 } else if (addr < 0x400) { 131 uint16_t i2caddr; 132 int rv; 133 134 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0) | 135 0xf000; 136 137 (void) i2c_bitbang_send_start(v, flags, ops); 138 rv = i2c_bitbang_write_byte(v, i2caddr >> 8, 139 flags & ~I2C_F_STOP, ops); 140 /* did a slave ack the 10-bit prefix? */ 141 if (rv != 0) 142 return rv; 143 144 /* send the lower 7-bits (+ read/write mode) */ 145 return (i2c_bitbang_write_byte(v, i2caddr & 0xff, 146 flags & ~I2C_F_STOP, ops)); 147 148 } else 149 return EINVAL; 150 } 151 152 int 153 i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags, 154 i2c_bitbang_ops_t ops) 155 { 156 int i; 157 uint8_t val = 0; 158 uint32_t bit; 159 160 DIR(INPUT); 161 SETBITS(SDA ); 162 163 for (i = 0; i < 8; i++) { 164 val <<= 1; 165 SETBITS(SDA | SCL); 166 if (i2c_wait_for_scl(v, ops) != 0) 167 return EIO; 168 delay(4); /* clock high time (4.0 uS) */ 169 if (READ & SDA) 170 val |= 1; 171 SETBITS(SDA ); 172 delay(5); /* clock low time (4.7 uS) */ 173 } 174 175 bit = (flags & I2C_F_LAST) ? SDA : 0; 176 DIR(OUTPUT); 177 SETBITS(bit ); 178 delay(1); /* data setup time (250 nS) */ 179 SETBITS(bit | SCL); 180 if (i2c_wait_for_scl(v, ops) != 0) 181 return EIO; 182 delay(4); /* clock high time (4.0 uS) */ 183 SETBITS(bit ); 184 delay(5); /* clock low time (4.7 uS) */ 185 186 DIR(INPUT); 187 SETBITS(SDA ); 188 delay(5); 189 190 if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST)) 191 (void) i2c_bitbang_send_stop(v, flags, ops); 192 193 *valp = val; 194 return (0); 195 } 196 197 int 198 i2c_bitbang_write_byte(void *v, uint8_t val, int flags, 199 i2c_bitbang_ops_t ops) 200 { 201 uint32_t bit; 202 uint8_t mask; 203 int error; 204 205 DIR(OUTPUT); 206 207 for (mask = 0x80; mask != 0; mask >>= 1) { 208 bit = (val & mask) ? SDA : 0; 209 SETBITS(bit ); 210 delay(1); /* data setup time (250 nS) */ 211 SETBITS(bit | SCL); 212 if (i2c_wait_for_scl(v, ops)) 213 return EIO; 214 delay(4); /* clock high time (4.0 uS) */ 215 SETBITS(bit ); 216 delay(5); /* clock low time (4.7 uS) */ 217 } 218 219 DIR(INPUT); 220 221 SETBITS(SDA ); 222 delay(5); 223 SETBITS(SDA | SCL); 224 if (i2c_wait_for_scl(v, ops) != 0) 225 return EIO; 226 delay(4); 227 error = (READ & SDA) ? EIO : 0; 228 SETBITS(SDA ); 229 delay(5); 230 231 if (flags & I2C_F_STOP) 232 (void) i2c_bitbang_send_stop(v, flags, ops); 233 234 return (error); 235 } 236