xref: /netbsd-src/sys/dev/i2c/gttwsi_core.c (revision d909946ca08dceb44d7d0f22ec9488679695d976)
1 /*	$NetBSD: gttwsi_core.c,v 1.2 2014/11/23 13:37:27 jmcneill Exp $	*/
2 /*
3  * Copyright (c) 2008 Eiji Kawauchi.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed for the NetBSD Project by
17  *      Eiji Kawauchi.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 /*
33  * Copyright (c) 2005 Brocade Communcations, inc.
34  * All rights reserved.
35  *
36  * Written by Matt Thomas for Brocade Communcations, Inc.
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions
40  * are met:
41  * 1. Redistributions of source code must retain the above copyright
42  *    notice, this list of conditions and the following disclaimer.
43  * 2. Redistributions in binary form must reproduce the above copyright
44  *    notice, this list of conditions and the following disclaimer in the
45  *    documentation and/or other materials provided with the distribution.
46  * 3. The name of Brocade Communications, Inc. may not be used to endorse
47  *    or promote products derived from this software without specific prior
48  *    written permission.
49  *
50  * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
51  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53  * ARE DISCLAIMED.  IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
54  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
60  * OF THE POSSIBILITY OF SUCH DAMAGE.
61  */
62 //#define TWSI_DEBUG
63 
64 /*
65  * Marvell Two-Wire Serial Interface (aka I2C) master driver
66  */
67 
68 #include <sys/cdefs.h>
69 __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.2 2014/11/23 13:37:27 jmcneill Exp $");
70 #include "locators.h"
71 
72 #include <sys/param.h>
73 #include <sys/bus.h>
74 #include <sys/condvar.h>
75 #include <sys/device.h>
76 #include <sys/errno.h>
77 #include <sys/kernel.h>
78 #include <sys/mutex.h>
79 #include <sys/systm.h>
80 
81 #include <dev/i2c/i2cvar.h>
82 
83 #include <dev/i2c/gttwsireg.h>
84 #include <dev/i2c/gttwsivar.h>
85 
86 static int	gttwsi_acquire_bus(void *, int);
87 static void	gttwsi_release_bus(void *, int);
88 static int	gttwsi_send_start(void *v, int flags);
89 static int	gttwsi_send_stop(void *v, int flags);
90 static int	gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
91 static int	gttwsi_read_byte(void *v, uint8_t *valp, int flags);
92 static int	gttwsi_write_byte(void *v, uint8_t val, int flags);
93 
94 static int	gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t, int);
95 
96 static inline uint32_t
97 gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)
98 {
99 	uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
100 #ifdef TWSI_DEBUG
101 	printf("I2C:R:%02x:%02x\n", reg, val);
102 #else
103 	DELAY(TWSI_READ_DELAY);
104 #endif
105 	return val;
106 }
107 
108 static inline void
109 gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
110 {
111 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
112 #ifdef TWSI_DEBUG
113 	printf("I2C:W:%02x:%02x\n", reg, val);
114 #else
115 	DELAY(TWSI_WRITE_DELAY);
116 #endif
117 	return;
118 }
119 
120 
121 
122 /* ARGSUSED */
123 void
124 gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh)
125 {
126 	struct gttwsi_softc * const sc = device_private(self);
127 	prop_dictionary_t cfg = device_properties(self);
128 
129 	aprint_naive("\n");
130 	aprint_normal(": Marvell TWSI controller\n");
131 
132 	sc->sc_dev = self;
133 	sc->sc_bust = iot;
134 	sc->sc_bush = ioh;
135 
136 	mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
137 	mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
138 	cv_init(&sc->sc_cv, device_xname(self));
139 
140 	prop_dictionary_get_bool(cfg, "iflg-rwc", &sc->sc_iflg_rwc);
141 
142 	sc->sc_started = false;
143 	sc->sc_i2c.ic_cookie = sc;
144 	sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus;
145 	sc->sc_i2c.ic_release_bus = gttwsi_release_bus;
146 	sc->sc_i2c.ic_exec = NULL;
147 	sc->sc_i2c.ic_send_start = gttwsi_send_start;
148 	sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
149 	sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
150 	sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
151 	sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
152 
153 	/*
154 	 * Put the controller into Soft Reset.
155 	 */
156 	/* reset */
157 	gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
158 
159 }
160 
161 void
162 gttwsi_config_children(device_t self)
163 {
164 	struct gttwsi_softc * const sc = device_private(self);
165 	struct i2cbus_attach_args iba;
166 
167 	memset(&iba, 0, sizeof(iba));
168 	iba.iba_tag = &sc->sc_i2c;
169 
170 	(void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
171 }
172 
173 int
174 gttwsi_intr(void *arg)
175 {
176 	struct gttwsi_softc *sc = arg;
177 	uint32_t val;
178 
179 	val = gttwsi_read_4(sc, TWSI_CONTROL);
180 	if (val & CONTROL_IFLG) {
181 		gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
182 		mutex_enter(&sc->sc_mtx);
183 		cv_signal(&sc->sc_cv);
184 		mutex_exit(&sc->sc_mtx);
185 
186 		return 1;	/* handled */
187 	}
188 	return 0;
189 }
190 
191 /* ARGSUSED */
192 static int
193 gttwsi_acquire_bus(void *arg, int flags)
194 {
195 	struct gttwsi_softc *sc = arg;
196 
197 	mutex_enter(&sc->sc_buslock);
198 	return 0;
199 }
200 
201 /* ARGSUSED */
202 static void
203 gttwsi_release_bus(void *arg, int flags)
204 {
205 	struct gttwsi_softc *sc = arg;
206 
207 	mutex_exit(&sc->sc_buslock);
208 }
209 
210 static int
211 gttwsi_send_start(void *v, int flags)
212 {
213 	struct gttwsi_softc *sc = v;
214 	int expect;
215 
216 	if (sc->sc_started)
217 		expect = STAT_RSCT;
218 	else
219 		expect = STAT_SCT;
220 	sc->sc_started = true;
221 	return gttwsi_wait(sc, CONTROL_START, expect, flags);
222 }
223 
224 static int
225 gttwsi_send_stop(void *v, int flags)
226 {
227 	struct gttwsi_softc *sc = v;
228 	int retry = TWSI_RETRY_COUNT;
229 	uint32_t control;
230 
231 	sc->sc_started = false;
232 
233 	/* Interrupt is not generated for STAT_NRS. */
234 	control = CONTROL_STOP | CONTROL_TWSIEN;
235 	if (sc->sc_iflg_rwc)
236 		control |= CONTROL_IFLG;
237 	gttwsi_write_4(sc, TWSI_CONTROL, control);
238 	while (retry > 0) {
239 		if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS)
240 			return 0;
241 		retry--;
242 		DELAY(TWSI_STAT_DELAY);
243 	}
244 
245 	aprint_error_dev(sc->sc_dev, "send STOP failed\n");
246 	return -1;
247 }
248 
249 static int
250 gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
251 {
252 	struct gttwsi_softc *sc = v;
253 	uint32_t data, expect;
254 	int error, read;
255 
256 	gttwsi_send_start(v, flags);
257 
258 	read = (flags & I2C_F_READ) != 0;
259 	if (read)
260 		expect = STAT_ARBT_AR;
261 	else
262 		expect = STAT_AWBT_AR;
263 
264 	/*
265 	 * First byte contains whether this xfer is a read or write.
266 	 */
267 	data = read;
268 	if (addr > 0x7f) {
269 		/*
270 		 * If this is a 10bit request, the first address byte is
271 		 * 0b11110<b9><b8><r/w>.
272 		 */
273 		data |= 0xf0 | ((addr & 0x300) >> 7);
274 		gttwsi_write_4(sc, TWSI_DATA, data);
275 		error = gttwsi_wait(sc, 0, expect, flags);
276 		if (error)
277 			return error;
278 		/*
279 		 * The first address byte has been sent, now to send
280 		 * the second one.
281 		 */
282 		if (read)
283 			expect = STAT_SARBT_AR;
284 		else
285 			expect = STAT_SAWBT_AR;
286 		data = (uint8_t)addr;
287 	} else
288 		data |= (addr << 1);
289 
290 	gttwsi_write_4(sc, TWSI_DATA, data);
291 	return gttwsi_wait(sc, 0, expect, flags);
292 }
293 
294 static int
295 gttwsi_read_byte(void *v, uint8_t *valp, int flags)
296 {
297 	struct gttwsi_softc *sc = v;
298 	int error;
299 
300 	if (flags & I2C_F_LAST)
301 		error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, flags);
302 	else
303 		error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags);
304 	if (!error)
305 		*valp = gttwsi_read_4(sc, TWSI_DATA);
306 	if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
307 		error = gttwsi_send_stop(sc, flags);
308 	return error;
309 }
310 
311 static int
312 gttwsi_write_byte(void *v, uint8_t val, int flags)
313 {
314 	struct gttwsi_softc *sc = v;
315 	int error;
316 
317 	gttwsi_write_4(sc, TWSI_DATA, val);
318 	error = gttwsi_wait(sc, 0, STAT_MTDB_AR, flags);
319 	if (flags & I2C_F_STOP)
320 		gttwsi_send_stop(sc, flags);
321 	return error;
322 }
323 
324 static int
325 gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
326 	    int flags)
327 {
328 	uint32_t status;
329 	int timo, error = 0;
330 
331 	DELAY(5);
332 	if (!(flags & I2C_F_POLL))
333 		control |= CONTROL_INTEN;
334 	if (sc->sc_iflg_rwc)
335 		control |= CONTROL_IFLG;
336 	gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
337 
338 	timo = 0;
339 	for (;;) {
340 		control = gttwsi_read_4(sc, TWSI_CONTROL);
341 		if (control & CONTROL_IFLG)
342 			break;
343 		if (!(flags & I2C_F_POLL)) {
344 			mutex_enter(&sc->sc_mtx);
345 			error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
346 			mutex_exit(&sc->sc_mtx);
347 			if (error)
348 				return error;
349 		}
350 		DELAY(TWSI_RETRY_DELAY);
351 		if (timo++ > 1000000)	/* 1sec */
352 			break;
353 	}
354 
355 	status = gttwsi_read_4(sc, TWSI_STATUS);
356 	if (status != expect) {
357 		aprint_error_dev(sc->sc_dev,
358 		    "unexpected status 0x%x: expect 0x%x\n", status, expect);
359 		return EIO;
360 	}
361 	return error;
362 }
363