1 /* $NetBSD: ds1307.c,v 1.23 2016/10/04 15:06:59 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.23 2016/10/04 15:06:59 kiyohara Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 struct dsrtc_model { 57 uint16_t dm_model; 58 uint8_t dm_ch_reg; 59 uint8_t dm_ch_value; 60 uint8_t dm_rtc_start; 61 uint8_t dm_rtc_size; 62 uint8_t dm_nvram_start; 63 uint8_t dm_nvram_size; 64 uint8_t dm_flags; 65 #define DSRTC_FLAG_CLOCK_HOLD 1 66 #define DSRTC_FLAG_BCD 2 67 #define DSRTC_FLAG_TEMP 4 68 }; 69 70 static const struct dsrtc_model dsrtc_models[] = { 71 { 72 .dm_model = 1307, 73 .dm_ch_reg = DSXXXX_SECONDS, 74 .dm_ch_value = DS1307_SECONDS_CH, 75 .dm_rtc_start = DS1307_RTC_START, 76 .dm_rtc_size = DS1307_RTC_SIZE, 77 .dm_nvram_start = DS1307_NVRAM_START, 78 .dm_nvram_size = DS1307_NVRAM_SIZE, 79 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 80 }, { 81 .dm_model = 1339, 82 .dm_rtc_start = DS1339_RTC_START, 83 .dm_rtc_size = DS1339_RTC_SIZE, 84 .dm_flags = DSRTC_FLAG_BCD, 85 }, { 86 .dm_model = 1340, 87 .dm_ch_reg = DSXXXX_SECONDS, 88 .dm_ch_value = DS1340_SECONDS_EOSC, 89 .dm_rtc_start = DS1340_RTC_START, 90 .dm_rtc_size = DS1340_RTC_SIZE, 91 .dm_flags = DSRTC_FLAG_BCD, 92 }, { 93 .dm_model = 1672, 94 .dm_rtc_start = DS1672_RTC_START, 95 .dm_rtc_size = DS1672_RTC_SIZE, 96 .dm_ch_reg = DS1672_CONTROL, 97 .dm_ch_value = DS1672_CONTROL_CH, 98 .dm_flags = 0, 99 }, { 100 .dm_model = 3231, 101 .dm_rtc_start = DS3232_RTC_START, 102 .dm_rtc_size = DS3232_RTC_SIZE, 103 /* 104 * XXX 105 * the DS3232 likely has the temperature sensor too but I can't 106 * easily verify or test that right now 107 */ 108 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 109 }, { 110 .dm_model = 3232, 111 .dm_rtc_start = DS3232_RTC_START, 112 .dm_rtc_size = DS3232_RTC_SIZE, 113 .dm_nvram_start = DS3232_NVRAM_START, 114 .dm_nvram_size = DS3232_NVRAM_SIZE, 115 .dm_flags = DSRTC_FLAG_BCD, 116 }, 117 }; 118 119 struct dsrtc_softc { 120 device_t sc_dev; 121 i2c_tag_t sc_tag; 122 uint8_t sc_address; 123 bool sc_open; 124 struct dsrtc_model sc_model; 125 struct todr_chip_handle sc_todr; 126 struct sysmon_envsys *sc_sme; 127 envsys_data_t sc_sensor; 128 }; 129 130 static void dsrtc_attach(device_t, device_t, void *); 131 static int dsrtc_match(device_t, cfdata_t, void *); 132 133 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 134 dsrtc_match, dsrtc_attach, NULL, NULL); 135 extern struct cfdriver dsrtc_cd; 136 137 dev_type_open(dsrtc_open); 138 dev_type_close(dsrtc_close); 139 dev_type_read(dsrtc_read); 140 dev_type_write(dsrtc_write); 141 142 const struct cdevsw dsrtc_cdevsw = { 143 .d_open = dsrtc_open, 144 .d_close = dsrtc_close, 145 .d_read = dsrtc_read, 146 .d_write = dsrtc_write, 147 .d_ioctl = noioctl, 148 .d_stop = nostop, 149 .d_tty = notty, 150 .d_poll = nopoll, 151 .d_mmap = nommap, 152 .d_kqfilter = nokqfilter, 153 .d_discard = nodiscard, 154 .d_flag = D_OTHER 155 }; 156 157 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 158 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 159 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 160 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 161 162 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 163 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 164 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 165 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 166 167 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 168 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 169 170 static const struct dsrtc_model * 171 dsrtc_model(u_int model) 172 { 173 /* no model given, assume it's a DS1307 (the first one) */ 174 if (model == 0) 175 return &dsrtc_models[0]; 176 177 for (const struct dsrtc_model *dm = dsrtc_models; 178 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 179 if (dm->dm_model == model) 180 return dm; 181 } 182 return NULL; 183 } 184 185 static int 186 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 187 { 188 struct i2c_attach_args *ia = arg; 189 190 if (ia->ia_name) { 191 /* direct config - check name */ 192 if (strcmp(ia->ia_name, "dsrtc") == 0) 193 return 1; 194 } else { 195 /* indirect config - check typical address */ 196 if (ia->ia_addr == DS1307_ADDR) 197 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 198 } 199 return 0; 200 } 201 202 static void 203 dsrtc_attach(device_t parent, device_t self, void *arg) 204 { 205 struct dsrtc_softc *sc = device_private(self); 206 struct i2c_attach_args *ia = arg; 207 const struct dsrtc_model * const dm = 208 dsrtc_model(device_cfdata(self)->cf_flags); 209 210 aprint_naive(": Real-time Clock%s\n", 211 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 212 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 213 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 214 215 sc->sc_tag = ia->ia_tag; 216 sc->sc_address = ia->ia_addr; 217 sc->sc_model = *dm; 218 sc->sc_dev = self; 219 sc->sc_open = 0; 220 sc->sc_todr.cookie = sc; 221 if (dm->dm_flags & DSRTC_FLAG_BCD) { 222 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 223 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 224 } else { 225 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 226 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 227 } 228 sc->sc_todr.todr_setwen = NULL; 229 230 todr_attach(&sc->sc_todr); 231 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 232 int error; 233 234 sc->sc_sme = sysmon_envsys_create(); 235 sc->sc_sme->sme_name = device_xname(self); 236 sc->sc_sme->sme_cookie = sc; 237 sc->sc_sme->sme_refresh = dsrtc_refresh; 238 239 sc->sc_sensor.units = ENVSYS_STEMP; 240 sc->sc_sensor.state = ENVSYS_SINVALID; 241 sc->sc_sensor.flags = 0; 242 (void)strlcpy(sc->sc_sensor.desc, "temperature", 243 sizeof(sc->sc_sensor.desc)); 244 245 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 246 aprint_error_dev(self, "unable to attach sensor\n"); 247 goto bad; 248 } 249 250 error = sysmon_envsys_register(sc->sc_sme); 251 if (error) { 252 aprint_error_dev(self, 253 "error %d registering with sysmon\n", error); 254 goto bad; 255 } 256 } 257 return; 258 bad: 259 sysmon_envsys_destroy(sc->sc_sme); 260 } 261 262 /*ARGSUSED*/ 263 int 264 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 265 { 266 struct dsrtc_softc *sc; 267 268 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 269 return ENXIO; 270 271 /* XXX: Locking */ 272 if (sc->sc_open) 273 return EBUSY; 274 275 sc->sc_open = true; 276 return 0; 277 } 278 279 /*ARGSUSED*/ 280 int 281 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 282 { 283 struct dsrtc_softc *sc; 284 285 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 286 return ENXIO; 287 288 sc->sc_open = false; 289 return 0; 290 } 291 292 /*ARGSUSED*/ 293 int 294 dsrtc_read(dev_t dev, struct uio *uio, int flags) 295 { 296 struct dsrtc_softc *sc; 297 int error; 298 299 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 300 return ENXIO; 301 302 const struct dsrtc_model * const dm = &sc->sc_model; 303 if (uio->uio_offset >= dm->dm_nvram_size) 304 return EINVAL; 305 306 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 307 return error; 308 309 KASSERT(uio->uio_offset >= 0); 310 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 311 uint8_t ch, cmd; 312 const u_int a = uio->uio_offset; 313 cmd = a + dm->dm_nvram_start; 314 if ((error = iic_exec(sc->sc_tag, 315 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 316 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 317 iic_release_bus(sc->sc_tag, 0); 318 aprint_error_dev(sc->sc_dev, 319 "%s: read failed at 0x%x: %d\n", 320 __func__, a, error); 321 return error; 322 } 323 if ((error = uiomove(&ch, 1, uio)) != 0) { 324 iic_release_bus(sc->sc_tag, 0); 325 return error; 326 } 327 } 328 329 iic_release_bus(sc->sc_tag, 0); 330 331 return 0; 332 } 333 334 /*ARGSUSED*/ 335 int 336 dsrtc_write(dev_t dev, struct uio *uio, int flags) 337 { 338 struct dsrtc_softc *sc; 339 int error; 340 341 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 342 return ENXIO; 343 344 const struct dsrtc_model * const dm = &sc->sc_model; 345 if (uio->uio_offset >= dm->dm_nvram_size) 346 return EINVAL; 347 348 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 349 return error; 350 351 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 352 uint8_t cmdbuf[2]; 353 const u_int a = (int)uio->uio_offset; 354 cmdbuf[0] = a + dm->dm_nvram_start; 355 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 356 break; 357 358 if ((error = iic_exec(sc->sc_tag, 359 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 360 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "%s: write failed at 0x%x: %d\n", 363 __func__, a, error); 364 break; 365 } 366 } 367 368 iic_release_bus(sc->sc_tag, 0); 369 370 return error; 371 } 372 373 static int 374 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 375 { 376 struct dsrtc_softc *sc = ch->cookie; 377 struct clock_ymdhms check; 378 int retries; 379 380 memset(dt, 0, sizeof(*dt)); 381 memset(&check, 0, sizeof(check)); 382 383 /* 384 * Since we don't support Burst Read, we have to read the clock twice 385 * until we get two consecutive identical results. 386 */ 387 retries = 5; 388 do { 389 dsrtc_clock_read_ymdhms(sc, dt); 390 dsrtc_clock_read_ymdhms(sc, &check); 391 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 392 393 return 0; 394 } 395 396 static int 397 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 398 { 399 struct dsrtc_softc *sc = ch->cookie; 400 401 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 402 return -1; 403 404 return 0; 405 } 406 407 static int 408 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 409 { 410 struct dsrtc_model * const dm = &sc->sc_model; 411 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 412 int error; 413 414 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 415 416 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 417 aprint_error_dev(sc->sc_dev, 418 "%s: failed to acquire I2C bus: %d\n", 419 __func__, error); 420 return 0; 421 } 422 423 /* Read each RTC register in order. */ 424 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 425 cmdbuf[0] = dm->dm_rtc_start + i; 426 427 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 428 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 429 } 430 431 /* Done with I2C */ 432 iic_release_bus(sc->sc_tag, I2C_F_POLL); 433 434 if (error != 0) { 435 aprint_error_dev(sc->sc_dev, 436 "%s: failed to read rtc at 0x%x: %d\n", 437 __func__, cmdbuf[0], error); 438 return 0; 439 } 440 441 /* 442 * Convert the RTC's register values into something useable 443 */ 444 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 445 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 446 447 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 448 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 449 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 450 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 451 dt->dt_hour += 12; 452 } else 453 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 454 DSXXXX_HOURS_24MASK); 455 456 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 457 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 458 459 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 460 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 461 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 462 dt->dt_year += 100; 463 464 return 1; 465 } 466 467 static int 468 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 469 { 470 struct dsrtc_model * const dm = &sc->sc_model; 471 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 472 int error; 473 474 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 475 476 /* 477 * Convert our time representation into something the DSXXXX 478 * can understand. 479 */ 480 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 481 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 482 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 483 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 484 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 485 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 486 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 487 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 488 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 489 490 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 491 aprint_error_dev(sc->sc_dev, 492 "%s: failed to acquire I2C bus: %d\n", 493 __func__, error); 494 return 0; 495 } 496 497 /* Stop the clock */ 498 cmdbuf[0] = dm->dm_ch_reg; 499 500 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 501 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 502 iic_release_bus(sc->sc_tag, I2C_F_POLL); 503 aprint_error_dev(sc->sc_dev, 504 "%s: failed to read Hold Clock: %d\n", 505 __func__, error); 506 return 0; 507 } 508 509 cmdbuf[1] |= dm->dm_ch_value; 510 511 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 512 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 513 iic_release_bus(sc->sc_tag, I2C_F_POLL); 514 aprint_error_dev(sc->sc_dev, 515 "%s: failed to write Hold Clock: %d\n", 516 __func__, error); 517 return 0; 518 } 519 520 /* 521 * Write registers in reverse order. The last write (to the Seconds 522 * register) will undo the Clock Hold, above. 523 */ 524 uint8_t op = I2C_OP_WRITE; 525 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 526 cmdbuf[0] = dm->dm_rtc_start + i; 527 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 528 op = I2C_OP_WRITE_WITH_STOP; 529 } 530 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 531 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 532 iic_release_bus(sc->sc_tag, I2C_F_POLL); 533 aprint_error_dev(sc->sc_dev, 534 "%s: failed to write rtc at 0x%x: %d\n", 535 __func__, i, error); 536 /* XXX: Clock Hold is likely still asserted! */ 537 return 0; 538 } 539 } 540 /* 541 * If the clock hold register isn't the same register as seconds, 542 * we need to reeanble the clock. 543 */ 544 if (op != I2C_OP_WRITE_WITH_STOP) { 545 cmdbuf[0] = dm->dm_ch_reg; 546 cmdbuf[1] &= ~dm->dm_ch_value; 547 548 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 549 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 550 I2C_F_POLL)) != 0) { 551 iic_release_bus(sc->sc_tag, I2C_F_POLL); 552 aprint_error_dev(sc->sc_dev, 553 "%s: failed to Hold Clock: %d\n", 554 __func__, error); 555 return 0; 556 } 557 } 558 559 iic_release_bus(sc->sc_tag, I2C_F_POLL); 560 561 return 1; 562 } 563 564 static int 565 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 566 { 567 struct dsrtc_softc *sc = ch->cookie; 568 struct timeval check; 569 int retries; 570 571 memset(tv, 0, sizeof(*tv)); 572 memset(&check, 0, sizeof(check)); 573 574 /* 575 * Since we don't support Burst Read, we have to read the clock twice 576 * until we get two consecutive identical results. 577 */ 578 retries = 5; 579 do { 580 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 581 dsrtc_clock_read_timeval(sc, &check.tv_sec); 582 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 583 584 return 0; 585 } 586 587 static int 588 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 589 { 590 struct dsrtc_softc *sc = ch->cookie; 591 592 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 593 return -1; 594 595 return 0; 596 } 597 598 /* 599 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 600 * it, since some I2C controllers don't support anything other than single-byte 601 * transfers. 602 */ 603 static int 604 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 605 { 606 const struct dsrtc_model * const dm = &sc->sc_model; 607 uint8_t buf[4]; 608 int error; 609 610 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 611 aprint_error_dev(sc->sc_dev, 612 "%s: failed to acquire I2C bus: %d\n", 613 __func__, error); 614 return 0; 615 } 616 617 /* read all registers: */ 618 uint8_t reg = dm->dm_rtc_start; 619 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 620 ®, 1, buf, 4, I2C_F_POLL); 621 622 /* Done with I2C */ 623 iic_release_bus(sc->sc_tag, I2C_F_POLL); 624 625 if (error != 0) { 626 aprint_error_dev(sc->sc_dev, 627 "%s: failed to read rtc at 0x%x: %d\n", 628 __func__, reg, error); 629 return 0; 630 } 631 632 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 633 *tp = v; 634 635 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 636 __func__, v); 637 638 return 1; 639 } 640 641 static int 642 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 643 { 644 const struct dsrtc_model * const dm = &sc->sc_model; 645 size_t buflen = dm->dm_rtc_size + 2; 646 uint8_t buf[buflen]; 647 int error; 648 649 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 650 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 651 652 buf[0] = dm->dm_rtc_start; 653 buf[1] = (t >> 0) & 0xff; 654 buf[2] = (t >> 8) & 0xff; 655 buf[3] = (t >> 16) & 0xff; 656 buf[4] = (t >> 24) & 0xff; 657 buf[5] = 0; 658 659 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 660 aprint_error_dev(sc->sc_dev, 661 "%s: failed to acquire I2C bus: %d\n", 662 __func__, error); 663 return 0; 664 } 665 666 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 667 &buf, buflen, NULL, 0, I2C_F_POLL); 668 669 /* Done with I2C */ 670 iic_release_bus(sc->sc_tag, I2C_F_POLL); 671 672 /* send data */ 673 if (error != 0) { 674 aprint_error_dev(sc->sc_dev, 675 "%s: failed to set time: %d\n", 676 __func__, error); 677 return 0; 678 } 679 680 return 1; 681 } 682 683 static int 684 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 685 { 686 int error, tc; 687 uint8_t reg = DS3232_TEMP_MSB; 688 uint8_t buf[2]; 689 690 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 691 return ENOTSUP; 692 693 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 694 aprint_error_dev(sc->sc_dev, 695 "%s: failed to acquire I2C bus: %d\n", 696 __func__, error); 697 return 0; 698 } 699 700 /* read temperature registers: */ 701 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 702 ®, 1, buf, 2, I2C_F_POLL); 703 704 /* Done with I2C */ 705 iic_release_bus(sc->sc_tag, I2C_F_POLL); 706 707 if (error != 0) { 708 aprint_error_dev(sc->sc_dev, 709 "%s: failed to read temperature: %d\n", 710 __func__, error); 711 return 0; 712 } 713 714 /* convert to microkelvin */ 715 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 716 *temp = tc + 273150000; 717 return 1; 718 } 719 720 static void 721 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 722 { 723 struct dsrtc_softc *sc = sme->sme_cookie; 724 uint32_t temp = 0; /* XXX gcc */ 725 726 if (dsrtc_read_temp(sc, &temp) == 0) { 727 edata->state = ENVSYS_SINVALID; 728 return; 729 } 730 731 edata->value_cur = temp; 732 733 edata->state = ENVSYS_SVALID; 734 } 735