1 /* $NetBSD: dbcool.c,v 1.48 2018/02/06 10:02:09 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.48 2018/02/06 10:02:09 mrg Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 109 110 /* Set-up subroutines */ 111 static void dbcool_setup_controllers(struct dbcool_softc *); 112 static int dbcool_setup_sensors(struct dbcool_softc *); 113 static int dbcool_attach_sensor(struct dbcool_softc *, int); 114 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 115 struct chip_id *); 116 117 #ifdef DBCOOL_DEBUG 118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 120 #endif /* DBCOOL_DEBUG */ 121 122 /* 123 * Descriptions for SYSCTL entries 124 */ 125 struct dbc_sysctl_info { 126 const char *name; 127 const char *desc; 128 bool lockable; 129 int (*helper)(SYSCTLFN_PROTO); 130 }; 131 132 static struct dbc_sysctl_info dbc_sysctl_table[] = { 133 /* 134 * The first several entries must remain in the same order as the 135 * corresponding entries in enum dbc_pwm_params 136 */ 137 { "behavior", "operating behavior and temp selector", 138 true, sysctl_dbcool_behavior }, 139 { "min_duty", "minimum fan controller PWM duty cycle", 140 true, sysctl_dbcool_duty }, 141 { "max_duty", "maximum fan controller PWM duty cycle", 142 true, sysctl_dbcool_duty }, 143 { "cur_duty", "current fan controller PWM duty cycle", 144 false, sysctl_dbcool_duty }, 145 146 /* 147 * The rest of these should be in the order in which they 148 * are to be stored in the sysctl tree; the table index is 149 * used as the high-order bits of the sysctl_num to maintain 150 * the sequence. 151 * 152 * If you rearrange the order of these items, be sure to 153 * update the sysctl_index in the XXX_sensor_table[] for 154 * the various chips! 155 */ 156 { "Trange", "temp slope/range to reach 100% duty cycle", 157 true, sysctl_dbcool_slope }, 158 { "Tmin", "temp at which to start fan controller", 159 true, sysctl_dbcool_temp }, 160 { "Ttherm", "temp at which THERM is asserted", 161 true, sysctl_dbcool_temp }, 162 { "Thyst", "temp hysteresis for stopping fan controller", 163 true, sysctl_dbcool_thyst }, 164 { "Tmin", "temp at which to start fan controller", 165 true, sysctl_adm1030_temp }, 166 { "Trange", "temp slope/range to reach 100% duty cycle", 167 true, sysctl_adm1030_trange }, 168 }; 169 170 static const char *dbc_sensor_names[] = { 171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 173 "V5", "V12", "Vtt", "Imon", "VID" 174 }; 175 176 /* 177 * Following table derived from product data-sheets 178 */ 179 static int64_t nominal_voltages[] = { 180 -1, /* Vcc can be either 3.3 or 5.0V 181 at 3/4 scale */ 182 2249939, /* Vccp 2.25V 3/4 scale */ 183 2497436, /* 2.5VIN 2.5V 3/4 scale */ 184 5002466, /* 5VIN 5V 3/4 scale */ 185 12000000, /* 12VIN 12V 3/4 scale */ 186 1690809, /* Vtt, Imon 2.25V full scale */ 187 1689600, /* AIN1, AIN2 2.25V full scale */ 188 0 189 }; 190 191 /* 192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 193 * nom-voltage-index 194 */ 195 struct dbcool_sensor ADT7490_sensor_table[] = { 196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 197 DBCOOL_LOCAL_HIGHLIM, 198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 200 DBCOOL_REMOTE1_HIGHLIM, 201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 203 DBCOOL_REMOTE2_HIGHLIM, 204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 205 { DBC_VOLT, { DBCOOL_VCCP, 206 DBCOOL_VCCP_HIGHLIM, 207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 208 { DBC_VOLT, { DBCOOL_VCC, 209 DBCOOL_VCC_HIGHLIM, 210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 211 { DBC_VOLT, { DBCOOL_25VIN, 212 DBCOOL_25VIN_HIGHLIM, 213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 214 { DBC_VOLT, { DBCOOL_5VIN, 215 DBCOOL_5VIN_HIGHLIM, 216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 217 { DBC_VOLT, { DBCOOL_12VIN, 218 DBCOOL_12VIN_HIGHLIM, 219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 220 { DBC_VOLT, { DBCOOL_VTT, 221 DBCOOL_VTT_HIGHLIM, 222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 223 { DBC_VOLT, { DBCOOL_IMON, 224 DBCOOL_IMON_HIGHLIM, 225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 227 DBCOOL_NO_REG, 228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 230 DBCOOL_NO_REG, 231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 233 DBCOOL_NO_REG, 234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 236 DBCOOL_NO_REG, 237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 238 { DBC_VID, { DBCOOL_VID_REG, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 16, 0, 0 }, 241 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 0, 5, 0 }, 244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 0, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 0, 7, 0 }, 250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 251 DBCOOL_NO_REG, 252 DBCOOL_NO_REG }, 1, 5, 0 }, 253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 254 DBCOOL_NO_REG, 255 DBCOOL_NO_REG }, 1, 6, 0 }, 256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 257 DBCOOL_NO_REG, 258 DBCOOL_NO_REG }, 1, 7, 0 }, 259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 260 DBCOOL_NO_REG, 261 DBCOOL_NO_REG }, 2, 5, 0 }, 262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 263 DBCOOL_NO_REG, 264 DBCOOL_NO_REG }, 2, 6, 0 }, 265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 266 DBCOOL_NO_REG, 267 DBCOOL_NO_REG }, 2, 7, 0 }, 268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 269 }; 270 271 struct dbcool_sensor ADT7476_sensor_table[] = { 272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 273 DBCOOL_LOCAL_HIGHLIM, 274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 276 DBCOOL_REMOTE1_HIGHLIM, 277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 279 DBCOOL_REMOTE2_HIGHLIM, 280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 281 { DBC_VOLT, { DBCOOL_VCCP, 282 DBCOOL_VCCP_HIGHLIM, 283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 284 { DBC_VOLT, { DBCOOL_VCC, 285 DBCOOL_VCC_HIGHLIM, 286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 287 { DBC_VOLT, { DBCOOL_25VIN, 288 DBCOOL_25VIN_HIGHLIM, 289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 290 { DBC_VOLT, { DBCOOL_5VIN, 291 DBCOOL_5VIN_HIGHLIM, 292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 293 { DBC_VOLT, { DBCOOL_12VIN, 294 DBCOOL_12VIN_HIGHLIM, 295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 297 DBCOOL_NO_REG, 298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 300 DBCOOL_NO_REG, 301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 303 DBCOOL_NO_REG, 304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 306 DBCOOL_NO_REG, 307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 308 { DBC_VID, { DBCOOL_VID_REG, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 16, 0, 0 }, 311 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 0, 5, 0 }, 314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 0, 6, 0 }, 317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 318 DBCOOL_NO_REG, 319 DBCOOL_NO_REG }, 0, 7, 0 }, 320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 321 DBCOOL_NO_REG, 322 DBCOOL_NO_REG }, 1, 5, 0 }, 323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 324 DBCOOL_NO_REG, 325 DBCOOL_NO_REG }, 1, 6, 0 }, 326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 327 DBCOOL_NO_REG, 328 DBCOOL_NO_REG }, 1, 7, 0 }, 329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 330 DBCOOL_NO_REG, 331 DBCOOL_NO_REG }, 2, 5, 0 }, 332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 333 DBCOOL_NO_REG, 334 DBCOOL_NO_REG }, 2, 6, 0 }, 335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 336 DBCOOL_NO_REG, 337 DBCOOL_NO_REG }, 2, 7, 0 }, 338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 339 }; 340 341 struct dbcool_sensor ADT7475_sensor_table[] = { 342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 343 DBCOOL_LOCAL_HIGHLIM, 344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 346 DBCOOL_REMOTE1_HIGHLIM, 347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 349 DBCOOL_REMOTE2_HIGHLIM, 350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 351 { DBC_VOLT, { DBCOOL_VCCP, 352 DBCOOL_VCCP_HIGHLIM, 353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 354 { DBC_VOLT, { DBCOOL_VCC, 355 DBCOOL_VCC_HIGHLIM, 356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 358 DBCOOL_NO_REG, 359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 361 DBCOOL_NO_REG, 362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 364 DBCOOL_NO_REG, 365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 367 DBCOOL_NO_REG, 368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 369 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 0, 5, 0 }, 372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 0, 6, 0 }, 375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 376 DBCOOL_NO_REG, 377 DBCOOL_NO_REG }, 0, 7, 0 }, 378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 379 DBCOOL_NO_REG, 380 DBCOOL_NO_REG }, 1, 5, 0 }, 381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 382 DBCOOL_NO_REG, 383 DBCOOL_NO_REG }, 1, 6, 0 }, 384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 385 DBCOOL_NO_REG, 386 DBCOOL_NO_REG }, 1, 7, 0 }, 387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 388 DBCOOL_NO_REG, 389 DBCOOL_NO_REG }, 2, 5, 0 }, 390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 391 DBCOOL_NO_REG, 392 DBCOOL_NO_REG }, 2, 6, 0 }, 393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 394 DBCOOL_NO_REG, 395 DBCOOL_NO_REG }, 2, 7, 0 }, 396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 397 }; 398 399 /* 400 * The registers of dbcool_power_control must be in the same order as 401 * in enum dbc_pwm_params 402 */ 403 struct dbcool_power_control ADT7475_power_table[] = { 404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 406 "fan_control_1" }, 407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 409 "fan_control_2" }, 410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 412 "fan_control_3" }, 413 { { 0, 0, 0, 0 }, NULL } 414 }; 415 416 struct dbcool_sensor ADT7466_sensor_table[] = { 417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 418 DBCOOL_ADT7466_LCL_TEMP_HILIM, 419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 421 DBCOOL_ADT7466_REM_TEMP_HILIM, 422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 423 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 424 DBCOOL_ADT7466_VCC_HILIM, 425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 427 DBCOOL_ADT7466_AIN1_HILIM, 428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 430 DBCOOL_ADT7466_AIN2_HILIM, 431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 433 DBCOOL_NO_REG, 434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 436 DBCOOL_NO_REG, 437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 439 }; 440 441 struct dbcool_sensor ADM1027_sensor_table[] = { 442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 443 DBCOOL_LOCAL_HIGHLIM, 444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 446 DBCOOL_REMOTE1_HIGHLIM, 447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 449 DBCOOL_REMOTE2_HIGHLIM, 450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 451 { DBC_VOLT, { DBCOOL_VCCP, 452 DBCOOL_VCCP_HIGHLIM, 453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 454 { DBC_VOLT, { DBCOOL_VCC, 455 DBCOOL_VCC_HIGHLIM, 456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 457 { DBC_VOLT, { DBCOOL_25VIN, 458 DBCOOL_25VIN_HIGHLIM, 459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 460 { DBC_VOLT, { DBCOOL_5VIN, 461 DBCOOL_5VIN_HIGHLIM, 462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 463 { DBC_VOLT, { DBCOOL_12VIN, 464 DBCOOL_12VIN_HIGHLIM, 465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 467 DBCOOL_NO_REG, 468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 470 DBCOOL_NO_REG, 471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 473 DBCOOL_NO_REG, 474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 476 DBCOOL_NO_REG, 477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 478 { DBC_VID, { DBCOOL_VID_REG, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 16, 0, 0 }, 481 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 0, 5, 0 }, 484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 485 DBCOOL_NO_REG, 486 DBCOOL_NO_REG }, 0, 6, 0 }, 487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 488 DBCOOL_NO_REG, 489 DBCOOL_NO_REG }, 0, 7, 0 }, 490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 491 DBCOOL_NO_REG, 492 DBCOOL_NO_REG }, 1, 5, 0 }, 493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 494 DBCOOL_NO_REG, 495 DBCOOL_NO_REG }, 1, 6, 0 }, 496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 497 DBCOOL_NO_REG, 498 DBCOOL_NO_REG }, 1, 7, 0 }, 499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 500 DBCOOL_NO_REG, 501 DBCOOL_NO_REG }, 2, 5, 0 }, 502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 503 DBCOOL_NO_REG, 504 DBCOOL_NO_REG }, 2, 6, 0 }, 505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 506 DBCOOL_NO_REG, 507 DBCOOL_NO_REG }, 2, 7, 0 }, 508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 509 }; 510 511 struct dbcool_sensor ADM1030_sensor_table[] = { 512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 513 DBCOOL_ADM1030_L_HI_LIM, 514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 516 DBCOOL_ADM1030_R_HI_LIM, 517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 519 DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 522 DBCOOL_NO_REG, 523 DBCOOL_NO_REG }, 0, 8, 0 }, 524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 525 DBCOOL_NO_REG, 526 DBCOOL_NO_REG }, 0, 9, 0 }, 527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 528 DBCOOL_NO_REG, 529 DBCOOL_NO_REG }, 0, 6, 0 }, 530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 531 DBCOOL_NO_REG, 532 DBCOOL_NO_REG }, 1, 8, 0 }, 533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 534 DBCOOL_NO_REG, 535 DBCOOL_NO_REG }, 1, 9, 0 }, 536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 537 DBCOOL_NO_REG, 538 DBCOOL_NO_REG }, 1, 6, 0 }, 539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 540 }; 541 542 struct dbcool_power_control ADM1030_power_table[] = { 543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 544 DBCOOL_ADM1030_FAN_SPEED_CFG }, 545 "fan_control_1" }, 546 { { 0, 0, 0, 0 }, NULL } 547 }; 548 549 struct dbcool_sensor ADM1031_sensor_table[] = { 550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 551 DBCOOL_ADM1030_L_HI_LIM, 552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 554 DBCOOL_ADM1030_R_HI_LIM, 555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 557 DBCOOL_ADM1031_R2_HI_LIM, 558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 560 DBCOOL_NO_REG, 561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 563 DBCOOL_NO_REG, 564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 566 DBCOOL_NO_REG, 567 DBCOOL_NO_REG }, 0, 8, 0 }, 568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 569 DBCOOL_NO_REG, 570 DBCOOL_NO_REG }, 0, 9, 0 }, 571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 572 DBCOOL_NO_REG, 573 DBCOOL_NO_REG }, 0, 6, 0 }, 574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 575 DBCOOL_NO_REG, 576 DBCOOL_NO_REG }, 1, 8, 0 }, 577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 578 DBCOOL_NO_REG, 579 DBCOOL_NO_REG }, 1, 9, 0 }, 580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 581 DBCOOL_NO_REG, 582 DBCOOL_NO_REG }, 1, 6, 0 }, 583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 584 DBCOOL_NO_REG, 585 DBCOOL_NO_REG }, 2, 8, 0 }, 586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 587 DBCOOL_NO_REG, 588 DBCOOL_NO_REG }, 2, 9, 0 }, 589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 590 DBCOOL_NO_REG, 591 DBCOOL_NO_REG }, 2, 6, 0 }, 592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 593 }; 594 595 struct dbcool_power_control ADM1031_power_table[] = { 596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 597 DBCOOL_ADM1030_FAN_SPEED_CFG }, 598 "fan_control_1" }, 599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 600 DBCOOL_ADM1030_FAN_SPEED_CFG }, 601 "fan_control_2" }, 602 { { 0, 0, 0, 0 }, NULL } 603 }; 604 605 struct dbcool_sensor EMC6D103S_sensor_table[] = { 606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 607 DBCOOL_LOCAL_HIGHLIM, 608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 610 DBCOOL_REMOTE1_HIGHLIM, 611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 613 DBCOOL_REMOTE2_HIGHLIM, 614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 615 { DBC_VOLT, { DBCOOL_VCCP, 616 DBCOOL_VCCP_HIGHLIM, 617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 618 { DBC_VOLT, { DBCOOL_VCC, 619 DBCOOL_VCC_HIGHLIM, 620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 621 { DBC_VOLT, { DBCOOL_25VIN, 622 DBCOOL_25VIN_HIGHLIM, 623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 624 { DBC_VOLT, { DBCOOL_5VIN, 625 DBCOOL_5VIN_HIGHLIM, 626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 627 { DBC_VOLT, { DBCOOL_12VIN, 628 DBCOOL_12VIN_HIGHLIM, 629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 631 DBCOOL_NO_REG, 632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 634 DBCOOL_NO_REG, 635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 637 DBCOOL_NO_REG, 638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 640 DBCOOL_NO_REG, 641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 642 { DBC_VID, { DBCOOL_VID_REG, 643 DBCOOL_NO_REG, 644 DBCOOL_NO_REG }, 16, 0, 0 }, 645 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 646 DBCOOL_NO_REG, 647 DBCOOL_NO_REG }, 0, 5, 0 }, 648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 649 DBCOOL_NO_REG, 650 DBCOOL_NO_REG }, 0, 6, 0 }, 651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 652 DBCOOL_NO_REG, 653 DBCOOL_NO_REG }, 1, 5, 0 }, 654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 655 DBCOOL_NO_REG, 656 DBCOOL_NO_REG }, 1, 6, 0 }, 657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 658 DBCOOL_NO_REG, 659 DBCOOL_NO_REG }, 2, 5, 0 }, 660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 661 DBCOOL_NO_REG, 662 DBCOOL_NO_REG }, 2, 6, 0 }, 663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 664 }; 665 666 struct chip_id chip_table[] = { 667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 668 ADT7490_sensor_table, ADT7475_power_table, 669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 670 90000 * 60, "ADT7490" }, 671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 672 ADT7476_sensor_table, ADT7475_power_table, 673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 674 90000 * 60, "ADT7476" }, 675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 676 ADT7475_sensor_table, ADT7475_power_table, 677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 678 90000 * 60, "ADT7475" }, 679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 680 ADT7475_sensor_table, ADT7475_power_table, 681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 682 90000 * 60, "ADT7460/ADT7463" }, 683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 684 ADT7475_sensor_table, ADT7475_power_table, 685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 686 90000 * 60, "ADT7463-1" }, 687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 688 ADT7476_sensor_table, ADT7475_power_table, 689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 691 90000 * 60, "ADT7467/ADT7468" }, 692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 693 ADT7466_sensor_table, NULL, 694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 695 82000 * 60, "ADT7466" }, 696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 697 ADM1027_sensor_table, ADT7475_power_table, 698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 699 90000 * 60, "ADT7463" }, 700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 701 ADM1027_sensor_table, ADT7475_power_table, 702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 703 DBCFLAG_HAS_VID_SEL, 704 90000 * 60, "ADT7463" }, 705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 706 ADM1027_sensor_table, ADT7475_power_table, 707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 708 90000 * 60, "ADM1027" }, 709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 710 ADM1030_sensor_table, ADM1030_power_table, 711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 712 11250 * 60, "ADM1030" }, 713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 714 ADM1031_sensor_table, ADM1030_power_table, 715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 716 11250 * 60, "ADM1031" }, 717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 718 EMC6D103S_sensor_table, ADT7475_power_table, 719 DBCFLAG_4BIT_VER, 720 90000 * 60, "EMC6D103S" }, 721 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 722 }; 723 724 static const char *behavior[] = { 725 "remote1", "local", "remote2", "full-speed", 726 "disabled", "local+remote2","all-temps", "manual" 727 }; 728 729 static char dbcool_cur_behav[16]; 730 731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 732 dbcool_match, dbcool_attach, dbcool_detach, NULL); 733 734 static const char * dbcool_compats[] = { 735 "i2c-adm1031", 736 "adt7467", 737 "adt7460", 738 "adm1030", 739 NULL 740 }; 741 int 742 dbcool_match(device_t parent, cfdata_t cf, void *aux) 743 { 744 struct i2c_attach_args *ia = aux; 745 struct dbcool_chipset dc; 746 dc.dc_tag = ia->ia_tag; 747 dc.dc_addr = ia->ia_addr; 748 dc.dc_chip = NULL; 749 dc.dc_readreg = dbcool_readreg; 750 dc.dc_writereg = dbcool_writereg; 751 752 /* Direct config - match compats */ 753 if (ia->ia_name) { 754 if (ia->ia_ncompat > 0) { 755 if (iic_compat_match(ia, dbcool_compats)) 756 return 1; 757 } 758 /* Indirect config - check address and chip ID */ 759 } else { 760 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 761 return 0; 762 if (dbcool_chip_ident(&dc) >= 0) 763 return 1; 764 } 765 return 0; 766 } 767 768 void 769 dbcool_attach(device_t parent, device_t self, void *aux) 770 { 771 struct dbcool_softc *sc = device_private(self); 772 struct i2c_attach_args *args = aux; 773 uint8_t ver; 774 775 sc->sc_dc.dc_addr = args->ia_addr; 776 sc->sc_dc.dc_tag = args->ia_tag; 777 sc->sc_dc.dc_chip = NULL; 778 sc->sc_dc.dc_readreg = dbcool_readreg; 779 sc->sc_dc.dc_writereg = dbcool_writereg; 780 (void)dbcool_chip_ident(&sc->sc_dc); 781 sc->sc_dev = self; 782 783 aprint_naive("\n"); 784 aprint_normal("\n"); 785 786 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 787 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 788 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 789 { 790 aprint_normal_dev(self, "SMSC %s Controller " 791 "(rev 0x%02x, stepping 0x%02x)\n", 792 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 793 } else { 794 aprint_normal_dev(self, "%s dBCool(tm) Controller " 795 "(rev 0x%02x, stepping 0x%02x)\n", 796 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 797 } 798 else 799 aprint_normal_dev(self, "%s dBCool(tm) Controller " 800 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 801 802 sc->sc_sysctl_log = NULL; 803 804 #ifdef _MODULE 805 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 806 #endif 807 808 dbcool_setup(self); 809 810 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 811 aprint_error_dev(self, "couldn't establish power handler\n"); 812 } 813 814 static int 815 dbcool_detach(device_t self, int flags) 816 { 817 struct dbcool_softc *sc = device_private(self); 818 819 pmf_device_deregister(self); 820 821 sysmon_envsys_unregister(sc->sc_sme); 822 823 sysctl_teardown(&sc->sc_sysctl_log); 824 825 sc->sc_sme = NULL; 826 return 0; 827 } 828 829 /* On suspend, we save the state of the SHDN bit, then set it */ 830 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 831 { 832 struct dbcool_softc *sc = device_private(dev); 833 uint8_t reg, bit, cfg; 834 835 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 836 return true; 837 838 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 839 reg = DBCOOL_ADT7466_CONFIG2; 840 bit = DBCOOL_ADT7466_CFG2_SHDN; 841 } else { 842 reg = DBCOOL_CONFIG2_REG; 843 bit = DBCOOL_CFG2_SHDN; 844 } 845 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 846 sc->sc_suspend = cfg & bit; 847 cfg |= bit; 848 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 849 850 return true; 851 } 852 853 /* On resume, we restore the previous state of the SHDN bit (which 854 we saved in sc_suspend) */ 855 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 856 { 857 struct dbcool_softc *sc = device_private(dev); 858 uint8_t reg, cfg; 859 860 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 861 return true; 862 863 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 864 reg = DBCOOL_ADT7466_CONFIG2; 865 } else { 866 reg = DBCOOL_CONFIG2_REG; 867 } 868 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 869 cfg &= ~sc->sc_suspend; 870 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 871 872 return true; 873 874 } 875 876 uint8_t 877 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 878 { 879 uint8_t data = 0; 880 881 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 882 return data; 883 884 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 885 /* ADM1027 doesn't support i2c read_byte protocol */ 886 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 887 goto bad; 888 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 889 } else 890 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 891 0); 892 893 bad: 894 iic_release_bus(dc->dc_tag, 0); 895 return data; 896 } 897 898 void 899 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 900 { 901 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 902 return; 903 904 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 905 906 iic_release_bus(dc->dc_tag, 0); 907 } 908 909 static bool 910 dbcool_islocked(struct dbcool_softc *sc) 911 { 912 uint8_t cfg_reg; 913 914 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 915 return 0; 916 917 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 918 cfg_reg = DBCOOL_ADT7466_CONFIG1; 919 else 920 cfg_reg = DBCOOL_CONFIG1_REG; 921 922 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 923 return 1; 924 else 925 return 0; 926 } 927 928 static int 929 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 930 { 931 uint8_t t1, t2, t3, val, ext = 0; 932 int temp; 933 934 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 935 /* 936 * ADT7466 temps are in strange location 937 */ 938 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 939 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 940 if (extres) 941 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 942 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 943 /* 944 * ADM1030 temps are in their own special place, too 945 */ 946 if (extres) { 947 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 948 if (reg == DBCOOL_ADM1030_L_TEMP) 949 ext >>= 6; 950 else if (reg == DBCOOL_ADM1031_R2_TEMP) 951 ext >>= 4; 952 else 953 ext >>= 1; 954 ext &= 0x03; 955 } 956 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 957 } else if (extres) { 958 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 959 960 /* Read all msb regs to unlatch them */ 961 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 962 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 963 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 964 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 965 switch (reg) { 966 case DBCOOL_REMOTE1_TEMP: 967 val = t1; 968 ext >>= 2; 969 break; 970 case DBCOOL_LOCAL_TEMP: 971 val = t3; 972 ext >>= 4; 973 break; 974 case DBCOOL_REMOTE2_TEMP: 975 val = t2; 976 ext >>= 6; 977 break; 978 default: 979 val = 0; 980 break; 981 } 982 ext &= 0x03; 983 } 984 else 985 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 986 987 /* Check for invalid temp values */ 988 if ((sc->sc_temp_offset == 0 && val == 0x80) || 989 (sc->sc_temp_offset != 0 && val == 0)) 990 return 0; 991 992 /* If using offset mode, adjust, else treat as signed */ 993 if (sc->sc_temp_offset) { 994 temp = val; 995 temp -= sc->sc_temp_offset; 996 } else 997 temp = (int8_t)val; 998 999 /* Convert degC to uK and include extended precision bits */ 1000 temp *= 1000000; 1001 temp += 250000 * (int)ext; 1002 temp += 273150000U; 1003 1004 return temp; 1005 } 1006 1007 static int 1008 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 1009 { 1010 int rpm; 1011 uint8_t rpm_lo, rpm_hi; 1012 1013 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1014 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1015 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1016 else 1017 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1018 1019 rpm = (rpm_hi << 8) | rpm_lo; 1020 if (rpm == 0xffff) 1021 return 0; /* 0xffff indicates stalled/failed fan */ 1022 1023 /* don't divide by zero */ 1024 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1025 } 1026 1027 /* Provide chip's supply voltage, in microvolts */ 1028 static int 1029 dbcool_supply_voltage(struct dbcool_softc *sc) 1030 { 1031 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1032 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1033 return 5002500; 1034 else 1035 return 3300000; 1036 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1037 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1038 DBCOOL_ADT7466_CFG1_Vcc) 1039 return 5000000; 1040 else 1041 return 3300000; 1042 } else 1043 return 3300000; 1044 } 1045 1046 /* 1047 * Nominal voltages are calculated in microvolts 1048 */ 1049 static int 1050 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1051 { 1052 uint8_t ext = 0, v1, v2, v3, v4, val; 1053 int64_t ret; 1054 int64_t nom; 1055 1056 nom = nominal_voltages[nom_idx]; 1057 if (nom < 0) 1058 nom = sc->sc_supply_voltage; 1059 1060 /* ADT7466 voltages are in strange locations with only 8-bits */ 1061 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1062 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1063 else 1064 /* 1065 * It's a "normal" dbCool chip - check for regs that 1066 * share extended resolution bits since we have to 1067 * read all the MSB registers to unlatch them. 1068 */ 1069 if (!extres) 1070 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1071 else if (reg == DBCOOL_12VIN) { 1072 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1073 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1074 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1075 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1076 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1077 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1078 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1079 if (reg == DBCOOL_IMON) { 1080 val = v1; 1081 ext >>= 6; 1082 } else { 1083 val = v2; 1084 ext >>= 4; 1085 } 1086 ext &= 0x0f; 1087 } else { 1088 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1089 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1090 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1091 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1092 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1093 1094 switch (reg) { 1095 case DBCOOL_25VIN: 1096 val = v1; 1097 break; 1098 case DBCOOL_VCCP: 1099 val = v2; 1100 ext >>= 2; 1101 break; 1102 case DBCOOL_VCC: 1103 val = v3; 1104 ext >>= 4; 1105 break; 1106 case DBCOOL_5VIN: 1107 val = v4; 1108 ext >>= 6; 1109 break; 1110 default: 1111 val = nom = 0; 1112 } 1113 ext &= 0x03; 1114 } 1115 1116 /* 1117 * Scale the nominal value by the 10-bit fraction 1118 * 1119 * Returned value is in microvolts. 1120 */ 1121 ret = val; 1122 ret <<= 2; 1123 ret |= ext; 1124 ret = (ret * nom) / 0x300; 1125 1126 return ret; 1127 } 1128 1129 static int 1130 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1131 { 1132 struct sysctlnode node; 1133 struct dbcool_softc *sc; 1134 int reg, error; 1135 uint8_t chipreg; 1136 uint8_t newreg; 1137 1138 node = *rnode; 1139 sc = (struct dbcool_softc *)node.sysctl_data; 1140 chipreg = node.sysctl_num & 0xff; 1141 1142 if (sc->sc_temp_offset) { 1143 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1144 reg -= sc->sc_temp_offset; 1145 } else 1146 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1147 1148 node.sysctl_data = ® 1149 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1150 1151 if (error || newp == NULL) 1152 return error; 1153 1154 /* We were asked to update the value - sanity check before writing */ 1155 if (*(int *)node.sysctl_data < -64 || 1156 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1157 return EINVAL; 1158 1159 newreg = *(int *)node.sysctl_data; 1160 newreg += sc->sc_temp_offset; 1161 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1162 return 0; 1163 } 1164 1165 static int 1166 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1167 { 1168 struct sysctlnode node; 1169 struct dbcool_softc *sc; 1170 int reg, error; 1171 uint8_t chipreg, oldreg, newreg; 1172 1173 node = *rnode; 1174 sc = (struct dbcool_softc *)node.sysctl_data; 1175 chipreg = node.sysctl_num & 0xff; 1176 1177 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1178 reg = (oldreg >> 1) & ~0x03; 1179 1180 node.sysctl_data = ® 1181 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1182 1183 if (error || newp == NULL) 1184 return error; 1185 1186 /* We were asked to update the value - sanity check before writing */ 1187 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1188 return EINVAL; 1189 1190 newreg = *(int *)node.sysctl_data; 1191 newreg &= ~0x03; 1192 newreg <<= 1; 1193 newreg |= (oldreg & 0x07); 1194 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1195 return 0; 1196 } 1197 1198 static int 1199 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1200 { 1201 struct sysctlnode node; 1202 struct dbcool_softc *sc; 1203 int reg, error, newval; 1204 uint8_t chipreg, oldreg, newreg; 1205 1206 node = *rnode; 1207 sc = (struct dbcool_softc *)node.sysctl_data; 1208 chipreg = node.sysctl_num & 0xff; 1209 1210 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1211 reg = oldreg & 0x07; 1212 1213 node.sysctl_data = ® 1214 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1215 1216 if (error || newp == NULL) 1217 return error; 1218 1219 /* We were asked to update the value - sanity check before writing */ 1220 newval = *(int *)node.sysctl_data; 1221 1222 if (newval == 5) 1223 newreg = 0; 1224 else if (newval == 10) 1225 newreg = 1; 1226 else if (newval == 20) 1227 newreg = 2; 1228 else if (newval == 40) 1229 newreg = 3; 1230 else if (newval == 80) 1231 newreg = 4; 1232 else 1233 return EINVAL; 1234 1235 newreg |= (oldreg & ~0x07); 1236 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1237 return 0; 1238 } 1239 1240 static int 1241 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1242 { 1243 struct sysctlnode node; 1244 struct dbcool_softc *sc; 1245 int reg, error; 1246 uint8_t chipreg, oldreg, newreg; 1247 1248 node = *rnode; 1249 sc = (struct dbcool_softc *)node.sysctl_data; 1250 chipreg = node.sysctl_num & 0xff; 1251 1252 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1253 reg = (uint32_t)oldreg; 1254 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1255 reg = ((reg & 0x0f) * 100) / 15; 1256 else 1257 reg = (reg * 100) / 255; 1258 node.sysctl_data = ® 1259 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1260 1261 if (error || newp == NULL) 1262 return error; 1263 1264 /* We were asked to update the value - sanity check before writing */ 1265 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1266 return EINVAL; 1267 1268 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1269 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1270 newreg |= oldreg & 0xf0; 1271 } else 1272 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1273 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1274 return 0; 1275 } 1276 1277 static int 1278 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1279 { 1280 struct sysctlnode node; 1281 struct dbcool_softc *sc; 1282 int i, reg, error; 1283 uint8_t chipreg, oldreg, newreg; 1284 1285 node = *rnode; 1286 sc = (struct dbcool_softc *)node.sysctl_data; 1287 chipreg = node.sysctl_num & 0xff; 1288 1289 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1290 1291 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1292 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1293 reg = 4; 1294 else if ((oldreg & 0x80) == 0) 1295 reg = 7; 1296 else if ((oldreg & 0x60) == 0) 1297 reg = 4; 1298 else 1299 reg = 6; 1300 } else 1301 reg = (oldreg >> 5) & 0x07; 1302 1303 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1304 node.sysctl_data = dbcool_cur_behav; 1305 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1306 1307 if (error || newp == NULL) 1308 return error; 1309 1310 /* We were asked to update the value - convert string to value */ 1311 newreg = __arraycount(behavior); 1312 for (i = 0; i < __arraycount(behavior); i++) 1313 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1314 break; 1315 if (i >= __arraycount(behavior)) 1316 return EINVAL; 1317 1318 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1319 /* 1320 * ADM1030 splits fan controller behavior across two 1321 * registers. We also do not support Auto-Filter mode 1322 * nor do we support Manual-RPM-feedback. 1323 */ 1324 if (newreg == 4) { 1325 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1326 oldreg &= ~0x01; 1327 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1328 } else { 1329 if (newreg == 0) 1330 newreg = 4; 1331 else if (newreg == 6) 1332 newreg = 7; 1333 else if (newreg == 7) 1334 newreg = 0; 1335 else 1336 return EINVAL; 1337 newreg <<= 5; 1338 newreg |= (oldreg & 0x1f); 1339 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1340 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1341 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1342 } 1343 } else { 1344 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1345 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1346 } 1347 return 0; 1348 } 1349 1350 static int 1351 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1352 { 1353 struct sysctlnode node; 1354 struct dbcool_softc *sc; 1355 int reg, error; 1356 uint8_t chipreg; 1357 uint8_t newreg; 1358 1359 node = *rnode; 1360 sc = (struct dbcool_softc *)node.sysctl_data; 1361 chipreg = node.sysctl_num & 0xff; 1362 1363 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1364 node.sysctl_data = ® 1365 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1366 1367 if (error || newp == NULL) 1368 return error; 1369 1370 /* We were asked to update the value - sanity check before writing */ 1371 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1372 return EINVAL; 1373 1374 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1375 (*(int *)node.sysctl_data << 4); 1376 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1377 return 0; 1378 } 1379 1380 static int 1381 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1382 { 1383 struct sysctlnode node; 1384 struct dbcool_softc *sc; 1385 int reg, error; 1386 uint8_t chipreg; 1387 uint8_t newreg, newhyst; 1388 1389 node = *rnode; 1390 sc = (struct dbcool_softc *)node.sysctl_data; 1391 chipreg = node.sysctl_num & 0x7f; 1392 1393 /* retrieve 4-bit value */ 1394 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1395 if ((node.sysctl_num & 0x80) == 0) 1396 reg = newreg >> 4; 1397 else 1398 reg = newreg; 1399 reg = reg & 0x0f; 1400 1401 node.sysctl_data = ® 1402 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1403 1404 if (error || newp == NULL) 1405 return error; 1406 1407 /* We were asked to update the value - sanity check before writing */ 1408 newhyst = *(int *)node.sysctl_data; 1409 if (newhyst > 0x0f) 1410 return EINVAL; 1411 1412 /* Insert new value into field and update register */ 1413 if ((node.sysctl_num & 0x80) == 0) { 1414 newreg &= 0x0f; 1415 newreg |= (newhyst << 4); 1416 } else { 1417 newreg &= 0xf0; 1418 newreg |= newhyst; 1419 } 1420 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1421 return 0; 1422 } 1423 1424 #ifdef DBCOOL_DEBUG 1425 1426 /* 1427 * These routines can be used for debugging. reg_select is used to 1428 * select any arbitrary register in the device. reg_access is used 1429 * to read (and optionally update) the selected register. 1430 * 1431 * No attempt is made to validate the data passed. If you use these 1432 * routines, you are assumed to know what you're doing! 1433 * 1434 * Caveat user 1435 */ 1436 static int 1437 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1438 { 1439 struct sysctlnode node; 1440 struct dbcool_softc *sc; 1441 int reg, error; 1442 1443 node = *rnode; 1444 sc = (struct dbcool_softc *)node.sysctl_data; 1445 1446 reg = sc->sc_user_reg; 1447 node.sysctl_data = ® 1448 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1449 1450 if (error || newp == NULL) 1451 return error; 1452 1453 sc->sc_user_reg = *(int *)node.sysctl_data; 1454 return 0; 1455 } 1456 1457 static int 1458 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1459 { 1460 struct sysctlnode node; 1461 struct dbcool_softc *sc; 1462 int reg, error; 1463 uint8_t chipreg; 1464 uint8_t newreg; 1465 1466 node = *rnode; 1467 sc = (struct dbcool_softc *)node.sysctl_data; 1468 chipreg = sc->sc_user_reg; 1469 1470 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1471 node.sysctl_data = ® 1472 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1473 1474 if (error || newp == NULL) 1475 return error; 1476 1477 newreg = *(int *)node.sysctl_data; 1478 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1479 return 0; 1480 } 1481 #endif /* DBCOOL_DEBUG */ 1482 1483 /* 1484 * Encode an index number and register number for use as a sysctl_num 1485 * so we can select the correct device register later. 1486 */ 1487 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1488 1489 void 1490 dbcool_setup(device_t self) 1491 { 1492 struct dbcool_softc *sc = device_private(self); 1493 const struct sysctlnode *me = NULL; 1494 #ifdef DBCOOL_DEBUG 1495 struct sysctlnode *node = NULL; 1496 #endif 1497 uint8_t cfg_val, cfg_reg; 1498 int ret, error; 1499 1500 /* 1501 * Some chips are capable of reporting an extended temperature range 1502 * by default. On these models, config register 5 bit 0 can be set 1503 * to 1 for compatability with other chips that report 2s complement. 1504 */ 1505 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1506 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1507 sc->sc_temp_offset = 64; 1508 else 1509 sc->sc_temp_offset = 0; 1510 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1511 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1512 DBCOOL_CFG5_TWOSCOMP) 1513 sc->sc_temp_offset = 0; 1514 else 1515 sc->sc_temp_offset = 64; 1516 } else 1517 sc->sc_temp_offset = 0; 1518 1519 /* Determine Vcc for this chip */ 1520 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1521 1522 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1523 CTLFLAG_READWRITE, 1524 CTLTYPE_NODE, device_xname(self), NULL, 1525 NULL, 0, NULL, 0, 1526 CTL_HW, CTL_CREATE, CTL_EOL); 1527 if (ret == 0) 1528 sc->sc_root_sysctl_num = me->sysctl_num; 1529 else 1530 sc->sc_root_sysctl_num = 0; 1531 1532 aprint_debug_dev(self, 1533 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1534 sc->sc_supply_voltage / 1000000, 1535 sc->sc_supply_voltage % 1000000, 1536 sc->sc_temp_offset ? "extended" : "normal"); 1537 1538 /* Create the sensors for this device */ 1539 sc->sc_sme = sysmon_envsys_create(); 1540 if (dbcool_setup_sensors(sc)) 1541 goto out; 1542 1543 if (sc->sc_root_sysctl_num != 0) { 1544 /* If supported, create sysctl tree for fan PWM controllers */ 1545 if (sc->sc_dc.dc_chip->power != NULL) 1546 dbcool_setup_controllers(sc); 1547 1548 #ifdef DBCOOL_DEBUG 1549 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1550 (void *)&node, 1551 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1552 sysctl_dbcool_reg_select, 1553 0, (void *)sc, sizeof(int), 1554 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1555 if (node != NULL) 1556 node->sysctl_data = sc; 1557 1558 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1559 (void *)&node, 1560 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1561 sysctl_dbcool_reg_access, 1562 0, (void *)sc, sizeof(int), 1563 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1564 if (node != NULL) 1565 node->sysctl_data = sc; 1566 #endif /* DBCOOL_DEBUG */ 1567 } 1568 1569 /* 1570 * Read and rewrite config register to activate device 1571 */ 1572 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1573 cfg_reg = DBCOOL_ADM1030_CFG1; 1574 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1575 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1576 else 1577 cfg_reg = DBCOOL_CONFIG1_REG; 1578 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1579 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1580 cfg_val |= DBCOOL_CFG1_START; 1581 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1582 } 1583 if (dbcool_islocked(sc)) 1584 aprint_normal_dev(self, "configuration locked\n"); 1585 1586 sc->sc_sme->sme_name = device_xname(self); 1587 sc->sc_sme->sme_cookie = sc; 1588 sc->sc_sme->sme_refresh = dbcool_refresh; 1589 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1590 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1591 1592 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1593 aprint_error_dev(self, 1594 "unable to register with sysmon (%d)\n", error); 1595 goto out; 1596 } 1597 1598 return; 1599 1600 out: 1601 sysmon_envsys_destroy(sc->sc_sme); 1602 } 1603 1604 static int 1605 dbcool_setup_sensors(struct dbcool_softc *sc) 1606 { 1607 int i; 1608 int error = 0; 1609 uint8_t vid_reg, vid_val; 1610 struct chip_id *chip = sc->sc_dc.dc_chip; 1611 1612 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1613 if (i < DBCOOL_MAXSENSORS) 1614 sc->sc_sysctl_num[i] = -1; 1615 else if (chip->table[i].type != DBC_CTL) { 1616 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1617 break; 1618 } 1619 switch (chip->table[i].type) { 1620 case DBC_TEMP: 1621 sc->sc_sensor[i].units = ENVSYS_STEMP; 1622 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1623 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1624 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1625 error = dbcool_attach_sensor(sc, i); 1626 break; 1627 case DBC_VOLT: 1628 /* 1629 * If 12V-In pin has been reconfigured as 6th bit 1630 * of VID code, don't create a 12V-In sensor 1631 */ 1632 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1633 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1634 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1635 0x80)) 1636 break; 1637 1638 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1639 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1640 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1641 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1642 error = dbcool_attach_sensor(sc, i); 1643 break; 1644 case DBC_FAN: 1645 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1646 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1647 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1648 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1649 error = dbcool_attach_sensor(sc, i); 1650 break; 1651 case DBC_VID: 1652 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1653 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1654 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1655 1656 /* retrieve 5- or 6-bit value */ 1657 vid_reg = chip->table[i].reg.val_reg; 1658 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1659 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1660 vid_val &= 0x3f; 1661 else 1662 vid_val &= 0x1f; 1663 sc->sc_sensor[i].value_cur = vid_val; 1664 1665 error = dbcool_attach_sensor(sc, i); 1666 break; 1667 case DBC_CTL: 1668 error = dbcool_attach_temp_control(sc, i, chip); 1669 if (error) { 1670 aprint_error_dev(sc->sc_dev, 1671 "attach index %d failed %d\n", 1672 i, error); 1673 error = 0; 1674 } 1675 break; 1676 default: 1677 aprint_error_dev(sc->sc_dev, 1678 "sensor_table index %d has bad type %d\n", 1679 i, chip->table[i].type); 1680 break; 1681 } 1682 if (error) 1683 break; 1684 } 1685 return error; 1686 } 1687 1688 static int 1689 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1690 { 1691 int name_index; 1692 int error = 0; 1693 1694 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1695 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1696 sizeof(sc->sc_sensor[idx].desc)); 1697 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1698 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1699 1700 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1701 return error; 1702 } 1703 1704 static int 1705 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1706 struct chip_id *chip) 1707 { 1708 const struct sysctlnode *me2 = NULL, *node; 1709 int j, ret, sysctl_index, rw_flag; 1710 uint8_t sysctl_reg; 1711 char name[SYSCTL_NAMELEN]; 1712 1713 /* Search for the corresponding temp sensor */ 1714 for (j = 0; j < idx; j++) { 1715 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1716 continue; 1717 if (chip->table[j].name_index == chip->table[idx].name_index) 1718 break; 1719 } 1720 if (j >= idx) /* Temp sensor not found */ 1721 return ENOENT; 1722 1723 /* create sysctl node for the sensor if not one already there */ 1724 if (sc->sc_sysctl_num[j] == -1) { 1725 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1726 CTLFLAG_READWRITE, 1727 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1728 NULL, 0, NULL, 0, 1729 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1730 CTL_EOL); 1731 if (me2 != NULL) 1732 sc->sc_sysctl_num[j] = me2->sysctl_num; 1733 else 1734 return ret; 1735 } 1736 /* add sysctl leaf node for this control variable */ 1737 sysctl_index = chip->table[idx].sysctl_index; 1738 sysctl_reg = chip->table[idx].reg.val_reg; 1739 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1740 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1741 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1742 else 1743 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1744 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1745 CTLTYPE_INT, name, 1746 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1747 dbc_sysctl_table[sysctl_index].helper, 1748 0, (void *)sc, sizeof(int), 1749 CTL_HW, sc->sc_root_sysctl_num, 1750 sc->sc_sysctl_num[j], 1751 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1752 1753 return ret; 1754 } 1755 1756 static void 1757 dbcool_setup_controllers(struct dbcool_softc *sc) 1758 { 1759 int i, j, rw_flag; 1760 uint8_t sysctl_reg; 1761 struct chip_id *chip = sc->sc_dc.dc_chip; 1762 const struct sysctlnode *me2 = NULL; 1763 const struct sysctlnode *node = NULL; 1764 char name[SYSCTL_NAMELEN]; 1765 1766 for (i = 0; chip->power[i].desc != NULL; i++) { 1767 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1768 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1769 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1770 CTLTYPE_NODE, name, NULL, 1771 NULL, 0, NULL, 0, 1772 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1773 1774 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1775 if (j == DBC_PWM_MAX_DUTY && 1776 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1777 continue; 1778 sysctl_reg = chip->power[i].power_regs[j]; 1779 if (sysctl_reg == DBCOOL_NO_REG) 1780 continue; 1781 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1782 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1783 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1784 else 1785 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1786 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1787 &node, rw_flag, 1788 (j == DBC_PWM_BEHAVIOR)? 1789 CTLTYPE_STRING:CTLTYPE_INT, 1790 name, 1791 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1792 dbc_sysctl_table[j].helper, 1793 0, sc, 1794 ( j == DBC_PWM_BEHAVIOR)? 1795 sizeof(dbcool_cur_behav): sizeof(int), 1796 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1797 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1798 } 1799 } 1800 } 1801 1802 static void 1803 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1804 { 1805 struct dbcool_softc *sc=sme->sme_cookie; 1806 int i, nom_volt_idx, cur; 1807 struct reg_list *reg; 1808 1809 i = edata->sensor; 1810 reg = sc->sc_regs[i]; 1811 1812 edata->state = ENVSYS_SVALID; 1813 switch (edata->units) 1814 { 1815 case ENVSYS_STEMP: 1816 cur = dbcool_read_temp(sc, reg->val_reg, true); 1817 break; 1818 case ENVSYS_SVOLTS_DC: 1819 nom_volt_idx = sc->sc_nom_volt[i]; 1820 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1821 true); 1822 break; 1823 case ENVSYS_SFANRPM: 1824 cur = dbcool_read_rpm(sc, reg->val_reg); 1825 break; 1826 case ENVSYS_INTEGER: 1827 return; 1828 default: 1829 edata->state = ENVSYS_SINVALID; 1830 return; 1831 } 1832 1833 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1834 edata->state = ENVSYS_SINVALID; 1835 1836 /* 1837 * If fan is "stalled" but has no low limit, treat 1838 * it as though the fan is not installed. 1839 */ 1840 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1841 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1842 edata->state = ENVSYS_SINVALID; 1843 1844 edata->value_cur = cur; 1845 } 1846 1847 int 1848 dbcool_chip_ident(struct dbcool_chipset *dc) 1849 { 1850 /* verify this is a supported dbCool chip */ 1851 uint8_t c_id, d_id, r_id; 1852 int i; 1853 1854 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1855 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1856 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1857 1858 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1859 * NULL when we call dc->dc_readreg above we use 1860 * send_byte/receive_byte which doesn't work. 1861 * 1862 * So if we only get 0's back then try again with dc->dc_chip 1863 * set to the EMC6D103S_DEVICEID and which doesn't have 1864 * DBCFLAG_NO_READBYTE set so read_byte will be used 1865 */ 1866 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1867 for (i = 0; chip_table[i].company != 0; i++) 1868 if ((SMSC_COMPANYID == chip_table[i].company) && 1869 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1870 dc->dc_chip = &chip_table[i]; 1871 break; 1872 } 1873 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1874 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1875 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1876 } 1877 1878 for (i = 0; chip_table[i].company != 0; i++) 1879 if ((c_id == chip_table[i].company) && 1880 (d_id == chip_table[i].device || 1881 chip_table[i].device == 0xff) && 1882 (r_id == chip_table[i].rev || 1883 chip_table[i].rev == 0xff)) { 1884 dc->dc_chip = &chip_table[i]; 1885 return i; 1886 } 1887 1888 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1889 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1890 r_id); 1891 1892 return -1; 1893 } 1894 1895 /* 1896 * Retrieve sensor limits from the chip registers 1897 */ 1898 static void 1899 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1900 sysmon_envsys_lim_t *limits, uint32_t *props) 1901 { 1902 int index = edata->sensor; 1903 struct dbcool_softc *sc = sme->sme_cookie; 1904 1905 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1906 switch (edata->units) { 1907 case ENVSYS_STEMP: 1908 dbcool_get_temp_limits(sc, index, limits, props); 1909 break; 1910 case ENVSYS_SVOLTS_DC: 1911 dbcool_get_volt_limits(sc, index, limits, props); 1912 break; 1913 case ENVSYS_SFANRPM: 1914 dbcool_get_fan_limits(sc, index, limits, props); 1915 1916 /* FALLTHROUGH */ 1917 default: 1918 break; 1919 } 1920 *props &= ~PROP_DRIVER_LIMITS; 1921 1922 /* If both limits provided, make sure they're sane */ 1923 if ((*props & PROP_CRITMIN) && 1924 (*props & PROP_CRITMAX) && 1925 (limits->sel_critmin >= limits->sel_critmax)) 1926 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1927 1928 /* 1929 * If this is the first time through, save these values 1930 * in case user overrides them and then requests a reset. 1931 */ 1932 if (sc->sc_defprops[index] == 0) { 1933 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1934 sc->sc_deflims[index] = *limits; 1935 } 1936 } 1937 1938 static void 1939 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1940 sysmon_envsys_lim_t *lims, uint32_t *props) 1941 { 1942 struct reg_list *reg = sc->sc_regs[idx]; 1943 uint8_t lo_lim, hi_lim; 1944 1945 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1946 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1947 1948 if (sc->sc_temp_offset) { 1949 if (lo_lim > 0x01) { 1950 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1951 *props |= PROP_CRITMIN; 1952 } 1953 if (hi_lim != 0xff) { 1954 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1955 *props |= PROP_CRITMAX; 1956 } 1957 } else { 1958 if (lo_lim != 0x80 && lo_lim != 0x81) { 1959 lims->sel_critmin = (int8_t)lo_lim; 1960 *props |= PROP_CRITMIN; 1961 } 1962 1963 if (hi_lim != 0x7f) { 1964 lims->sel_critmax = (int8_t)hi_lim; 1965 *props |= PROP_CRITMAX; 1966 } 1967 } 1968 1969 /* Convert temp limits to microKelvin */ 1970 lims->sel_critmin *= 1000000; 1971 lims->sel_critmin += 273150000; 1972 lims->sel_critmax *= 1000000; 1973 lims->sel_critmax += 273150000; 1974 } 1975 1976 static void 1977 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1978 sysmon_envsys_lim_t *lims, uint32_t *props) 1979 { 1980 struct reg_list *reg = sc->sc_regs[idx]; 1981 int64_t limit; 1982 int nom; 1983 1984 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1985 if (nom < 0) 1986 nom = dbcool_supply_voltage(sc); 1987 nom *= 1000000; /* scale for microvolts */ 1988 1989 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1990 if (limit != 0x00 && limit != 0xff) { 1991 limit *= nom; 1992 limit /= 0xc0; 1993 lims->sel_critmin = limit; 1994 *props |= PROP_CRITMIN; 1995 } 1996 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1997 if (limit != 0x00 && limit != 0xff) { 1998 limit *= nom; 1999 limit /= 0xc0; 2000 lims->sel_critmax = limit; 2001 *props |= PROP_CRITMAX; 2002 } 2003 } 2004 2005 static void 2006 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2007 sysmon_envsys_lim_t *lims, uint32_t *props) 2008 { 2009 struct reg_list *reg = sc->sc_regs[idx]; 2010 int32_t limit; 2011 2012 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2013 if (limit) { 2014 lims->sel_critmin = limit; 2015 *props |= PROP_CRITMIN; 2016 } 2017 } 2018 2019 /* 2020 * Update sensor limits in the chip registers 2021 */ 2022 static void 2023 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2024 sysmon_envsys_lim_t *limits, uint32_t *props) 2025 { 2026 int index = edata->sensor; 2027 struct dbcool_softc *sc = sme->sme_cookie; 2028 2029 if (limits == NULL) { 2030 limits = &sc->sc_deflims[index]; 2031 props = &sc->sc_defprops[index]; 2032 } 2033 switch (edata->units) { 2034 case ENVSYS_STEMP: 2035 dbcool_set_temp_limits(sc, index, limits, props); 2036 break; 2037 case ENVSYS_SVOLTS_DC: 2038 dbcool_set_volt_limits(sc, index, limits, props); 2039 break; 2040 case ENVSYS_SFANRPM: 2041 dbcool_set_fan_limits(sc, index, limits, props); 2042 2043 /* FALLTHROUGH */ 2044 default: 2045 break; 2046 } 2047 *props &= ~PROP_DRIVER_LIMITS; 2048 } 2049 2050 static void 2051 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2052 sysmon_envsys_lim_t *lims, uint32_t *props) 2053 { 2054 struct reg_list *reg = sc->sc_regs[idx]; 2055 int32_t limit; 2056 2057 if (*props & PROP_CRITMIN) { 2058 limit = lims->sel_critmin - 273150000; 2059 limit /= 1000000; 2060 if (sc->sc_temp_offset) { 2061 limit += sc->sc_temp_offset; 2062 if (limit < 0) 2063 limit = 0; 2064 else if (limit > 255) 2065 limit = 255; 2066 } else { 2067 if (limit < -127) 2068 limit = -127; 2069 else if (limit > 127) 2070 limit = 127; 2071 } 2072 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2073 (uint8_t)limit); 2074 } else if (*props & PROP_DRIVER_LIMITS) { 2075 if (sc->sc_temp_offset) 2076 limit = 0x00; 2077 else 2078 limit = 0x80; 2079 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2080 (uint8_t)limit); 2081 } 2082 2083 if (*props & PROP_CRITMAX) { 2084 limit = lims->sel_critmax - 273150000; 2085 limit /= 1000000; 2086 if (sc->sc_temp_offset) { 2087 limit += sc->sc_temp_offset; 2088 if (limit < 0) 2089 limit = 0; 2090 else if (limit > 255) 2091 limit = 255; 2092 } else { 2093 if (limit < -127) 2094 limit = -127; 2095 else if (limit > 127) 2096 limit = 127; 2097 } 2098 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2099 (uint8_t)limit); 2100 } else if (*props & PROP_DRIVER_LIMITS) { 2101 if (sc->sc_temp_offset) 2102 limit = 0xff; 2103 else 2104 limit = 0x7f; 2105 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2106 (uint8_t)limit); 2107 } 2108 } 2109 2110 static void 2111 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2112 sysmon_envsys_lim_t *lims, uint32_t *props) 2113 { 2114 struct reg_list *reg = sc->sc_regs[idx]; 2115 int64_t limit; 2116 int nom; 2117 2118 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2119 if (nom < 0) 2120 nom = dbcool_supply_voltage(sc); 2121 nom *= 1000000; /* scale for microvolts */ 2122 2123 if (*props & PROP_CRITMIN) { 2124 limit = lims->sel_critmin; 2125 limit *= 0xc0; 2126 limit /= nom; 2127 if (limit > 0xff) 2128 limit = 0xff; 2129 else if (limit < 0) 2130 limit = 0; 2131 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2132 } else if (*props & PROP_DRIVER_LIMITS) 2133 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2134 2135 if (*props & PROP_CRITMAX) { 2136 limit = lims->sel_critmax; 2137 limit *= 0xc0; 2138 limit /= nom; 2139 if (limit > 0xff) 2140 limit = 0xff; 2141 else if (limit < 0) 2142 limit = 0; 2143 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2144 } else if (*props & PROP_DRIVER_LIMITS) 2145 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2146 } 2147 2148 static void 2149 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2150 sysmon_envsys_lim_t *lims, uint32_t *props) 2151 { 2152 struct reg_list *reg = sc->sc_regs[idx]; 2153 int32_t limit, dividend; 2154 2155 if (*props & PROP_CRITMIN) { 2156 limit = lims->sel_critmin; 2157 if (limit == 0) 2158 limit = 0xffff; 2159 else { 2160 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2161 dividend = 11250 * 60; 2162 else 2163 dividend = 90000 * 60; 2164 limit = limit / dividend; 2165 if (limit > 0xffff) 2166 limit = 0xffff; 2167 } 2168 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2169 limit & 0xff); 2170 limit >>= 8; 2171 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2172 limit & 0xff); 2173 } else if (*props & PROP_DRIVER_LIMITS) { 2174 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2175 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2176 } 2177 } 2178 2179 MODULE(MODULE_CLASS_DRIVER, dbcool, "i2cexec,sysmon_envsys"); 2180 2181 #ifdef _MODULE 2182 #include "ioconf.c" 2183 #endif 2184 2185 static int 2186 dbcool_modcmd(modcmd_t cmd, void *opaque) 2187 { 2188 int error = 0; 2189 #ifdef _MODULE 2190 static struct sysctllog *dbcool_sysctl_clog; 2191 #endif 2192 2193 switch (cmd) { 2194 case MODULE_CMD_INIT: 2195 #ifdef _MODULE 2196 error = config_init_component(cfdriver_ioconf_dbcool, 2197 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2198 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2199 #endif 2200 return error; 2201 case MODULE_CMD_FINI: 2202 #ifdef _MODULE 2203 error = config_fini_component(cfdriver_ioconf_dbcool, 2204 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2205 sysctl_teardown(&dbcool_sysctl_clog); 2206 #endif 2207 return error; 2208 default: 2209 return ENOTTY; 2210 } 2211 } 2212