1 /* $NetBSD: at24cxx.c,v 1.30 2018/06/26 06:34:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.30 2018/06/26 06:34:55 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 #include "ioconf.h" 57 58 /* 59 * AT24Cxx EEPROM I2C address: 60 * 101 0xxx 61 * (and others depending on the exact model) The bigger 8-bit parts 62 * decode multiple addresses. The bigger 16-bit parts do too (those 63 * larger than 512kb). Be sure to check the datasheet of your EEPROM 64 * because there's much variation between models. 65 */ 66 #define AT24CXX_ADDRMASK 0x3f8 67 #define AT24CXX_ADDR 0x50 68 69 #define AT24CXX_WRITE_CYCLE_MS 10 70 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 71 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 72 73 #include "seeprom.h" 74 75 #if NSEEPROM > 0 76 77 struct seeprom_softc { 78 device_t sc_dev; 79 i2c_tag_t sc_tag; 80 int sc_address; 81 int sc_size; 82 int sc_cmdlen; 83 int sc_open; 84 }; 85 86 static int seeprom_match(device_t, cfdata_t, void *); 87 static void seeprom_attach(device_t, device_t, void *); 88 89 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 90 seeprom_match, seeprom_attach, NULL, NULL); 91 92 dev_type_open(seeprom_open); 93 dev_type_close(seeprom_close); 94 dev_type_read(seeprom_read); 95 dev_type_write(seeprom_write); 96 97 const struct cdevsw seeprom_cdevsw = { 98 .d_open = seeprom_open, 99 .d_close = seeprom_close, 100 .d_read = seeprom_read, 101 .d_write = seeprom_write, 102 .d_ioctl = noioctl, 103 .d_stop = nostop, 104 .d_tty = notty, 105 .d_poll = nopoll, 106 .d_mmap = nommap, 107 .d_kqfilter = nokqfilter, 108 .d_discard = nodiscard, 109 .d_flag = D_OTHER 110 }; 111 112 static int seeprom_wait_idle(struct seeprom_softc *); 113 114 static const struct device_compatible_entry compat_data[] = { 115 { "i2c-at24c64", 8192 }, 116 { "i2c-at34c02", 256 }, 117 { "atmel,24c02", 256 }, 118 { "atmel,24c16", 2048 }, 119 { NULL, 0 } 120 }; 121 122 static int 123 seeprom_match(device_t parent, cfdata_t cf, void *aux) 124 { 125 struct i2c_attach_args *ia = aux; 126 int match_result; 127 128 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 129 return match_result; 130 131 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 132 return I2C_MATCH_ADDRESS_ONLY; 133 134 return 0; 135 } 136 137 static void 138 seeprom_attach(device_t parent, device_t self, void *aux) 139 { 140 struct seeprom_softc *sc = device_private(self); 141 struct i2c_attach_args *ia = aux; 142 const struct device_compatible_entry *dce; 143 144 sc->sc_tag = ia->ia_tag; 145 sc->sc_address = ia->ia_addr; 146 sc->sc_dev = self; 147 148 if (ia->ia_name != NULL) { 149 aprint_naive(": %s", ia->ia_name); 150 aprint_normal(": %s", ia->ia_name); 151 } else { 152 aprint_naive(": EEPROM"); 153 aprint_normal(": AT24Cxx or compatible EEPROM"); 154 } 155 156 /* 157 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 158 * word to select the offset into the EEPROM page. The 159 * AT24C04/08/16 decode fewer of the i2c address bits, 160 * using the bottom 1, 2, or 3 to select the 256-byte 161 * super-page. 162 * 163 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 164 * word and decode all of the i2c address bits. 165 * 166 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 167 * switching to select the proper super-page. This isn't 168 * supported by this driver. 169 */ 170 if (device_cfdata(self)->cf_flags) 171 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 172 173 if (sc->sc_size <= 0 && ia->ia_ncompat > 0) { 174 if (iic_compatible_match(ia, compat_data, &dce)) 175 sc->sc_size = dce->data; 176 } 177 178 switch (sc->sc_size) { 179 case 128: /* 1Kbit */ 180 case 256: /* 2Kbit */ 181 case 512: /* 4Kbit */ 182 case 1024: /* 8Kbit */ 183 case 2048: /* 16Kbit */ 184 sc->sc_cmdlen = 1; 185 aprint_normal(": size %d\n", sc->sc_size); 186 break; 187 188 case 4096: /* 32Kbit */ 189 case 8192: /* 64Kbit */ 190 case 16384: /* 128Kbit */ 191 case 32768: /* 256Kbit */ 192 case 65536: /* 512Kbit */ 193 sc->sc_cmdlen = 2; 194 aprint_normal(": size %d\n", sc->sc_size); 195 break; 196 197 default: 198 /* 199 * Default to 2KB. If we happen to have a 2KB 200 * EEPROM this will allow us to access it. If we 201 * have a smaller one, the worst that can happen 202 * is that we end up trying to read a different 203 * EEPROM on the bus when accessing it. 204 * 205 * Obviously this will not work for 4KB or 8KB 206 * EEPROMs, but them's the breaks. 207 */ 208 aprint_normal("\n"); 209 aprint_error_dev(self, "invalid size specified; " 210 "assuming 2KB (16Kb)\n"); 211 sc->sc_size = 2048; 212 sc->sc_cmdlen = 1; 213 } 214 215 sc->sc_open = 0; 216 } 217 218 /*ARGSUSED*/ 219 int 220 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 221 { 222 struct seeprom_softc *sc; 223 224 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 225 return (ENXIO); 226 227 /* XXX: Locking */ 228 229 if (sc->sc_open) 230 return (EBUSY); 231 232 sc->sc_open = 1; 233 return (0); 234 } 235 236 /*ARGSUSED*/ 237 int 238 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 239 { 240 struct seeprom_softc *sc; 241 242 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 243 return (ENXIO); 244 245 sc->sc_open = 0; 246 return (0); 247 } 248 249 /*ARGSUSED*/ 250 int 251 seeprom_read(dev_t dev, struct uio *uio, int flags) 252 { 253 struct seeprom_softc *sc; 254 i2c_addr_t addr; 255 u_int8_t ch, cmdbuf[2]; 256 int a, error; 257 258 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 259 return (ENXIO); 260 261 if (uio->uio_offset >= sc->sc_size) 262 return (EINVAL); 263 264 /* 265 * Even though the AT24Cxx EEPROMs support sequential 266 * reads within a page, some I2C controllers do not 267 * support anything other than single-byte transfers, 268 * so we're stuck with this lowest-common-denominator. 269 */ 270 271 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 272 a = (int)uio->uio_offset; 273 if (sc->sc_cmdlen == 1) { 274 addr = sc->sc_address + (a >> 8); 275 cmdbuf[0] = a & 0xff; 276 } else { 277 addr = sc->sc_address; 278 cmdbuf[0] = AT24CXX_ADDR_HI(a); 279 cmdbuf[1] = AT24CXX_ADDR_LO(a); 280 } 281 282 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 283 return (error); 284 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 285 addr, cmdbuf, sc->sc_cmdlen, 286 &ch, 1, 0)) != 0) { 287 iic_release_bus(sc->sc_tag, 0); 288 aprint_error_dev(sc->sc_dev, 289 "seeprom_read: byte read failed at 0x%x\n", a); 290 return (error); 291 } 292 iic_release_bus(sc->sc_tag, 0); 293 294 if ((error = uiomove(&ch, 1, uio)) != 0) { 295 return (error); 296 } 297 } 298 299 return (0); 300 } 301 302 /*ARGSUSED*/ 303 int 304 seeprom_write(dev_t dev, struct uio *uio, int flags) 305 { 306 struct seeprom_softc *sc; 307 i2c_addr_t addr; 308 u_int8_t ch, cmdbuf[2]; 309 int a, error; 310 311 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 312 return (ENXIO); 313 314 if (uio->uio_offset >= sc->sc_size) 315 return (EINVAL); 316 317 /* 318 * See seeprom_read() for why we don't use sequential 319 * writes within a page. 320 */ 321 322 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 323 a = (int)uio->uio_offset; 324 if (sc->sc_cmdlen == 1) { 325 addr = sc->sc_address + (a >> 8); 326 cmdbuf[0] = a & 0xff; 327 } else { 328 addr = sc->sc_address; 329 cmdbuf[0] = AT24CXX_ADDR_HI(a); 330 cmdbuf[1] = AT24CXX_ADDR_LO(a); 331 } 332 if ((error = uiomove(&ch, 1, uio)) != 0) { 333 iic_release_bus(sc->sc_tag, 0); 334 return (error); 335 } 336 337 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 338 return (error); 339 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 340 addr, cmdbuf, sc->sc_cmdlen, 341 &ch, 1, 0)) != 0) { 342 iic_release_bus(sc->sc_tag, 0); 343 aprint_error_dev(sc->sc_dev, 344 "seeprom_write: byte write failed at 0x%x\n", a); 345 return (error); 346 } 347 iic_release_bus(sc->sc_tag, 0); 348 349 /* Wait until the device commits the byte. */ 350 if ((error = seeprom_wait_idle(sc)) != 0) { 351 return (error); 352 } 353 } 354 355 return (0); 356 } 357 358 static int 359 seeprom_wait_idle(struct seeprom_softc *sc) 360 { 361 uint8_t cmdbuf[2] = { 0, 0 }; 362 int rv, timeout; 363 u_int8_t dummy; 364 int error; 365 366 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 367 if (timeout == 0) 368 timeout = 1; 369 370 delay(10); 371 372 /* 373 * Read the byte at address 0. This is just a dummy 374 * read to wait for the EEPROM's write cycle to complete. 375 */ 376 for (;;) { 377 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 378 return error; 379 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 380 sc->sc_address, cmdbuf, sc->sc_cmdlen, &dummy, 1, 0); 381 iic_release_bus(sc->sc_tag, 0); 382 if (error == 0) 383 break; 384 385 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 386 if (rv != EWOULDBLOCK) 387 return (rv); 388 } 389 390 return (0); 391 } 392 393 #endif /* NSEEPROM > 0 */ 394 395 int 396 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 397 u_int8_t *rvp, size_t len) 398 { 399 i2c_addr_t addr; 400 int cmdlen; 401 uint8_t cmdbuf[2]; 402 403 if (len == 0) 404 return (0); 405 406 /* We are very forgiving about devsize during bootstrap. */ 407 cmdlen = (devsize >= 4096) ? 2 : 1; 408 409 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 410 return (-1); 411 412 while (len) { 413 if (cmdlen == 1) { 414 addr = i2caddr + (offset >> 8); 415 cmdbuf[0] = offset & 0xff; 416 } else { 417 addr = i2caddr; 418 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 419 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 420 } 421 422 /* Read a single byte. */ 423 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 424 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 425 iic_release_bus(tag, I2C_F_POLL); 426 return (-1); 427 } 428 429 len--; 430 rvp++; 431 offset++; 432 } 433 434 iic_release_bus(tag, I2C_F_POLL); 435 return (0); 436 } 437