1 /* $NetBSD: at24cxx.c,v 1.13 2013/02/08 15:14:11 jdc Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.13 2013/02/08 15:14:11 jdc Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x78 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 device_t sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(device_t, cfdata_t, void *); 85 static void seeprom_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 seeprom_open, seeprom_close, seeprom_read, seeprom_write, noioctl, 98 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 99 }; 100 101 static int seeprom_wait_idle(struct seeprom_softc *); 102 103 static const char * seeprom_compats[] = { 104 "i2c-at24c64", 105 NULL 106 }; 107 108 static int 109 seeprom_match(device_t parent, cfdata_t cf, void *aux) 110 { 111 struct i2c_attach_args *ia = aux; 112 113 if (ia->ia_name) { 114 if (iic_compat_match(ia, seeprom_compats)) 115 return (1); 116 } else { 117 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 118 return (1); 119 } 120 121 return (0); 122 } 123 124 static void 125 seeprom_attach(device_t parent, device_t self, void *aux) 126 { 127 struct seeprom_softc *sc = device_private(self); 128 struct i2c_attach_args *ia = aux; 129 130 sc->sc_tag = ia->ia_tag; 131 sc->sc_address = ia->ia_addr; 132 sc->sc_dev = self; 133 134 if (ia->ia_name != NULL) { 135 aprint_naive(": %s", ia->ia_name); 136 aprint_normal(": %s", ia->ia_name); 137 } else { 138 aprint_naive(": EEPROM"); 139 aprint_normal(": AT24Cxx EEPROM"); 140 } 141 142 /* 143 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 144 * word to select the offset into the EEPROM page. The 145 * AT24C04/08/16 decode fewer of the i2c address bits, 146 * using the bottom 1, 2, or 3 to select the 256-byte 147 * super-page. 148 * 149 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 150 * word and decode all of the i2c address bits. 151 * 152 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 153 * switching to select the proper super-page. This isn't 154 * supported by this driver. 155 */ 156 sc->sc_size = ia->ia_size; 157 switch (sc->sc_size) { 158 case 128: /* 1Kbit */ 159 case 256: /* 2Kbit */ 160 case 512: /* 4Kbit */ 161 case 1024: /* 8Kbit */ 162 case 2048: /* 16Kbit */ 163 sc->sc_cmdlen = 1; 164 aprint_normal(": size %d\n", sc->sc_size); 165 break; 166 167 case 4096: /* 32Kbit */ 168 case 8192: /* 64Kbit */ 169 case 16384: /* 128Kbit */ 170 case 32768: /* 256Kbit */ 171 case 65536: /* 512Kbit */ 172 sc->sc_cmdlen = 2; 173 aprint_normal(": size %d\n", sc->sc_size); 174 break; 175 176 default: 177 /* 178 * Default to 2KB. If we happen to have a 2KB 179 * EEPROM this will allow us to access it. If we 180 * have a smaller one, the worst that can happen 181 * is that we end up trying to read a different 182 * EEPROM on the bus when accessing it. 183 * 184 * Obviously this will not work for 4KB or 8KB 185 * EEPROMs, but them's the breaks. 186 */ 187 aprint_normal("\n"); 188 aprint_error_dev(self, "invalid size specified; " 189 "assuming 2KB (16Kb)\n"); 190 sc->sc_size = 2048; 191 sc->sc_cmdlen = 1; 192 } 193 194 sc->sc_open = 0; 195 } 196 197 /*ARGSUSED*/ 198 int 199 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 200 { 201 struct seeprom_softc *sc; 202 203 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 204 return (ENXIO); 205 206 /* XXX: Locking */ 207 208 if (sc->sc_open) 209 return (EBUSY); 210 211 sc->sc_open = 1; 212 return (0); 213 } 214 215 /*ARGSUSED*/ 216 int 217 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 218 { 219 struct seeprom_softc *sc; 220 221 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 222 return (ENXIO); 223 224 sc->sc_open = 0; 225 return (0); 226 } 227 228 /*ARGSUSED*/ 229 int 230 seeprom_read(dev_t dev, struct uio *uio, int flags) 231 { 232 struct seeprom_softc *sc; 233 i2c_addr_t addr; 234 u_int8_t ch, cmdbuf[2]; 235 int a, error; 236 237 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 238 return (ENXIO); 239 240 if (uio->uio_offset >= sc->sc_size) 241 return (EINVAL); 242 243 /* 244 * Even though the AT24Cxx EEPROMs support sequential 245 * reads within a page, some I2C controllers do not 246 * support anything other than single-byte transfers, 247 * so we're stuck with this lowest-common-denominator. 248 */ 249 250 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 251 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 252 return (error); 253 254 a = (int)uio->uio_offset; 255 if (sc->sc_cmdlen == 1) { 256 addr = sc->sc_address + (a >> 8); 257 cmdbuf[0] = a & 0xff; 258 } else { 259 addr = sc->sc_address; 260 cmdbuf[0] = AT24CXX_ADDR_HI(a); 261 cmdbuf[1] = AT24CXX_ADDR_LO(a); 262 } 263 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 264 addr, cmdbuf, sc->sc_cmdlen, 265 &ch, 1, 0)) != 0) { 266 iic_release_bus(sc->sc_tag, 0); 267 aprint_error_dev(sc->sc_dev, 268 "seeprom_read: byte read failed at 0x%x\n", a); 269 return (error); 270 } 271 if ((error = uiomove(&ch, 1, uio)) != 0) { 272 iic_release_bus(sc->sc_tag, 0); 273 return (error); 274 } 275 iic_release_bus(sc->sc_tag, 0); 276 } 277 278 return (0); 279 } 280 281 /*ARGSUSED*/ 282 int 283 seeprom_write(dev_t dev, struct uio *uio, int flags) 284 { 285 struct seeprom_softc *sc; 286 i2c_addr_t addr; 287 u_int8_t ch, cmdbuf[2]; 288 int a, error; 289 290 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 291 return (ENXIO); 292 293 if (uio->uio_offset >= sc->sc_size) 294 return (EINVAL); 295 296 /* 297 * See seeprom_read() for why we don't use sequential 298 * writes within a page. 299 */ 300 301 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 302 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 303 return (error); 304 305 a = (int)uio->uio_offset; 306 if (sc->sc_cmdlen == 1) { 307 addr = sc->sc_address + (a >> 8); 308 cmdbuf[0] = a & 0xff; 309 } else { 310 addr = sc->sc_address; 311 cmdbuf[0] = AT24CXX_ADDR_HI(a); 312 cmdbuf[1] = AT24CXX_ADDR_LO(a); 313 } 314 if ((error = uiomove(&ch, 1, uio)) != 0) { 315 iic_release_bus(sc->sc_tag, 0); 316 return (error); 317 } 318 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 319 addr, cmdbuf, sc->sc_cmdlen, 320 &ch, 1, 0)) != 0) { 321 iic_release_bus(sc->sc_tag, 0); 322 aprint_error_dev(sc->sc_dev, 323 "seeprom_write: byte write failed at 0x%x\n", a); 324 return (error); 325 } 326 327 /* Wait until the device commits the byte. */ 328 if ((error = seeprom_wait_idle(sc)) != 0) { 329 iic_release_bus(sc->sc_tag, 0); 330 return (error); 331 } 332 iic_release_bus(sc->sc_tag, 0); 333 } 334 335 return (0); 336 } 337 338 static int 339 seeprom_wait_idle(struct seeprom_softc *sc) 340 { 341 uint8_t cmdbuf[2] = { 0, 0 }; 342 int rv, timeout; 343 u_int8_t dummy; 344 345 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 346 if (timeout == 0) 347 timeout = 1; 348 349 delay(10); 350 351 /* 352 * Read the byte at address 0. This is just a dummy 353 * read to wait for the EEPROM's write cycle to complete. 354 */ 355 while (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 356 cmdbuf, sc->sc_cmdlen, &dummy, 1, 0)) { 357 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 358 if (rv != EWOULDBLOCK) 359 return (rv); 360 } 361 362 return (0); 363 } 364 365 #endif /* NSEEPROM > 0 */ 366 367 int 368 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 369 u_int8_t *rvp, size_t len) 370 { 371 i2c_addr_t addr; 372 int cmdlen; 373 uint8_t cmdbuf[2]; 374 375 if (len == 0) 376 return (0); 377 378 /* We are very forgiving about devsize during bootstrap. */ 379 cmdlen = (devsize >= 4096) ? 2 : 1; 380 381 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 382 return (-1); 383 384 while (len) { 385 if (cmdlen == 1) { 386 addr = i2caddr + (offset >> 8); 387 cmdbuf[0] = offset & 0xff; 388 } else { 389 addr = i2caddr; 390 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 391 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 392 } 393 394 /* Read a single byte. */ 395 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 396 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 397 iic_release_bus(tag, I2C_F_POLL); 398 return (-1); 399 } 400 401 len--; 402 rvp++; 403 offset++; 404 } 405 406 iic_release_bus(tag, I2C_F_POLL); 407 return (0); 408 } 409