1 /* $NetBSD: at24cxx.c,v 1.17 2014/03/16 05:20:27 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.17 2014/03/16 05:20:27 dholland Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x3f8 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 device_t sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(device_t, cfdata_t, void *); 85 static void seeprom_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 .d_open = seeprom_open, 98 .d_close = seeprom_close, 99 .d_read = seeprom_read, 100 .d_write = seeprom_write, 101 .d_ioctl = noioctl, 102 .d_stop = nostop, 103 .d_tty = notty, 104 .d_poll = nopoll, 105 .d_mmap = nommap, 106 .d_kqfilter = nokqfilter, 107 .d_flag = D_OTHER 108 }; 109 110 static int seeprom_wait_idle(struct seeprom_softc *); 111 112 static const char * seeprom_compats[] = { 113 "i2c-at24c64", 114 "i2c-at34c02", 115 NULL 116 }; 117 118 static int 119 seeprom_match(device_t parent, cfdata_t cf, void *aux) 120 { 121 struct i2c_attach_args *ia = aux; 122 123 if (ia->ia_name) { 124 if (iic_compat_match(ia, seeprom_compats)) 125 return (1); 126 } else { 127 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 128 return (1); 129 } 130 131 return (0); 132 } 133 134 static void 135 seeprom_attach(device_t parent, device_t self, void *aux) 136 { 137 struct seeprom_softc *sc = device_private(self); 138 struct i2c_attach_args *ia = aux; 139 140 sc->sc_tag = ia->ia_tag; 141 sc->sc_address = ia->ia_addr; 142 sc->sc_dev = self; 143 144 if (ia->ia_name != NULL) { 145 aprint_naive(": %s", ia->ia_name); 146 aprint_normal(": %s", ia->ia_name); 147 } else { 148 aprint_naive(": EEPROM"); 149 aprint_normal(": AT24Cxx or compatible EEPROM"); 150 } 151 152 /* 153 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 154 * word to select the offset into the EEPROM page. The 155 * AT24C04/08/16 decode fewer of the i2c address bits, 156 * using the bottom 1, 2, or 3 to select the 256-byte 157 * super-page. 158 * 159 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 160 * word and decode all of the i2c address bits. 161 * 162 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 163 * switching to select the proper super-page. This isn't 164 * supported by this driver. 165 */ 166 if (device_cfdata(self)->cf_flags) 167 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 168 else 169 sc->sc_size = ia->ia_size; 170 switch (sc->sc_size) { 171 case 128: /* 1Kbit */ 172 case 256: /* 2Kbit */ 173 case 512: /* 4Kbit */ 174 case 1024: /* 8Kbit */ 175 case 2048: /* 16Kbit */ 176 sc->sc_cmdlen = 1; 177 aprint_normal(": size %d\n", sc->sc_size); 178 break; 179 180 case 4096: /* 32Kbit */ 181 case 8192: /* 64Kbit */ 182 case 16384: /* 128Kbit */ 183 case 32768: /* 256Kbit */ 184 case 65536: /* 512Kbit */ 185 sc->sc_cmdlen = 2; 186 aprint_normal(": size %d\n", sc->sc_size); 187 break; 188 189 default: 190 /* 191 * Default to 2KB. If we happen to have a 2KB 192 * EEPROM this will allow us to access it. If we 193 * have a smaller one, the worst that can happen 194 * is that we end up trying to read a different 195 * EEPROM on the bus when accessing it. 196 * 197 * Obviously this will not work for 4KB or 8KB 198 * EEPROMs, but them's the breaks. 199 */ 200 aprint_normal("\n"); 201 aprint_error_dev(self, "invalid size specified; " 202 "assuming 2KB (16Kb)\n"); 203 sc->sc_size = 2048; 204 sc->sc_cmdlen = 1; 205 } 206 207 sc->sc_open = 0; 208 } 209 210 /*ARGSUSED*/ 211 int 212 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 213 { 214 struct seeprom_softc *sc; 215 216 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 217 return (ENXIO); 218 219 /* XXX: Locking */ 220 221 if (sc->sc_open) 222 return (EBUSY); 223 224 sc->sc_open = 1; 225 return (0); 226 } 227 228 /*ARGSUSED*/ 229 int 230 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 231 { 232 struct seeprom_softc *sc; 233 234 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 235 return (ENXIO); 236 237 sc->sc_open = 0; 238 return (0); 239 } 240 241 /*ARGSUSED*/ 242 int 243 seeprom_read(dev_t dev, struct uio *uio, int flags) 244 { 245 struct seeprom_softc *sc; 246 i2c_addr_t addr; 247 u_int8_t ch, cmdbuf[2]; 248 int a, error; 249 250 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 251 return (ENXIO); 252 253 if (uio->uio_offset >= sc->sc_size) 254 return (EINVAL); 255 256 /* 257 * Even though the AT24Cxx EEPROMs support sequential 258 * reads within a page, some I2C controllers do not 259 * support anything other than single-byte transfers, 260 * so we're stuck with this lowest-common-denominator. 261 */ 262 263 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 264 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 265 return (error); 266 267 a = (int)uio->uio_offset; 268 if (sc->sc_cmdlen == 1) { 269 addr = sc->sc_address + (a >> 8); 270 cmdbuf[0] = a & 0xff; 271 } else { 272 addr = sc->sc_address; 273 cmdbuf[0] = AT24CXX_ADDR_HI(a); 274 cmdbuf[1] = AT24CXX_ADDR_LO(a); 275 } 276 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 277 addr, cmdbuf, sc->sc_cmdlen, 278 &ch, 1, 0)) != 0) { 279 iic_release_bus(sc->sc_tag, 0); 280 aprint_error_dev(sc->sc_dev, 281 "seeprom_read: byte read failed at 0x%x\n", a); 282 return (error); 283 } 284 if ((error = uiomove(&ch, 1, uio)) != 0) { 285 iic_release_bus(sc->sc_tag, 0); 286 return (error); 287 } 288 iic_release_bus(sc->sc_tag, 0); 289 } 290 291 return (0); 292 } 293 294 /*ARGSUSED*/ 295 int 296 seeprom_write(dev_t dev, struct uio *uio, int flags) 297 { 298 struct seeprom_softc *sc; 299 i2c_addr_t addr; 300 u_int8_t ch, cmdbuf[2]; 301 int a, error; 302 303 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 304 return (ENXIO); 305 306 if (uio->uio_offset >= sc->sc_size) 307 return (EINVAL); 308 309 /* 310 * See seeprom_read() for why we don't use sequential 311 * writes within a page. 312 */ 313 314 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 315 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 316 return (error); 317 318 a = (int)uio->uio_offset; 319 if (sc->sc_cmdlen == 1) { 320 addr = sc->sc_address + (a >> 8); 321 cmdbuf[0] = a & 0xff; 322 } else { 323 addr = sc->sc_address; 324 cmdbuf[0] = AT24CXX_ADDR_HI(a); 325 cmdbuf[1] = AT24CXX_ADDR_LO(a); 326 } 327 if ((error = uiomove(&ch, 1, uio)) != 0) { 328 iic_release_bus(sc->sc_tag, 0); 329 return (error); 330 } 331 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 332 addr, cmdbuf, sc->sc_cmdlen, 333 &ch, 1, 0)) != 0) { 334 iic_release_bus(sc->sc_tag, 0); 335 aprint_error_dev(sc->sc_dev, 336 "seeprom_write: byte write failed at 0x%x\n", a); 337 return (error); 338 } 339 340 /* Wait until the device commits the byte. */ 341 if ((error = seeprom_wait_idle(sc)) != 0) { 342 iic_release_bus(sc->sc_tag, 0); 343 return (error); 344 } 345 iic_release_bus(sc->sc_tag, 0); 346 } 347 348 return (0); 349 } 350 351 static int 352 seeprom_wait_idle(struct seeprom_softc *sc) 353 { 354 uint8_t cmdbuf[2] = { 0, 0 }; 355 int rv, timeout; 356 u_int8_t dummy; 357 358 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 359 if (timeout == 0) 360 timeout = 1; 361 362 delay(10); 363 364 /* 365 * Read the byte at address 0. This is just a dummy 366 * read to wait for the EEPROM's write cycle to complete. 367 */ 368 while (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 369 cmdbuf, sc->sc_cmdlen, &dummy, 1, 0)) { 370 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 371 if (rv != EWOULDBLOCK) 372 return (rv); 373 } 374 375 return (0); 376 } 377 378 #endif /* NSEEPROM > 0 */ 379 380 int 381 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 382 u_int8_t *rvp, size_t len) 383 { 384 i2c_addr_t addr; 385 int cmdlen; 386 uint8_t cmdbuf[2]; 387 388 if (len == 0) 389 return (0); 390 391 /* We are very forgiving about devsize during bootstrap. */ 392 cmdlen = (devsize >= 4096) ? 2 : 1; 393 394 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 395 return (-1); 396 397 while (len) { 398 if (cmdlen == 1) { 399 addr = i2caddr + (offset >> 8); 400 cmdbuf[0] = offset & 0xff; 401 } else { 402 addr = i2caddr; 403 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 404 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 405 } 406 407 /* Read a single byte. */ 408 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 409 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 410 iic_release_bus(tag, I2C_F_POLL); 411 return (-1); 412 } 413 414 len--; 415 rvp++; 416 offset++; 417 } 418 419 iic_release_bus(tag, I2C_F_POLL); 420 return (0); 421 } 422