1 /* $NetBSD: at24cxx.c,v 1.20 2015/09/27 13:02:21 phx Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.20 2015/09/27 13:02:21 phx Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x3f8 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 device_t sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(device_t, cfdata_t, void *); 85 static void seeprom_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 .d_open = seeprom_open, 98 .d_close = seeprom_close, 99 .d_read = seeprom_read, 100 .d_write = seeprom_write, 101 .d_ioctl = noioctl, 102 .d_stop = nostop, 103 .d_tty = notty, 104 .d_poll = nopoll, 105 .d_mmap = nommap, 106 .d_kqfilter = nokqfilter, 107 .d_discard = nodiscard, 108 .d_flag = D_OTHER 109 }; 110 111 static int seeprom_wait_idle(struct seeprom_softc *); 112 113 static const char * seeprom_compats[] = { 114 "i2c-at24c64", 115 "i2c-at34c02", 116 NULL 117 }; 118 119 static int 120 seeprom_match(device_t parent, cfdata_t cf, void *aux) 121 { 122 struct i2c_attach_args *ia = aux; 123 124 if (ia->ia_name) { 125 if (ia->ia_ncompat > 0) { 126 if (iic_compat_match(ia, seeprom_compats)) 127 return (1); 128 } else { 129 if (strcmp(ia->ia_name, "seeprom") == 0) 130 return (1); 131 } 132 } else { 133 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 134 return (1); 135 } 136 137 return (0); 138 } 139 140 static void 141 seeprom_attach(device_t parent, device_t self, void *aux) 142 { 143 struct seeprom_softc *sc = device_private(self); 144 struct i2c_attach_args *ia = aux; 145 146 sc->sc_tag = ia->ia_tag; 147 sc->sc_address = ia->ia_addr; 148 sc->sc_dev = self; 149 150 if (ia->ia_name != NULL) { 151 aprint_naive(": %s", ia->ia_name); 152 aprint_normal(": %s", ia->ia_name); 153 } else { 154 aprint_naive(": EEPROM"); 155 aprint_normal(": AT24Cxx or compatible EEPROM"); 156 } 157 158 /* 159 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 160 * word to select the offset into the EEPROM page. The 161 * AT24C04/08/16 decode fewer of the i2c address bits, 162 * using the bottom 1, 2, or 3 to select the 256-byte 163 * super-page. 164 * 165 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 166 * word and decode all of the i2c address bits. 167 * 168 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 169 * switching to select the proper super-page. This isn't 170 * supported by this driver. 171 */ 172 if (device_cfdata(self)->cf_flags) 173 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 174 else 175 sc->sc_size = ia->ia_size; 176 switch (sc->sc_size) { 177 case 128: /* 1Kbit */ 178 case 256: /* 2Kbit */ 179 case 512: /* 4Kbit */ 180 case 1024: /* 8Kbit */ 181 case 2048: /* 16Kbit */ 182 sc->sc_cmdlen = 1; 183 aprint_normal(": size %d\n", sc->sc_size); 184 break; 185 186 case 4096: /* 32Kbit */ 187 case 8192: /* 64Kbit */ 188 case 16384: /* 128Kbit */ 189 case 32768: /* 256Kbit */ 190 case 65536: /* 512Kbit */ 191 sc->sc_cmdlen = 2; 192 aprint_normal(": size %d\n", sc->sc_size); 193 break; 194 195 default: 196 /* 197 * Default to 2KB. If we happen to have a 2KB 198 * EEPROM this will allow us to access it. If we 199 * have a smaller one, the worst that can happen 200 * is that we end up trying to read a different 201 * EEPROM on the bus when accessing it. 202 * 203 * Obviously this will not work for 4KB or 8KB 204 * EEPROMs, but them's the breaks. 205 */ 206 aprint_normal("\n"); 207 aprint_error_dev(self, "invalid size specified; " 208 "assuming 2KB (16Kb)\n"); 209 sc->sc_size = 2048; 210 sc->sc_cmdlen = 1; 211 } 212 213 sc->sc_open = 0; 214 } 215 216 /*ARGSUSED*/ 217 int 218 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 219 { 220 struct seeprom_softc *sc; 221 222 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 223 return (ENXIO); 224 225 /* XXX: Locking */ 226 227 if (sc->sc_open) 228 return (EBUSY); 229 230 sc->sc_open = 1; 231 return (0); 232 } 233 234 /*ARGSUSED*/ 235 int 236 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 237 { 238 struct seeprom_softc *sc; 239 240 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 241 return (ENXIO); 242 243 sc->sc_open = 0; 244 return (0); 245 } 246 247 /*ARGSUSED*/ 248 int 249 seeprom_read(dev_t dev, struct uio *uio, int flags) 250 { 251 struct seeprom_softc *sc; 252 i2c_addr_t addr; 253 u_int8_t ch, cmdbuf[2]; 254 int a, error; 255 256 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 257 return (ENXIO); 258 259 if (uio->uio_offset >= sc->sc_size) 260 return (EINVAL); 261 262 /* 263 * Even though the AT24Cxx EEPROMs support sequential 264 * reads within a page, some I2C controllers do not 265 * support anything other than single-byte transfers, 266 * so we're stuck with this lowest-common-denominator. 267 */ 268 269 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 270 a = (int)uio->uio_offset; 271 if (sc->sc_cmdlen == 1) { 272 addr = sc->sc_address + (a >> 8); 273 cmdbuf[0] = a & 0xff; 274 } else { 275 addr = sc->sc_address; 276 cmdbuf[0] = AT24CXX_ADDR_HI(a); 277 cmdbuf[1] = AT24CXX_ADDR_LO(a); 278 } 279 280 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 281 return (error); 282 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 283 addr, cmdbuf, sc->sc_cmdlen, 284 &ch, 1, 0)) != 0) { 285 iic_release_bus(sc->sc_tag, 0); 286 aprint_error_dev(sc->sc_dev, 287 "seeprom_read: byte read failed at 0x%x\n", a); 288 return (error); 289 } 290 iic_release_bus(sc->sc_tag, 0); 291 292 if ((error = uiomove(&ch, 1, uio)) != 0) { 293 return (error); 294 } 295 } 296 297 return (0); 298 } 299 300 /*ARGSUSED*/ 301 int 302 seeprom_write(dev_t dev, struct uio *uio, int flags) 303 { 304 struct seeprom_softc *sc; 305 i2c_addr_t addr; 306 u_int8_t ch, cmdbuf[2]; 307 int a, error; 308 309 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 310 return (ENXIO); 311 312 if (uio->uio_offset >= sc->sc_size) 313 return (EINVAL); 314 315 /* 316 * See seeprom_read() for why we don't use sequential 317 * writes within a page. 318 */ 319 320 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 321 a = (int)uio->uio_offset; 322 if (sc->sc_cmdlen == 1) { 323 addr = sc->sc_address + (a >> 8); 324 cmdbuf[0] = a & 0xff; 325 } else { 326 addr = sc->sc_address; 327 cmdbuf[0] = AT24CXX_ADDR_HI(a); 328 cmdbuf[1] = AT24CXX_ADDR_LO(a); 329 } 330 if ((error = uiomove(&ch, 1, uio)) != 0) { 331 iic_release_bus(sc->sc_tag, 0); 332 return (error); 333 } 334 335 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 336 return (error); 337 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 338 addr, cmdbuf, sc->sc_cmdlen, 339 &ch, 1, 0)) != 0) { 340 iic_release_bus(sc->sc_tag, 0); 341 aprint_error_dev(sc->sc_dev, 342 "seeprom_write: byte write failed at 0x%x\n", a); 343 return (error); 344 } 345 iic_release_bus(sc->sc_tag, 0); 346 347 /* Wait until the device commits the byte. */ 348 if ((error = seeprom_wait_idle(sc)) != 0) { 349 return (error); 350 } 351 } 352 353 return (0); 354 } 355 356 static int 357 seeprom_wait_idle(struct seeprom_softc *sc) 358 { 359 uint8_t cmdbuf[2] = { 0, 0 }; 360 int rv, timeout; 361 u_int8_t dummy; 362 int error; 363 364 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 365 if (timeout == 0) 366 timeout = 1; 367 368 delay(10); 369 370 /* 371 * Read the byte at address 0. This is just a dummy 372 * read to wait for the EEPROM's write cycle to complete. 373 */ 374 for (;;) { 375 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 376 return error; 377 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 378 sc->sc_address, cmdbuf, sc->sc_cmdlen, &dummy, 1, 0); 379 iic_release_bus(sc->sc_tag, 0); 380 if (error == 0) 381 break; 382 383 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 384 if (rv != EWOULDBLOCK) 385 return (rv); 386 } 387 388 return (0); 389 } 390 391 #endif /* NSEEPROM > 0 */ 392 393 int 394 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 395 u_int8_t *rvp, size_t len) 396 { 397 i2c_addr_t addr; 398 int cmdlen; 399 uint8_t cmdbuf[2]; 400 401 if (len == 0) 402 return (0); 403 404 /* We are very forgiving about devsize during bootstrap. */ 405 cmdlen = (devsize >= 4096) ? 2 : 1; 406 407 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 408 return (-1); 409 410 while (len) { 411 if (cmdlen == 1) { 412 addr = i2caddr + (offset >> 8); 413 cmdbuf[0] = offset & 0xff; 414 } else { 415 addr = i2caddr; 416 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 417 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 418 } 419 420 /* Read a single byte. */ 421 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 422 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 423 iic_release_bus(tag, I2C_F_POLL); 424 return (-1); 425 } 426 427 len--; 428 rvp++; 429 offset++; 430 } 431 432 iic_release_bus(tag, I2C_F_POLL); 433 return (0); 434 } 435