1 /* $NetBSD: at24cxx.c,v 1.10 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.10 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x78 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 struct device sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(struct device *, struct cfdata *, void *); 85 static void seeprom_attach(struct device *, struct device *, void *); 86 87 CFATTACH_DECL(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 seeprom_open, seeprom_close, seeprom_read, seeprom_write, noioctl, 98 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 99 }; 100 101 static int seeprom_wait_idle(struct seeprom_softc *); 102 103 104 static int 105 seeprom_match(struct device *parent, struct cfdata *cf, void *aux) 106 { 107 struct i2c_attach_args *ia = aux; 108 109 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 110 return (1); 111 112 return (0); 113 } 114 115 static void 116 seeprom_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct seeprom_softc *sc = device_private(self); 119 struct i2c_attach_args *ia = aux; 120 121 sc->sc_tag = ia->ia_tag; 122 sc->sc_address = ia->ia_addr; 123 124 aprint_naive(": EEPROM\n"); 125 aprint_normal(": AT24Cxx EEPROM\n"); 126 127 /* 128 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 129 * word to select the offset into the EEPROM page. The 130 * AT24C04/08/16 decode fewer of the i2c address bits, 131 * using the bottom 1, 2, or 3 to select the 256-byte 132 * super-page. 133 * 134 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 135 * word and decode all of the i2c address bits. 136 * 137 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 138 * switching to select the proper super-page. This isn't 139 * supported by this driver. 140 */ 141 sc->sc_size = ia->ia_size; 142 switch (sc->sc_size) { 143 case 128: /* 1Kbit */ 144 case 256: /* 2Kbit */ 145 case 512: /* 4Kbit */ 146 case 1024: /* 8Kbit */ 147 case 2048: /* 16Kbit */ 148 sc->sc_cmdlen = 1; 149 break; 150 151 case 4096: /* 32Kbit */ 152 case 8192: /* 64Kbit */ 153 case 16384: /* 128Kbit */ 154 case 32768: /* 256Kbit */ 155 case 65536: /* 512Kbit */ 156 sc->sc_cmdlen = 2; 157 break; 158 159 default: 160 /* 161 * Default to 2KB. If we happen to have a 2KB 162 * EEPROM this will allow us to access it. If we 163 * have a smaller one, the worst that can happen 164 * is that we end up trying to read a different 165 * EEPROM on the bus when accessing it. 166 * 167 * Obviously this will not work for 4KB or 8KB 168 * EEPROMs, but them's the breaks. 169 */ 170 aprint_error_dev(&sc->sc_dev, "invalid size specified; " 171 "assuming 2KB (16Kb)\n"); 172 sc->sc_size = 2048; 173 sc->sc_cmdlen = 1; 174 } 175 176 sc->sc_open = 0; 177 } 178 179 /*ARGSUSED*/ 180 int 181 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 182 { 183 struct seeprom_softc *sc; 184 185 if ((sc = device_lookup(&seeprom_cd, minor(dev))) == NULL) 186 return (ENXIO); 187 188 /* XXX: Locking */ 189 190 if (sc->sc_open) 191 return (EBUSY); 192 193 sc->sc_open = 1; 194 return (0); 195 } 196 197 /*ARGSUSED*/ 198 int 199 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 200 { 201 struct seeprom_softc *sc; 202 203 if ((sc = device_lookup(&seeprom_cd, minor(dev))) == NULL) 204 return (ENXIO); 205 206 sc->sc_open = 0; 207 return (0); 208 } 209 210 /*ARGSUSED*/ 211 int 212 seeprom_read(dev_t dev, struct uio *uio, int flags) 213 { 214 struct seeprom_softc *sc; 215 i2c_addr_t addr; 216 u_int8_t ch, cmdbuf[2]; 217 int a, error; 218 219 if ((sc = device_lookup(&seeprom_cd, minor(dev))) == NULL) 220 return (ENXIO); 221 222 if (uio->uio_offset >= sc->sc_size) 223 return (EINVAL); 224 225 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 226 return (error); 227 228 /* 229 * Even though the AT24Cxx EEPROMs support sequential 230 * reads within a page, some I2C controllers do not 231 * support anything other than single-byte transfers, 232 * so we're stuck with this lowest-common-denominator. 233 */ 234 235 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 236 a = (int)uio->uio_offset; 237 if (sc->sc_cmdlen == 1) { 238 addr = sc->sc_address + (a >> 8); 239 cmdbuf[0] = a & 0xff; 240 } else { 241 addr = sc->sc_address; 242 cmdbuf[0] = AT24CXX_ADDR_HI(a); 243 cmdbuf[1] = AT24CXX_ADDR_LO(a); 244 } 245 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 246 addr, cmdbuf, sc->sc_cmdlen, 247 &ch, 1, 0)) != 0) { 248 iic_release_bus(sc->sc_tag, 0); 249 aprint_error_dev(&sc->sc_dev, "seeprom_read: byte read failed at 0x%x\n", a); 250 return (error); 251 } 252 if ((error = uiomove(&ch, 1, uio)) != 0) { 253 iic_release_bus(sc->sc_tag, 0); 254 return (error); 255 } 256 } 257 258 iic_release_bus(sc->sc_tag, 0); 259 260 return (0); 261 } 262 263 /*ARGSUSED*/ 264 int 265 seeprom_write(dev_t dev, struct uio *uio, int flags) 266 { 267 struct seeprom_softc *sc; 268 i2c_addr_t addr; 269 u_int8_t ch, cmdbuf[2]; 270 int a, error; 271 272 if ((sc = device_lookup(&seeprom_cd, minor(dev))) == NULL) 273 return (ENXIO); 274 275 if (uio->uio_offset >= sc->sc_size) 276 return (EINVAL); 277 278 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 279 return (error); 280 281 /* 282 * See seeprom_read() for why we don't use sequential 283 * writes within a page. 284 */ 285 286 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 287 a = (int)uio->uio_offset; 288 if (sc->sc_cmdlen == 1) { 289 addr = sc->sc_address + (a >> 8); 290 cmdbuf[0] = a & 0xff; 291 } else { 292 addr = sc->sc_address; 293 cmdbuf[0] = AT24CXX_ADDR_HI(a); 294 cmdbuf[1] = AT24CXX_ADDR_LO(a); 295 } 296 if ((error = uiomove(&ch, 1, uio)) != 0) { 297 iic_release_bus(sc->sc_tag, 0); 298 return (error); 299 } 300 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 301 addr, cmdbuf, sc->sc_cmdlen, 302 &ch, 1, 0)) != 0) { 303 iic_release_bus(sc->sc_tag, 0); 304 aprint_error_dev(&sc->sc_dev, "seeprom_write: byte write failed at 0x%x\n", a); 305 return (error); 306 } 307 308 /* Wait until the device commits the byte. */ 309 if ((error = seeprom_wait_idle(sc)) != 0) { 310 iic_release_bus(sc->sc_tag, 0); 311 return (error); 312 } 313 } 314 315 iic_release_bus(sc->sc_tag, 0); 316 317 return (0); 318 } 319 320 static int 321 seeprom_wait_idle(struct seeprom_softc *sc) 322 { 323 uint8_t cmdbuf[2] = { 0, 0 }; 324 int rv, timeout; 325 u_int8_t dummy; 326 327 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 328 if (timeout == 0) 329 timeout = 1; 330 331 delay(10); 332 333 /* 334 * Read the byte at address 0. This is just a dummy 335 * read to wait for the EEPROM's write cycle to complete. 336 */ 337 while (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 338 cmdbuf, sc->sc_cmdlen, &dummy, 1, 0)) { 339 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 340 if (rv != EWOULDBLOCK) 341 return (rv); 342 } 343 344 return (0); 345 } 346 347 #endif /* NSEEPROM > 0 */ 348 349 int 350 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 351 u_int8_t *rvp, size_t len) 352 { 353 i2c_addr_t addr; 354 int cmdlen; 355 uint8_t cmdbuf[2]; 356 357 if (len == 0) 358 return (0); 359 360 /* We are very forgiving about devsize during bootstrap. */ 361 cmdlen = (devsize >= 4096) ? 2 : 1; 362 363 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 364 return (-1); 365 366 while (len) { 367 if (cmdlen == 1) { 368 addr = i2caddr + (offset >> 8); 369 cmdbuf[0] = offset & 0xff; 370 } else { 371 addr = i2caddr; 372 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 373 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 374 } 375 376 /* Read a single byte. */ 377 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 378 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 379 iic_release_bus(tag, I2C_F_POLL); 380 return (-1); 381 } 382 383 len--; 384 rvp++; 385 offset++; 386 } 387 388 iic_release_bus(tag, I2C_F_POLL); 389 return (0); 390 } 391