1 /* $NetBSD: at24cxx.c,v 1.25 2017/10/28 04:53:55 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.25 2017/10/28 04:53:55 riastradh Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 #include "ioconf.h" 57 58 /* 59 * AT24Cxx EEPROM I2C address: 60 * 101 0xxx 61 * (and others depending on the exact model) The bigger 8-bit parts 62 * decode multiple addresses. The bigger 16-bit parts do too (those 63 * larger than 512kb). Be sure to check the datasheet of your EEPROM 64 * because there's much variation between models. 65 */ 66 #define AT24CXX_ADDRMASK 0x3f8 67 #define AT24CXX_ADDR 0x50 68 69 #define AT24CXX_WRITE_CYCLE_MS 10 70 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 71 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 72 73 #include "seeprom.h" 74 75 #if NSEEPROM > 0 76 77 struct seeprom_softc { 78 device_t sc_dev; 79 i2c_tag_t sc_tag; 80 int sc_address; 81 int sc_size; 82 int sc_cmdlen; 83 int sc_open; 84 }; 85 86 static int seeprom_match(device_t, cfdata_t, void *); 87 static void seeprom_attach(device_t, device_t, void *); 88 89 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 90 seeprom_match, seeprom_attach, NULL, NULL); 91 92 dev_type_open(seeprom_open); 93 dev_type_close(seeprom_close); 94 dev_type_read(seeprom_read); 95 dev_type_write(seeprom_write); 96 97 const struct cdevsw seeprom_cdevsw = { 98 .d_open = seeprom_open, 99 .d_close = seeprom_close, 100 .d_read = seeprom_read, 101 .d_write = seeprom_write, 102 .d_ioctl = noioctl, 103 .d_stop = nostop, 104 .d_tty = notty, 105 .d_poll = nopoll, 106 .d_mmap = nommap, 107 .d_kqfilter = nokqfilter, 108 .d_discard = nodiscard, 109 .d_flag = D_OTHER 110 }; 111 112 static int seeprom_wait_idle(struct seeprom_softc *); 113 114 static const char * seeprom_compats[] = { 115 "i2c-at24c64", 116 "i2c-at34c02", 117 "atmel,24c02", 118 "atmel,24c16", 119 NULL 120 }; 121 122 static const struct seeprom_size { 123 const char *name; 124 int size; 125 } seeprom_sizes[] = { 126 { "atmel,24c02", 256 }, 127 { "atmel,24c16", 2048 }, 128 }; 129 130 static int 131 seeprom_match(device_t parent, cfdata_t cf, void *aux) 132 { 133 struct i2c_attach_args *ia = aux; 134 135 if (ia->ia_name) { 136 if (ia->ia_ncompat > 0) { 137 if (iic_compat_match(ia, seeprom_compats)) 138 return (1); 139 } else { 140 if (strcmp(ia->ia_name, "seeprom") == 0) 141 return (1); 142 } 143 } else { 144 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 145 return (1); 146 } 147 148 return (0); 149 } 150 151 static void 152 seeprom_attach(device_t parent, device_t self, void *aux) 153 { 154 struct seeprom_softc *sc = device_private(self); 155 struct i2c_attach_args *ia = aux; 156 u_int n, m; 157 158 sc->sc_tag = ia->ia_tag; 159 sc->sc_address = ia->ia_addr; 160 sc->sc_dev = self; 161 162 if (ia->ia_name != NULL) { 163 aprint_naive(": %s", ia->ia_name); 164 aprint_normal(": %s", ia->ia_name); 165 } else { 166 aprint_naive(": EEPROM"); 167 aprint_normal(": AT24Cxx or compatible EEPROM"); 168 } 169 170 /* 171 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 172 * word to select the offset into the EEPROM page. The 173 * AT24C04/08/16 decode fewer of the i2c address bits, 174 * using the bottom 1, 2, or 3 to select the 256-byte 175 * super-page. 176 * 177 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 178 * word and decode all of the i2c address bits. 179 * 180 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 181 * switching to select the proper super-page. This isn't 182 * supported by this driver. 183 */ 184 if (device_cfdata(self)->cf_flags) 185 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 186 else 187 sc->sc_size = ia->ia_size; 188 189 if (sc->sc_size <= 0 && ia->ia_ncompat > 0) { 190 for (n = 0; n < __arraycount(seeprom_sizes); n++) { 191 for (m = 0; m < ia->ia_ncompat; m++) { 192 if (!strcmp(seeprom_sizes[n].name, 193 ia->ia_compat[m])) { 194 sc->sc_size = seeprom_sizes[n].size; 195 break; 196 } 197 } 198 } 199 } 200 201 switch (sc->sc_size) { 202 case 128: /* 1Kbit */ 203 case 256: /* 2Kbit */ 204 case 512: /* 4Kbit */ 205 case 1024: /* 8Kbit */ 206 case 2048: /* 16Kbit */ 207 sc->sc_cmdlen = 1; 208 aprint_normal(": size %d\n", sc->sc_size); 209 break; 210 211 case 4096: /* 32Kbit */ 212 case 8192: /* 64Kbit */ 213 case 16384: /* 128Kbit */ 214 case 32768: /* 256Kbit */ 215 case 65536: /* 512Kbit */ 216 sc->sc_cmdlen = 2; 217 aprint_normal(": size %d\n", sc->sc_size); 218 break; 219 220 default: 221 /* 222 * Default to 2KB. If we happen to have a 2KB 223 * EEPROM this will allow us to access it. If we 224 * have a smaller one, the worst that can happen 225 * is that we end up trying to read a different 226 * EEPROM on the bus when accessing it. 227 * 228 * Obviously this will not work for 4KB or 8KB 229 * EEPROMs, but them's the breaks. 230 */ 231 aprint_normal("\n"); 232 aprint_error_dev(self, "invalid size specified; " 233 "assuming 2KB (16Kb)\n"); 234 sc->sc_size = 2048; 235 sc->sc_cmdlen = 1; 236 } 237 238 sc->sc_open = 0; 239 } 240 241 /*ARGSUSED*/ 242 int 243 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 244 { 245 struct seeprom_softc *sc; 246 247 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 248 return (ENXIO); 249 250 /* XXX: Locking */ 251 252 if (sc->sc_open) 253 return (EBUSY); 254 255 sc->sc_open = 1; 256 return (0); 257 } 258 259 /*ARGSUSED*/ 260 int 261 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 262 { 263 struct seeprom_softc *sc; 264 265 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 266 return (ENXIO); 267 268 sc->sc_open = 0; 269 return (0); 270 } 271 272 /*ARGSUSED*/ 273 int 274 seeprom_read(dev_t dev, struct uio *uio, int flags) 275 { 276 struct seeprom_softc *sc; 277 i2c_addr_t addr; 278 u_int8_t ch, cmdbuf[2]; 279 int a, error; 280 281 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 282 return (ENXIO); 283 284 if (uio->uio_offset >= sc->sc_size) 285 return (EINVAL); 286 287 /* 288 * Even though the AT24Cxx EEPROMs support sequential 289 * reads within a page, some I2C controllers do not 290 * support anything other than single-byte transfers, 291 * so we're stuck with this lowest-common-denominator. 292 */ 293 294 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 295 a = (int)uio->uio_offset; 296 if (sc->sc_cmdlen == 1) { 297 addr = sc->sc_address + (a >> 8); 298 cmdbuf[0] = a & 0xff; 299 } else { 300 addr = sc->sc_address; 301 cmdbuf[0] = AT24CXX_ADDR_HI(a); 302 cmdbuf[1] = AT24CXX_ADDR_LO(a); 303 } 304 305 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 306 return (error); 307 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 308 addr, cmdbuf, sc->sc_cmdlen, 309 &ch, 1, 0)) != 0) { 310 iic_release_bus(sc->sc_tag, 0); 311 aprint_error_dev(sc->sc_dev, 312 "seeprom_read: byte read failed at 0x%x\n", a); 313 return (error); 314 } 315 iic_release_bus(sc->sc_tag, 0); 316 317 if ((error = uiomove(&ch, 1, uio)) != 0) { 318 return (error); 319 } 320 } 321 322 return (0); 323 } 324 325 /*ARGSUSED*/ 326 int 327 seeprom_write(dev_t dev, struct uio *uio, int flags) 328 { 329 struct seeprom_softc *sc; 330 i2c_addr_t addr; 331 u_int8_t ch, cmdbuf[2]; 332 int a, error; 333 334 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 335 return (ENXIO); 336 337 if (uio->uio_offset >= sc->sc_size) 338 return (EINVAL); 339 340 /* 341 * See seeprom_read() for why we don't use sequential 342 * writes within a page. 343 */ 344 345 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 346 a = (int)uio->uio_offset; 347 if (sc->sc_cmdlen == 1) { 348 addr = sc->sc_address + (a >> 8); 349 cmdbuf[0] = a & 0xff; 350 } else { 351 addr = sc->sc_address; 352 cmdbuf[0] = AT24CXX_ADDR_HI(a); 353 cmdbuf[1] = AT24CXX_ADDR_LO(a); 354 } 355 if ((error = uiomove(&ch, 1, uio)) != 0) { 356 iic_release_bus(sc->sc_tag, 0); 357 return (error); 358 } 359 360 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 361 return (error); 362 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 363 addr, cmdbuf, sc->sc_cmdlen, 364 &ch, 1, 0)) != 0) { 365 iic_release_bus(sc->sc_tag, 0); 366 aprint_error_dev(sc->sc_dev, 367 "seeprom_write: byte write failed at 0x%x\n", a); 368 return (error); 369 } 370 iic_release_bus(sc->sc_tag, 0); 371 372 /* Wait until the device commits the byte. */ 373 if ((error = seeprom_wait_idle(sc)) != 0) { 374 return (error); 375 } 376 } 377 378 return (0); 379 } 380 381 static int 382 seeprom_wait_idle(struct seeprom_softc *sc) 383 { 384 uint8_t cmdbuf[2] = { 0, 0 }; 385 int rv, timeout; 386 u_int8_t dummy; 387 int error; 388 389 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 390 if (timeout == 0) 391 timeout = 1; 392 393 delay(10); 394 395 /* 396 * Read the byte at address 0. This is just a dummy 397 * read to wait for the EEPROM's write cycle to complete. 398 */ 399 for (;;) { 400 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 401 return error; 402 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 403 sc->sc_address, cmdbuf, sc->sc_cmdlen, &dummy, 1, 0); 404 iic_release_bus(sc->sc_tag, 0); 405 if (error == 0) 406 break; 407 408 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 409 if (rv != EWOULDBLOCK) 410 return (rv); 411 } 412 413 return (0); 414 } 415 416 #endif /* NSEEPROM > 0 */ 417 418 int 419 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 420 u_int8_t *rvp, size_t len) 421 { 422 i2c_addr_t addr; 423 int cmdlen; 424 uint8_t cmdbuf[2]; 425 426 if (len == 0) 427 return (0); 428 429 /* We are very forgiving about devsize during bootstrap. */ 430 cmdlen = (devsize >= 4096) ? 2 : 1; 431 432 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 433 return (-1); 434 435 while (len) { 436 if (cmdlen == 1) { 437 addr = i2caddr + (offset >> 8); 438 cmdbuf[0] = offset & 0xff; 439 } else { 440 addr = i2caddr; 441 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 442 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 443 } 444 445 /* Read a single byte. */ 446 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 447 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 448 iic_release_bus(tag, I2C_F_POLL); 449 return (-1); 450 } 451 452 len--; 453 rvp++; 454 offset++; 455 } 456 457 iic_release_bus(tag, I2C_F_POLL); 458 return (0); 459 } 460