1 /* $NetBSD: at24cxx.c,v 1.18 2014/07/25 08:10:37 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.18 2014/07/25 08:10:37 dholland Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x3f8 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 device_t sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(device_t, cfdata_t, void *); 85 static void seeprom_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 .d_open = seeprom_open, 98 .d_close = seeprom_close, 99 .d_read = seeprom_read, 100 .d_write = seeprom_write, 101 .d_ioctl = noioctl, 102 .d_stop = nostop, 103 .d_tty = notty, 104 .d_poll = nopoll, 105 .d_mmap = nommap, 106 .d_kqfilter = nokqfilter, 107 .d_discard = nodiscard, 108 .d_flag = D_OTHER 109 }; 110 111 static int seeprom_wait_idle(struct seeprom_softc *); 112 113 static const char * seeprom_compats[] = { 114 "i2c-at24c64", 115 "i2c-at34c02", 116 NULL 117 }; 118 119 static int 120 seeprom_match(device_t parent, cfdata_t cf, void *aux) 121 { 122 struct i2c_attach_args *ia = aux; 123 124 if (ia->ia_name) { 125 if (iic_compat_match(ia, seeprom_compats)) 126 return (1); 127 } else { 128 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 129 return (1); 130 } 131 132 return (0); 133 } 134 135 static void 136 seeprom_attach(device_t parent, device_t self, void *aux) 137 { 138 struct seeprom_softc *sc = device_private(self); 139 struct i2c_attach_args *ia = aux; 140 141 sc->sc_tag = ia->ia_tag; 142 sc->sc_address = ia->ia_addr; 143 sc->sc_dev = self; 144 145 if (ia->ia_name != NULL) { 146 aprint_naive(": %s", ia->ia_name); 147 aprint_normal(": %s", ia->ia_name); 148 } else { 149 aprint_naive(": EEPROM"); 150 aprint_normal(": AT24Cxx or compatible EEPROM"); 151 } 152 153 /* 154 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 155 * word to select the offset into the EEPROM page. The 156 * AT24C04/08/16 decode fewer of the i2c address bits, 157 * using the bottom 1, 2, or 3 to select the 256-byte 158 * super-page. 159 * 160 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 161 * word and decode all of the i2c address bits. 162 * 163 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 164 * switching to select the proper super-page. This isn't 165 * supported by this driver. 166 */ 167 if (device_cfdata(self)->cf_flags) 168 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 169 else 170 sc->sc_size = ia->ia_size; 171 switch (sc->sc_size) { 172 case 128: /* 1Kbit */ 173 case 256: /* 2Kbit */ 174 case 512: /* 4Kbit */ 175 case 1024: /* 8Kbit */ 176 case 2048: /* 16Kbit */ 177 sc->sc_cmdlen = 1; 178 aprint_normal(": size %d\n", sc->sc_size); 179 break; 180 181 case 4096: /* 32Kbit */ 182 case 8192: /* 64Kbit */ 183 case 16384: /* 128Kbit */ 184 case 32768: /* 256Kbit */ 185 case 65536: /* 512Kbit */ 186 sc->sc_cmdlen = 2; 187 aprint_normal(": size %d\n", sc->sc_size); 188 break; 189 190 default: 191 /* 192 * Default to 2KB. If we happen to have a 2KB 193 * EEPROM this will allow us to access it. If we 194 * have a smaller one, the worst that can happen 195 * is that we end up trying to read a different 196 * EEPROM on the bus when accessing it. 197 * 198 * Obviously this will not work for 4KB or 8KB 199 * EEPROMs, but them's the breaks. 200 */ 201 aprint_normal("\n"); 202 aprint_error_dev(self, "invalid size specified; " 203 "assuming 2KB (16Kb)\n"); 204 sc->sc_size = 2048; 205 sc->sc_cmdlen = 1; 206 } 207 208 sc->sc_open = 0; 209 } 210 211 /*ARGSUSED*/ 212 int 213 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 214 { 215 struct seeprom_softc *sc; 216 217 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 218 return (ENXIO); 219 220 /* XXX: Locking */ 221 222 if (sc->sc_open) 223 return (EBUSY); 224 225 sc->sc_open = 1; 226 return (0); 227 } 228 229 /*ARGSUSED*/ 230 int 231 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 232 { 233 struct seeprom_softc *sc; 234 235 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 236 return (ENXIO); 237 238 sc->sc_open = 0; 239 return (0); 240 } 241 242 /*ARGSUSED*/ 243 int 244 seeprom_read(dev_t dev, struct uio *uio, int flags) 245 { 246 struct seeprom_softc *sc; 247 i2c_addr_t addr; 248 u_int8_t ch, cmdbuf[2]; 249 int a, error; 250 251 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 252 return (ENXIO); 253 254 if (uio->uio_offset >= sc->sc_size) 255 return (EINVAL); 256 257 /* 258 * Even though the AT24Cxx EEPROMs support sequential 259 * reads within a page, some I2C controllers do not 260 * support anything other than single-byte transfers, 261 * so we're stuck with this lowest-common-denominator. 262 */ 263 264 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 265 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 266 return (error); 267 268 a = (int)uio->uio_offset; 269 if (sc->sc_cmdlen == 1) { 270 addr = sc->sc_address + (a >> 8); 271 cmdbuf[0] = a & 0xff; 272 } else { 273 addr = sc->sc_address; 274 cmdbuf[0] = AT24CXX_ADDR_HI(a); 275 cmdbuf[1] = AT24CXX_ADDR_LO(a); 276 } 277 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 278 addr, cmdbuf, sc->sc_cmdlen, 279 &ch, 1, 0)) != 0) { 280 iic_release_bus(sc->sc_tag, 0); 281 aprint_error_dev(sc->sc_dev, 282 "seeprom_read: byte read failed at 0x%x\n", a); 283 return (error); 284 } 285 if ((error = uiomove(&ch, 1, uio)) != 0) { 286 iic_release_bus(sc->sc_tag, 0); 287 return (error); 288 } 289 iic_release_bus(sc->sc_tag, 0); 290 } 291 292 return (0); 293 } 294 295 /*ARGSUSED*/ 296 int 297 seeprom_write(dev_t dev, struct uio *uio, int flags) 298 { 299 struct seeprom_softc *sc; 300 i2c_addr_t addr; 301 u_int8_t ch, cmdbuf[2]; 302 int a, error; 303 304 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 305 return (ENXIO); 306 307 if (uio->uio_offset >= sc->sc_size) 308 return (EINVAL); 309 310 /* 311 * See seeprom_read() for why we don't use sequential 312 * writes within a page. 313 */ 314 315 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 316 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 317 return (error); 318 319 a = (int)uio->uio_offset; 320 if (sc->sc_cmdlen == 1) { 321 addr = sc->sc_address + (a >> 8); 322 cmdbuf[0] = a & 0xff; 323 } else { 324 addr = sc->sc_address; 325 cmdbuf[0] = AT24CXX_ADDR_HI(a); 326 cmdbuf[1] = AT24CXX_ADDR_LO(a); 327 } 328 if ((error = uiomove(&ch, 1, uio)) != 0) { 329 iic_release_bus(sc->sc_tag, 0); 330 return (error); 331 } 332 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 333 addr, cmdbuf, sc->sc_cmdlen, 334 &ch, 1, 0)) != 0) { 335 iic_release_bus(sc->sc_tag, 0); 336 aprint_error_dev(sc->sc_dev, 337 "seeprom_write: byte write failed at 0x%x\n", a); 338 return (error); 339 } 340 341 /* Wait until the device commits the byte. */ 342 if ((error = seeprom_wait_idle(sc)) != 0) { 343 iic_release_bus(sc->sc_tag, 0); 344 return (error); 345 } 346 iic_release_bus(sc->sc_tag, 0); 347 } 348 349 return (0); 350 } 351 352 static int 353 seeprom_wait_idle(struct seeprom_softc *sc) 354 { 355 uint8_t cmdbuf[2] = { 0, 0 }; 356 int rv, timeout; 357 u_int8_t dummy; 358 359 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 360 if (timeout == 0) 361 timeout = 1; 362 363 delay(10); 364 365 /* 366 * Read the byte at address 0. This is just a dummy 367 * read to wait for the EEPROM's write cycle to complete. 368 */ 369 while (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 370 cmdbuf, sc->sc_cmdlen, &dummy, 1, 0)) { 371 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 372 if (rv != EWOULDBLOCK) 373 return (rv); 374 } 375 376 return (0); 377 } 378 379 #endif /* NSEEPROM > 0 */ 380 381 int 382 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 383 u_int8_t *rvp, size_t len) 384 { 385 i2c_addr_t addr; 386 int cmdlen; 387 uint8_t cmdbuf[2]; 388 389 if (len == 0) 390 return (0); 391 392 /* We are very forgiving about devsize during bootstrap. */ 393 cmdlen = (devsize >= 4096) ? 2 : 1; 394 395 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 396 return (-1); 397 398 while (len) { 399 if (cmdlen == 1) { 400 addr = i2caddr + (offset >> 8); 401 cmdbuf[0] = offset & 0xff; 402 } else { 403 addr = i2caddr; 404 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 405 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 406 } 407 408 /* Read a single byte. */ 409 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 410 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 411 iic_release_bus(tag, I2C_F_POLL); 412 return (-1); 413 } 414 415 len--; 416 rvp++; 417 offset++; 418 } 419 420 iic_release_bus(tag, I2C_F_POLL); 421 return (0); 422 } 423