1 /* $NetBSD: at24cxx.c,v 1.16 2013/10/25 14:32:10 jdc Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.16 2013/10/25 14:32:10 jdc Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/i2c/i2cvar.h> 54 #include <dev/i2c/at24cxxvar.h> 55 56 /* 57 * AT24Cxx EEPROM I2C address: 58 * 101 0xxx 59 * (and others depending on the exact model) The bigger 8-bit parts 60 * decode multiple addresses. The bigger 16-bit parts do too (those 61 * larger than 512kb). Be sure to check the datasheet of your EEPROM 62 * because there's much variation between models. 63 */ 64 #define AT24CXX_ADDRMASK 0x3f8 65 #define AT24CXX_ADDR 0x50 66 67 #define AT24CXX_WRITE_CYCLE_MS 10 68 #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) 69 #define AT24CXX_ADDR_LO(a) ((a) & 0xff) 70 71 #include "seeprom.h" 72 73 #if NSEEPROM > 0 74 75 struct seeprom_softc { 76 device_t sc_dev; 77 i2c_tag_t sc_tag; 78 int sc_address; 79 int sc_size; 80 int sc_cmdlen; 81 int sc_open; 82 }; 83 84 static int seeprom_match(device_t, cfdata_t, void *); 85 static void seeprom_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), 88 seeprom_match, seeprom_attach, NULL, NULL); 89 extern struct cfdriver seeprom_cd; 90 91 dev_type_open(seeprom_open); 92 dev_type_close(seeprom_close); 93 dev_type_read(seeprom_read); 94 dev_type_write(seeprom_write); 95 96 const struct cdevsw seeprom_cdevsw = { 97 seeprom_open, seeprom_close, seeprom_read, seeprom_write, noioctl, 98 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 99 }; 100 101 static int seeprom_wait_idle(struct seeprom_softc *); 102 103 static const char * seeprom_compats[] = { 104 "i2c-at24c64", 105 "i2c-at34c02", 106 NULL 107 }; 108 109 static int 110 seeprom_match(device_t parent, cfdata_t cf, void *aux) 111 { 112 struct i2c_attach_args *ia = aux; 113 114 if (ia->ia_name) { 115 if (iic_compat_match(ia, seeprom_compats)) 116 return (1); 117 } else { 118 if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) 119 return (1); 120 } 121 122 return (0); 123 } 124 125 static void 126 seeprom_attach(device_t parent, device_t self, void *aux) 127 { 128 struct seeprom_softc *sc = device_private(self); 129 struct i2c_attach_args *ia = aux; 130 131 sc->sc_tag = ia->ia_tag; 132 sc->sc_address = ia->ia_addr; 133 sc->sc_dev = self; 134 135 if (ia->ia_name != NULL) { 136 aprint_naive(": %s", ia->ia_name); 137 aprint_normal(": %s", ia->ia_name); 138 } else { 139 aprint_naive(": EEPROM"); 140 aprint_normal(": AT24Cxx or compatible EEPROM"); 141 } 142 143 /* 144 * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command 145 * word to select the offset into the EEPROM page. The 146 * AT24C04/08/16 decode fewer of the i2c address bits, 147 * using the bottom 1, 2, or 3 to select the 256-byte 148 * super-page. 149 * 150 * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command 151 * word and decode all of the i2c address bits. 152 * 153 * The AT24C1024 EEPROMs use a 2 byte command and also do bank 154 * switching to select the proper super-page. This isn't 155 * supported by this driver. 156 */ 157 if (device_cfdata(self)->cf_flags) 158 sc->sc_size = (device_cfdata(self)->cf_flags << 7); 159 else 160 sc->sc_size = ia->ia_size; 161 switch (sc->sc_size) { 162 case 128: /* 1Kbit */ 163 case 256: /* 2Kbit */ 164 case 512: /* 4Kbit */ 165 case 1024: /* 8Kbit */ 166 case 2048: /* 16Kbit */ 167 sc->sc_cmdlen = 1; 168 aprint_normal(": size %d\n", sc->sc_size); 169 break; 170 171 case 4096: /* 32Kbit */ 172 case 8192: /* 64Kbit */ 173 case 16384: /* 128Kbit */ 174 case 32768: /* 256Kbit */ 175 case 65536: /* 512Kbit */ 176 sc->sc_cmdlen = 2; 177 aprint_normal(": size %d\n", sc->sc_size); 178 break; 179 180 default: 181 /* 182 * Default to 2KB. If we happen to have a 2KB 183 * EEPROM this will allow us to access it. If we 184 * have a smaller one, the worst that can happen 185 * is that we end up trying to read a different 186 * EEPROM on the bus when accessing it. 187 * 188 * Obviously this will not work for 4KB or 8KB 189 * EEPROMs, but them's the breaks. 190 */ 191 aprint_normal("\n"); 192 aprint_error_dev(self, "invalid size specified; " 193 "assuming 2KB (16Kb)\n"); 194 sc->sc_size = 2048; 195 sc->sc_cmdlen = 1; 196 } 197 198 sc->sc_open = 0; 199 } 200 201 /*ARGSUSED*/ 202 int 203 seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) 204 { 205 struct seeprom_softc *sc; 206 207 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 208 return (ENXIO); 209 210 /* XXX: Locking */ 211 212 if (sc->sc_open) 213 return (EBUSY); 214 215 sc->sc_open = 1; 216 return (0); 217 } 218 219 /*ARGSUSED*/ 220 int 221 seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) 222 { 223 struct seeprom_softc *sc; 224 225 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 226 return (ENXIO); 227 228 sc->sc_open = 0; 229 return (0); 230 } 231 232 /*ARGSUSED*/ 233 int 234 seeprom_read(dev_t dev, struct uio *uio, int flags) 235 { 236 struct seeprom_softc *sc; 237 i2c_addr_t addr; 238 u_int8_t ch, cmdbuf[2]; 239 int a, error; 240 241 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 242 return (ENXIO); 243 244 if (uio->uio_offset >= sc->sc_size) 245 return (EINVAL); 246 247 /* 248 * Even though the AT24Cxx EEPROMs support sequential 249 * reads within a page, some I2C controllers do not 250 * support anything other than single-byte transfers, 251 * so we're stuck with this lowest-common-denominator. 252 */ 253 254 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 255 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 256 return (error); 257 258 a = (int)uio->uio_offset; 259 if (sc->sc_cmdlen == 1) { 260 addr = sc->sc_address + (a >> 8); 261 cmdbuf[0] = a & 0xff; 262 } else { 263 addr = sc->sc_address; 264 cmdbuf[0] = AT24CXX_ADDR_HI(a); 265 cmdbuf[1] = AT24CXX_ADDR_LO(a); 266 } 267 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 268 addr, cmdbuf, sc->sc_cmdlen, 269 &ch, 1, 0)) != 0) { 270 iic_release_bus(sc->sc_tag, 0); 271 aprint_error_dev(sc->sc_dev, 272 "seeprom_read: byte read failed at 0x%x\n", a); 273 return (error); 274 } 275 if ((error = uiomove(&ch, 1, uio)) != 0) { 276 iic_release_bus(sc->sc_tag, 0); 277 return (error); 278 } 279 iic_release_bus(sc->sc_tag, 0); 280 } 281 282 return (0); 283 } 284 285 /*ARGSUSED*/ 286 int 287 seeprom_write(dev_t dev, struct uio *uio, int flags) 288 { 289 struct seeprom_softc *sc; 290 i2c_addr_t addr; 291 u_int8_t ch, cmdbuf[2]; 292 int a, error; 293 294 if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) 295 return (ENXIO); 296 297 if (uio->uio_offset >= sc->sc_size) 298 return (EINVAL); 299 300 /* 301 * See seeprom_read() for why we don't use sequential 302 * writes within a page. 303 */ 304 305 while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { 306 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 307 return (error); 308 309 a = (int)uio->uio_offset; 310 if (sc->sc_cmdlen == 1) { 311 addr = sc->sc_address + (a >> 8); 312 cmdbuf[0] = a & 0xff; 313 } else { 314 addr = sc->sc_address; 315 cmdbuf[0] = AT24CXX_ADDR_HI(a); 316 cmdbuf[1] = AT24CXX_ADDR_LO(a); 317 } 318 if ((error = uiomove(&ch, 1, uio)) != 0) { 319 iic_release_bus(sc->sc_tag, 0); 320 return (error); 321 } 322 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 323 addr, cmdbuf, sc->sc_cmdlen, 324 &ch, 1, 0)) != 0) { 325 iic_release_bus(sc->sc_tag, 0); 326 aprint_error_dev(sc->sc_dev, 327 "seeprom_write: byte write failed at 0x%x\n", a); 328 return (error); 329 } 330 331 /* Wait until the device commits the byte. */ 332 if ((error = seeprom_wait_idle(sc)) != 0) { 333 iic_release_bus(sc->sc_tag, 0); 334 return (error); 335 } 336 iic_release_bus(sc->sc_tag, 0); 337 } 338 339 return (0); 340 } 341 342 static int 343 seeprom_wait_idle(struct seeprom_softc *sc) 344 { 345 uint8_t cmdbuf[2] = { 0, 0 }; 346 int rv, timeout; 347 u_int8_t dummy; 348 349 timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; 350 if (timeout == 0) 351 timeout = 1; 352 353 delay(10); 354 355 /* 356 * Read the byte at address 0. This is just a dummy 357 * read to wait for the EEPROM's write cycle to complete. 358 */ 359 while (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 360 cmdbuf, sc->sc_cmdlen, &dummy, 1, 0)) { 361 rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr", timeout); 362 if (rv != EWOULDBLOCK) 363 return (rv); 364 } 365 366 return (0); 367 } 368 369 #endif /* NSEEPROM > 0 */ 370 371 int 372 seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, 373 u_int8_t *rvp, size_t len) 374 { 375 i2c_addr_t addr; 376 int cmdlen; 377 uint8_t cmdbuf[2]; 378 379 if (len == 0) 380 return (0); 381 382 /* We are very forgiving about devsize during bootstrap. */ 383 cmdlen = (devsize >= 4096) ? 2 : 1; 384 385 if (iic_acquire_bus(tag, I2C_F_POLL) != 0) 386 return (-1); 387 388 while (len) { 389 if (cmdlen == 1) { 390 addr = i2caddr + (offset >> 8); 391 cmdbuf[0] = offset & 0xff; 392 } else { 393 addr = i2caddr; 394 cmdbuf[0] = AT24CXX_ADDR_HI(offset); 395 cmdbuf[1] = AT24CXX_ADDR_LO(offset); 396 } 397 398 /* Read a single byte. */ 399 if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, 400 cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { 401 iic_release_bus(tag, I2C_F_POLL); 402 return (-1); 403 } 404 405 len--; 406 rvp++; 407 offset++; 408 } 409 410 iic_release_bus(tag, I2C_F_POLL); 411 return (0); 412 } 413