xref: /netbsd-src/sys/dev/hpc/hpciovar.h (revision 95e1ffb15694e54f29f8baaa4232152b703c2a5a)
1*95e1ffb1Schristos /*	$NetBSD: hpciovar.h,v 1.6 2005/12/11 12:21:22 christos Exp $	*/
226b0905dStakemura 
326b0905dStakemura /*-
426b0905dStakemura  * Copyright (c) 2001 TAKEMURA Shin.
526b0905dStakemura  * All rights reserved.
626b0905dStakemura  *
726b0905dStakemura  * Redistribution and use in source and binary forms, with or without
826b0905dStakemura  * modification, are permitted provided that the following conditions
926b0905dStakemura  * are met:
1026b0905dStakemura  * 1. Redistributions of source code must retain the above copyright
1126b0905dStakemura  *    notice, this list of conditions and the following disclaimer.
1226b0905dStakemura  * 2. Redistributions in binary form must reproduce the above copyright
1326b0905dStakemura  *    notice, this list of conditions and the following disclaimer in the
1426b0905dStakemura  *    documentation and/or other materials provided with the distribution.
1526b0905dStakemura  * 3. Neither the name of the project nor the names of its contributors
1626b0905dStakemura  *    may be used to endorse or promote products derived from this software
1726b0905dStakemura  *    without specific prior written permission.
1826b0905dStakemura  *
1926b0905dStakemura  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
2026b0905dStakemura  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2126b0905dStakemura  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2226b0905dStakemura  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
2326b0905dStakemura  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2426b0905dStakemura  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2526b0905dStakemura  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2626b0905dStakemura  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2726b0905dStakemura  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2826b0905dStakemura  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2926b0905dStakemura  * SUCH DAMAGE.
3026b0905dStakemura  *
3126b0905dStakemura  */
3226b0905dStakemura 
3326b0905dStakemura #ifndef _DEV_HPC_HPCIOVAR_H_
3426b0905dStakemura #define _DEV_HPC_HPCIOVAR_H_
3526b0905dStakemura 
3626b0905dStakemura struct hpcio_chip;
3726b0905dStakemura typedef struct hpcio_chip *hpcio_chip_t;
3826b0905dStakemura typedef void *hpcio_intr_handle_t;
3926b0905dStakemura struct hpcio_chip {
4026b0905dStakemura 	int hc_chipid;
417cb32336She 	const char *hc_name;
4226b0905dStakemura 	void *hc_sc;
4326b0905dStakemura 	int (*hc_portread)(hpcio_chip_t, int);
4426b0905dStakemura 	void (*hc_portwrite)(hpcio_chip_t, int, int);
45859a6a49Such 	hpcio_intr_handle_t(*hc_intr_establish)(hpcio_chip_t, int, int,
46859a6a49Such 	    int (*)(void *), void *);
4726b0905dStakemura 	void (*hc_intr_disestablish)(hpcio_chip_t, hpcio_intr_handle_t);
4826b0905dStakemura 	void (*hc_intr_clear)(hpcio_chip_t, hpcio_intr_handle_t);
4954d9a46bStakemura 	void (*hc_register_iochip)(hpcio_chip_t, hpcio_chip_t);
5026b0905dStakemura 	void (*hc_update)(hpcio_chip_t);
5126b0905dStakemura 	void (*hc_dump)(hpcio_chip_t);
5226b0905dStakemura };
5326b0905dStakemura 
5426b0905dStakemura struct hpcio_attach_args {
557cb32336She 	const char *haa_busname;
5626b0905dStakemura 	void *haa_sc;
5726b0905dStakemura 	hpcio_chip_t (*haa_getchip)(void*, int);
5854d9a46bStakemura 	bus_space_tag_t haa_iot;	/* I/O space tag */
5926b0905dStakemura };
60a8304325Stakemura #define HPCIO_BUSNAME	"hpcioif"
6126b0905dStakemura 
6226b0905dStakemura #define hpcio_portread(hc, port)					\
6326b0905dStakemura 		((*(hc)->hc_portread)((hc), (port)))
6426b0905dStakemura #define hpcio_portwrite(hc, port, data)					\
6526b0905dStakemura 		((*(hc)->hc_portwrite)((hc), (port), (data)))
6626b0905dStakemura #define hpcio_intr_establish(hc, port, mode, func, arg)			\
6726b0905dStakemura 		((*(hc)->hc_intr_establish)((hc),(port),(mode),(func),(arg)))
6826b0905dStakemura #define hpcio_intr_disestablish(hc, handle)				\
6926b0905dStakemura 		((*(hc)->hc_intr_disestablish)((hc), (handle)))
7026b0905dStakemura #define hpcio_intr_clear(hc, handle)					\
7126b0905dStakemura 		((*(hc)->hc_intr_clear)((hc), (handle)))
7254d9a46bStakemura #define hpcio_register_iochip(hc, iochip)				\
7354d9a46bStakemura 		((*(hc)->hc_register_iochip)((hc), (iochip)))
7426b0905dStakemura #define hpcio_update(hc)						\
7526b0905dStakemura 		((*(hc)->hc_update)(hc))
7626b0905dStakemura #define hpcio_dump(hc)							\
7726b0905dStakemura 		((*(hc)->hc_dump)(hc))
7826b0905dStakemura 
7926b0905dStakemura /* interrupt trigger options. */
8026b0905dStakemura #define HPCIO_INTR_EDGE		(1<<0)
8126b0905dStakemura #define HPCIO_INTR_LEVEL	(0<<0)
8226b0905dStakemura #define HPCIO_INTR_HOLD		(1<<1)
8326b0905dStakemura #define HPCIO_INTR_THROUGH	(0<<1)
8426b0905dStakemura #define HPCIO_INTR_HIGH		(1<<2)
8526b0905dStakemura #define HPCIO_INTR_LOW		(0<<2)
8626b0905dStakemura #define HPCIO_INTR_POSEDGE	(1<<3)
8726b0905dStakemura #define HPCIO_INTR_NEGEDGE	(1<<4)
8826b0905dStakemura 
8926b0905dStakemura #define HPCIO_INTR_LEVEL_HIGH_HOLD					\
9026b0905dStakemura 		(HPCIO_INTR_LEVEL|HPCIO_INTR_HIGH|HPCIO_INTR_HOLD)
9126b0905dStakemura #define HPCIO_INTR_LEVEL_HIGH_THROUGH					\
9226b0905dStakemura 		(HPCIO_INTR_LEVEL|HPCIO_INTR_HIGH|HPCIO_INTR_THROUGH)
9326b0905dStakemura #define HPCIO_INTR_LEVEL_LOW_HOLD					\
9426b0905dStakemura 		(HPCIO_INTR_LEVEL|HPCIO_INTR_LOW|HPCIO_INTR_HOLD)
9526b0905dStakemura #define HPCIO_INTR_LEVEL_LOW_THROUGH					\
9626b0905dStakemura 		(HPCIO_INTR_LEVEL|HPCIO_INTR_LOW|HPCIO_INTR_THROUGH)
9726b0905dStakemura #define HPCIO_INTR_EDGE_HOLD						\
9826b0905dStakemura 		(HPCIO_INTR_EDGE|HPCIO_INTR_HOLD)
9926b0905dStakemura #define HPCIO_INTR_EDGE_THROUGH						\
10026b0905dStakemura 		(HPCIO_INTR_EDGE|HPCIO_INTR_THROUGH)
10126b0905dStakemura 
10226b0905dStakemura #endif /* !_DEV_HPC_HPCIOVAR_H_ */
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