1 /* $NetBSD: dwc3_fdt.c,v 1.7 2019/04/19 19:05:56 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.7 2019/04/19 19:05:56 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/xhcireg.h> 44 #include <dev/usb/xhcivar.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define DWC3_GCTL 0xc110 49 #define GCTL_PRTCAP __BITS(13,12) 50 #define GCTL_PRTCAP_HOST 1 51 #define GCTL_PRTCAP_DEVICE 2 52 #define GCTL_PRTCAP_OTG 3 53 #define GCTL_CORESOFTRESET __BIT(11) 54 55 #define DWC3_SNPSID 0xc120 56 #define DWC3_SNPSID_REV __BITS(15,0) 57 58 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 4)) 59 #define GUSB2PHYCFG_PHYSOFTRST __BIT(31) 60 #define GUSB2PHYCFG_U2_FREECLK_EXISTS __BIT(30) 61 #define GUSB2PHYCFG_USBTRDTIM __BITS(13,10) 62 #define GUSB2PHYCFG_SUSPHY __BIT(6) 63 #define GUSB2PHYCFG_PHYIF __BIT(3) 64 #define GUSB2PHYCFG_ENBLSLPM __BIT(0) 65 66 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 4)) 67 #define GUSB3PIPECTL_PHYSOFTRST __BIT(31) 68 #define GUSB3PIPECTL_UX_EXIT_PX __BIT(27) 69 #define GUSB3PIPECTL_DEPOCHANGE __BIT(18) 70 #define GUSB3PIPECTL_SUSPHY __BIT(17) 71 72 #define DWC3_DCFG 0xc700 73 #define DCFG_SPEED __BITS(2,0) 74 #define DCFG_SPEED_HS 0 75 #define DCFG_SPEED_FS 1 76 #define DCFG_SPEED_LS 2 77 #define DCFG_SPEED_SS 4 78 #define DCFG_SPEED_SS_PLUS 5 79 80 static int dwc3_fdt_match(device_t, cfdata_t, void *); 81 static void dwc3_fdt_attach(device_t, device_t, void *); 82 83 CFATTACH_DECL2_NEW(dwc3_fdt, sizeof(struct xhci_softc), 84 dwc3_fdt_match, dwc3_fdt_attach, NULL, 85 xhci_activate, NULL, xhci_childdet); 86 87 #define RD4(sc, reg) \ 88 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 89 #define WR4(sc, reg, val) \ 90 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 91 #define SET4(sc, reg, mask) \ 92 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 93 #define CLR4(sc, reg, mask) \ 94 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 95 96 static void 97 dwc3_fdt_soft_reset(struct xhci_softc *sc) 98 { 99 /* Put core in reset */ 100 SET4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 101 102 /* Assert USB3 PHY reset */ 103 SET4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 104 105 /* Assert USB2 PHY reset */ 106 SET4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 107 108 delay(100000); 109 110 /* Clear USB3 PHY reset */ 111 CLR4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 112 113 /* Clear USB2 PHY reset */ 114 CLR4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 115 116 delay(100000); 117 118 /* Take core out of reset */ 119 CLR4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 120 } 121 122 static void 123 dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle) 124 { 125 const char *max_speed, *phy_type; 126 u_int phyif_utmi_bits; 127 uint32_t val; 128 129 val = RD4(sc, DWC3_GUSB2PHYCFG(0)); 130 if (of_getprop_uint32(phandle, "snps,phyif-utmi-bits", &phyif_utmi_bits) != 0) { 131 phy_type = fdtbus_get_string(phandle, "phy_type"); 132 if (phy_type && strcmp(phy_type, "utmi_wide") == 0) 133 phyif_utmi_bits = 16; 134 else if (phy_type && strcmp(phy_type, "utmi") == 0) 135 phyif_utmi_bits = 8; 136 else 137 phyif_utmi_bits = 0; 138 } 139 if (phyif_utmi_bits == 16) { 140 val |= GUSB2PHYCFG_PHYIF; 141 val &= ~GUSB2PHYCFG_USBTRDTIM; 142 val |= __SHIFTIN(5, GUSB2PHYCFG_USBTRDTIM); 143 } else if (phyif_utmi_bits == 8) { 144 val &= ~GUSB2PHYCFG_PHYIF; 145 val &= ~GUSB2PHYCFG_USBTRDTIM; 146 val |= __SHIFTIN(9, GUSB2PHYCFG_USBTRDTIM); 147 } 148 if (of_hasprop(phandle, "snps,dis-enblslpm-quirk") || 149 of_hasprop(phandle, "snps,dis_enblslpm_quirk")) 150 val &= ~GUSB2PHYCFG_ENBLSLPM; 151 if (of_hasprop(phandle, "snps,dis-u2-freeclk-exists-quirk")) 152 val &= ~GUSB2PHYCFG_U2_FREECLK_EXISTS; 153 if (of_hasprop(phandle, "snps,dis_u2_susphy_quirk")) 154 val &= ~GUSB2PHYCFG_SUSPHY; 155 WR4(sc, DWC3_GUSB2PHYCFG(0), val); 156 157 val = RD4(sc, DWC3_GUSB3PIPECTL(0)); 158 val &= ~GUSB3PIPECTL_UX_EXIT_PX; 159 if (of_hasprop(phandle, "snps,dis_u3_susphy_quirk")) 160 val &= ~GUSB3PIPECTL_SUSPHY; 161 if (of_hasprop(phandle, "snps,dis-del-phy-power-chg-quirk")) 162 val &= ~GUSB3PIPECTL_DEPOCHANGE; 163 WR4(sc, DWC3_GUSB3PIPECTL(0), val); 164 165 max_speed = fdtbus_get_string(phandle, "maximum-speed"); 166 if (max_speed == NULL) 167 max_speed = "super-speed"; 168 169 val = RD4(sc, DWC3_DCFG); 170 val &= ~DCFG_SPEED; 171 if (strcmp(max_speed, "low-speed") == 0) 172 val |= __SHIFTIN(DCFG_SPEED_LS, DCFG_SPEED); 173 else if (strcmp(max_speed, "full-speed") == 0) 174 val |= __SHIFTIN(DCFG_SPEED_FS, DCFG_SPEED); 175 else if (strcmp(max_speed, "high-speed") == 0) 176 val |= __SHIFTIN(DCFG_SPEED_HS, DCFG_SPEED); 177 else if (strcmp(max_speed, "super-speed") == 0) 178 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); 179 else 180 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); /* default to super speed */ 181 WR4(sc, DWC3_DCFG, val); 182 } 183 184 static void 185 dwc3_fdt_set_mode(struct xhci_softc *sc, u_int mode) 186 { 187 uint32_t val; 188 189 val = RD4(sc, DWC3_GCTL); 190 val &= ~GCTL_PRTCAP; 191 val |= __SHIFTIN(mode, GCTL_PRTCAP); 192 WR4(sc, DWC3_GCTL, val); 193 } 194 195 static int 196 dwc3_fdt_match(device_t parent, cfdata_t cf, void *aux) 197 { 198 const char * const compatible[] = { 199 "allwinner,sun50i-h6-dwc3", 200 "amlogic,meson-gxl-dwc3", 201 "rockchip,rk3328-dwc3", 202 "rockchip,rk3399-dwc3", 203 "samsung,exynos5250-dwusb3", 204 NULL 205 }; 206 struct fdt_attach_args * const faa = aux; 207 208 return of_match_compatible(faa->faa_phandle, compatible); 209 } 210 211 static void 212 dwc3_fdt_attach(device_t parent, device_t self, void *aux) 213 { 214 struct xhci_softc * const sc = device_private(self); 215 struct fdt_attach_args * const faa = aux; 216 const int phandle = faa->faa_phandle; 217 struct fdtbus_reset *rst; 218 struct fdtbus_phy *phy; 219 struct clk *clk; 220 char intrstr[128]; 221 bus_addr_t addr; 222 bus_size_t size; 223 int error; 224 void *ih; 225 u_int n; 226 227 /* Find dwc3 sub-node */ 228 const int dwc3_phandle = of_find_firstchild_byname(phandle, "dwc3"); 229 if (dwc3_phandle <= 0) { 230 aprint_error(": couldn't find dwc3 child node\n"); 231 return; 232 } 233 234 /* Only host mode is supported */ 235 const char *dr_mode = fdtbus_get_string(dwc3_phandle, "dr_mode"); 236 if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) { 237 aprint_error(": '%s' not supported\n", dr_mode); 238 return; 239 } 240 241 /* Enable clocks */ 242 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 243 if (clk_enable(clk) != 0) { 244 aprint_error(": couldn't enable clock #%d\n", n); 245 return; 246 } 247 /* De-assert resets */ 248 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 249 if (fdtbus_reset_deassert(rst) != 0) { 250 aprint_error(": couldn't de-assert reset #%d\n", n); 251 return; 252 } 253 254 /* Get resources */ 255 if (fdtbus_get_reg(dwc3_phandle, 0, &addr, &size) != 0) { 256 aprint_error(": couldn't get registers\n"); 257 return; 258 } 259 260 sc->sc_dev = self; 261 sc->sc_bus.ub_hcpriv = sc; 262 sc->sc_bus.ub_dmatag = faa->faa_dmat; 263 sc->sc_iot = faa->faa_bst; 264 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 265 aprint_error(": couldn't map registers\n"); 266 return; 267 } 268 269 aprint_naive("\n"); 270 aprint_normal(": DesignWare USB3 XHCI"); 271 const uint32_t snpsid = RD4(sc, DWC3_SNPSID); 272 const u_int rev = __SHIFTOUT(snpsid, DWC3_SNPSID_REV); 273 aprint_normal(" (rev. %d.%03x)\n", rev >> 12, rev & 0xfff); 274 275 /* Enable PHY devices */ 276 for (n = 0; (phy = fdtbus_phy_get_index(dwc3_phandle, n)) != NULL; n++) { 277 if (fdtbus_phy_enable(phy, true) != 0) 278 aprint_error_dev(self, "couldn't enable phy #%d\n", n); 279 } 280 281 dwc3_fdt_soft_reset(sc); 282 dwc3_fdt_enable_phy(sc, dwc3_phandle); 283 dwc3_fdt_set_mode(sc, GCTL_PRTCAP_HOST); 284 285 if (!fdtbus_intr_str(dwc3_phandle, 0, intrstr, sizeof(intrstr))) { 286 aprint_error_dev(self, "failed to decode interrupt\n"); 287 return; 288 } 289 290 ih = fdtbus_intr_establish(dwc3_phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 291 xhci_intr, sc); 292 if (ih == NULL) { 293 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 294 intrstr); 295 return; 296 } 297 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 298 299 sc->sc_bus.ub_revision = USBREV_3_0; 300 error = xhci_init(sc); 301 if (error) { 302 aprint_error_dev(self, "init failed, error = %d\n", error); 303 return; 304 } 305 306 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 307 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 308 } 309