1 /* $NetBSD: ebusreg.h,v 1.7 2005/12/11 12:21:20 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _DEV_EBUS_EBUSREG_H_ 32 #define _DEV_EBUS_EBUSREG_H_ 33 34 /* 35 * SPARC `ebus' 36 * 37 * The `ebus' bus is designed to plug traditional PC-ISA devices into 38 * an SPARC system with as few costs as possible, without sacrificing 39 * to performance. Typically, it is implemented in the PCIO IC from 40 * SME, which also implements a `hme-compatible' PCI network device 41 * (`network'). The ebus has 4 DMA channels, similar to the DMA seen 42 * in the ESP SCSI DMA. 43 * 44 * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide 45 * serial ports for the keyboard and mouse (`se'), floppy disk 46 * controller (`fdthree'), parallel port controller (`bpp') connected 47 * to the ebus, and a PCI-IDE controller (connected directly to the 48 * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual 49 * channel serial controller (`su' providing ttya and ttyb), an MK48T59 50 * EEPROM/clock controller (also where the idprom, including the 51 * ethernet address, is located), the audio system (`SUNW,CS4231', same 52 * as other UltraSPARC and some SPARC systems), and other various 53 * internal devices found on traditional SPARC systems such as the 54 * `power', `flashprom', etc., devices. Other machines with this 55 * device include microSPARC-IIep based systems, e.g. JavaStation10. 56 * 57 * The ebus uses an interrupt mapping scheme similar to PCI, though 58 * the actual structures are different. 59 */ 60 61 /* 62 * EBus PROM structures. There's no official OFW binding for EBus, 63 * so ms-IIep PROMs deviate from de-facto standard used on Ultra's. 64 * 65 * EBus address is represented in PROM by 2 cells: bar and offset. 66 * "bar" specifies the EBus BAR register used to translate the 67 * "offset" into PCI address space. 68 * 69 * On Ultra the bar is the _offset_ of the BAR in PCI config space but 70 * in (some?) ms-IIep systems (e.g. Krups) it's the _number_ of the 71 * BAR - e.g. BAR1 is represented by 1 in Krups PROM, while on Ultra 72 * it's 0x14. 73 */ 74 75 struct ebus_regs { 76 uint32_t hi; /* high bits of physaddr */ 77 uint32_t lo; 78 uint32_t size; 79 }; 80 81 #define EBUS_ADDR_FROM_REG(reg) BUS_ADDR((reg)->hi, (reg)->lo) 82 83 84 struct ebus_ranges { 85 uint32_t child_hi; /* child high phys addr */ 86 uint32_t child_lo; /* child low phys addr */ 87 uint32_t phys_hi; /* parent high phys addr */ 88 uint32_t phys_mid; /* parent mid phys addr */ 89 uint32_t phys_lo; /* parent low phys addr */ 90 uint32_t size; 91 }; 92 93 94 /* NB: ms-IIep PROMs lack these interrupt-related properties */ 95 struct ebus_interrupt_map { 96 uint32_t hi; /* high phys addr mask */ 97 uint32_t lo; /* low phys addr mask */ 98 uint32_t intr; /* interrupt mask */ 99 int32_t cnode; /* child node */ 100 uint32_t cintr; /* child interrupt */ 101 }; 102 103 struct ebus_interrupt_map_mask { 104 uint32_t hi; /* high phys addr */ 105 uint32_t lo; /* low phys addr */ 106 uint32_t intr; /* interrupt */ 107 }; 108 109 110 /* 111 * DMA controller registers. 112 * 113 * The "next" registers are at the same locations. 114 * Which one you write to depends on EN_NEXT bit in the DCSR. 115 */ 116 #define EBUS_DMAC_DCSR 0 /* control/status register */ 117 #define EBUS_DMAC_DACR 4 /* address count register */ 118 #define EBUS_DMAC_DNAR 4 /* next address register */ 119 #define EBUS_DMAC_DBCR 8 /* byte count register */ 120 #define EBUS_DMAC_DNBR 8 /* next byte register */ 121 122 #define EBUS_DMAC_SIZE 12 123 124 125 /* 126 * DCSR bits (PCIO manual, Table 7-23, pp 134-135) 127 * 128 * On Reset all the register bits except ID will be 0 and CYC_PENDING 129 * will reflect the status of any pending requests. 130 */ 131 #define EBDMA_INT_PEND 0x00000001 /* interrupt pending */ 132 #define EBDMA_ERR_PEND 0x00000002 /* error pending */ 133 #define EBDMA_DRAIN 0x00000004 /* fifo's being drained to memory */ 134 #define EBDMA_INT_EN 0x00000010 /* enable interrupts */ 135 #define EBDMA_RESET 0x00000080 /* reset - write 0 to clear */ 136 #define EBDMA_WRITE 0x00000100 /* 0: mem->dev, 1: dev->mem */ 137 #define EBDMA_EN_DMA 0x00000200 /* enable DMA */ 138 #define EBDMA_CYC_PEND 0x00000400 /* DMA cycle pending 139 - not safe to clear reset */ 140 #define EBDMA_DIAG_RD_DONE 0x00000800 /* DIAG mode: DMA read completed */ 141 #define EBDMA_DIAG_WR_DONE 0x00001000 /* DIAG mode: DMA write completed */ 142 #define EBDMA_EN_CNT 0x00002000 /* enable byte counter */ 143 #define EBDMA_TC 0x00004000 /* terminal count 144 - write 1 to clear */ 145 #define EBDMA_DIS_CSR_DRN 0x00010000 /* disable fifo draining 146 on slave writes to CSR */ 147 #define EBDMA_BURST_SIZE_MASK 0x000c0000 /* burst sizes: */ 148 #define EBDMA_BURST_SIZE_4 0x00000000 /* 00 - 4 words */ 149 #define EBDMA_BURST_SIZE_8 0x00040000 /* 01 - 8 words */ 150 #define EBDMA_BURST_SIZE_1 0x00080000 /* 10 - 1 word */ 151 #define EBDMA_BURST_SIZE_16 0x000c0000 /* 11 - 16 words */ 152 #define EBDMA_DIAG_EN 0x00100000 /* enable diag mode */ 153 #define EBDMA_DIS_ERR_PEND 0x00400000 /* disable stop/interrupt 154 on error pedning */ 155 #define EBDMA_TCI_DIS 0x00800000 /* disable interrupt on TC */ 156 #define EBDMA_EN_NEXT 0x01000000 /* enable next address autoload 157 (must set EN_CNT too) */ 158 #define EBDMA_DMA_ON 0x02000000 /* DMA is able to respond */ 159 #define EBDMA_A_LOADED 0x04000000 /* DACR loaded 160 (directly or from DNAR) */ 161 #define EBDMA_NA_LOADED 0x08000000 /* DNAR loaded */ 162 #define EBDMA_ID_MASK 0xf0000000 /* Device ID = 0xC */ 163 164 #define EBUS_DCSR_BITS \ 165 "\20\34NA_LOADED\33A_LOADED\32DMA_ON\31EN_NEXT\30TCI_DIS\27DIS_ERR_PEND" \ 166 "\25DIAG_EN\21DIS_CSR_DRN\17TC\16EN_CNT\15DIAG_WR_DONE\14DIAG_RD_DONE" \ 167 "\13CYC_PEND\12EN_DMA\11WRITE\10RESET\6INT_EN\3DRAIN\2ERR_PEND\1INT_PEND" 168 169 #endif /* _DEV_EBUS_EBUSREG_H_ */ 170