1 /* $NetBSD: dz.c,v 1.18 2005/12/11 12:21:20 christos Exp $ */ 2 /* 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Ralph Campbell and Rick Macklem. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * Ralph Campbell and Rick Macklem. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Berkeley and its contributors. 52 * 4. Neither the name of the University nor the names of its contributors 53 * may be used to endorse or promote products derived from this software 54 * without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 57 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 59 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 62 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 66 * SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.18 2005/12/11 12:21:20 christos Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/ioctl.h> 76 #include <sys/tty.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/conf.h> 80 #include <sys/file.h> 81 #include <sys/uio.h> 82 #include <sys/kernel.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 86 #include <machine/bus.h> 87 88 #include <dev/dec/dzreg.h> 89 #include <dev/dec/dzvar.h> 90 91 #include <dev/cons.h> 92 93 #define DZ_READ_BYTE(adr) \ 94 bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr) 95 #define DZ_READ_WORD(adr) \ 96 bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr) 97 #define DZ_WRITE_BYTE(adr, val) \ 98 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr, val) 99 #define DZ_WRITE_WORD(adr, val) \ 100 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_dr.adr, val) 101 #define DZ_BARRIER() \ 102 bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg, \ 103 sc->sc_dr.dr_winsize, \ 104 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ) 105 106 #include "ioconf.h" 107 108 /* Flags used to monitor modem bits, make them understood outside driver */ 109 110 #define DML_DTR TIOCM_DTR 111 #define DML_DCD TIOCM_CD 112 #define DML_RI TIOCM_RI 113 #define DML_BRK 0100000 /* no equivalent, we will mask */ 114 115 static const struct speedtab dzspeedtab[] = 116 { 117 { 0, 0 }, 118 { 50, DZ_LPR_B50 }, 119 { 75, DZ_LPR_B75 }, 120 { 110, DZ_LPR_B110 }, 121 { 134, DZ_LPR_B134 }, 122 { 150, DZ_LPR_B150 }, 123 { 300, DZ_LPR_B300 }, 124 { 600, DZ_LPR_B600 }, 125 { 1200, DZ_LPR_B1200 }, 126 { 1800, DZ_LPR_B1800 }, 127 { 2000, DZ_LPR_B2000 }, 128 { 2400, DZ_LPR_B2400 }, 129 { 3600, DZ_LPR_B3600 }, 130 { 4800, DZ_LPR_B4800 }, 131 { 7200, DZ_LPR_B7200 }, 132 { 9600, DZ_LPR_B9600 }, 133 { 19200, DZ_LPR_B19200 }, 134 { -1, -1 } 135 }; 136 137 static void dzstart(struct tty *); 138 static int dzparam(struct tty *, struct termios *); 139 static unsigned dzmctl(struct dz_softc *, int, int, int); 140 static void dzscan(void *); 141 142 dev_type_open(dzopen); 143 dev_type_close(dzclose); 144 dev_type_read(dzread); 145 dev_type_write(dzwrite); 146 dev_type_ioctl(dzioctl); 147 dev_type_stop(dzstop); 148 dev_type_tty(dztty); 149 dev_type_poll(dzpoll); 150 151 const struct cdevsw dz_cdevsw = { 152 dzopen, dzclose, dzread, dzwrite, dzioctl, 153 dzstop, dztty, dzpoll, nommap, ttykqfilter, D_TTY 154 }; 155 156 /* 157 * The DZ series doesn't interrupt on carrier transitions, 158 * so we have to use a timer to watch it. 159 */ 160 int dz_timer; /* true if timer started */ 161 struct callout dzscan_ch; 162 static struct cnm_state dz_cnm_state; 163 164 void 165 dzattach(struct dz_softc *sc, struct evcnt *parent_evcnt, int consline) 166 { 167 int n; 168 169 sc->sc_rxint = sc->sc_brk = 0; 170 sc->sc_consline = consline; 171 172 sc->sc_dr.dr_tcrw = sc->sc_dr.dr_tcr; 173 DZ_WRITE_WORD(dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE); 174 DZ_WRITE_BYTE(dr_dtr, 0); 175 DZ_WRITE_BYTE(dr_break, 0); 176 DZ_BARRIER(); 177 178 /* Initialize our softc structure. Should be done in open? */ 179 180 for (n = 0; n < sc->sc_type; n++) { 181 sc->sc_dz[n].dz_sc = sc; 182 sc->sc_dz[n].dz_line = n; 183 sc->sc_dz[n].dz_tty = ttymalloc(); 184 } 185 186 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 187 sc->sc_dev.dv_xname, "rintr"); 188 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 189 sc->sc_dev.dv_xname, "tintr"); 190 191 /* Console magic keys */ 192 cn_init_magic(&dz_cnm_state); 193 cn_set_magic("\047\001"); /* default magic is BREAK */ 194 /* VAX will change it in MD code */ 195 196 /* Alas no interrupt on modem bit changes, so we manually scan */ 197 198 if (dz_timer == 0) { 199 dz_timer = 1; 200 callout_init(&dzscan_ch); 201 callout_reset(&dzscan_ch, hz, dzscan, NULL); 202 } 203 printf("\n"); 204 } 205 206 /* Receiver Interrupt */ 207 208 void 209 dzrint(void *arg) 210 { 211 struct dz_softc *sc = arg; 212 struct tty *tp; 213 int cc, mcc, line; 214 unsigned c; 215 int overrun = 0; 216 217 sc->sc_rxint++; 218 219 while ((c = DZ_READ_WORD(dr_rbuf)) & DZ_RBUF_DATA_VALID) { 220 cc = c & 0xFF; 221 line = DZ_PORT(c>>8); 222 tp = sc->sc_dz[line].dz_tty; 223 224 /* Must be caught early */ 225 if (sc->sc_dz[line].dz_catch && 226 (*sc->sc_dz[line].dz_catch)(sc->sc_dz[line].dz_private, cc)) 227 continue; 228 229 if ((c & (DZ_RBUF_FRAMING_ERR | 0xff)) == DZ_RBUF_FRAMING_ERR) 230 mcc = CNC_BREAK; 231 else 232 mcc = cc; 233 234 cn_check_magic(tp->t_dev, mcc, dz_cnm_state); 235 236 if (!(tp->t_state & TS_ISOPEN)) { 237 wakeup((caddr_t)&tp->t_rawq); 238 continue; 239 } 240 241 if ((c & DZ_RBUF_OVERRUN_ERR) && overrun == 0) { 242 log(LOG_WARNING, "%s: silo overflow, line %d\n", 243 sc->sc_dev.dv_xname, line); 244 overrun = 1; 245 } 246 247 if (c & DZ_RBUF_FRAMING_ERR) 248 cc |= TTY_FE; 249 if (c & DZ_RBUF_PARITY_ERR) 250 cc |= TTY_PE; 251 252 (*tp->t_linesw->l_rint)(cc, tp); 253 } 254 } 255 256 /* Transmitter Interrupt */ 257 258 void 259 dzxint(void *arg) 260 { 261 struct dz_softc *sc = arg; 262 struct tty *tp; 263 struct clist *cl; 264 int line, ch, csr; 265 u_char tcr; 266 267 /* 268 * Switch to POLLED mode. 269 * Some simple measurements indicated that even on 270 * one port, by freeing the scanner in the controller 271 * by either providing a character or turning off 272 * the port when output is complete, the transmitter 273 * was ready to accept more output when polled again. 274 * With just two ports running the game "worms," 275 * almost every interrupt serviced both transmitters! 276 * Each UART is double buffered, so if the scanner 277 * is quick enough and timing works out, we can even 278 * feed the same port twice. 279 * 280 * Ragge 980517: 281 * Do not need to turn off interrupts, already at interrupt level. 282 * Remove the pdma stuff; no great need of it right now. 283 */ 284 285 while (((csr = DZ_READ_WORD(dr_csr)) & DZ_CSR_TX_READY) != 0) { 286 287 line = DZ_PORT(csr>>8); 288 289 tp = sc->sc_dz[line].dz_tty; 290 cl = &tp->t_outq; 291 tp->t_state &= ~TS_BUSY; 292 293 /* Just send out a char if we have one */ 294 /* As long as we can fill the chip buffer, we just loop here */ 295 if (cl->c_cc) { 296 tp->t_state |= TS_BUSY; 297 ch = getc(cl); 298 DZ_WRITE_BYTE(dr_tbuf, ch); 299 DZ_BARRIER(); 300 continue; 301 } 302 /* Nothing to send; clear the scan bit */ 303 /* Clear xmit scanner bit; dzstart may set it again */ 304 tcr = DZ_READ_WORD(dr_tcrw); 305 tcr &= 255; 306 tcr &= ~(1 << line); 307 DZ_WRITE_BYTE(dr_tcr, tcr); 308 DZ_BARRIER(); 309 if (sc->sc_dz[line].dz_catch) 310 continue; 311 312 if (tp->t_state & TS_FLUSH) 313 tp->t_state &= ~TS_FLUSH; 314 else 315 ndflush (&tp->t_outq, cl->c_cc); 316 317 (*tp->t_linesw->l_start)(tp); 318 } 319 } 320 321 int 322 dzopen(dev_t dev, int flag, int mode, struct lwp *l) 323 { 324 struct proc *p = l->l_proc; 325 struct tty *tp; 326 int unit, line; 327 struct dz_softc *sc; 328 int s, error = 0; 329 330 unit = DZ_I2C(minor(dev)); 331 line = DZ_PORT(minor(dev)); 332 if (unit >= dz_cd.cd_ndevs || dz_cd.cd_devs[unit] == NULL) 333 return (ENXIO); 334 335 sc = dz_cd.cd_devs[unit]; 336 337 if (line >= sc->sc_type) 338 return ENXIO; 339 340 /* if some other device is using the line, it's busy */ 341 if (sc->sc_dz[line].dz_catch) 342 return EBUSY; 343 344 tp = sc->sc_dz[line].dz_tty; 345 if (tp == NULL) 346 return (ENODEV); 347 tp->t_oproc = dzstart; 348 tp->t_param = dzparam; 349 tp->t_dev = dev; 350 if ((tp->t_state & TS_ISOPEN) == 0) { 351 ttychars(tp); 352 if (tp->t_ispeed == 0) { 353 tp->t_iflag = TTYDEF_IFLAG; 354 tp->t_oflag = TTYDEF_OFLAG; 355 tp->t_cflag = TTYDEF_CFLAG; 356 tp->t_lflag = TTYDEF_LFLAG; 357 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 358 } 359 (void) dzparam(tp, &tp->t_termios); 360 ttsetwater(tp); 361 } else if ((tp->t_state & TS_XCLUDE) && 362 suser(p->p_ucred, &p->p_acflag) != 0) 363 return (EBUSY); 364 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 365 if (dzmctl(sc, line, DML_DTR, DMBIS) & DML_DCD) 366 tp->t_state |= TS_CARR_ON; 367 s = spltty(); 368 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 369 !(tp->t_state & TS_CARR_ON)) { 370 tp->t_wopen++; 371 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 372 TTIPRI | PCATCH, ttopen, 0); 373 tp->t_wopen--; 374 if (error) 375 break; 376 } 377 (void) splx(s); 378 if (error) 379 return (error); 380 return ((*tp->t_linesw->l_open)(dev, tp)); 381 } 382 383 /*ARGSUSED*/ 384 int 385 dzclose(dev_t dev, int flag, int mode, struct lwp *l) 386 { 387 struct dz_softc *sc; 388 struct tty *tp; 389 int unit, line; 390 391 392 unit = DZ_I2C(minor(dev)); 393 line = DZ_PORT(minor(dev)); 394 sc = dz_cd.cd_devs[unit]; 395 396 tp = sc->sc_dz[line].dz_tty; 397 398 (*tp->t_linesw->l_close)(tp, flag); 399 400 /* Make sure a BREAK state is not left enabled. */ 401 (void) dzmctl(sc, line, DML_BRK, DMBIC); 402 403 /* Do a hangup if so required. */ 404 if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN)) 405 (void) dzmctl(sc, line, 0, DMSET); 406 407 return (ttyclose(tp)); 408 } 409 410 int 411 dzread(dev_t dev, struct uio *uio, int flag) 412 { 413 struct tty *tp; 414 struct dz_softc *sc; 415 416 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 417 418 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 419 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 420 } 421 422 int 423 dzwrite(dev_t dev, struct uio *uio, int flag) 424 { 425 struct tty *tp; 426 struct dz_softc *sc; 427 428 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 429 430 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 431 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 432 } 433 434 int 435 dzpoll(dev, events, l) 436 dev_t dev; 437 int events; 438 struct lwp *l; 439 { 440 struct tty *tp; 441 struct dz_softc *sc; 442 443 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 444 445 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 446 return ((*tp->t_linesw->l_poll)(tp, events, l)); 447 } 448 449 /*ARGSUSED*/ 450 int 451 dzioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 452 { 453 struct dz_softc *sc; 454 struct tty *tp; 455 int unit, line; 456 int error; 457 458 unit = DZ_I2C(minor(dev)); 459 line = DZ_PORT(minor(dev)); 460 sc = dz_cd.cd_devs[unit]; 461 tp = sc->sc_dz[line].dz_tty; 462 463 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 464 if (error >= 0) 465 return (error); 466 467 error = ttioctl(tp, cmd, data, flag, l); 468 if (error >= 0) 469 return (error); 470 471 switch (cmd) { 472 473 case TIOCSBRK: 474 (void) dzmctl(sc, line, DML_BRK, DMBIS); 475 break; 476 477 case TIOCCBRK: 478 (void) dzmctl(sc, line, DML_BRK, DMBIC); 479 break; 480 481 case TIOCSDTR: 482 (void) dzmctl(sc, line, DML_DTR, DMBIS); 483 break; 484 485 case TIOCCDTR: 486 (void) dzmctl(sc, line, DML_DTR, DMBIC); 487 break; 488 489 case TIOCMSET: 490 (void) dzmctl(sc, line, *(int *)data, DMSET); 491 break; 492 493 case TIOCMBIS: 494 (void) dzmctl(sc, line, *(int *)data, DMBIS); 495 break; 496 497 case TIOCMBIC: 498 (void) dzmctl(sc, line, *(int *)data, DMBIC); 499 break; 500 501 case TIOCMGET: 502 *(int *)data = (dzmctl(sc, line, 0, DMGET) & ~DML_BRK); 503 break; 504 505 default: 506 return (EPASSTHROUGH); 507 } 508 return (0); 509 } 510 511 struct tty * 512 dztty(dev_t dev) 513 { 514 struct dz_softc *sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 515 struct tty *tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 516 517 return (tp); 518 } 519 520 /*ARGSUSED*/ 521 void 522 dzstop(struct tty *tp, int flag) 523 { 524 if (tp->t_state & TS_BUSY) 525 if (!(tp->t_state & TS_TTSTOP)) 526 tp->t_state |= TS_FLUSH; 527 } 528 529 void 530 dzstart(struct tty *tp) 531 { 532 struct dz_softc *sc; 533 struct clist *cl; 534 int unit, line, s; 535 char state; 536 537 unit = DZ_I2C(minor(tp->t_dev)); 538 line = DZ_PORT(minor(tp->t_dev)); 539 sc = dz_cd.cd_devs[unit]; 540 541 s = spltty(); 542 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) { 543 splx(s); 544 return; 545 } 546 cl = &tp->t_outq; 547 if (cl->c_cc <= tp->t_lowat) { 548 if (tp->t_state & TS_ASLEEP) { 549 tp->t_state &= ~TS_ASLEEP; 550 wakeup((caddr_t)cl); 551 } 552 selwakeup(&tp->t_wsel); 553 } 554 if (cl->c_cc == 0) { 555 splx(s); 556 return; 557 } 558 559 tp->t_state |= TS_BUSY; 560 561 state = DZ_READ_WORD(dr_tcrw) & 255; 562 if ((state & (1 << line)) == 0) { 563 DZ_WRITE_BYTE(dr_tcr, state | (1 << line)); 564 DZ_BARRIER(); 565 } 566 dzxint(sc); 567 splx(s); 568 } 569 570 static int 571 dzparam(struct tty *tp, struct termios *t) 572 { 573 struct dz_softc *sc; 574 int cflag = t->c_cflag; 575 int unit, line; 576 int ispeed = ttspeedtab(t->c_ispeed, dzspeedtab); 577 int ospeed = ttspeedtab(t->c_ospeed, dzspeedtab); 578 unsigned lpr; 579 int s; 580 581 unit = DZ_I2C(minor(tp->t_dev)); 582 line = DZ_PORT(minor(tp->t_dev)); 583 sc = dz_cd.cd_devs[unit]; 584 585 /* check requested parameters */ 586 if (ospeed < 0 || ispeed < 0 || ispeed != ospeed) 587 return (EINVAL); 588 589 tp->t_ispeed = t->c_ispeed; 590 tp->t_ospeed = t->c_ospeed; 591 tp->t_cflag = cflag; 592 593 if (ospeed == 0) { 594 (void) dzmctl(sc, line, 0, DMSET); /* hang up line */ 595 return (0); 596 } 597 598 s = spltty(); 599 600 lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line; 601 602 switch (cflag & CSIZE) 603 { 604 case CS5: 605 lpr |= DZ_LPR_5_BIT_CHAR; 606 break; 607 case CS6: 608 lpr |= DZ_LPR_6_BIT_CHAR; 609 break; 610 case CS7: 611 lpr |= DZ_LPR_7_BIT_CHAR; 612 break; 613 default: 614 lpr |= DZ_LPR_8_BIT_CHAR; 615 break; 616 } 617 if (cflag & PARENB) 618 lpr |= DZ_LPR_PARENB; 619 if (cflag & PARODD) 620 lpr |= DZ_LPR_OPAR; 621 if (cflag & CSTOPB) 622 lpr |= DZ_LPR_2_STOP; 623 624 DZ_WRITE_WORD(dr_lpr, lpr); 625 DZ_BARRIER(); 626 627 (void) splx(s); 628 return (0); 629 } 630 631 static unsigned 632 dzmctl(struct dz_softc *sc, int line, int bits, int how) 633 { 634 unsigned status; 635 unsigned mbits; 636 unsigned bit; 637 int s; 638 639 s = spltty(); 640 641 mbits = 0; 642 643 bit = (1 << line); 644 645 /* external signals as seen from the port */ 646 647 status = DZ_READ_BYTE(dr_dcd) | sc->sc_dsr; 648 649 if (status & bit) 650 mbits |= DML_DCD; 651 652 status = DZ_READ_BYTE(dr_ring); 653 654 if (status & bit) 655 mbits |= DML_RI; 656 657 /* internal signals/state delivered to port */ 658 659 status = DZ_READ_BYTE(dr_dtr); 660 661 if (status & bit) 662 mbits |= DML_DTR; 663 664 if (sc->sc_brk & bit) 665 mbits |= DML_BRK; 666 667 switch (how) 668 { 669 case DMSET: 670 mbits = bits; 671 break; 672 673 case DMBIS: 674 mbits |= bits; 675 break; 676 677 case DMBIC: 678 mbits &= ~bits; 679 break; 680 681 case DMGET: 682 (void) splx(s); 683 return (mbits); 684 } 685 686 if (mbits & DML_DTR) { 687 DZ_WRITE_BYTE(dr_dtr, DZ_READ_BYTE(dr_dtr) | bit); 688 } else { 689 DZ_WRITE_BYTE(dr_dtr, DZ_READ_BYTE(dr_dtr) & ~bit); 690 } 691 692 if (mbits & DML_BRK) { 693 sc->sc_brk |= bit; 694 DZ_WRITE_BYTE(dr_break, sc->sc_brk); 695 } else { 696 sc->sc_brk &= ~bit; 697 DZ_WRITE_BYTE(dr_break, sc->sc_brk); 698 } 699 700 DZ_BARRIER(); 701 (void) splx(s); 702 return (mbits); 703 } 704 705 /* 706 * This is called by timeout() periodically. 707 * Check to see if modem status bits have changed. 708 */ 709 static void 710 dzscan(void *arg) 711 { 712 struct dz_softc *sc; 713 struct tty *tp; 714 int n, bit, port; 715 unsigned csr; 716 int s; 717 718 s = spltty(); 719 720 for (n = 0; n < dz_cd.cd_ndevs; n++) { 721 722 if (dz_cd.cd_devs[n] == NULL) 723 continue; 724 725 sc = dz_cd.cd_devs[n]; 726 727 for (port = 0; port < sc->sc_type; port++) { 728 729 tp = sc->sc_dz[port].dz_tty; 730 bit = (1 << port); 731 732 if ((DZ_READ_BYTE(dr_dcd) | sc->sc_dsr) & bit) { 733 if (!(tp->t_state & TS_CARR_ON)) 734 (*tp->t_linesw->l_modem) (tp, 1); 735 } else if ((tp->t_state & TS_CARR_ON) && 736 (*tp->t_linesw->l_modem)(tp, 0) == 0) { 737 DZ_WRITE_BYTE(dr_tcr, 738 (DZ_READ_WORD(dr_tcrw) & 255) & ~bit); 739 DZ_BARRIER(); 740 } 741 } 742 743 /* 744 * If the RX interrupt rate is this high, switch 745 * the controller to Silo Alarm - which means don't 746 * interrupt until the RX silo has 16 characters in 747 * it (the silo is 64 characters in all). 748 * Avoid oscillating SA on and off by not turning 749 * if off unless the rate is appropriately low. 750 */ 751 752 csr = DZ_READ_WORD(dr_csr); 753 754 if (sc->sc_rxint > (16*10)) { 755 if ((csr & DZ_CSR_SAE) == 0) 756 DZ_WRITE_WORD(dr_csr, csr | DZ_CSR_SAE); 757 } else if ((csr & DZ_CSR_SAE) != 0) 758 if (sc->sc_rxint < 10) 759 DZ_WRITE_WORD(dr_csr, csr & ~(DZ_CSR_SAE)); 760 761 DZ_BARRIER(); 762 sc->sc_rxint = 0; 763 } 764 (void) splx(s); 765 callout_reset(&dzscan_ch, hz, dzscan, NULL); 766 } 767 768 /* 769 * Called after an ubareset. The DZ card is reset, but the only thing 770 * that must be done is to start the receiver and transmitter again. 771 * No DMA setup to care about. 772 */ 773 void 774 dzreset(struct device *dev) 775 { 776 struct dz_softc *sc = (void *)dev; 777 struct tty *tp; 778 int i; 779 780 for (i = 0; i < sc->sc_type; i++) { 781 tp = sc->sc_dz[i].dz_tty; 782 783 if (((tp->t_state & TS_ISOPEN) == 0) || (tp->t_wopen == 0)) 784 continue; 785 786 dzparam(tp, &tp->t_termios); 787 dzmctl(sc, i, DML_DTR, DMSET); 788 tp->t_state &= ~TS_BUSY; 789 dzstart(tp); /* Kick off transmitter again */ 790 } 791 } 792