1 /* $NetBSD: dz.c,v 1.31 2007/11/07 15:56:14 ad Exp $ */ 2 /* 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Ralph Campbell and Rick Macklem. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * Ralph Campbell and Rick Macklem. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Berkeley and its contributors. 52 * 4. Neither the name of the University nor the names of its contributors 53 * may be used to endorse or promote products derived from this software 54 * without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 57 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 59 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 62 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 63 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 64 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 66 * SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.31 2007/11/07 15:56:14 ad Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/ioctl.h> 76 #include <sys/tty.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/conf.h> 80 #include <sys/file.h> 81 #include <sys/uio.h> 82 #include <sys/kernel.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 #include <sys/kauth.h> 86 87 #include <sys/bus.h> 88 89 #include <dev/dec/dzreg.h> 90 #include <dev/dec/dzvar.h> 91 92 #include <dev/cons.h> 93 94 #ifdef __mips__ 95 #define DZ_DELAY(x) DELAY(x) 96 #define control __attribute ((noinline)) 97 #else /* presumably vax */ 98 #define DZ_DELAY(x) /* nothing */ 99 #define control inline 100 #endif 101 102 static control uint 103 dz_read1(struct dz_softc *sc, u_int off) 104 { 105 u_int rv; 106 107 rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 108 DZ_DELAY(1); 109 return rv; 110 } 111 112 static control u_int 113 dz_read2(struct dz_softc *sc, u_int off) 114 { 115 u_int rv; 116 117 rv = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 118 DZ_DELAY(1); 119 return rv; 120 } 121 122 static control void 123 dz_write1(struct dz_softc *sc, u_int off, u_int val) 124 { 125 126 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val); 127 bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg, 128 sc->sc_dr.dr_winsize, BUS_SPACE_BARRIER_WRITE | 129 BUS_SPACE_BARRIER_READ); 130 DZ_DELAY(10); 131 } 132 133 static control void 134 dz_write2(struct dz_softc *sc, u_int off, u_int val) 135 { 136 137 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val); 138 bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_dr.dr_firstreg, 139 sc->sc_dr.dr_winsize, BUS_SPACE_BARRIER_WRITE | 140 BUS_SPACE_BARRIER_READ); 141 DZ_DELAY(10); 142 } 143 144 #include "ioconf.h" 145 146 /* Flags used to monitor modem bits, make them understood outside driver */ 147 148 #define DML_DTR TIOCM_DTR 149 #define DML_DCD TIOCM_CD 150 #define DML_RI TIOCM_RI 151 #define DML_BRK 0100000 /* no equivalent, we will mask */ 152 153 static const struct speedtab dzspeedtab[] = 154 { 155 { 0, 0 }, 156 { 50, DZ_LPR_B50 }, 157 { 75, DZ_LPR_B75 }, 158 { 110, DZ_LPR_B110 }, 159 { 134, DZ_LPR_B134 }, 160 { 150, DZ_LPR_B150 }, 161 { 300, DZ_LPR_B300 }, 162 { 600, DZ_LPR_B600 }, 163 { 1200, DZ_LPR_B1200 }, 164 { 1800, DZ_LPR_B1800 }, 165 { 2000, DZ_LPR_B2000 }, 166 { 2400, DZ_LPR_B2400 }, 167 { 3600, DZ_LPR_B3600 }, 168 { 4800, DZ_LPR_B4800 }, 169 { 7200, DZ_LPR_B7200 }, 170 { 9600, DZ_LPR_B9600 }, 171 { 19200, DZ_LPR_B19200 }, 172 { -1, -1 } 173 }; 174 175 static void dzstart(struct tty *); 176 static int dzparam(struct tty *, struct termios *); 177 static unsigned dzmctl(struct dz_softc *, int, int, int); 178 static void dzscan(void *); 179 180 dev_type_open(dzopen); 181 dev_type_close(dzclose); 182 dev_type_read(dzread); 183 dev_type_write(dzwrite); 184 dev_type_ioctl(dzioctl); 185 dev_type_stop(dzstop); 186 dev_type_tty(dztty); 187 dev_type_poll(dzpoll); 188 189 const struct cdevsw dz_cdevsw = { 190 dzopen, dzclose, dzread, dzwrite, dzioctl, 191 dzstop, dztty, dzpoll, nommap, ttykqfilter, D_TTY 192 }; 193 194 /* 195 * The DZ series doesn't interrupt on carrier transitions, 196 * so we have to use a timer to watch it. 197 */ 198 int dz_timer; /* true if timer started */ 199 struct callout dzscan_ch; 200 static struct cnm_state dz_cnm_state; 201 202 void 203 dzattach(struct dz_softc *sc, struct evcnt *parent_evcnt, int consline) 204 { 205 int n; 206 207 sc->sc_rxint = sc->sc_brk = 0; 208 sc->sc_consline = consline; 209 210 sc->sc_dr.dr_tcrw = sc->sc_dr.dr_tcr; 211 dz_write2(sc, sc->sc_dr.dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE); 212 dz_write1(sc, sc->sc_dr.dr_dtr, 0); 213 dz_write1(sc, sc->sc_dr.dr_break, 0); 214 DELAY(10000); 215 216 /* Initialize our softc structure. Should be done in open? */ 217 218 for (n = 0; n < sc->sc_type; n++) { 219 sc->sc_dz[n].dz_sc = sc; 220 sc->sc_dz[n].dz_line = n; 221 sc->sc_dz[n].dz_tty = ttymalloc(); 222 } 223 224 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 225 sc->sc_dev.dv_xname, "rintr"); 226 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 227 sc->sc_dev.dv_xname, "tintr"); 228 229 /* Console magic keys */ 230 cn_init_magic(&dz_cnm_state); 231 cn_set_magic("\047\001"); /* default magic is BREAK */ 232 /* VAX will change it in MD code */ 233 234 /* Alas no interrupt on modem bit changes, so we manually scan */ 235 if (dz_timer == 0) { 236 dz_timer = 1; 237 callout_init(&dzscan_ch, 0); 238 callout_reset(&dzscan_ch, hz, dzscan, NULL); 239 } 240 printf("\n"); 241 } 242 243 /* Receiver Interrupt */ 244 245 void 246 dzrint(void *arg) 247 { 248 struct dz_softc *sc = arg; 249 struct tty *tp; 250 int cc, mcc, line; 251 unsigned c; 252 int overrun = 0; 253 254 sc->sc_rxint++; 255 256 while ((c = dz_read2(sc, sc->sc_dr.dr_rbuf)) & DZ_RBUF_DATA_VALID) { 257 cc = c & 0xFF; 258 line = DZ_PORT(c>>8); 259 tp = sc->sc_dz[line].dz_tty; 260 261 /* Must be caught early */ 262 if (sc->sc_dz[line].dz_catch && 263 (*sc->sc_dz[line].dz_catch)(sc->sc_dz[line].dz_private, cc)) 264 continue; 265 266 if ((c & (DZ_RBUF_FRAMING_ERR | 0xff)) == DZ_RBUF_FRAMING_ERR) 267 mcc = CNC_BREAK; 268 else 269 mcc = cc; 270 271 cn_check_magic(tp->t_dev, mcc, dz_cnm_state); 272 273 if (!(tp->t_state & TS_ISOPEN)) { 274 wakeup((void *)&tp->t_rawq); 275 continue; 276 } 277 278 if ((c & DZ_RBUF_OVERRUN_ERR) && overrun == 0) { 279 log(LOG_WARNING, "%s: silo overflow, line %d\n", 280 sc->sc_dev.dv_xname, line); 281 overrun = 1; 282 } 283 284 if (c & DZ_RBUF_FRAMING_ERR) 285 cc |= TTY_FE; 286 if (c & DZ_RBUF_PARITY_ERR) 287 cc |= TTY_PE; 288 289 (*tp->t_linesw->l_rint)(cc, tp); 290 } 291 } 292 293 /* Transmitter Interrupt */ 294 295 void 296 dzxint(void *arg) 297 { 298 struct dz_softc *sc = arg; 299 struct tty *tp; 300 struct clist *cl; 301 int line, ch, csr; 302 u_char tcr; 303 304 /* 305 * Switch to POLLED mode. 306 * Some simple measurements indicated that even on 307 * one port, by freeing the scanner in the controller 308 * by either providing a character or turning off 309 * the port when output is complete, the transmitter 310 * was ready to accept more output when polled again. 311 * With just two ports running the game "worms," 312 * almost every interrupt serviced both transmitters! 313 * Each UART is double buffered, so if the scanner 314 * is quick enough and timing works out, we can even 315 * feed the same port twice. 316 * 317 * Ragge 980517: 318 * Do not need to turn off interrupts, already at interrupt level. 319 * Remove the pdma stuff; no great need of it right now. 320 */ 321 322 for (;;) { 323 csr = dz_read2(sc, sc->sc_dr.dr_csr); 324 if ((csr & DZ_CSR_TX_READY) == 0) 325 break; 326 327 line = DZ_PORT(csr >> 8); 328 tp = sc->sc_dz[line].dz_tty; 329 cl = &tp->t_outq; 330 tp->t_state &= ~TS_BUSY; 331 332 /* Just send out a char if we have one */ 333 /* As long as we can fill the chip buffer, we just loop here */ 334 if (cl->c_cc) { 335 tp->t_state |= TS_BUSY; 336 ch = getc(cl); 337 dz_write1(sc, sc->sc_dr.dr_tbuf, ch); 338 continue; 339 } 340 341 /* Nothing to send; clear the scan bit */ 342 /* Clear xmit scanner bit; dzstart may set it again */ 343 tcr = dz_read2(sc, sc->sc_dr.dr_tcrw); 344 tcr &= 255; 345 tcr &= ~(1 << line); 346 dz_write1(sc, sc->sc_dr.dr_tcr, tcr); 347 if (sc->sc_dz[line].dz_catch) 348 continue; 349 350 if (tp->t_state & TS_FLUSH) 351 tp->t_state &= ~TS_FLUSH; 352 else 353 ndflush (&tp->t_outq, cl->c_cc); 354 355 (*tp->t_linesw->l_start)(tp); 356 } 357 } 358 359 int 360 dzopen(dev_t dev, int flag, int mode, struct lwp *l) 361 { 362 struct tty *tp; 363 int unit, line; 364 struct dz_softc *sc; 365 int error = 0; 366 367 unit = DZ_I2C(minor(dev)); 368 line = DZ_PORT(minor(dev)); 369 if (unit >= dz_cd.cd_ndevs || dz_cd.cd_devs[unit] == NULL) 370 return (ENXIO); 371 372 sc = dz_cd.cd_devs[unit]; 373 374 if (line >= sc->sc_type) 375 return ENXIO; 376 377 /* if some other device is using the line, it's busy */ 378 if (sc->sc_dz[line].dz_catch) 379 return EBUSY; 380 381 tp = sc->sc_dz[line].dz_tty; 382 if (tp == NULL) 383 return (ENODEV); 384 tp->t_oproc = dzstart; 385 tp->t_param = dzparam; 386 tp->t_dev = dev; 387 388 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 389 return (EBUSY); 390 391 if ((tp->t_state & TS_ISOPEN) == 0) { 392 ttychars(tp); 393 if (tp->t_ispeed == 0) { 394 tp->t_iflag = TTYDEF_IFLAG; 395 tp->t_oflag = TTYDEF_OFLAG; 396 tp->t_cflag = TTYDEF_CFLAG; 397 tp->t_lflag = TTYDEF_LFLAG; 398 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 399 } 400 (void) dzparam(tp, &tp->t_termios); 401 ttsetwater(tp); 402 } 403 404 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 405 if (dzmctl(sc, line, DML_DTR, DMBIS) & DML_DCD) 406 tp->t_state |= TS_CARR_ON; 407 mutex_spin_enter(&tty_lock); 408 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 409 !(tp->t_state & TS_CARR_ON)) { 410 tp->t_wopen++; 411 error = ttysleep(tp, &tp->t_rawq.c_cv, true, 0); 412 tp->t_wopen--; 413 if (error) 414 break; 415 } 416 mutex_spin_exit(&tty_lock); 417 if (error) 418 return (error); 419 return ((*tp->t_linesw->l_open)(dev, tp)); 420 } 421 422 /*ARGSUSED*/ 423 int 424 dzclose(dev_t dev, int flag, int mode, struct lwp *l) 425 { 426 struct dz_softc *sc; 427 struct tty *tp; 428 int unit, line; 429 430 431 unit = DZ_I2C(minor(dev)); 432 line = DZ_PORT(minor(dev)); 433 sc = dz_cd.cd_devs[unit]; 434 435 tp = sc->sc_dz[line].dz_tty; 436 437 (*tp->t_linesw->l_close)(tp, flag); 438 439 /* Make sure a BREAK state is not left enabled. */ 440 (void) dzmctl(sc, line, DML_BRK, DMBIC); 441 442 /* Do a hangup if so required. */ 443 if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN)) 444 (void) dzmctl(sc, line, 0, DMSET); 445 446 return (ttyclose(tp)); 447 } 448 449 int 450 dzread(dev_t dev, struct uio *uio, int flag) 451 { 452 struct tty *tp; 453 struct dz_softc *sc; 454 455 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 456 457 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 458 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 459 } 460 461 int 462 dzwrite(dev_t dev, struct uio *uio, int flag) 463 { 464 struct tty *tp; 465 struct dz_softc *sc; 466 467 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 468 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 469 470 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 471 } 472 473 int 474 dzpoll(dev, events, l) 475 dev_t dev; 476 int events; 477 struct lwp *l; 478 { 479 struct tty *tp; 480 struct dz_softc *sc; 481 482 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 483 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 484 485 return ((*tp->t_linesw->l_poll)(tp, events, l)); 486 } 487 488 /*ARGSUSED*/ 489 int 490 dzioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 491 { 492 struct dz_softc *sc; 493 struct tty *tp; 494 int unit, line; 495 int error; 496 497 unit = DZ_I2C(minor(dev)); 498 line = DZ_PORT(minor(dev)); 499 sc = dz_cd.cd_devs[unit]; 500 tp = sc->sc_dz[line].dz_tty; 501 502 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 503 if (error >= 0) 504 return (error); 505 506 error = ttioctl(tp, cmd, data, flag, l); 507 if (error >= 0) 508 return (error); 509 510 switch (cmd) { 511 case TIOCSBRK: 512 (void) dzmctl(sc, line, DML_BRK, DMBIS); 513 break; 514 515 case TIOCCBRK: 516 (void) dzmctl(sc, line, DML_BRK, DMBIC); 517 break; 518 519 case TIOCSDTR: 520 (void) dzmctl(sc, line, DML_DTR, DMBIS); 521 break; 522 523 case TIOCCDTR: 524 (void) dzmctl(sc, line, DML_DTR, DMBIC); 525 break; 526 527 case TIOCMSET: 528 (void) dzmctl(sc, line, *(int *)data, DMSET); 529 break; 530 531 case TIOCMBIS: 532 (void) dzmctl(sc, line, *(int *)data, DMBIS); 533 break; 534 535 case TIOCMBIC: 536 (void) dzmctl(sc, line, *(int *)data, DMBIC); 537 break; 538 539 case TIOCMGET: 540 *(int *)data = (dzmctl(sc, line, 0, DMGET) & ~DML_BRK); 541 break; 542 543 default: 544 return (EPASSTHROUGH); 545 } 546 return (0); 547 } 548 549 struct tty * 550 dztty(dev_t dev) 551 { 552 struct dz_softc *sc; 553 struct tty *tp; 554 555 sc = dz_cd.cd_devs[DZ_I2C(minor(dev))]; 556 tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty; 557 558 return (tp); 559 } 560 561 /*ARGSUSED*/ 562 void 563 dzstop(struct tty *tp, int flag) 564 { 565 566 if ((tp->t_state & (TS_BUSY | TS_TTSTOP)) == TS_BUSY) 567 tp->t_state |= TS_FLUSH; 568 } 569 570 void 571 dzstart(struct tty *tp) 572 { 573 struct dz_softc *sc; 574 struct clist *cl; 575 int unit, line, s; 576 char state; 577 578 unit = DZ_I2C(minor(tp->t_dev)); 579 line = DZ_PORT(minor(tp->t_dev)); 580 sc = dz_cd.cd_devs[unit]; 581 582 s = spltty(); 583 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) { 584 splx(s); 585 return; 586 } 587 cl = &tp->t_outq; 588 if (cl->c_cc <= tp->t_lowat) { 589 if (tp->t_state & TS_ASLEEP) { 590 tp->t_state &= ~TS_ASLEEP; 591 wakeup((void *)cl); 592 } 593 selwakeup(&tp->t_wsel); 594 } 595 if (cl->c_cc == 0) { 596 splx(s); 597 return; 598 } 599 600 tp->t_state |= TS_BUSY; 601 602 state = dz_read2(sc, sc->sc_dr.dr_tcrw) & 255; 603 if ((state & (1 << line)) == 0) 604 dz_write1(sc, sc->sc_dr.dr_tcr, state | (1 << line)); 605 dzxint(sc); 606 splx(s); 607 } 608 609 static int 610 dzparam(struct tty *tp, struct termios *t) 611 { 612 struct dz_softc *sc; 613 int cflag = t->c_cflag; 614 int unit, line; 615 int ispeed = ttspeedtab(t->c_ispeed, dzspeedtab); 616 int ospeed = ttspeedtab(t->c_ospeed, dzspeedtab); 617 unsigned lpr; 618 int s; 619 620 unit = DZ_I2C(minor(tp->t_dev)); 621 line = DZ_PORT(minor(tp->t_dev)); 622 sc = dz_cd.cd_devs[unit]; 623 624 /* check requested parameters */ 625 if (ospeed < 0 || ispeed < 0 || ispeed != ospeed) 626 return (EINVAL); 627 628 tp->t_ispeed = t->c_ispeed; 629 tp->t_ospeed = t->c_ospeed; 630 tp->t_cflag = cflag; 631 632 if (ospeed == 0) { 633 (void) dzmctl(sc, line, 0, DMSET); /* hang up line */ 634 return (0); 635 } 636 637 s = spltty(); 638 639 /* XXX This is wrong. Flush output or the chip gets very confused. */ 640 ttywait(tp); 641 642 lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line; 643 644 switch (cflag & CSIZE) 645 { 646 case CS5: 647 lpr |= DZ_LPR_5_BIT_CHAR; 648 break; 649 case CS6: 650 lpr |= DZ_LPR_6_BIT_CHAR; 651 break; 652 case CS7: 653 lpr |= DZ_LPR_7_BIT_CHAR; 654 break; 655 default: 656 lpr |= DZ_LPR_8_BIT_CHAR; 657 break; 658 } 659 if (cflag & PARENB) 660 lpr |= DZ_LPR_PARENB; 661 if (cflag & PARODD) 662 lpr |= DZ_LPR_OPAR; 663 if (cflag & CSTOPB) 664 lpr |= DZ_LPR_2_STOP; 665 666 dz_write2(sc, sc->sc_dr.dr_lpr, lpr); 667 (void) splx(s); 668 DELAY(10000); 669 670 return (0); 671 } 672 673 static unsigned 674 dzmctl(struct dz_softc *sc, int line, int bits, int how) 675 { 676 unsigned status; 677 unsigned mbits; 678 unsigned bit; 679 int s; 680 681 s = spltty(); 682 mbits = 0; 683 bit = (1 << line); 684 685 /* external signals as seen from the port */ 686 status = dz_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr; 687 if (status & bit) 688 mbits |= DML_DCD; 689 status = dz_read1(sc, sc->sc_dr.dr_ring); 690 if (status & bit) 691 mbits |= DML_RI; 692 693 /* internal signals/state delivered to port */ 694 status = dz_read1(sc, sc->sc_dr.dr_dtr); 695 if (status & bit) 696 mbits |= DML_DTR; 697 if (sc->sc_brk & bit) 698 mbits |= DML_BRK; 699 700 switch (how) 701 { 702 case DMSET: 703 mbits = bits; 704 break; 705 706 case DMBIS: 707 mbits |= bits; 708 break; 709 710 case DMBIC: 711 mbits &= ~bits; 712 break; 713 714 case DMGET: 715 (void) splx(s); 716 return (mbits); 717 } 718 719 if (mbits & DML_DTR) { 720 dz_write1(sc, sc->sc_dr.dr_dtr, dz_read1(sc, sc->sc_dr.dr_dtr) | bit); 721 } else { 722 dz_write1(sc, sc->sc_dr.dr_dtr, dz_read1(sc, sc->sc_dr.dr_dtr) & ~bit); 723 } 724 725 if (mbits & DML_BRK) { 726 sc->sc_brk |= bit; 727 dz_write1(sc, sc->sc_dr.dr_break, sc->sc_brk); 728 } else { 729 sc->sc_brk &= ~bit; 730 dz_write1(sc, sc->sc_dr.dr_break, sc->sc_brk); 731 } 732 733 (void) splx(s); 734 735 return (mbits); 736 } 737 738 /* 739 * This is called by timeout() periodically. 740 * Check to see if modem status bits have changed. 741 */ 742 static void 743 dzscan(void *arg) 744 { 745 struct dz_softc *sc; 746 struct tty *tp; 747 int n, bit, port; 748 unsigned csr, tmp; 749 int s; 750 751 s = spltty(); 752 for (n = 0; n < dz_cd.cd_ndevs; n++) { 753 if ((sc = dz_cd.cd_devs[n]) == NULL) 754 continue; 755 756 for (port = 0; port < sc->sc_type; port++) { 757 tp = sc->sc_dz[port].dz_tty; 758 bit = (1 << port); 759 760 if ((dz_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr) & bit) { 761 if (!(tp->t_state & TS_CARR_ON)) 762 (*tp->t_linesw->l_modem) (tp, 1); 763 } else if ((tp->t_state & TS_CARR_ON) && 764 (*tp->t_linesw->l_modem)(tp, 0) == 0) { 765 tmp = dz_read2(sc, sc->sc_dr.dr_tcrw) & 255; 766 dz_write1(sc, sc->sc_dr.dr_tcr, tmp & ~bit); 767 } 768 } 769 770 /* 771 * If the RX interrupt rate is this high, switch 772 * the controller to Silo Alarm - which means don't 773 * interrupt until the RX silo has 16 characters in 774 * it (the silo is 64 characters in all). 775 * Avoid oscillating SA on and off by not turning 776 * if off unless the rate is appropriately low. 777 */ 778 csr = dz_read2(sc, sc->sc_dr.dr_csr); 779 tmp = csr; 780 if (sc->sc_rxint > 16*10) 781 csr |= DZ_CSR_SAE; 782 else if (sc->sc_rxint < 10) 783 csr &= ~DZ_CSR_SAE; 784 if (csr != tmp) 785 dz_write2(sc, sc->sc_dr.dr_csr, csr); 786 sc->sc_rxint = 0; 787 788 dzxint(sc); 789 dzrint(sc); 790 } 791 (void) splx(s); 792 callout_reset(&dzscan_ch, hz, dzscan, NULL); 793 } 794 795 /* 796 * Called after an ubareset. The DZ card is reset, but the only thing 797 * that must be done is to start the receiver and transmitter again. 798 * No DMA setup to care about. 799 */ 800 void 801 dzreset(struct device *dev) 802 { 803 struct dz_softc *sc = (void *)dev; 804 struct tty *tp; 805 int i; 806 807 for (i = 0; i < sc->sc_type; i++) { 808 tp = sc->sc_dz[i].dz_tty; 809 810 if (((tp->t_state & TS_ISOPEN) == 0) || (tp->t_wopen == 0)) 811 continue; 812 813 dzparam(tp, &tp->t_termios); 814 dzmctl(sc, i, DML_DTR, DMSET); 815 tp->t_state &= ~TS_BUSY; 816 dzstart(tp); /* Kick off transmitter again */ 817 } 818 } 819