1 /* $NetBSD: rbus_ppb.c,v 1.41 2011/08/01 11:20:28 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr@sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.41 2011/08/01 11:20:28 drochner Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/kmem.h> 49 50 #if NRND > 0 51 #include <sys/rnd.h> 52 #endif 53 54 #include <machine/endian.h> 55 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 #include <dev/pci/ppbreg.h> 63 64 #include <dev/ic/i82365reg.h> 65 66 #include <dev/cardbus/rbus.h> 67 #include <dev/pci/pccbbreg.h> 68 #include <dev/pci/pccbbvar.h> 69 70 #include <dev/cardbus/cardbusvar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <x86/pci/pci_addr_fixup.h> 74 #include <x86/pci/pci_bus_fixup.h> 75 #include <i386/pci/pci_intr_fixup.h> 76 #include <i386/pci/pcibios.h> 77 78 struct ppb_softc; 79 80 static int ppb_cardbus_match(device_t, cfdata_t, void *); 81 static void ppb_cardbus_attach(device_t, device_t, void *); 82 static int ppb_activate(device_t, enum devact); 83 int rppbprint(void *, const char *); 84 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int); 85 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *); 86 87 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *); 88 89 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int, 90 void *, int, bus_addr_t *, bus_size_t); 91 92 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *); 93 94 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int, 95 void *, int, bus_addr_t *, bus_size_t); 96 97 unsigned int rbus_round_up(unsigned int, unsigned int); 98 99 100 struct ppb_cardbus_softc { 101 device_t sc_dev; 102 pcitag_t sc_tag; 103 int foo; 104 }; 105 106 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc), 107 ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate); 108 109 #ifdef CBB_DEBUG 110 int rbus_ppb_debug = 0; /* hack with kdb */ 111 #define DPRINTF(X) if(rbus_ppb_debug) printf X 112 #else 113 #define DPRINTF(X) 114 #endif 115 116 static int 117 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct cardbus_attach_args *ca = aux; 120 121 if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 122 PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 123 return (1); 124 125 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 126 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 127 /* XXX */ 128 printf("recognizing generic bridge chip\n"); 129 } 130 131 return (0); 132 } 133 134 135 int 136 rppbprint(void *aux, const char *pnp) 137 { 138 struct pcibus_attach_args *pba = aux; 139 140 /* only PCIs can attach to PPBs; easy. */ 141 if (pnp) 142 aprint_normal("pci at %s", pnp); 143 aprint_normal(" bus %d (rbus)", pba->pba_bus); 144 return (UNCONF); 145 } 146 147 int 148 rbus_intr_fixup(pci_chipset_tag_t pc, 149 int minbus, 150 int maxbus, 151 int line) 152 { 153 pci_device_foreach_min(pc, minbus, 154 maxbus, rbus_do_header_fixup, (void *)&line); 155 return 0; 156 } 157 158 void 159 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context) 160 { 161 int pin, irq; 162 int bus, device, function; 163 pcireg_t intr, id; 164 int *pline = (int *)context; 165 int line = *pline; 166 167 pci_decompose_tag(pc, tag, &bus, &device, &function); 168 id = pci_conf_read(pc, tag, PCI_ID_REG); 169 170 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 171 pin = PCI_INTERRUPT_PIN(intr); 172 irq = PCI_INTERRUPT_LINE(intr); 173 174 #if 0 175 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 176 bus, device, function, pin, line); 177 #endif 178 179 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 180 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 181 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 182 183 } 184 185 /* 186 * This function takes a range of PCI bus numbers and 187 * allocates space for all devices found in this space (the BARs) from 188 * the rbus space maps (I/O and memory). 189 * 190 * It assumes that "rbus" is defined. The whole concept does. 191 * 192 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 193 * This function is mostly stolen from 194 * pci_addr_fixup.c:pciaddr_resource_reserve. 195 * 196 */ 197 struct rbus_pci_addr_fixup_context { 198 struct ppb_cardbus_softc *csc; 199 cardbus_chipset_tag_t ct; 200 struct cardbus_softc *sc; 201 struct cardbus_attach_args *caa; 202 int minbus; 203 int maxbus; 204 bus_size_t *bussize_ioreqs; 205 bus_size_t *bussize_memreqs; 206 rbus_tag_t *iobustags; 207 rbus_tag_t *membustags; 208 }; 209 210 unsigned int 211 rbus_round_up(unsigned int size, unsigned int minval) 212 { 213 unsigned int power2; 214 215 if(size == 0) { 216 return 0; 217 } 218 219 power2=minval; 220 221 while(power2 < (1 << 31) && 222 power2 < size) { 223 power2 = power2 << 1; 224 } 225 226 return power2; 227 } 228 229 static void 230 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 231 cardbus_chipset_tag_t ct, 232 struct cardbus_softc *sc, 233 pci_chipset_tag_t pc, 234 struct cardbus_attach_args *caa, 235 int minbus, const int maxbus) 236 { 237 struct rbus_pci_addr_fixup_context rct; 238 const size_t size = sizeof(bus_size_t[maxbus+1]); 239 int busnum; 240 bus_addr_t start; 241 bus_space_handle_t handle; 242 u_int32_t reg; 243 244 rct.csc=csc; 245 rct.ct=ct; 246 rct.sc=sc; 247 rct.caa=caa; 248 rct.minbus = minbus; 249 rct.maxbus = maxbus; 250 if ((rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 251 (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL || 252 (rct.iobustags = 253 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL || 254 (rct.membustags = 255 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL) 256 panic("%s: memory allocation failed", __func__); 257 258 printf("%s: sizing buses %d-%d\n", 259 device_xname(rct.csc->sc_dev), 260 minbus, maxbus); 261 262 pci_device_foreach_min(pc, minbus, maxbus, 263 rbus_pci_phys_countspace, &rct); 264 265 /* 266 * we need to determine amount of address space for each 267 * bus. To do this, we have to roll up amounts and then 268 * we need to divide up the cardbus's extent to allocate 269 * some space to each bus. 270 */ 271 272 for(busnum=maxbus; busnum > minbus; busnum--) { 273 if(pci_bus_parent[busnum] != 0) { 274 if(pci_bus_parent[busnum] < minbus || 275 pci_bus_parent[busnum] >= maxbus) { 276 printf("%s: bus %d has illegal parent %d\n", 277 device_xname(rct.csc->sc_dev), 278 busnum, pci_bus_parent[busnum]); 279 continue; 280 } 281 282 /* first round amount of space up */ 283 rct.bussize_ioreqs[busnum] = 284 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 285 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 286 rct.bussize_ioreqs[busnum]; 287 288 rct.bussize_memreqs[busnum] = 289 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 290 rct.bussize_memreqs[pci_bus_parent[busnum]] += 291 rct.bussize_memreqs[busnum]; 292 293 } 294 } 295 296 rct.bussize_ioreqs[minbus] = 297 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 298 rct.bussize_memreqs[minbus] = 299 rbus_round_up(rct.bussize_memreqs[minbus], 8); 300 301 printf("%s: total needs IO %08zx and MEM %08zx\n", 302 device_xname(rct.csc->sc_dev), 303 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 304 305 if(!caa->ca_rbus_iot) { 306 panic("no iot bus"); 307 } 308 309 if(rct.bussize_ioreqs[minbus]) { 310 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 311 rct.bussize_ioreqs[minbus], 312 rct.bussize_ioreqs[minbus]-1 /* mask */, 313 rct.bussize_ioreqs[minbus] /* align */, 314 /* flags */ 0, 315 &start, 316 &handle) != 0) { 317 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 318 rct.bussize_ioreqs[minbus], minbus); 319 } 320 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 321 start, 322 rct.bussize_ioreqs[minbus], 323 0 /* offset to add to physical address 324 to make processor address */, 325 RBUS_SPACE_DEDICATE); 326 } 327 328 if(rct.bussize_memreqs[minbus]) { 329 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 330 rct.bussize_memreqs[minbus], 331 rct.bussize_memreqs[minbus]-1 /* mask */, 332 rct.bussize_memreqs[minbus] /* align */, 333 /* flags */ 0, 334 &start, 335 &handle) != 0) { 336 panic("%s: can not allocate %zu bytes in MEM bus %d", 337 device_xname(rct.csc->sc_dev), 338 rct.bussize_memreqs[minbus], minbus); 339 } 340 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 341 start, 342 rct.bussize_memreqs[minbus], 343 0 /* offset to add to physical 344 address to make processor 345 address */, 346 RBUS_SPACE_DEDICATE); 347 } 348 349 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 350 int busparent; 351 352 busparent = pci_bus_parent[busnum]; 353 354 printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n", 355 device_xname(rct.csc->sc_dev), 356 busnum, 357 busparent, 358 rct.bussize_ioreqs[busnum], 359 rct.bussize_memreqs[busnum]); 360 361 if(busparent > maxbus) { 362 panic("rbus_ppb: illegal parent"); 363 } 364 365 if(rct.bussize_ioreqs[busnum]) { 366 if(rbus_space_alloc(rct.iobustags[busparent], 367 0, 368 rct.bussize_ioreqs[busnum], 369 rct.bussize_ioreqs[busnum]-1 /*mask */, 370 rct.bussize_ioreqs[busnum] /* align */, 371 /* flags */ 0, 372 &start, 373 &handle) != 0) { 374 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d", 375 rct.bussize_ioreqs[busnum], busnum); 376 } 377 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 378 start, 379 rct.bussize_ioreqs[busnum], 380 0 /* offset to add to physical 381 address 382 to make processor address */, 383 RBUS_SPACE_DEDICATE); 384 385 /* program the bridge */ 386 387 /* enable I/O space */ 388 reg = pci_conf_read(pc, pci_bus_tag[busnum], 389 PCI_COMMAND_STATUS_REG); 390 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 391 pci_conf_write(pc, pci_bus_tag[busnum], 392 PCI_COMMAND_STATUS_REG, reg); 393 394 /* now init the limit register for I/O */ 395 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 396 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 397 ((((start + 398 rct.bussize_ioreqs[busnum] + 399 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 400 } 401 402 if(rct.bussize_memreqs[busnum]) { 403 if(rbus_space_alloc(rct.membustags[busparent], 404 0, 405 rct.bussize_memreqs[busnum] /* size */, 406 rct.bussize_memreqs[busnum]-1 /*mask */, 407 rct.bussize_memreqs[busnum] /* align */, 408 /* flags */ 0, 409 &start, 410 &handle) != 0) { 411 panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d", 412 rct.bussize_memreqs[busnum], busnum); 413 } 414 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 415 start, 416 rct.bussize_memreqs[busnum], 417 0 /* offset to add to physical 418 address to make processor 419 address */, 420 RBUS_SPACE_DEDICATE); 421 422 /* program the bridge */ 423 /* enable memory space */ 424 reg = pci_conf_read(pc, pci_bus_tag[busnum], 425 PCI_COMMAND_STATUS_REG); 426 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 427 pci_conf_write(pc, pci_bus_tag[busnum], 428 PCI_COMMAND_STATUS_REG, reg); 429 430 /* now init the limit register for memory */ 431 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 432 ((start & PPB_MEM_MASK) 433 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 434 (((start + 435 rct.bussize_memreqs[busnum] + 436 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 437 << PPB_MEMLIMIT_SHIFT)); 438 439 /* and set the prefetchable limits as well */ 440 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 441 ((start & PPB_MEM_MASK) 442 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 443 (((start + 444 rct.bussize_memreqs[busnum] + 445 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 446 << PPB_MEMLIMIT_SHIFT)); 447 448 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 449 } 450 } 451 452 printf("%s: configuring buses %d-%d\n", 453 device_xname(rct.csc->sc_dev), 454 minbus, maxbus); 455 pci_device_foreach_min(pc, minbus, maxbus, 456 rbus_pci_phys_allocate, &rct); 457 458 kmem_free(rct.bussize_ioreqs, size); 459 kmem_free(rct.bussize_memreqs, size); 460 kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t)); 461 kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t)); 462 } 463 464 static void 465 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context) 466 { 467 int bus, device, function; 468 struct rbus_pci_addr_fixup_context *rct = 469 (struct rbus_pci_addr_fixup_context *)context; 470 471 pci_decompose_tag(pc, tag, &bus, &device, &function); 472 473 printf("%s: configuring device %02x:%02x:%02x\n", 474 device_xname(rct->csc->sc_dev), 475 bus, device, function); 476 477 pciaddr_resource_manage(pc, tag, 478 rbus_do_phys_countspace, context); 479 } 480 481 482 int 483 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 484 { 485 struct rbus_pci_addr_fixup_context *rct = 486 (struct rbus_pci_addr_fixup_context *)ctx; 487 int bus, device, function; 488 489 pci_decompose_tag(pc, tag, &bus, &device, &function); 490 491 if(size > (1<<24)) { 492 printf("%s: skipping huge space request of size=%08x\n", 493 device_xname(rct->csc->sc_dev), (unsigned int)size); 494 return 0; 495 } 496 497 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 498 rct->bussize_ioreqs[bus] += size; 499 } else { 500 rct->bussize_memreqs[bus]+= size; 501 } 502 503 return 0; 504 } 505 506 static void 507 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context) 508 { 509 int bus, device, function, command; 510 struct rbus_pci_addr_fixup_context *rct = 511 (struct rbus_pci_addr_fixup_context *)context; 512 513 pci_decompose_tag(pc, tag, &bus, &device, &function); 514 515 printf("%s: configuring device %02x:%02x:%02x\n", 516 device_xname(rct->csc->sc_dev), 517 bus, device, function); 518 519 pciaddr_resource_manage(pc, tag, 520 rbus_do_phys_allocate, context); 521 522 /* now turn the device's memory and I/O on */ 523 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 524 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 525 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 526 } 527 528 int 529 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 530 { 531 struct rbus_pci_addr_fixup_context *rct = 532 (struct rbus_pci_addr_fixup_context *)ctx; 533 cardbus_chipset_tag_t ct = rct->ct; 534 struct cardbus_softc *sc = rct->sc; 535 cardbus_function_t *cf = sc->sc_cf; 536 rbus_tag_t rbustag; 537 bus_space_tag_t bustag; 538 bus_addr_t mask = size -1; 539 bus_addr_t base = 0; 540 bus_space_handle_t handle; 541 int busflags = 0; 542 int flags = 0; 543 const char *bustype; 544 int bus, device, function; 545 546 pci_decompose_tag(pc, tag, &bus, &device, &function); 547 548 /* 549 * some devices come up with garbage in them (Tulip?) 550 * we are in charge here, so give them address 551 * space anyway. 552 * 553 * XXX this may be due to no secondary PCI reset!!! 554 */ 555 #if 0 556 if (*addr) { 557 printf("Already allocated space at %08x\n", 558 (unsigned int)*addr); 559 return (0); 560 } 561 #endif 562 563 if(size > (1<<24)) { 564 printf("%s: skipping huge space request of size=%08x\n", 565 device_xname(rct->csc->sc_dev), (unsigned int)size); 566 return 0; 567 } 568 569 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 570 bustag = sc->sc_iot; 571 rbustag = rct->iobustags[bus]; 572 bustype = "io"; 573 } else { 574 bustag = sc->sc_memt; 575 rbustag = rct->membustags[bus]; 576 bustype = "mem"; 577 } 578 579 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 580 mask, size, busflags|flags, 581 addr, &handle)) { 582 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 583 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg); 584 585 *addr = 0; 586 pci_conf_write(pc, tag, mapreg, *addr); 587 return (1); 588 } 589 590 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 591 device_xname(rct->csc->sc_dev), 592 bustype, 593 (unsigned int)size, 594 bus, device, function, (unsigned int)*addr); 595 596 /* write new address to PCI device configuration header */ 597 pci_conf_write(pc, tag, mapreg, *addr); 598 599 /* check */ 600 { 601 DPRINTF(("%s: pci_addr_fixup: ", 602 device_xname(rct->csc->sc_dev))); 603 #ifdef CBB_DEBUG 604 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 605 #endif 606 } 607 608 /* double check that the value got inserted correctly */ 609 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 610 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 611 printf("%s: fixup failed. (new address=%#x)\n", 612 device_xname(rct->csc->sc_dev), 613 (unsigned)*addr); 614 return (1); 615 } 616 617 DPRINTF(("new address 0x%08x\n", 618 (unsigned)*addr)); 619 620 return (0); 621 } 622 623 static void 624 ppb_cardbus_attach(device_t parent, device_t self, void *aux) 625 { 626 struct ppb_cardbus_softc *csc = device_private(self); 627 struct cardbus_softc *parent_sc = device_private(parent); 628 struct cardbus_attach_args *ca = aux; 629 cardbus_devfunc_t ct = ca->ca_ct; 630 cardbus_chipset_tag_t cc = ct->ct_cc; 631 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 632 struct pcibus_attach_args pba; 633 char devinfo[256]; 634 pcireg_t busdata; 635 int mybus, rv; 636 u_int16_t pciirq; 637 int minbus, maxbus; 638 639 csc->sc_dev = self; 640 641 mybus = ct->ct_bus; 642 pciirq = 0; 643 rv = 0; 644 645 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 646 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 647 648 csc->sc_tag = ca->ca_tag; 649 650 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 651 minbus = pcibios_max_bus; 652 maxbus = minbus; /* XXX; gcc */ 653 654 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 655 aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0); 656 657 /* 658 * first, pull the reset wire on the secondary bridge 659 * to clear all devices 660 */ 661 busdata = Cardbus_conf_read(ct, ca->ca_tag, 662 PPB_REG_BRIDGECONTROL); 663 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 664 busdata | PPB_BC_SECONDARY_RESET); 665 delay(1); 666 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL, 667 busdata); 668 669 /* then go initialize the bridge control registers */ 670 maxbus = pci_bus_fixup(psc->sc_pc, 0); 671 } 672 673 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO); 674 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 675 aprint_error_dev(self, "still not configured, not fixable.\n"); 676 return; 677 } 678 679 #if 0 680 minbus = PPB_BUSINFO_SECONDARY(busdata); 681 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 682 #endif 683 684 /* now, go and assign addresses for the new devices */ 685 rbus_pci_addr_fixup(csc, cc, parent_sc, 686 psc->sc_pc, 687 ca, 688 minbus, maxbus); 689 690 /* 691 * now configure all connected devices to the IRQ which 692 * was assigned to this slot, as they will all arrive from 693 * that IRQ. 694 */ 695 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0); 696 697 /* 698 * enable direct routing of interrupts. We do this because 699 * we can not manage to get pccb_intr_establish() called until 700 * PCI subsystem is merged with rbus. The major thing that this 701 * routine does is avoid calling the driver's interrupt routine 702 * when the card has been removed. 703 * 704 * The rbus_ppb.c can not cope with card desertions until the merging 705 * anyway. 706 */ 707 pccbb_intr_route(psc); 708 709 /* 710 * Attach the PCI bus than hangs off of it. 711 * 712 * XXX Don't pass-through Memory Read Multiple. Should we? 713 * XXX Consult the spec... 714 */ 715 pba.pba_iot = ca->ca_iot; 716 pba.pba_memt = ca->ca_memt; 717 pba.pba_dmat = ca->ca_dmat; 718 pba.pba_pc = psc->sc_pc; 719 pba.pba_flags = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY; 720 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 721 pba.pba_bridgetag = &csc->sc_tag; 722 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 723 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 724 725 config_found_ia(self, "pcibus", &pba, rppbprint); 726 } 727 728 int 729 ppb_activate(device_t self, enum devact act) 730 { 731 printf("ppb_activate called\n"); 732 return 0; 733 } 734 735