1 /* $NetBSD: rbus_ppb.c,v 1.2 2001/11/13 12:51:13 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr@sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.2 2001/11/13 12:51:13 lukem Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <machine/endian.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/ppbreg.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include <dev/pci/pccbbreg.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include <dev/cardbus/cardbusvar.h> 77 #include <dev/cardbus/cardbusdevs.h> 78 79 #include <i386/pci/pci_addr_fixup.h> 80 #include <i386/pci/pci_bus_fixup.h> 81 #include <i386/pci/pci_intr_fixup.h> 82 #include <i386/pci/pcibios.h> 83 84 struct ppb_softc; 85 86 static int ppb_cardbus_match __P((struct device *, struct cfdata *, void *)); 87 static void ppb_cardbus_attach __P((struct device *, struct device *, void *)); 88 static int ppb_cardbus_detach __P((struct device * self, int flags)); 89 /*static*/ void ppb_cardbus_setup __P((struct ppb_softc * sc)); 90 /*static*/ int ppb_cardbus_enable __P((struct ppb_softc * sc)); 91 /*static*/ void ppb_cardbus_disable __P((struct ppb_softc * sc)); 92 static int ppb_activate __P((struct device *self, enum devact act)); 93 int rppbprint __P((void *aux, const char *pnp)); 94 int rbus_intr_fixup __P((pci_chipset_tag_t pc, int minbus, 95 int maxbus, int line)); 96 void rbus_do_header_fixup __P((pci_chipset_tag_t pc, pcitag_t tag, 97 void *context)); 98 99 static void rbus_pci_phys_allocate __P((pci_chipset_tag_t pc, 100 pcitag_t tag, 101 void *context)); 102 103 static int rbus_do_phys_allocate __P((pci_chipset_tag_t pc, 104 pcitag_t tag, 105 int mapreg, 106 void *ctx, 107 int type, 108 bus_addr_t *addr, 109 bus_size_t size)); 110 111 static void rbus_pci_phys_countspace __P((pci_chipset_tag_t pc, 112 pcitag_t tag, 113 void *context)); 114 115 static int rbus_do_phys_countspace __P((pci_chipset_tag_t pc, 116 pcitag_t tag, 117 int mapreg, 118 void *ctx, 119 int type, 120 bus_addr_t *addr, 121 bus_size_t size)); 122 123 unsigned int rbus_round_up __P((unsigned int size, unsigned int min)); 124 125 126 struct ppb_cardbus_softc { 127 struct device sc_dev; 128 int foo; 129 }; 130 131 struct cfattach rbus_ppb_ca = { 132 sizeof(struct ppb_cardbus_softc), 133 ppb_cardbus_match, 134 ppb_cardbus_attach, 135 ppb_cardbus_detach, 136 ppb_activate 137 }; 138 139 #ifdef CBB_DEBUG 140 int rbus_ppb_debug = 0; /* hack with kdb */ 141 #define DPRINTF(X) if(rbus_ppb_debug) printf X 142 #else 143 #define DPRINTF(X) 144 #endif 145 146 static int 147 ppb_cardbus_match(parent, match, aux) 148 struct device *parent; 149 struct cfdata *match; 150 void *aux; 151 { 152 struct cardbus_attach_args *ca = aux; 153 154 if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 155 CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 156 return (1); 157 158 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 159 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 160 /* XXX */ 161 printf("recognizing generic bridge chip\n"); 162 } 163 164 return (0); 165 } 166 167 168 int 169 rppbprint(aux, pnp) 170 void *aux; 171 const char *pnp; 172 { 173 struct pcibus_attach_args *pba = aux; 174 175 /* only PCIs can attach to PPBs; easy. */ 176 if (pnp) 177 printf("pci at %s", pnp); 178 printf(" bus %d (rbus)", pba->pba_bus); 179 return (UNCONF); 180 } 181 182 int 183 rbus_intr_fixup(pci_chipset_tag_t pc, 184 int minbus, 185 int maxbus, 186 int line) 187 { 188 pci_device_foreach_min(pc, minbus, 189 maxbus, rbus_do_header_fixup, (void *)&line); 190 return 0; 191 } 192 193 void 194 rbus_do_header_fixup(pc, tag, context) 195 pci_chipset_tag_t pc; 196 pcitag_t tag; 197 void *context; 198 { 199 int pin, irq; 200 int bus, device, function; 201 pcireg_t intr, id; 202 int *pline = (int *)context; 203 int line = *pline; 204 205 pci_decompose_tag(pc, tag, &bus, &device, &function); 206 id = pci_conf_read(pc, tag, PCI_ID_REG); 207 208 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 209 pin = PCI_INTERRUPT_PIN(intr); 210 irq = PCI_INTERRUPT_LINE(intr); 211 212 #if 0 213 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 214 bus, device, function, pin, line); 215 #endif 216 217 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 218 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 219 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 220 221 } 222 223 /* 224 * This function takes a range of PCI bus numbers and 225 * allocates space for all devices found in this space (the BARs) from 226 * the rbus space maps (I/O and memory). 227 * 228 * It assumes that "rbus" is defined. The whole concept does. 229 * 230 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 231 * This function is mostly stolen from 232 * pci_addr_fixup.c:pciaddr_resource_reserve. 233 * 234 */ 235 struct rbus_pci_addr_fixup_context { 236 struct ppb_cardbus_softc *csc; 237 cardbus_chipset_tag_t ct; 238 struct cardbus_softc *sc; 239 struct cardbus_attach_args *caa; 240 int minbus; 241 int maxbus; 242 bus_size_t *bussize_ioreqs; 243 bus_size_t *bussize_memreqs; 244 rbus_tag_t *iobustags; 245 rbus_tag_t *membustags; 246 }; 247 248 unsigned int 249 rbus_round_up(unsigned int size, unsigned int min) 250 { 251 unsigned int power2; 252 253 if(size == 0) { 254 return 0; 255 } 256 257 power2=min; 258 259 while(power2 < (1 << 31) && 260 power2 < size) { 261 power2 = power2 << 1; 262 } 263 264 return power2; 265 } 266 267 static void 268 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 269 cardbus_chipset_tag_t ct, 270 struct cardbus_softc *sc, 271 pci_chipset_tag_t pc, 272 struct cardbus_attach_args *caa, 273 int minbus, int maxbus) 274 { 275 struct rbus_pci_addr_fixup_context rct; 276 int size, busnum; 277 bus_addr_t start; 278 bus_space_handle_t handle; 279 u_int32_t reg; 280 281 rct.csc=csc; 282 rct.ct=ct; 283 rct.sc=sc; 284 rct.caa=caa; 285 rct.minbus = minbus; 286 rct.maxbus = maxbus; 287 size = sizeof(bus_size_t)*(maxbus+1); 288 rct.bussize_ioreqs = alloca(size); 289 rct.bussize_memreqs = alloca(size); 290 rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t)); 291 rct.membustags = alloca(maxbus * sizeof(rbus_tag_t)); 292 293 bzero(rct.bussize_ioreqs, size); 294 bzero(rct.bussize_memreqs, size); 295 296 printf("%s: sizing buses %d-%d\n", 297 rct.csc->sc_dev.dv_xname, 298 minbus, maxbus); 299 300 pci_device_foreach_min(pc, minbus, maxbus, 301 rbus_pci_phys_countspace, &rct); 302 303 /* 304 * we need to determine amount of address space for each 305 * bus. To do this, we have to roll up amounts and then 306 * we need to divide up the cardbus's extent to allocate 307 * some space to each bus. 308 */ 309 310 for(busnum=maxbus; busnum > minbus; busnum--) { 311 if(pci_bus_parent[busnum] != 0) { 312 if(pci_bus_parent[busnum] < minbus || 313 pci_bus_parent[busnum] >= maxbus) { 314 printf("%s: bus %d has illegal parent %d\n", 315 rct.csc->sc_dev.dv_xname, 316 busnum, pci_bus_parent[busnum]); 317 continue; 318 } 319 320 /* first round amount of space up */ 321 rct.bussize_ioreqs[busnum] = 322 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 323 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 324 rct.bussize_ioreqs[busnum]; 325 326 rct.bussize_memreqs[busnum] = 327 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 328 rct.bussize_memreqs[pci_bus_parent[busnum]] += 329 rct.bussize_memreqs[busnum]; 330 331 } 332 } 333 334 rct.bussize_ioreqs[minbus] = 335 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 336 rct.bussize_memreqs[minbus] = 337 rbus_round_up(rct.bussize_memreqs[minbus], 8); 338 339 printf("%s: total needs IO %08lx and MEM %08lx\n", 340 rct.csc->sc_dev.dv_xname, 341 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 342 343 if(!caa->ca_rbus_iot) { 344 panic("no iot bus"); 345 } 346 347 if(rct.bussize_ioreqs[minbus]) { 348 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 349 rct.bussize_ioreqs[minbus], 350 rct.bussize_ioreqs[minbus]-1 /* mask */, 351 rct.bussize_ioreqs[minbus] /* align */, 352 /* flags */ 0, 353 &start, 354 &handle) != 0) { 355 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 356 rct.bussize_ioreqs[minbus], minbus); 357 } 358 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 359 start, 360 rct.bussize_ioreqs[minbus], 361 0 /* offset to add to physical address 362 to make processor address */, 363 RBUS_SPACE_DEDICATE); 364 } 365 366 if(rct.bussize_memreqs[minbus]) { 367 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 368 rct.bussize_memreqs[minbus], 369 rct.bussize_memreqs[minbus]-1 /* mask */, 370 rct.bussize_memreqs[minbus] /* align */, 371 /* flags */ 0, 372 &start, 373 &handle) != 0) { 374 panic("%s: can not allocate %ld bytes in MEM bus %d\n", 375 rct.csc->sc_dev.dv_xname, 376 rct.bussize_memreqs[minbus], minbus); 377 } 378 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 379 start, 380 rct.bussize_memreqs[minbus], 381 0 /* offset to add to physical 382 address to make processor 383 address */, 384 RBUS_SPACE_DEDICATE); 385 } 386 387 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 388 int busparent; 389 390 busparent = pci_bus_parent[busnum]; 391 392 printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n", 393 rct.csc->sc_dev.dv_xname, 394 busnum, 395 busparent, 396 rct.bussize_ioreqs[busnum], 397 rct.bussize_memreqs[busnum]); 398 399 if(busparent > maxbus) { 400 panic("rbus_ppb: illegal parent"); 401 } 402 403 if(rct.bussize_ioreqs[busnum]) { 404 if(rbus_space_alloc(rct.iobustags[busparent], 405 0, 406 rct.bussize_ioreqs[busnum], 407 rct.bussize_ioreqs[busnum]-1 /*mask */, 408 rct.bussize_ioreqs[busnum] /* align */, 409 /* flags */ 0, 410 &start, 411 &handle) != 0) { 412 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 413 rct.bussize_ioreqs[busnum], busnum); 414 } 415 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 416 start, 417 rct.bussize_ioreqs[busnum], 418 0 /* offset to add to physical 419 address 420 to make processor address */, 421 RBUS_SPACE_DEDICATE); 422 423 /* program the bridge */ 424 425 /* enable I/O space */ 426 reg = pci_conf_read(pc, pci_bus_tag[busnum], 427 PCI_COMMAND_STATUS_REG); 428 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 429 pci_conf_write(pc, pci_bus_tag[busnum], 430 PCI_COMMAND_STATUS_REG, reg); 431 432 /* now init the limit register for I/O */ 433 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 434 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 435 ((((start + 436 rct.bussize_ioreqs[busnum] + 437 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 438 } 439 440 if(rct.bussize_memreqs[busnum]) { 441 if(rbus_space_alloc(rct.membustags[busparent], 442 0, 443 rct.bussize_memreqs[busnum] /* size */, 444 rct.bussize_memreqs[busnum]-1 /*mask */, 445 rct.bussize_memreqs[busnum] /* align */, 446 /* flags */ 0, 447 &start, 448 &handle) != 0) { 449 panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d\n", 450 rct.bussize_memreqs[busnum], busnum); 451 } 452 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 453 start, 454 rct.bussize_memreqs[busnum], 455 0 /* offset to add to physical 456 address to make processor 457 address */, 458 RBUS_SPACE_DEDICATE); 459 460 /* program the bridge */ 461 /* enable memory space */ 462 reg = pci_conf_read(pc, pci_bus_tag[busnum], 463 PCI_COMMAND_STATUS_REG); 464 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 465 pci_conf_write(pc, pci_bus_tag[busnum], 466 PCI_COMMAND_STATUS_REG, reg); 467 468 /* now init the limit register for memory */ 469 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 470 ((start & PPB_MEM_MASK) 471 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 472 (((start + 473 rct.bussize_memreqs[busnum] + 474 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 475 << PPB_MEMLIMIT_SHIFT)); 476 477 /* and set the prefetchable limits as well */ 478 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 479 ((start & PPB_MEM_MASK) 480 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 481 (((start + 482 rct.bussize_memreqs[busnum] + 483 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 484 << PPB_MEMLIMIT_SHIFT)); 485 486 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 487 } 488 } 489 490 printf("%s: configuring buses %d-%d\n", 491 rct.csc->sc_dev.dv_xname, 492 minbus, maxbus); 493 pci_device_foreach_min(pc, minbus, maxbus, 494 rbus_pci_phys_allocate, &rct); 495 } 496 497 static void 498 rbus_pci_phys_countspace(pc, tag, context) 499 pci_chipset_tag_t pc; 500 pcitag_t tag; 501 void *context; 502 { 503 int bus, device, function; 504 struct rbus_pci_addr_fixup_context *rct = 505 (struct rbus_pci_addr_fixup_context *)context; 506 507 pci_decompose_tag(pc, tag, &bus, &device, &function); 508 509 printf("%s: configuring device %02x:%02x:%02x\n", 510 rct->csc->sc_dev.dv_xname, 511 bus, device, function); 512 513 pciaddr_resource_manage(pc, tag, 514 rbus_do_phys_countspace, context); 515 } 516 517 518 int 519 rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size) 520 pci_chipset_tag_t pc; 521 pcitag_t tag; 522 void *ctx; 523 int mapreg, type; 524 bus_addr_t *addr; 525 bus_size_t size; 526 { 527 struct rbus_pci_addr_fixup_context *rct = 528 (struct rbus_pci_addr_fixup_context *)ctx; 529 int bus, device, function; 530 531 pci_decompose_tag(pc, tag, &bus, &device, &function); 532 533 if(size > (1<<24)) { 534 printf("%s: skipping huge space request of size=%08x\n", 535 rct->csc->sc_dev.dv_xname, (unsigned int)size); 536 return 0; 537 } 538 539 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 540 rct->bussize_ioreqs[bus] += size; 541 } else { 542 rct->bussize_memreqs[bus]+= size; 543 } 544 545 return 0; 546 } 547 548 static void 549 rbus_pci_phys_allocate(pc, tag, context) 550 pci_chipset_tag_t pc; 551 pcitag_t tag; 552 void *context; 553 { 554 int bus, device, function, command; 555 struct rbus_pci_addr_fixup_context *rct = 556 (struct rbus_pci_addr_fixup_context *)context; 557 //cardbus_chipset_tag_t ct = rct->ct; 558 // struct cardbus_softc *sc = rct->sc; 559 560 pci_decompose_tag(pc, tag, &bus, &device, &function); 561 562 printf("%s: configuring device %02x:%02x:%02x\n", 563 rct->csc->sc_dev.dv_xname, 564 bus, device, function); 565 566 pciaddr_resource_manage(pc, tag, 567 rbus_do_phys_allocate, context); 568 569 /* now turn the device's memory and I/O on */ 570 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 571 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 572 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 573 } 574 575 int 576 rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size) 577 pci_chipset_tag_t pc; 578 pcitag_t tag; 579 void *ctx; 580 int mapreg, type; 581 bus_addr_t *addr; 582 bus_size_t size; 583 { 584 struct rbus_pci_addr_fixup_context *rct = 585 (struct rbus_pci_addr_fixup_context *)ctx; 586 cardbus_chipset_tag_t ct = rct->ct; 587 struct cardbus_softc *sc = rct->sc; 588 cardbus_function_t *cf = sc->sc_cf; 589 rbus_tag_t rbustag; 590 bus_space_tag_t bustag; 591 bus_addr_t mask = size -1; 592 bus_addr_t base = 0; 593 bus_space_handle_t handle; 594 int busflags = 0; 595 int flags = 0; 596 char *bustype; 597 int bus, device, function; 598 599 pci_decompose_tag(pc, tag, &bus, &device, &function); 600 601 /* 602 * some devices come up with garbage in them (Tulip?) 603 * we are in charge here, so give them address 604 * space anyway. 605 * 606 * XXX this may be due to no secondary PCI reset!!! 607 */ 608 #if 0 609 if (*addr) { 610 printf("Already allocated space at %08x\n", 611 (unsigned int)*addr); 612 return (0); 613 } 614 #endif 615 616 if(size > (1<<24)) { 617 printf("%s: skipping huge space request of size=%08x\n", 618 rct->csc->sc_dev.dv_xname, (unsigned int)size); 619 return 0; 620 } 621 622 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 623 bustag = sc->sc_iot; 624 rbustag = rct->iobustags[bus]; 625 bustype = "io"; 626 } else { 627 bustag = sc->sc_memt; 628 rbustag = rct->membustags[bus]; 629 bustype = "mem"; 630 } 631 632 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 633 mask, size, busflags|flags, 634 addr, &handle)) { 635 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 636 rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg); 637 638 *addr = 0; 639 pci_conf_write(pc, tag, mapreg, *addr); 640 return (1); 641 } 642 643 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 644 rct->csc->sc_dev.dv_xname, 645 bustype, 646 (unsigned int)size, 647 bus, device, function, (unsigned int)*addr); 648 649 /* write new address to PCI device configuration header */ 650 pci_conf_write(pc, tag, mapreg, *addr); 651 652 /* check */ 653 { 654 DPRINTF(("%s: pci_addr_fixup: ", 655 rct->csc->sc_dev.dv_xname)); 656 #ifdef CBB_DEBUG 657 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 658 #endif 659 } 660 661 /* double check that the value got inserted correctly */ 662 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 663 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 664 printf("%s: fixup failed. (new address=%#x)\n", 665 rct->csc->sc_dev.dv_xname, 666 (unsigned)*addr); 667 return (1); 668 } 669 670 DPRINTF(("new address 0x%08x\n", 671 (unsigned)*addr)); 672 673 return (0); 674 } 675 676 static void 677 ppb_cardbus_attach(parent, self, aux) 678 struct device *parent, *self; 679 void *aux; 680 { 681 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 682 struct cardbus_softc *parent_sc = 683 (struct cardbus_softc *) csc->sc_dev.dv_parent; 684 struct cardbus_attach_args *ca = aux; 685 cardbus_devfunc_t ct = ca->ca_ct; 686 cardbus_chipset_tag_t cc = ct->ct_cc; 687 cardbus_function_tag_t cf = ct->ct_cf; 688 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 689 struct pcibus_attach_args pba; 690 char devinfo[256]; 691 pcireg_t busdata; 692 int mybus, rv; 693 u_int16_t pciirq; 694 int minbus, maxbus; 695 696 mybus = ct->ct_bus; 697 pciirq = 0; 698 rv = 0; 699 700 /* shut up compiler */ 701 csc->foo=parent_sc->sc_intrline; 702 703 704 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo); 705 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 706 707 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 708 minbus = pcibios_max_bus; 709 710 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 711 printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n", 712 self->dv_xname, 0); 713 714 /* 715 * first, pull the reset wire on the secondary bridge 716 * to clear all devices 717 */ 718 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, 719 PPB_REG_BRIDGECONTROL); 720 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 721 busdata | PPB_BC_SECONDARY_RESET); 722 delay(1); 723 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 724 busdata); 725 726 /* then go initialize the bridge control registers */ 727 maxbus = pci_bus_fixup(psc->sc_pc, 0); 728 } 729 730 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 731 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 732 printf("%s: still not configured, not fixable.\n", 733 self->dv_xname); 734 return; 735 } 736 737 #if 0 738 minbus = PPB_BUSINFO_SECONDARY(busdata); 739 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 740 #endif 741 742 /* now, go and assign addresses for the new devices */ 743 rbus_pci_addr_fixup(csc, cc, parent_sc, 744 psc->sc_pc, 745 ca, 746 minbus, maxbus); 747 748 /* 749 * now configure all connected devices to the IRQ which 750 * was assigned to this slot, as they will all arrive from 751 * that IRQ. 752 */ 753 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 754 755 /* 756 * enable direct routing of interrupts. We do this because 757 * we can not manage to get pccb_intr_establish() called until 758 * PCI subsystem is merged with rbus. The major thing that this 759 * routine does is avoid calling the driver's interrupt routine 760 * when the card has been removed. 761 * 762 * The rbus_ppb.c can not cope with card desertions until the merging 763 * anyway. 764 */ 765 pccbb_intr_route(psc); 766 767 /* 768 * Attach the PCI bus than hangs off of it. 769 * 770 * XXX Don't pass-through Memory Read Multiple. Should we? 771 * XXX Consult the spec... 772 */ 773 pba.pba_busname = "pci"; 774 pba.pba_iot = ca->ca_iot; 775 pba.pba_memt = ca->ca_memt; 776 pba.pba_dmat = ca->ca_dmat; 777 pba.pba_pc = psc->sc_pc; 778 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 779 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 780 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 781 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 782 783 config_found(self, &pba, rppbprint); 784 } 785 786 void 787 ppb_cardbus_setup(struct ppb_softc * sc) 788 { 789 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc; 790 #if 0 791 cardbus_chipset_tag_t cc = psc->sc_cc; 792 cardbus_function_tag_t cf = psc->sc_cf; 793 #endif 794 795 /* shut up compiler */ 796 csc->foo=2; 797 798 printf("ppb_cardbus_setup called\n"); 799 #if 0 800 /* not sure what to do here */ 801 cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus, 802 csc->ct->ct_dev, csc->ct->ct_func); 803 804 command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG); 805 if (csc->base0_reg) { 806 Cardbus_conf_write(csc->ct, tag, 807 CARDBUS_BASE0_REG, csc->base0_reg); 808 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE); 809 command |= CARDBUS_COMMAND_MEM_ENABLE | 810 CARDBUS_COMMAND_MASTER_ENABLE; 811 } else if (csc->base1_reg) { 812 Cardbus_conf_write(csc->ct, tag, 813 CARDBUS_BASE1_REG, csc->base1_reg); 814 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE); 815 command |= (CARDBUS_COMMAND_IO_ENABLE | 816 CARDBUS_COMMAND_MASTER_ENABLE); 817 } 818 819 (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE); 820 821 /* enable the card */ 822 Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command); 823 #endif 824 } 825 826 int 827 ppb_cardbus_enable(struct ppb_softc * sc) 828 { 829 #if 0 830 struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc; 831 struct cardbus_softc *psc = 832 (struct cardbus_softc *) sc->sc_dev.dv_parent; 833 cardbus_chipset_tag_t cc = psc->sc_cc; 834 cardbus_function_tag_t cf = psc->sc_cf; 835 836 Cardbus_function_enable(csc->ct); 837 838 fxp_cardbus_setup(sc); 839 840 /* Map and establish the interrupt. */ 841 842 sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, 843 fxp_intr, sc); 844 if (NULL == sc->sc_ih) { 845 printf("%s: couldn't establish interrupt\n", 846 sc->sc_dev.dv_xname); 847 return 1; 848 } 849 850 printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, 851 psc->sc_intrline); 852 853 #endif 854 return 0; 855 } 856 857 void 858 ppb_cardbus_disable(struct ppb_softc * sc) 859 { 860 #if 0 861 struct cardbus_softc *psc = 862 (struct cardbus_softc *) sc->sc_dev.dv_parent; 863 cardbus_chipset_tag_t cc = psc->sc_cc; 864 cardbus_function_tag_t cf = psc->sc_cf; 865 866 /* Remove interrupt handler. */ 867 cardbus_intr_disestablish(cc, cf, sc->sc_ih); 868 869 Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct); 870 #endif 871 } 872 873 static int 874 ppb_cardbus_detach(self, flags) 875 struct device *self; 876 int flags; 877 { 878 /* struct ppb_softc *sc = (struct ppb_softc *) self;*/ 879 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 880 881 #if 0 882 struct cardbus_devfunc *ct = csc->ct; 883 int rv, reg; 884 885 #ifdef DIAGNOSTIC 886 if (ct == NULL) 887 panic("%s: data structure lacks\n", sc->sc_dev.dv_xname); 888 #endif 889 890 rv = fxp_detach(sc); 891 if (rv == 0) { 892 /* 893 * Unhook the interrupt handler. 894 */ 895 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 896 897 /* 898 * release bus space and close window 899 */ 900 if (csc->base0_reg) 901 reg = CARDBUS_BASE0_REG; 902 else 903 reg = CARDBUS_BASE1_REG; 904 Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size); 905 } 906 return (rv); 907 908 #endif 909 csc->foo=1; 910 return 0; 911 912 } 913 914 int 915 ppb_activate(self, act) 916 struct device *self; 917 enum devact act; 918 { 919 printf("ppb_activate called\n"); 920 return 0; 921 } 922 923